1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMPerfectShuffle.h"
21 #include "ARMRegisterInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Function.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Instruction.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Type.h"
32 #include "llvm/CodeGen/CallingConvLower.h"
33 #include "llvm/CodeGen/MachineBasicBlock.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/ADT/VectorExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/raw_ostream.h"
51 EnableARMLongCalls("arm-long-calls", cl::Hidden,
52 cl::desc("Generate calls via indirect call instructions."),
55 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
56 CCValAssign::LocInfo &LocInfo,
57 ISD::ArgFlagsTy &ArgFlags,
59 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
60 CCValAssign::LocInfo &LocInfo,
61 ISD::ArgFlagsTy &ArgFlags,
63 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
64 CCValAssign::LocInfo &LocInfo,
65 ISD::ArgFlagsTy &ArgFlags,
67 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
68 CCValAssign::LocInfo &LocInfo,
69 ISD::ArgFlagsTy &ArgFlags,
72 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
73 EVT PromotedBitwiseVT) {
74 if (VT != PromotedLdStVT) {
75 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
76 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
77 PromotedLdStVT.getSimpleVT());
79 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
80 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
81 PromotedLdStVT.getSimpleVT());
84 EVT ElemTy = VT.getVectorElementType();
85 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
86 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
87 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
88 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
89 if (ElemTy != MVT::i32) {
90 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
91 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
92 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
93 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
95 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
97 if (llvm::ModelWithRegSequence())
98 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
100 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
101 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
103 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
104 if (VT.isInteger()) {
105 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
106 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
107 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
110 // Promote all bit-wise operations.
111 if (VT.isInteger() && VT != PromotedBitwiseVT) {
112 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
113 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
114 PromotedBitwiseVT.getSimpleVT());
115 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
116 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
117 PromotedBitwiseVT.getSimpleVT());
118 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
123 // Neon does not support vector divide/remainder operations.
124 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
125 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
126 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
127 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
128 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
129 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
132 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
133 addRegisterClass(VT, ARM::DPRRegisterClass);
134 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
137 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
138 addRegisterClass(VT, ARM::QPRRegisterClass);
139 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
142 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
143 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
144 return new TargetLoweringObjectFileMachO();
146 return new ARMElfTargetObjectFile();
149 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
150 : TargetLowering(TM, createTLOF(TM)) {
151 Subtarget = &TM.getSubtarget<ARMSubtarget>();
153 if (Subtarget->isTargetDarwin()) {
154 // Uses VFP for Thumb libfuncs if available.
155 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
156 // Single-precision floating-point arithmetic.
157 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
158 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
159 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
160 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
162 // Double-precision floating-point arithmetic.
163 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
164 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
165 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
166 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
168 // Single-precision comparisons.
169 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
170 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
171 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
172 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
173 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
174 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
175 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
176 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
178 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
179 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
180 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
181 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
182 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
183 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
184 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
187 // Double-precision comparisons.
188 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
189 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
190 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
191 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
192 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
193 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
194 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
195 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
197 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
206 // Floating-point to integer conversions.
207 // i64 conversions are done via library routines even when generating VFP
208 // instructions, so use the same ones.
209 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
210 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
211 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
212 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
214 // Conversions between floating types.
215 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
216 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
218 // Integer to floating-point conversions.
219 // i64 conversions are done via library routines even when generating VFP
220 // instructions, so use the same ones.
221 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
222 // e.g., __floatunsidf vs. __floatunssidfvfp.
223 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
224 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
225 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
226 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
230 // These libcalls are not available in 32-bit.
231 setLibcallName(RTLIB::SHL_I128, 0);
232 setLibcallName(RTLIB::SRL_I128, 0);
233 setLibcallName(RTLIB::SRA_I128, 0);
235 // Libcalls should use the AAPCS base standard ABI, even if hard float
236 // is in effect, as per the ARM RTABI specification, section 4.1.2.
237 if (Subtarget->isAAPCS_ABI()) {
238 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
239 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
240 CallingConv::ARM_AAPCS);
244 if (Subtarget->isThumb1Only())
245 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
247 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
248 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
249 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
250 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
252 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
255 if (Subtarget->hasNEON()) {
256 addDRTypeForNEON(MVT::v2f32);
257 addDRTypeForNEON(MVT::v8i8);
258 addDRTypeForNEON(MVT::v4i16);
259 addDRTypeForNEON(MVT::v2i32);
260 addDRTypeForNEON(MVT::v1i64);
262 addQRTypeForNEON(MVT::v4f32);
263 addQRTypeForNEON(MVT::v2f64);
264 addQRTypeForNEON(MVT::v16i8);
265 addQRTypeForNEON(MVT::v8i16);
266 addQRTypeForNEON(MVT::v4i32);
267 addQRTypeForNEON(MVT::v2i64);
269 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
270 // neither Neon nor VFP support any arithmetic operations on it.
271 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
272 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
273 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
274 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
275 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
276 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
277 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
278 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
279 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
280 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
281 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
282 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
283 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
284 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
285 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
286 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
287 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
288 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
289 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
290 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
291 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
292 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
293 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
294 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
296 // Neon does not support some operations on v1i64 and v2i64 types.
297 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
298 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
299 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
300 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
302 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
303 setTargetDAGCombine(ISD::SHL);
304 setTargetDAGCombine(ISD::SRL);
305 setTargetDAGCombine(ISD::SRA);
306 setTargetDAGCombine(ISD::SIGN_EXTEND);
307 setTargetDAGCombine(ISD::ZERO_EXTEND);
308 setTargetDAGCombine(ISD::ANY_EXTEND);
309 setTargetDAGCombine(ISD::SELECT_CC);
312 computeRegisterProperties();
314 // ARM does not have f32 extending load.
315 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
317 // ARM does not have i1 sign extending load.
318 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
320 // ARM supports all 4 flavors of integer indexed load / store.
321 if (!Subtarget->isThumb1Only()) {
322 for (unsigned im = (unsigned)ISD::PRE_INC;
323 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
324 setIndexedLoadAction(im, MVT::i1, Legal);
325 setIndexedLoadAction(im, MVT::i8, Legal);
326 setIndexedLoadAction(im, MVT::i16, Legal);
327 setIndexedLoadAction(im, MVT::i32, Legal);
328 setIndexedStoreAction(im, MVT::i1, Legal);
329 setIndexedStoreAction(im, MVT::i8, Legal);
330 setIndexedStoreAction(im, MVT::i16, Legal);
331 setIndexedStoreAction(im, MVT::i32, Legal);
335 // i64 operation support.
336 if (Subtarget->isThumb1Only()) {
337 setOperationAction(ISD::MUL, MVT::i64, Expand);
338 setOperationAction(ISD::MULHU, MVT::i32, Expand);
339 setOperationAction(ISD::MULHS, MVT::i32, Expand);
340 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
341 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
343 setOperationAction(ISD::MUL, MVT::i64, Expand);
344 setOperationAction(ISD::MULHU, MVT::i32, Expand);
345 if (!Subtarget->hasV6Ops())
346 setOperationAction(ISD::MULHS, MVT::i32, Expand);
348 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
349 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
350 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
351 setOperationAction(ISD::SRL, MVT::i64, Custom);
352 setOperationAction(ISD::SRA, MVT::i64, Custom);
354 // ARM does not have ROTL.
355 setOperationAction(ISD::ROTL, MVT::i32, Expand);
356 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
357 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
358 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
359 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
361 // Only ARMv6 has BSWAP.
362 if (!Subtarget->hasV6Ops())
363 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
365 // These are expanded into libcalls.
366 if (!Subtarget->hasDivide()) {
367 // v7M has a hardware divider
368 setOperationAction(ISD::SDIV, MVT::i32, Expand);
369 setOperationAction(ISD::UDIV, MVT::i32, Expand);
371 setOperationAction(ISD::SREM, MVT::i32, Expand);
372 setOperationAction(ISD::UREM, MVT::i32, Expand);
373 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
374 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
376 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
377 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
378 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
379 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
380 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
382 setOperationAction(ISD::TRAP, MVT::Other, Legal);
384 // Use the default implementation.
385 setOperationAction(ISD::VASTART, MVT::Other, Custom);
386 setOperationAction(ISD::VAARG, MVT::Other, Expand);
387 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
388 setOperationAction(ISD::VAEND, MVT::Other, Expand);
389 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
390 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
391 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
392 // FIXME: Shouldn't need this, since no register is used, but the legalizer
393 // doesn't yet know how to not do that for SjLj.
394 setExceptionSelectorRegister(ARM::R0);
395 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
396 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
398 // If the subtarget does not have extract instructions, sign_extend_inreg
399 // needs to be expanded. Extract is available in ARM mode on v6 and up,
400 // and on most Thumb2 implementations.
401 if ((!Subtarget->isThumb() && !Subtarget->hasV6Ops())
402 || (Subtarget->isThumb2() && !Subtarget->hasT2ExtractPack())) {
403 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
404 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
408 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
409 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
410 // iff target supports vfp2.
411 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
413 // We want to custom lower some of our intrinsics.
414 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
415 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
416 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
418 setOperationAction(ISD::SETCC, MVT::i32, Expand);
419 setOperationAction(ISD::SETCC, MVT::f32, Expand);
420 setOperationAction(ISD::SETCC, MVT::f64, Expand);
421 setOperationAction(ISD::SELECT, MVT::i32, Expand);
422 setOperationAction(ISD::SELECT, MVT::f32, Expand);
423 setOperationAction(ISD::SELECT, MVT::f64, Expand);
424 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
425 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
426 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
428 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
429 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
430 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
431 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
432 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
434 // We don't support sin/cos/fmod/copysign/pow
435 setOperationAction(ISD::FSIN, MVT::f64, Expand);
436 setOperationAction(ISD::FSIN, MVT::f32, Expand);
437 setOperationAction(ISD::FCOS, MVT::f32, Expand);
438 setOperationAction(ISD::FCOS, MVT::f64, Expand);
439 setOperationAction(ISD::FREM, MVT::f64, Expand);
440 setOperationAction(ISD::FREM, MVT::f32, Expand);
441 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
442 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
443 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
445 setOperationAction(ISD::FPOW, MVT::f64, Expand);
446 setOperationAction(ISD::FPOW, MVT::f32, Expand);
448 // Various VFP goodness
449 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
450 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
451 if (Subtarget->hasVFP2()) {
452 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
453 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
454 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
455 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
457 // Special handling for half-precision FP.
458 if (!Subtarget->hasFP16()) {
459 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
460 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
464 // We have target-specific dag combine patterns for the following nodes:
465 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
466 setTargetDAGCombine(ISD::ADD);
467 setTargetDAGCombine(ISD::SUB);
468 setTargetDAGCombine(ISD::MUL);
470 setStackPointerRegisterToSaveRestore(ARM::SP);
472 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
473 setSchedulingPreference(Sched::RegPressure);
475 setSchedulingPreference(Sched::Hybrid);
477 // FIXME: If-converter should use instruction latency to determine
478 // profitability rather than relying on fixed limits.
479 if (Subtarget->getCPUString() == "generic") {
480 // Generic (and overly aggressive) if-conversion limits.
481 setIfCvtBlockSizeLimit(10);
482 setIfCvtDupBlockSizeLimit(2);
483 } else if (Subtarget->hasV7Ops()) {
484 setIfCvtBlockSizeLimit(3);
485 setIfCvtDupBlockSizeLimit(1);
486 } else if (Subtarget->hasV6Ops()) {
487 setIfCvtBlockSizeLimit(2);
488 setIfCvtDupBlockSizeLimit(1);
490 setIfCvtBlockSizeLimit(3);
491 setIfCvtDupBlockSizeLimit(2);
494 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
495 // Do not enable CodePlacementOpt for now: it currently runs after the
496 // ARMConstantIslandPass and messes up branch relaxation and placement
497 // of constant islands.
498 // benefitFromCodePlacementOpt = true;
501 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
504 case ARMISD::Wrapper: return "ARMISD::Wrapper";
505 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
506 case ARMISD::CALL: return "ARMISD::CALL";
507 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
508 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
509 case ARMISD::tCALL: return "ARMISD::tCALL";
510 case ARMISD::BRCOND: return "ARMISD::BRCOND";
511 case ARMISD::BR_JT: return "ARMISD::BR_JT";
512 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
513 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
514 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
515 case ARMISD::CMP: return "ARMISD::CMP";
516 case ARMISD::CMPZ: return "ARMISD::CMPZ";
517 case ARMISD::CMPFP: return "ARMISD::CMPFP";
518 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
519 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
520 case ARMISD::CMOV: return "ARMISD::CMOV";
521 case ARMISD::CNEG: return "ARMISD::CNEG";
523 case ARMISD::RBIT: return "ARMISD::RBIT";
525 case ARMISD::FTOSI: return "ARMISD::FTOSI";
526 case ARMISD::FTOUI: return "ARMISD::FTOUI";
527 case ARMISD::SITOF: return "ARMISD::SITOF";
528 case ARMISD::UITOF: return "ARMISD::UITOF";
530 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
531 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
532 case ARMISD::RRX: return "ARMISD::RRX";
534 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
535 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
537 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
538 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
540 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
542 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
544 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
545 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
547 case ARMISD::VCEQ: return "ARMISD::VCEQ";
548 case ARMISD::VCGE: return "ARMISD::VCGE";
549 case ARMISD::VCGEU: return "ARMISD::VCGEU";
550 case ARMISD::VCGT: return "ARMISD::VCGT";
551 case ARMISD::VCGTU: return "ARMISD::VCGTU";
552 case ARMISD::VTST: return "ARMISD::VTST";
554 case ARMISD::VSHL: return "ARMISD::VSHL";
555 case ARMISD::VSHRs: return "ARMISD::VSHRs";
556 case ARMISD::VSHRu: return "ARMISD::VSHRu";
557 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
558 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
559 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
560 case ARMISD::VSHRN: return "ARMISD::VSHRN";
561 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
562 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
563 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
564 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
565 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
566 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
567 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
568 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
569 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
570 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
571 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
572 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
573 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
574 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
575 case ARMISD::VDUP: return "ARMISD::VDUP";
576 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
577 case ARMISD::VEXT: return "ARMISD::VEXT";
578 case ARMISD::VREV64: return "ARMISD::VREV64";
579 case ARMISD::VREV32: return "ARMISD::VREV32";
580 case ARMISD::VREV16: return "ARMISD::VREV16";
581 case ARMISD::VZIP: return "ARMISD::VZIP";
582 case ARMISD::VUZP: return "ARMISD::VUZP";
583 case ARMISD::VTRN: return "ARMISD::VTRN";
584 case ARMISD::FMAX: return "ARMISD::FMAX";
585 case ARMISD::FMIN: return "ARMISD::FMIN";
589 /// getRegClassFor - Return the register class that should be used for the
590 /// specified value type.
591 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
592 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
593 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
594 // load / store 4 to 8 consecutive D registers.
595 if (Subtarget->hasNEON()) {
596 if (VT == MVT::v4i64)
597 return ARM::QQPRRegisterClass;
598 else if (VT == MVT::v8i64)
599 return ARM::QQQQPRRegisterClass;
601 return TargetLowering::getRegClassFor(VT);
604 /// getFunctionAlignment - Return the Log2 alignment of this function.
605 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
606 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
609 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
610 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
611 EVT VT = N->getValueType(i);
612 if (VT.isFloatingPoint() || VT.isVector())
613 return Sched::Latency;
615 return Sched::RegPressure;
618 //===----------------------------------------------------------------------===//
620 //===----------------------------------------------------------------------===//
622 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
623 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
625 default: llvm_unreachable("Unknown condition code!");
626 case ISD::SETNE: return ARMCC::NE;
627 case ISD::SETEQ: return ARMCC::EQ;
628 case ISD::SETGT: return ARMCC::GT;
629 case ISD::SETGE: return ARMCC::GE;
630 case ISD::SETLT: return ARMCC::LT;
631 case ISD::SETLE: return ARMCC::LE;
632 case ISD::SETUGT: return ARMCC::HI;
633 case ISD::SETUGE: return ARMCC::HS;
634 case ISD::SETULT: return ARMCC::LO;
635 case ISD::SETULE: return ARMCC::LS;
639 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
640 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
641 ARMCC::CondCodes &CondCode2) {
642 CondCode2 = ARMCC::AL;
644 default: llvm_unreachable("Unknown FP condition!");
646 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
648 case ISD::SETOGT: CondCode = ARMCC::GT; break;
650 case ISD::SETOGE: CondCode = ARMCC::GE; break;
651 case ISD::SETOLT: CondCode = ARMCC::MI; break;
652 case ISD::SETOLE: CondCode = ARMCC::LS; break;
653 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
654 case ISD::SETO: CondCode = ARMCC::VC; break;
655 case ISD::SETUO: CondCode = ARMCC::VS; break;
656 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
657 case ISD::SETUGT: CondCode = ARMCC::HI; break;
658 case ISD::SETUGE: CondCode = ARMCC::PL; break;
660 case ISD::SETULT: CondCode = ARMCC::LT; break;
662 case ISD::SETULE: CondCode = ARMCC::LE; break;
664 case ISD::SETUNE: CondCode = ARMCC::NE; break;
668 //===----------------------------------------------------------------------===//
669 // Calling Convention Implementation
670 //===----------------------------------------------------------------------===//
672 #include "ARMGenCallingConv.inc"
674 // APCS f64 is in register pairs, possibly split to stack
675 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
676 CCValAssign::LocInfo &LocInfo,
677 CCState &State, bool CanFail) {
678 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
680 // Try to get the first register.
681 if (unsigned Reg = State.AllocateReg(RegList, 4))
682 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
684 // For the 2nd half of a v2f64, do not fail.
688 // Put the whole thing on the stack.
689 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
690 State.AllocateStack(8, 4),
695 // Try to get the second register.
696 if (unsigned Reg = State.AllocateReg(RegList, 4))
697 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
699 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
700 State.AllocateStack(4, 4),
705 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
706 CCValAssign::LocInfo &LocInfo,
707 ISD::ArgFlagsTy &ArgFlags,
709 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
711 if (LocVT == MVT::v2f64 &&
712 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
714 return true; // we handled it
717 // AAPCS f64 is in aligned register pairs
718 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
719 CCValAssign::LocInfo &LocInfo,
720 CCState &State, bool CanFail) {
721 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
722 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
724 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
726 // For the 2nd half of a v2f64, do not just fail.
730 // Put the whole thing on the stack.
731 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
732 State.AllocateStack(8, 8),
738 for (i = 0; i < 2; ++i)
739 if (HiRegList[i] == Reg)
742 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
743 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
748 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
749 CCValAssign::LocInfo &LocInfo,
750 ISD::ArgFlagsTy &ArgFlags,
752 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
754 if (LocVT == MVT::v2f64 &&
755 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
757 return true; // we handled it
760 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
761 CCValAssign::LocInfo &LocInfo, CCState &State) {
762 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
763 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
765 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
767 return false; // we didn't handle it
770 for (i = 0; i < 2; ++i)
771 if (HiRegList[i] == Reg)
774 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
775 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
780 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
781 CCValAssign::LocInfo &LocInfo,
782 ISD::ArgFlagsTy &ArgFlags,
784 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
786 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
788 return true; // we handled it
791 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
792 CCValAssign::LocInfo &LocInfo,
793 ISD::ArgFlagsTy &ArgFlags,
795 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
799 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
800 /// given CallingConvention value.
801 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
803 bool isVarArg) const {
806 llvm_unreachable("Unsupported calling convention");
808 case CallingConv::Fast:
809 // Use target triple & subtarget features to do actual dispatch.
810 if (Subtarget->isAAPCS_ABI()) {
811 if (Subtarget->hasVFP2() &&
812 FloatABIType == FloatABI::Hard && !isVarArg)
813 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
815 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
817 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
818 case CallingConv::ARM_AAPCS_VFP:
819 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
820 case CallingConv::ARM_AAPCS:
821 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
822 case CallingConv::ARM_APCS:
823 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
827 /// LowerCallResult - Lower the result values of a call into the
828 /// appropriate copies out of appropriate physical registers.
830 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
831 CallingConv::ID CallConv, bool isVarArg,
832 const SmallVectorImpl<ISD::InputArg> &Ins,
833 DebugLoc dl, SelectionDAG &DAG,
834 SmallVectorImpl<SDValue> &InVals) const {
836 // Assign locations to each value returned by this call.
837 SmallVector<CCValAssign, 16> RVLocs;
838 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
839 RVLocs, *DAG.getContext());
840 CCInfo.AnalyzeCallResult(Ins,
841 CCAssignFnForNode(CallConv, /* Return*/ true,
844 // Copy all of the result registers out of their specified physreg.
845 for (unsigned i = 0; i != RVLocs.size(); ++i) {
846 CCValAssign VA = RVLocs[i];
849 if (VA.needsCustom()) {
850 // Handle f64 or half of a v2f64.
851 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
853 Chain = Lo.getValue(1);
854 InFlag = Lo.getValue(2);
855 VA = RVLocs[++i]; // skip ahead to next loc
856 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
858 Chain = Hi.getValue(1);
859 InFlag = Hi.getValue(2);
860 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
862 if (VA.getLocVT() == MVT::v2f64) {
863 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
864 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
865 DAG.getConstant(0, MVT::i32));
867 VA = RVLocs[++i]; // skip ahead to next loc
868 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
869 Chain = Lo.getValue(1);
870 InFlag = Lo.getValue(2);
871 VA = RVLocs[++i]; // skip ahead to next loc
872 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
873 Chain = Hi.getValue(1);
874 InFlag = Hi.getValue(2);
875 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
876 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
877 DAG.getConstant(1, MVT::i32));
880 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
882 Chain = Val.getValue(1);
883 InFlag = Val.getValue(2);
886 switch (VA.getLocInfo()) {
887 default: llvm_unreachable("Unknown loc info!");
888 case CCValAssign::Full: break;
889 case CCValAssign::BCvt:
890 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
894 InVals.push_back(Val);
900 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
901 /// by "Src" to address "Dst" of size "Size". Alignment information is
902 /// specified by the specific parameter attribute. The copy will be passed as
903 /// a byval function parameter.
904 /// Sometimes what we are copying is the end of a larger object, the part that
905 /// does not fit in registers.
907 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
908 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
910 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
911 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
912 /*isVolatile=*/false, /*AlwaysInline=*/false,
916 /// LowerMemOpCallTo - Store the argument to the stack.
918 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
919 SDValue StackPtr, SDValue Arg,
920 DebugLoc dl, SelectionDAG &DAG,
921 const CCValAssign &VA,
922 ISD::ArgFlagsTy Flags) const {
923 unsigned LocMemOffset = VA.getLocMemOffset();
924 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
925 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
926 if (Flags.isByVal()) {
927 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
929 return DAG.getStore(Chain, dl, Arg, PtrOff,
930 PseudoSourceValue::getStack(), LocMemOffset,
934 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
935 SDValue Chain, SDValue &Arg,
936 RegsToPassVector &RegsToPass,
937 CCValAssign &VA, CCValAssign &NextVA,
939 SmallVector<SDValue, 8> &MemOpChains,
940 ISD::ArgFlagsTy Flags) const {
942 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
943 DAG.getVTList(MVT::i32, MVT::i32), Arg);
944 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
946 if (NextVA.isRegLoc())
947 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
949 assert(NextVA.isMemLoc());
950 if (StackPtr.getNode() == 0)
951 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
953 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
959 /// LowerCall - Lowering a call into a callseq_start <-
960 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
963 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
964 CallingConv::ID CallConv, bool isVarArg,
966 const SmallVectorImpl<ISD::OutputArg> &Outs,
967 const SmallVectorImpl<ISD::InputArg> &Ins,
968 DebugLoc dl, SelectionDAG &DAG,
969 SmallVectorImpl<SDValue> &InVals) const {
970 // ARM target does not yet support tail call optimization.
973 // Analyze operands of the call, assigning locations to each operand.
974 SmallVector<CCValAssign, 16> ArgLocs;
975 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
977 CCInfo.AnalyzeCallOperands(Outs,
978 CCAssignFnForNode(CallConv, /* Return*/ false,
981 // Get a count of how many bytes are to be pushed on the stack.
982 unsigned NumBytes = CCInfo.getNextStackOffset();
984 // Adjust the stack pointer for the new arguments...
985 // These operations are automatically eliminated by the prolog/epilog pass
986 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
988 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
990 RegsToPassVector RegsToPass;
991 SmallVector<SDValue, 8> MemOpChains;
993 // Walk the register/memloc assignments, inserting copies/loads. In the case
994 // of tail call optimization, arguments are handled later.
995 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
998 CCValAssign &VA = ArgLocs[i];
999 SDValue Arg = Outs[realArgIdx].Val;
1000 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1002 // Promote the value if needed.
1003 switch (VA.getLocInfo()) {
1004 default: llvm_unreachable("Unknown loc info!");
1005 case CCValAssign::Full: break;
1006 case CCValAssign::SExt:
1007 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1009 case CCValAssign::ZExt:
1010 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1012 case CCValAssign::AExt:
1013 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1015 case CCValAssign::BCvt:
1016 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1020 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1021 if (VA.needsCustom()) {
1022 if (VA.getLocVT() == MVT::v2f64) {
1023 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1024 DAG.getConstant(0, MVT::i32));
1025 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1026 DAG.getConstant(1, MVT::i32));
1028 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1029 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1031 VA = ArgLocs[++i]; // skip ahead to next loc
1032 if (VA.isRegLoc()) {
1033 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1034 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1036 assert(VA.isMemLoc());
1038 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1039 dl, DAG, VA, Flags));
1042 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1043 StackPtr, MemOpChains, Flags);
1045 } else if (VA.isRegLoc()) {
1046 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1048 assert(VA.isMemLoc());
1050 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1051 dl, DAG, VA, Flags));
1055 if (!MemOpChains.empty())
1056 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1057 &MemOpChains[0], MemOpChains.size());
1059 // Build a sequence of copy-to-reg nodes chained together with token chain
1060 // and flag operands which copy the outgoing args into the appropriate regs.
1062 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1063 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1064 RegsToPass[i].second, InFlag);
1065 InFlag = Chain.getValue(1);
1068 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1069 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1070 // node so that legalize doesn't hack it.
1071 bool isDirect = false;
1072 bool isARMFunc = false;
1073 bool isLocalARMFunc = false;
1074 MachineFunction &MF = DAG.getMachineFunction();
1075 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1077 if (EnableARMLongCalls) {
1078 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1079 && "long-calls with non-static relocation model!");
1080 // Handle a global address or an external symbol. If it's not one of
1081 // those, the target's already in a register, so we don't need to do
1083 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1084 const GlobalValue *GV = G->getGlobal();
1085 // Create a constant pool entry for the callee address
1086 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1087 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1090 // Get the address of the callee into a register
1091 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1092 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1093 Callee = DAG.getLoad(getPointerTy(), dl,
1094 DAG.getEntryNode(), CPAddr,
1095 PseudoSourceValue::getConstantPool(), 0,
1097 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1098 const char *Sym = S->getSymbol();
1100 // Create a constant pool entry for the callee address
1101 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1102 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1103 Sym, ARMPCLabelIndex, 0);
1104 // Get the address of the callee into a register
1105 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1106 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1107 Callee = DAG.getLoad(getPointerTy(), dl,
1108 DAG.getEntryNode(), CPAddr,
1109 PseudoSourceValue::getConstantPool(), 0,
1112 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1113 const GlobalValue *GV = G->getGlobal();
1115 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1116 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1117 getTargetMachine().getRelocationModel() != Reloc::Static;
1118 isARMFunc = !Subtarget->isThumb() || isStub;
1119 // ARM call to a local ARM function is predicable.
1120 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
1121 // tBX takes a register source operand.
1122 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1123 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1124 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1127 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1128 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1129 Callee = DAG.getLoad(getPointerTy(), dl,
1130 DAG.getEntryNode(), CPAddr,
1131 PseudoSourceValue::getConstantPool(), 0,
1133 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1134 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1135 getPointerTy(), Callee, PICLabel);
1137 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
1138 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1140 bool isStub = Subtarget->isTargetDarwin() &&
1141 getTargetMachine().getRelocationModel() != Reloc::Static;
1142 isARMFunc = !Subtarget->isThumb() || isStub;
1143 // tBX takes a register source operand.
1144 const char *Sym = S->getSymbol();
1145 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1146 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1147 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1148 Sym, ARMPCLabelIndex, 4);
1149 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1150 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1151 Callee = DAG.getLoad(getPointerTy(), dl,
1152 DAG.getEntryNode(), CPAddr,
1153 PseudoSourceValue::getConstantPool(), 0,
1155 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1156 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1157 getPointerTy(), Callee, PICLabel);
1159 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1162 // FIXME: handle tail calls differently.
1164 if (Subtarget->isThumb()) {
1165 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1166 CallOpc = ARMISD::CALL_NOLINK;
1168 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1170 CallOpc = (isDirect || Subtarget->hasV5TOps())
1171 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1172 : ARMISD::CALL_NOLINK;
1174 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1175 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1176 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1177 InFlag = Chain.getValue(1);
1180 std::vector<SDValue> Ops;
1181 Ops.push_back(Chain);
1182 Ops.push_back(Callee);
1184 // Add argument registers to the end of the list so that they are known live
1186 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1187 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1188 RegsToPass[i].second.getValueType()));
1190 if (InFlag.getNode())
1191 Ops.push_back(InFlag);
1192 // Returns a chain and a flag for retval copy to use.
1193 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1194 &Ops[0], Ops.size());
1195 InFlag = Chain.getValue(1);
1197 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1198 DAG.getIntPtrConstant(0, true), InFlag);
1200 InFlag = Chain.getValue(1);
1202 // Handle result values, copying them out of physregs into vregs that we
1204 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1209 ARMTargetLowering::LowerReturn(SDValue Chain,
1210 CallingConv::ID CallConv, bool isVarArg,
1211 const SmallVectorImpl<ISD::OutputArg> &Outs,
1212 DebugLoc dl, SelectionDAG &DAG) const {
1214 // CCValAssign - represent the assignment of the return value to a location.
1215 SmallVector<CCValAssign, 16> RVLocs;
1217 // CCState - Info about the registers and stack slots.
1218 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1221 // Analyze outgoing return values.
1222 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1225 // If this is the first return lowered for this function, add
1226 // the regs to the liveout set for the function.
1227 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1228 for (unsigned i = 0; i != RVLocs.size(); ++i)
1229 if (RVLocs[i].isRegLoc())
1230 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1235 // Copy the result values into the output registers.
1236 for (unsigned i = 0, realRVLocIdx = 0;
1238 ++i, ++realRVLocIdx) {
1239 CCValAssign &VA = RVLocs[i];
1240 assert(VA.isRegLoc() && "Can only return in registers!");
1242 SDValue Arg = Outs[realRVLocIdx].Val;
1244 switch (VA.getLocInfo()) {
1245 default: llvm_unreachable("Unknown loc info!");
1246 case CCValAssign::Full: break;
1247 case CCValAssign::BCvt:
1248 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1252 if (VA.needsCustom()) {
1253 if (VA.getLocVT() == MVT::v2f64) {
1254 // Extract the first half and return it in two registers.
1255 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1256 DAG.getConstant(0, MVT::i32));
1257 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1258 DAG.getVTList(MVT::i32, MVT::i32), Half);
1260 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1261 Flag = Chain.getValue(1);
1262 VA = RVLocs[++i]; // skip ahead to next loc
1263 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1264 HalfGPRs.getValue(1), Flag);
1265 Flag = Chain.getValue(1);
1266 VA = RVLocs[++i]; // skip ahead to next loc
1268 // Extract the 2nd half and fall through to handle it as an f64 value.
1269 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1270 DAG.getConstant(1, MVT::i32));
1272 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1274 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1275 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1276 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1277 Flag = Chain.getValue(1);
1278 VA = RVLocs[++i]; // skip ahead to next loc
1279 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1282 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1284 // Guarantee that all emitted copies are
1285 // stuck together, avoiding something bad.
1286 Flag = Chain.getValue(1);
1291 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1293 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1298 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1299 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1300 // one of the above mentioned nodes. It has to be wrapped because otherwise
1301 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1302 // be used to form addressing mode. These wrapped nodes will be selected
1304 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1305 EVT PtrVT = Op.getValueType();
1306 // FIXME there is no actual debug info here
1307 DebugLoc dl = Op.getDebugLoc();
1308 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1310 if (CP->isMachineConstantPoolEntry())
1311 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1312 CP->getAlignment());
1314 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1315 CP->getAlignment());
1316 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1319 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1320 SelectionDAG &DAG) const {
1321 MachineFunction &MF = DAG.getMachineFunction();
1322 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1323 unsigned ARMPCLabelIndex = 0;
1324 DebugLoc DL = Op.getDebugLoc();
1325 EVT PtrVT = getPointerTy();
1326 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1327 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1329 if (RelocM == Reloc::Static) {
1330 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1332 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1333 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1334 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1335 ARMCP::CPBlockAddress,
1337 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1339 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1340 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1341 PseudoSourceValue::getConstantPool(), 0,
1343 if (RelocM == Reloc::Static)
1345 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1346 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1349 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1351 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1352 SelectionDAG &DAG) const {
1353 DebugLoc dl = GA->getDebugLoc();
1354 EVT PtrVT = getPointerTy();
1355 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1356 MachineFunction &MF = DAG.getMachineFunction();
1357 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1358 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1359 ARMConstantPoolValue *CPV =
1360 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1361 ARMCP::CPValue, PCAdj, "tlsgd", true);
1362 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1363 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1364 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1365 PseudoSourceValue::getConstantPool(), 0,
1367 SDValue Chain = Argument.getValue(1);
1369 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1370 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1372 // call __tls_get_addr.
1375 Entry.Node = Argument;
1376 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1377 Args.push_back(Entry);
1378 // FIXME: is there useful debug info available here?
1379 std::pair<SDValue, SDValue> CallResult =
1380 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1381 false, false, false, false,
1382 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1383 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1384 return CallResult.first;
1387 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1388 // "local exec" model.
1390 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1391 SelectionDAG &DAG) const {
1392 const GlobalValue *GV = GA->getGlobal();
1393 DebugLoc dl = GA->getDebugLoc();
1395 SDValue Chain = DAG.getEntryNode();
1396 EVT PtrVT = getPointerTy();
1397 // Get the Thread Pointer
1398 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1400 if (GV->isDeclaration()) {
1401 MachineFunction &MF = DAG.getMachineFunction();
1402 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1403 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1404 // Initial exec model.
1405 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1406 ARMConstantPoolValue *CPV =
1407 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1408 ARMCP::CPValue, PCAdj, "gottpoff", true);
1409 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1410 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1411 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1412 PseudoSourceValue::getConstantPool(), 0,
1414 Chain = Offset.getValue(1);
1416 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1417 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1419 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1420 PseudoSourceValue::getConstantPool(), 0,
1424 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1425 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1426 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1427 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1428 PseudoSourceValue::getConstantPool(), 0,
1432 // The address of the thread local variable is the add of the thread
1433 // pointer with the offset of the variable.
1434 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1438 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1439 // TODO: implement the "local dynamic" model
1440 assert(Subtarget->isTargetELF() &&
1441 "TLS not implemented for non-ELF targets");
1442 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1443 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1444 // otherwise use the "Local Exec" TLS Model
1445 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1446 return LowerToTLSGeneralDynamicModel(GA, DAG);
1448 return LowerToTLSExecModels(GA, DAG);
1451 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1452 SelectionDAG &DAG) const {
1453 EVT PtrVT = getPointerTy();
1454 DebugLoc dl = Op.getDebugLoc();
1455 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1456 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1457 if (RelocM == Reloc::PIC_) {
1458 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1459 ARMConstantPoolValue *CPV =
1460 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1461 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1462 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1463 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1465 PseudoSourceValue::getConstantPool(), 0,
1467 SDValue Chain = Result.getValue(1);
1468 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1469 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1471 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1472 PseudoSourceValue::getGOT(), 0,
1476 // If we have T2 ops, we can materialize the address directly via movt/movw
1477 // pair. This is always cheaper.
1478 if (Subtarget->useMovt()) {
1479 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1480 DAG.getTargetGlobalAddress(GV, PtrVT));
1482 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1483 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1484 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1485 PseudoSourceValue::getConstantPool(), 0,
1491 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1492 SelectionDAG &DAG) const {
1493 MachineFunction &MF = DAG.getMachineFunction();
1494 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1495 unsigned ARMPCLabelIndex = 0;
1496 EVT PtrVT = getPointerTy();
1497 DebugLoc dl = Op.getDebugLoc();
1498 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1499 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1501 if (RelocM == Reloc::Static)
1502 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1504 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1505 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1506 ARMConstantPoolValue *CPV =
1507 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1508 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1510 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1512 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1513 PseudoSourceValue::getConstantPool(), 0,
1515 SDValue Chain = Result.getValue(1);
1517 if (RelocM == Reloc::PIC_) {
1518 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1519 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1522 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1523 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1524 PseudoSourceValue::getGOT(), 0,
1530 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1531 SelectionDAG &DAG) const {
1532 assert(Subtarget->isTargetELF() &&
1533 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1534 MachineFunction &MF = DAG.getMachineFunction();
1535 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1536 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1537 EVT PtrVT = getPointerTy();
1538 DebugLoc dl = Op.getDebugLoc();
1539 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1540 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1541 "_GLOBAL_OFFSET_TABLE_",
1542 ARMPCLabelIndex, PCAdj);
1543 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1544 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1545 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1546 PseudoSourceValue::getConstantPool(), 0,
1548 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1549 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1553 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1554 DebugLoc dl = Op.getDebugLoc();
1555 SDValue Val = Subtarget->isThumb() ?
1556 DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::SP, MVT::i32) :
1557 DAG.getConstant(0, MVT::i32);
1558 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1559 Op.getOperand(1), Val);
1563 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1564 DebugLoc dl = Op.getDebugLoc();
1565 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1566 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1570 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1571 const ARMSubtarget *Subtarget)
1573 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1574 DebugLoc dl = Op.getDebugLoc();
1576 default: return SDValue(); // Don't custom lower most intrinsics.
1577 case Intrinsic::arm_thread_pointer: {
1578 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1579 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1581 case Intrinsic::eh_sjlj_lsda: {
1582 MachineFunction &MF = DAG.getMachineFunction();
1583 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1584 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1585 EVT PtrVT = getPointerTy();
1586 DebugLoc dl = Op.getDebugLoc();
1587 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1589 unsigned PCAdj = (RelocM != Reloc::PIC_)
1590 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1591 ARMConstantPoolValue *CPV =
1592 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1593 ARMCP::CPLSDA, PCAdj);
1594 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1595 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1597 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1598 PseudoSourceValue::getConstantPool(), 0,
1600 SDValue Chain = Result.getValue(1);
1602 if (RelocM == Reloc::PIC_) {
1603 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1604 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1611 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1612 const ARMSubtarget *Subtarget) {
1613 DebugLoc dl = Op.getDebugLoc();
1614 SDValue Op5 = Op.getOperand(5);
1616 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1617 if (isDeviceBarrier) {
1618 if (Subtarget->hasV7Ops())
1619 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0));
1621 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0),
1622 DAG.getConstant(0, MVT::i32));
1624 if (Subtarget->hasV7Ops())
1625 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
1627 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
1628 DAG.getConstant(0, MVT::i32));
1633 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
1634 MachineFunction &MF = DAG.getMachineFunction();
1635 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
1637 // vastart just stores the address of the VarArgsFrameIndex slot into the
1638 // memory location argument.
1639 DebugLoc dl = Op.getDebugLoc();
1640 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1641 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1642 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1643 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1648 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1649 SelectionDAG &DAG) const {
1650 SDNode *Node = Op.getNode();
1651 DebugLoc dl = Node->getDebugLoc();
1652 EVT VT = Node->getValueType(0);
1653 SDValue Chain = Op.getOperand(0);
1654 SDValue Size = Op.getOperand(1);
1655 SDValue Align = Op.getOperand(2);
1657 // Chain the dynamic stack allocation so that it doesn't modify the stack
1658 // pointer when other instructions are using the stack.
1659 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1661 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1662 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1663 if (AlignVal > StackAlign)
1664 // Do this now since selection pass cannot introduce new target
1665 // independent node.
1666 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1668 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1669 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1670 // do even more horrible hack later.
1671 MachineFunction &MF = DAG.getMachineFunction();
1672 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1673 if (AFI->isThumb1OnlyFunction()) {
1675 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1677 uint32_t Val = C->getZExtValue();
1678 if (Val <= 508 && ((Val & 3) == 0))
1682 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1685 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1686 SDValue Ops1[] = { Chain, Size, Align };
1687 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1688 Chain = Res.getValue(1);
1689 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1690 DAG.getIntPtrConstant(0, true), SDValue());
1691 SDValue Ops2[] = { Res, Chain };
1692 return DAG.getMergeValues(Ops2, 2, dl);
1696 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1697 SDValue &Root, SelectionDAG &DAG,
1698 DebugLoc dl) const {
1699 MachineFunction &MF = DAG.getMachineFunction();
1700 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1702 TargetRegisterClass *RC;
1703 if (AFI->isThumb1OnlyFunction())
1704 RC = ARM::tGPRRegisterClass;
1706 RC = ARM::GPRRegisterClass;
1708 // Transform the arguments stored in physical registers into virtual ones.
1709 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1710 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1713 if (NextVA.isMemLoc()) {
1714 MachineFrameInfo *MFI = MF.getFrameInfo();
1715 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true, false);
1717 // Create load node to retrieve arguments from the stack.
1718 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1719 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
1720 PseudoSourceValue::getFixedStack(FI), 0,
1723 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1724 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1727 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
1731 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1732 CallingConv::ID CallConv, bool isVarArg,
1733 const SmallVectorImpl<ISD::InputArg>
1735 DebugLoc dl, SelectionDAG &DAG,
1736 SmallVectorImpl<SDValue> &InVals)
1739 MachineFunction &MF = DAG.getMachineFunction();
1740 MachineFrameInfo *MFI = MF.getFrameInfo();
1742 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1744 // Assign locations to all of the incoming arguments.
1745 SmallVector<CCValAssign, 16> ArgLocs;
1746 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1748 CCInfo.AnalyzeFormalArguments(Ins,
1749 CCAssignFnForNode(CallConv, /* Return*/ false,
1752 SmallVector<SDValue, 16> ArgValues;
1754 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1755 CCValAssign &VA = ArgLocs[i];
1757 // Arguments stored in registers.
1758 if (VA.isRegLoc()) {
1759 EVT RegVT = VA.getLocVT();
1762 if (VA.needsCustom()) {
1763 // f64 and vector types are split up into multiple registers or
1764 // combinations of registers and stack slots.
1765 if (VA.getLocVT() == MVT::v2f64) {
1766 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1768 VA = ArgLocs[++i]; // skip ahead to next loc
1770 if (VA.isMemLoc()) {
1771 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(),
1773 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1774 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
1775 PseudoSourceValue::getFixedStack(FI), 0,
1778 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1781 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1782 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1783 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1784 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1785 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1787 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1790 TargetRegisterClass *RC;
1792 if (RegVT == MVT::f32)
1793 RC = ARM::SPRRegisterClass;
1794 else if (RegVT == MVT::f64)
1795 RC = ARM::DPRRegisterClass;
1796 else if (RegVT == MVT::v2f64)
1797 RC = ARM::QPRRegisterClass;
1798 else if (RegVT == MVT::i32)
1799 RC = (AFI->isThumb1OnlyFunction() ?
1800 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1802 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1804 // Transform the arguments in physical registers into virtual ones.
1805 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1806 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1809 // If this is an 8 or 16-bit value, it is really passed promoted
1810 // to 32 bits. Insert an assert[sz]ext to capture this, then
1811 // truncate to the right size.
1812 switch (VA.getLocInfo()) {
1813 default: llvm_unreachable("Unknown loc info!");
1814 case CCValAssign::Full: break;
1815 case CCValAssign::BCvt:
1816 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1818 case CCValAssign::SExt:
1819 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1820 DAG.getValueType(VA.getValVT()));
1821 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1823 case CCValAssign::ZExt:
1824 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1825 DAG.getValueType(VA.getValVT()));
1826 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1830 InVals.push_back(ArgValue);
1832 } else { // VA.isRegLoc()
1835 assert(VA.isMemLoc());
1836 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1838 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1839 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1842 // Create load nodes to retrieve arguments from the stack.
1843 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1844 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1845 PseudoSourceValue::getFixedStack(FI), 0,
1852 static const unsigned GPRArgRegs[] = {
1853 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1856 unsigned NumGPRs = CCInfo.getFirstUnallocated
1857 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1859 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1860 unsigned VARegSize = (4 - NumGPRs) * 4;
1861 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1862 unsigned ArgOffset = CCInfo.getNextStackOffset();
1863 if (VARegSaveSize) {
1864 // If this function is vararg, store any remaining integer argument regs
1865 // to their spots on the stack so that they may be loaded by deferencing
1866 // the result of va_next.
1867 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1868 AFI->setVarArgsFrameIndex(
1869 MFI->CreateFixedObject(VARegSaveSize,
1870 ArgOffset + VARegSaveSize - VARegSize,
1872 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
1875 SmallVector<SDValue, 4> MemOps;
1876 for (; NumGPRs < 4; ++NumGPRs) {
1877 TargetRegisterClass *RC;
1878 if (AFI->isThumb1OnlyFunction())
1879 RC = ARM::tGPRRegisterClass;
1881 RC = ARM::GPRRegisterClass;
1883 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1884 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1886 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1887 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()), 0,
1889 MemOps.push_back(Store);
1890 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1891 DAG.getConstant(4, getPointerTy()));
1893 if (!MemOps.empty())
1894 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1895 &MemOps[0], MemOps.size());
1897 // This will point to the next argument passed via stack.
1898 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset,
1905 /// isFloatingPointZero - Return true if this is +0.0.
1906 static bool isFloatingPointZero(SDValue Op) {
1907 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1908 return CFP->getValueAPF().isPosZero();
1909 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1910 // Maybe this has already been legalized into the constant pool?
1911 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1912 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1913 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1914 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1915 return CFP->getValueAPF().isPosZero();
1921 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1922 /// the given operands.
1924 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1925 SDValue &ARMCC, SelectionDAG &DAG,
1926 DebugLoc dl) const {
1927 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1928 unsigned C = RHSC->getZExtValue();
1929 if (!isLegalICmpImmediate(C)) {
1930 // Constant does not fit, try adjusting it by one?
1935 if (isLegalICmpImmediate(C-1)) {
1936 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1937 RHS = DAG.getConstant(C-1, MVT::i32);
1942 if (C > 0 && isLegalICmpImmediate(C-1)) {
1943 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1944 RHS = DAG.getConstant(C-1, MVT::i32);
1949 if (isLegalICmpImmediate(C+1)) {
1950 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1951 RHS = DAG.getConstant(C+1, MVT::i32);
1956 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
1957 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1958 RHS = DAG.getConstant(C+1, MVT::i32);
1965 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1966 ARMISD::NodeType CompareType;
1969 CompareType = ARMISD::CMP;
1974 CompareType = ARMISD::CMPZ;
1977 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1978 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1981 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1982 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1985 if (!isFloatingPointZero(RHS))
1986 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1988 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1989 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1992 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
1993 EVT VT = Op.getValueType();
1994 SDValue LHS = Op.getOperand(0);
1995 SDValue RHS = Op.getOperand(1);
1996 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1997 SDValue TrueVal = Op.getOperand(2);
1998 SDValue FalseVal = Op.getOperand(3);
1999 DebugLoc dl = Op.getDebugLoc();
2001 if (LHS.getValueType() == MVT::i32) {
2003 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2004 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2005 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
2008 ARMCC::CondCodes CondCode, CondCode2;
2009 FPCCToARMCC(CC, CondCode, CondCode2);
2011 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2012 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2013 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2014 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2016 if (CondCode2 != ARMCC::AL) {
2017 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
2018 // FIXME: Needs another CMP because flag can have but one use.
2019 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2020 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2021 Result, TrueVal, ARMCC2, CCR, Cmp2);
2026 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2027 SDValue Chain = Op.getOperand(0);
2028 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2029 SDValue LHS = Op.getOperand(2);
2030 SDValue RHS = Op.getOperand(3);
2031 SDValue Dest = Op.getOperand(4);
2032 DebugLoc dl = Op.getDebugLoc();
2034 if (LHS.getValueType() == MVT::i32) {
2036 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2037 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2038 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2039 Chain, Dest, ARMCC, CCR,Cmp);
2042 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2043 ARMCC::CondCodes CondCode, CondCode2;
2044 FPCCToARMCC(CC, CondCode, CondCode2);
2046 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2047 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2048 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2049 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2050 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
2051 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2052 if (CondCode2 != ARMCC::AL) {
2053 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
2054 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
2055 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2060 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2061 SDValue Chain = Op.getOperand(0);
2062 SDValue Table = Op.getOperand(1);
2063 SDValue Index = Op.getOperand(2);
2064 DebugLoc dl = Op.getDebugLoc();
2066 EVT PTy = getPointerTy();
2067 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2068 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2069 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2070 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2071 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2072 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2073 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2074 if (Subtarget->isThumb2()) {
2075 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2076 // which does another jump to the destination. This also makes it easier
2077 // to translate it to TBB / TBH later.
2078 // FIXME: This might not work if the function is extremely large.
2079 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2080 Addr, Op.getOperand(2), JTI, UId);
2082 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2083 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2084 PseudoSourceValue::getJumpTable(), 0,
2086 Chain = Addr.getValue(1);
2087 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2088 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2090 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2091 PseudoSourceValue::getJumpTable(), 0, false, false, 0);
2092 Chain = Addr.getValue(1);
2093 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2097 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2098 DebugLoc dl = Op.getDebugLoc();
2101 switch (Op.getOpcode()) {
2103 assert(0 && "Invalid opcode!");
2104 case ISD::FP_TO_SINT:
2105 Opc = ARMISD::FTOSI;
2107 case ISD::FP_TO_UINT:
2108 Opc = ARMISD::FTOUI;
2111 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2112 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2115 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2116 EVT VT = Op.getValueType();
2117 DebugLoc dl = Op.getDebugLoc();
2120 switch (Op.getOpcode()) {
2122 assert(0 && "Invalid opcode!");
2123 case ISD::SINT_TO_FP:
2124 Opc = ARMISD::SITOF;
2126 case ISD::UINT_TO_FP:
2127 Opc = ARMISD::UITOF;
2131 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2132 return DAG.getNode(Opc, dl, VT, Op);
2135 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
2136 // Implement fcopysign with a fabs and a conditional fneg.
2137 SDValue Tmp0 = Op.getOperand(0);
2138 SDValue Tmp1 = Op.getOperand(1);
2139 DebugLoc dl = Op.getDebugLoc();
2140 EVT VT = Op.getValueType();
2141 EVT SrcVT = Tmp1.getValueType();
2142 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2143 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
2144 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
2145 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2146 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
2149 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2150 MachineFunction &MF = DAG.getMachineFunction();
2151 MachineFrameInfo *MFI = MF.getFrameInfo();
2152 MFI->setReturnAddressIsTaken(true);
2154 EVT VT = Op.getValueType();
2155 DebugLoc dl = Op.getDebugLoc();
2156 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2158 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2159 SDValue Offset = DAG.getConstant(4, MVT::i32);
2160 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2161 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2162 NULL, 0, false, false, 0);
2165 // Return LR, which contains the return address. Mark it an implicit live-in.
2166 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
2167 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2170 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2171 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2172 MFI->setFrameAddressIsTaken(true);
2174 EVT VT = Op.getValueType();
2175 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2176 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2177 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2178 ? ARM::R7 : ARM::R11;
2179 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2181 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
2186 SDValue ARMTargetLowering::LowerSTACKADDR(SDValue Op, SelectionDAG &DAG) const {
2187 EVT VT = Op.getValueType();
2188 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2189 SDValue StackAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::SP, VT);
2193 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2194 /// expand a bit convert where either the source or destination type is i64 to
2195 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2196 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2197 /// vectors), since the legalizer won't know what to do with that.
2198 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2199 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2200 DebugLoc dl = N->getDebugLoc();
2201 SDValue Op = N->getOperand(0);
2203 // This function is only supposed to be called for i64 types, either as the
2204 // source or destination of the bit convert.
2205 EVT SrcVT = Op.getValueType();
2206 EVT DstVT = N->getValueType(0);
2207 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2208 "ExpandBIT_CONVERT called for non-i64 type");
2210 // Turn i64->f64 into VMOVDRR.
2211 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2212 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2213 DAG.getConstant(0, MVT::i32));
2214 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2215 DAG.getConstant(1, MVT::i32));
2216 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2219 // Turn f64->i64 into VMOVRRD.
2220 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2221 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2222 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2223 // Merge the pieces into a single i64 value.
2224 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2230 /// getZeroVector - Returns a vector of specified type with all zero elements.
2232 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2233 assert(VT.isVector() && "Expected a vector type");
2235 // Zero vectors are used to represent vector negation and in those cases
2236 // will be implemented with the NEON VNEG instruction. However, VNEG does
2237 // not support i64 elements, so sometimes the zero vectors will need to be
2238 // explicitly constructed. For those cases, and potentially other uses in
2239 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
2240 // to their dest type. This ensures they get CSE'd.
2242 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2243 SmallVector<SDValue, 8> Ops;
2246 if (VT.getSizeInBits() == 64) {
2247 Ops.assign(8, Cst); TVT = MVT::v8i8;
2249 Ops.assign(16, Cst); TVT = MVT::v16i8;
2251 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2253 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2256 /// getOnesVector - Returns a vector of specified type with all bits set.
2258 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2259 assert(VT.isVector() && "Expected a vector type");
2261 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their
2262 // dest type. This ensures they get CSE'd.
2264 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2265 SmallVector<SDValue, 8> Ops;
2268 if (VT.getSizeInBits() == 64) {
2269 Ops.assign(8, Cst); TVT = MVT::v8i8;
2271 Ops.assign(16, Cst); TVT = MVT::v16i8;
2273 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2275 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2278 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2279 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2280 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2281 SelectionDAG &DAG) const {
2282 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2283 EVT VT = Op.getValueType();
2284 unsigned VTBits = VT.getSizeInBits();
2285 DebugLoc dl = Op.getDebugLoc();
2286 SDValue ShOpLo = Op.getOperand(0);
2287 SDValue ShOpHi = Op.getOperand(1);
2288 SDValue ShAmt = Op.getOperand(2);
2290 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2292 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2294 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2295 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2296 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2297 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2298 DAG.getConstant(VTBits, MVT::i32));
2299 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2300 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2301 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2303 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2304 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2306 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2307 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
2310 SDValue Ops[2] = { Lo, Hi };
2311 return DAG.getMergeValues(Ops, 2, dl);
2314 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2315 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2316 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2317 SelectionDAG &DAG) const {
2318 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2319 EVT VT = Op.getValueType();
2320 unsigned VTBits = VT.getSizeInBits();
2321 DebugLoc dl = Op.getDebugLoc();
2322 SDValue ShOpLo = Op.getOperand(0);
2323 SDValue ShOpHi = Op.getOperand(1);
2324 SDValue ShAmt = Op.getOperand(2);
2327 assert(Op.getOpcode() == ISD::SHL_PARTS);
2328 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2329 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2330 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2331 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2332 DAG.getConstant(VTBits, MVT::i32));
2333 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2334 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2336 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2337 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2338 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2340 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2341 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
2344 SDValue Ops[2] = { Lo, Hi };
2345 return DAG.getMergeValues(Ops, 2, dl);
2348 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2349 const ARMSubtarget *ST) {
2350 EVT VT = N->getValueType(0);
2351 DebugLoc dl = N->getDebugLoc();
2353 if (!ST->hasV6T2Ops())
2356 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2357 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2360 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2361 const ARMSubtarget *ST) {
2362 EVT VT = N->getValueType(0);
2363 DebugLoc dl = N->getDebugLoc();
2365 // Lower vector shifts on NEON to use VSHL.
2366 if (VT.isVector()) {
2367 assert(ST->hasNEON() && "unexpected vector shift");
2369 // Left shifts translate directly to the vshiftu intrinsic.
2370 if (N->getOpcode() == ISD::SHL)
2371 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2372 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2373 N->getOperand(0), N->getOperand(1));
2375 assert((N->getOpcode() == ISD::SRA ||
2376 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2378 // NEON uses the same intrinsics for both left and right shifts. For
2379 // right shifts, the shift amounts are negative, so negate the vector of
2381 EVT ShiftVT = N->getOperand(1).getValueType();
2382 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2383 getZeroVector(ShiftVT, DAG, dl),
2385 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2386 Intrinsic::arm_neon_vshifts :
2387 Intrinsic::arm_neon_vshiftu);
2388 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2389 DAG.getConstant(vshiftInt, MVT::i32),
2390 N->getOperand(0), NegatedCount);
2393 // We can get here for a node like i32 = ISD::SHL i32, i64
2397 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2398 "Unknown shift to lower!");
2400 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2401 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2402 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2405 // If we are in thumb mode, we don't have RRX.
2406 if (ST->isThumb1Only()) return SDValue();
2408 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2409 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2410 DAG.getConstant(0, MVT::i32));
2411 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2412 DAG.getConstant(1, MVT::i32));
2414 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2415 // captures the result into a carry flag.
2416 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2417 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2419 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2420 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2422 // Merge the pieces into a single i64 value.
2423 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2426 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2427 SDValue TmpOp0, TmpOp1;
2428 bool Invert = false;
2432 SDValue Op0 = Op.getOperand(0);
2433 SDValue Op1 = Op.getOperand(1);
2434 SDValue CC = Op.getOperand(2);
2435 EVT VT = Op.getValueType();
2436 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2437 DebugLoc dl = Op.getDebugLoc();
2439 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2440 switch (SetCCOpcode) {
2441 default: llvm_unreachable("Illegal FP comparison"); break;
2443 case ISD::SETNE: Invert = true; // Fallthrough
2445 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2447 case ISD::SETLT: Swap = true; // Fallthrough
2449 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2451 case ISD::SETLE: Swap = true; // Fallthrough
2453 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2454 case ISD::SETUGE: Swap = true; // Fallthrough
2455 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2456 case ISD::SETUGT: Swap = true; // Fallthrough
2457 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2458 case ISD::SETUEQ: Invert = true; // Fallthrough
2460 // Expand this to (OLT | OGT).
2464 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2465 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2467 case ISD::SETUO: Invert = true; // Fallthrough
2469 // Expand this to (OLT | OGE).
2473 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2474 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2478 // Integer comparisons.
2479 switch (SetCCOpcode) {
2480 default: llvm_unreachable("Illegal integer comparison"); break;
2481 case ISD::SETNE: Invert = true;
2482 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2483 case ISD::SETLT: Swap = true;
2484 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2485 case ISD::SETLE: Swap = true;
2486 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2487 case ISD::SETULT: Swap = true;
2488 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2489 case ISD::SETULE: Swap = true;
2490 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2493 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2494 if (Opc == ARMISD::VCEQ) {
2497 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2499 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2502 // Ignore bitconvert.
2503 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2504 AndOp = AndOp.getOperand(0);
2506 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2508 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2509 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2516 std::swap(Op0, Op1);
2518 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2521 Result = DAG.getNOT(dl, Result, VT);
2526 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2527 /// VMOV instruction, and if so, return the constant being splatted.
2528 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2529 unsigned SplatBitSize, SelectionDAG &DAG) {
2530 switch (SplatBitSize) {
2532 // Any 1-byte value is OK.
2533 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2534 return DAG.getTargetConstant(SplatBits, MVT::i8);
2537 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2538 if ((SplatBits & ~0xff) == 0 ||
2539 (SplatBits & ~0xff00) == 0)
2540 return DAG.getTargetConstant(SplatBits, MVT::i16);
2544 // NEON's 32-bit VMOV supports splat values where:
2545 // * only one byte is nonzero, or
2546 // * the least significant byte is 0xff and the second byte is nonzero, or
2547 // * the least significant 2 bytes are 0xff and the third is nonzero.
2548 if ((SplatBits & ~0xff) == 0 ||
2549 (SplatBits & ~0xff00) == 0 ||
2550 (SplatBits & ~0xff0000) == 0 ||
2551 (SplatBits & ~0xff000000) == 0)
2552 return DAG.getTargetConstant(SplatBits, MVT::i32);
2554 if ((SplatBits & ~0xffff) == 0 &&
2555 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2556 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2558 if ((SplatBits & ~0xffffff) == 0 &&
2559 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2560 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2562 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2563 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2564 // VMOV.I32. A (very) minor optimization would be to replicate the value
2565 // and fall through here to test for a valid 64-bit splat. But, then the
2566 // caller would also need to check and handle the change in size.
2570 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2571 uint64_t BitMask = 0xff;
2573 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2574 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2576 else if ((SplatBits & BitMask) != 0)
2580 return DAG.getTargetConstant(Val, MVT::i64);
2584 llvm_unreachable("unexpected size for isVMOVSplat");
2591 /// getVMOVImm - If this is a build_vector of constants which can be
2592 /// formed by using a VMOV instruction of the specified element size,
2593 /// return the constant being splatted. The ByteSize field indicates the
2594 /// number of bytes of each element [1248].
2595 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2596 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2597 APInt SplatBits, SplatUndef;
2598 unsigned SplatBitSize;
2600 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2601 HasAnyUndefs, ByteSize * 8))
2604 if (SplatBitSize > ByteSize * 8)
2607 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2611 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2612 bool &ReverseVEXT, unsigned &Imm) {
2613 unsigned NumElts = VT.getVectorNumElements();
2614 ReverseVEXT = false;
2617 // If this is a VEXT shuffle, the immediate value is the index of the first
2618 // element. The other shuffle indices must be the successive elements after
2620 unsigned ExpectedElt = Imm;
2621 for (unsigned i = 1; i < NumElts; ++i) {
2622 // Increment the expected index. If it wraps around, it may still be
2623 // a VEXT but the source vectors must be swapped.
2625 if (ExpectedElt == NumElts * 2) {
2630 if (ExpectedElt != static_cast<unsigned>(M[i]))
2634 // Adjust the index value if the source operands will be swapped.
2641 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2642 /// instruction with the specified blocksize. (The order of the elements
2643 /// within each block of the vector is reversed.)
2644 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2645 unsigned BlockSize) {
2646 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2647 "Only possible block sizes for VREV are: 16, 32, 64");
2649 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2653 unsigned NumElts = VT.getVectorNumElements();
2654 unsigned BlockElts = M[0] + 1;
2656 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2659 for (unsigned i = 0; i < NumElts; ++i) {
2660 if ((unsigned) M[i] !=
2661 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2668 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
2669 unsigned &WhichResult) {
2670 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2674 unsigned NumElts = VT.getVectorNumElements();
2675 WhichResult = (M[0] == 0 ? 0 : 1);
2676 for (unsigned i = 0; i < NumElts; i += 2) {
2677 if ((unsigned) M[i] != i + WhichResult ||
2678 (unsigned) M[i+1] != i + NumElts + WhichResult)
2684 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
2685 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2686 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
2687 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2688 unsigned &WhichResult) {
2689 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2693 unsigned NumElts = VT.getVectorNumElements();
2694 WhichResult = (M[0] == 0 ? 0 : 1);
2695 for (unsigned i = 0; i < NumElts; i += 2) {
2696 if ((unsigned) M[i] != i + WhichResult ||
2697 (unsigned) M[i+1] != i + WhichResult)
2703 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
2704 unsigned &WhichResult) {
2705 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2709 unsigned NumElts = VT.getVectorNumElements();
2710 WhichResult = (M[0] == 0 ? 0 : 1);
2711 for (unsigned i = 0; i != NumElts; ++i) {
2712 if ((unsigned) M[i] != 2 * i + WhichResult)
2716 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2717 if (VT.is64BitVector() && EltSz == 32)
2723 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
2724 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2725 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
2726 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2727 unsigned &WhichResult) {
2728 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2732 unsigned Half = VT.getVectorNumElements() / 2;
2733 WhichResult = (M[0] == 0 ? 0 : 1);
2734 for (unsigned j = 0; j != 2; ++j) {
2735 unsigned Idx = WhichResult;
2736 for (unsigned i = 0; i != Half; ++i) {
2737 if ((unsigned) M[i + j * Half] != Idx)
2743 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2744 if (VT.is64BitVector() && EltSz == 32)
2750 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
2751 unsigned &WhichResult) {
2752 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2756 unsigned NumElts = VT.getVectorNumElements();
2757 WhichResult = (M[0] == 0 ? 0 : 1);
2758 unsigned Idx = WhichResult * NumElts / 2;
2759 for (unsigned i = 0; i != NumElts; i += 2) {
2760 if ((unsigned) M[i] != Idx ||
2761 (unsigned) M[i+1] != Idx + NumElts)
2766 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2767 if (VT.is64BitVector() && EltSz == 32)
2773 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
2774 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2775 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
2776 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2777 unsigned &WhichResult) {
2778 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2782 unsigned NumElts = VT.getVectorNumElements();
2783 WhichResult = (M[0] == 0 ? 0 : 1);
2784 unsigned Idx = WhichResult * NumElts / 2;
2785 for (unsigned i = 0; i != NumElts; i += 2) {
2786 if ((unsigned) M[i] != Idx ||
2787 (unsigned) M[i+1] != Idx)
2792 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2793 if (VT.is64BitVector() && EltSz == 32)
2800 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2801 // Canonicalize all-zeros and all-ones vectors.
2802 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
2803 if (ConstVal->isNullValue())
2804 return getZeroVector(VT, DAG, dl);
2805 if (ConstVal->isAllOnesValue())
2806 return getOnesVector(VT, DAG, dl);
2809 if (VT.is64BitVector()) {
2810 switch (Val.getValueType().getSizeInBits()) {
2811 case 8: CanonicalVT = MVT::v8i8; break;
2812 case 16: CanonicalVT = MVT::v4i16; break;
2813 case 32: CanonicalVT = MVT::v2i32; break;
2814 case 64: CanonicalVT = MVT::v1i64; break;
2815 default: llvm_unreachable("unexpected splat element type"); break;
2818 assert(VT.is128BitVector() && "unknown splat vector size");
2819 switch (Val.getValueType().getSizeInBits()) {
2820 case 8: CanonicalVT = MVT::v16i8; break;
2821 case 16: CanonicalVT = MVT::v8i16; break;
2822 case 32: CanonicalVT = MVT::v4i32; break;
2823 case 64: CanonicalVT = MVT::v2i64; break;
2824 default: llvm_unreachable("unexpected splat element type"); break;
2828 // Build a canonical splat for this value.
2829 SmallVector<SDValue, 8> Ops;
2830 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2831 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2833 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2836 // If this is a case we can't handle, return null and let the default
2837 // expansion code take care of it.
2838 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2839 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2840 DebugLoc dl = Op.getDebugLoc();
2841 EVT VT = Op.getValueType();
2843 APInt SplatBits, SplatUndef;
2844 unsigned SplatBitSize;
2846 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2847 if (SplatBitSize <= 64) {
2848 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2849 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2851 return BuildSplat(Val, VT, DAG, dl);
2855 // Scan through the operands to see if only one value is used.
2856 unsigned NumElts = VT.getVectorNumElements();
2857 bool isOnlyLowElement = true;
2858 bool usesOnlyOneValue = true;
2859 bool isConstant = true;
2861 for (unsigned i = 0; i < NumElts; ++i) {
2862 SDValue V = Op.getOperand(i);
2863 if (V.getOpcode() == ISD::UNDEF)
2866 isOnlyLowElement = false;
2867 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
2870 if (!Value.getNode())
2872 else if (V != Value)
2873 usesOnlyOneValue = false;
2876 if (!Value.getNode())
2877 return DAG.getUNDEF(VT);
2879 if (isOnlyLowElement)
2880 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
2882 // If all elements are constants, fall back to the default expansion, which
2883 // will generate a load from the constant pool.
2887 // Use VDUP for non-constant splats.
2888 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
2889 if (usesOnlyOneValue && EltSize <= 32)
2890 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
2892 // Vectors with 32- or 64-bit elements can be built by directly assigning
2893 // the subregisters.
2894 if (EltSize >= 32) {
2895 // Do the expansion with floating-point types, since that is what the VFP
2896 // registers are defined to use, and since i64 is not legal.
2897 EVT EltVT = EVT::getFloatingPointVT(EltSize);
2898 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
2899 SDValue Val = DAG.getUNDEF(VecVT);
2900 for (unsigned i = 0; i < NumElts; ++i) {
2901 SDValue Elt = Op.getOperand(i);
2902 if (Elt.getOpcode() == ISD::UNDEF)
2904 Elt = DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Elt);
2905 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Val, Elt,
2906 DAG.getConstant(i, MVT::i32));
2908 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
2914 /// isShuffleMaskLegal - Targets can use this to indicate that they only
2915 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
2916 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
2917 /// are assumed to be legal.
2919 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
2921 if (VT.getVectorNumElements() == 4 &&
2922 (VT.is128BitVector() || VT.is64BitVector())) {
2923 unsigned PFIndexes[4];
2924 for (unsigned i = 0; i != 4; ++i) {
2928 PFIndexes[i] = M[i];
2931 // Compute the index in the perfect shuffle table.
2932 unsigned PFTableIndex =
2933 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2934 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2935 unsigned Cost = (PFEntry >> 30);
2942 unsigned Imm, WhichResult;
2944 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
2945 isVREVMask(M, VT, 64) ||
2946 isVREVMask(M, VT, 32) ||
2947 isVREVMask(M, VT, 16) ||
2948 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
2949 isVTRNMask(M, VT, WhichResult) ||
2950 isVUZPMask(M, VT, WhichResult) ||
2951 isVZIPMask(M, VT, WhichResult) ||
2952 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
2953 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
2954 isVZIP_v_undef_Mask(M, VT, WhichResult));
2957 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2958 /// the specified operations to build the shuffle.
2959 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
2960 SDValue RHS, SelectionDAG &DAG,
2962 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2963 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2964 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2967 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2976 OP_VUZPL, // VUZP, left result
2977 OP_VUZPR, // VUZP, right result
2978 OP_VZIPL, // VZIP, left result
2979 OP_VZIPR, // VZIP, right result
2980 OP_VTRNL, // VTRN, left result
2981 OP_VTRNR // VTRN, right result
2984 if (OpNum == OP_COPY) {
2985 if (LHSID == (1*9+2)*9+3) return LHS;
2986 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2990 SDValue OpLHS, OpRHS;
2991 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
2992 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
2993 EVT VT = OpLHS.getValueType();
2996 default: llvm_unreachable("Unknown shuffle opcode!");
2998 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3003 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3004 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3008 return DAG.getNode(ARMISD::VEXT, dl, VT,
3010 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3013 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3014 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3017 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3018 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3021 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3022 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3026 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3027 SDValue V1 = Op.getOperand(0);
3028 SDValue V2 = Op.getOperand(1);
3029 DebugLoc dl = Op.getDebugLoc();
3030 EVT VT = Op.getValueType();
3031 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3032 SmallVector<int, 8> ShuffleMask;
3034 // Convert shuffles that are directly supported on NEON to target-specific
3035 // DAG nodes, instead of keeping them as shuffles and matching them again
3036 // during code selection. This is more efficient and avoids the possibility
3037 // of inconsistencies between legalization and selection.
3038 // FIXME: floating-point vectors should be canonicalized to integer vectors
3039 // of the same time so that they get CSEd properly.
3040 SVN->getMask(ShuffleMask);
3042 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3043 int Lane = SVN->getSplatIndex();
3044 // If this is undef splat, generate it via "just" vdup, if possible.
3045 if (Lane == -1) Lane = 0;
3047 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3048 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3050 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3051 DAG.getConstant(Lane, MVT::i32));
3056 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3059 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3060 DAG.getConstant(Imm, MVT::i32));
3063 if (isVREVMask(ShuffleMask, VT, 64))
3064 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3065 if (isVREVMask(ShuffleMask, VT, 32))
3066 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3067 if (isVREVMask(ShuffleMask, VT, 16))
3068 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3070 // Check for Neon shuffles that modify both input vectors in place.
3071 // If both results are used, i.e., if there are two shuffles with the same
3072 // source operands and with masks corresponding to both results of one of
3073 // these operations, DAG memoization will ensure that a single node is
3074 // used for both shuffles.
3075 unsigned WhichResult;
3076 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3077 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3078 V1, V2).getValue(WhichResult);
3079 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3080 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3081 V1, V2).getValue(WhichResult);
3082 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3083 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3084 V1, V2).getValue(WhichResult);
3086 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3087 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3088 V1, V1).getValue(WhichResult);
3089 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3090 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3091 V1, V1).getValue(WhichResult);
3092 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3093 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3094 V1, V1).getValue(WhichResult);
3096 // If the shuffle is not directly supported and it has 4 elements, use
3097 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3098 unsigned NumElts = VT.getVectorNumElements();
3100 unsigned PFIndexes[4];
3101 for (unsigned i = 0; i != 4; ++i) {
3102 if (ShuffleMask[i] < 0)
3105 PFIndexes[i] = ShuffleMask[i];
3108 // Compute the index in the perfect shuffle table.
3109 unsigned PFTableIndex =
3110 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3111 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3112 unsigned Cost = (PFEntry >> 30);
3115 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3118 // Implement shuffles with 32- or 64-bit elements as subreg copies.
3119 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3120 if (EltSize >= 32) {
3121 // Do the expansion with floating-point types, since that is what the VFP
3122 // registers are defined to use, and since i64 is not legal.
3123 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3124 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3125 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3126 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3127 SDValue Val = DAG.getUNDEF(VecVT);
3128 for (unsigned i = 0; i < NumElts; ++i) {
3129 if (ShuffleMask[i] < 0)
3131 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3132 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3133 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3135 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Val,
3136 Elt, DAG.getConstant(i, MVT::i32));
3138 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3144 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3145 EVT VT = Op.getValueType();
3146 DebugLoc dl = Op.getDebugLoc();
3147 SDValue Vec = Op.getOperand(0);
3148 SDValue Lane = Op.getOperand(1);
3149 assert(VT == MVT::i32 &&
3150 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3151 "unexpected type for custom-lowering vector extract");
3152 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3155 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3156 // The only time a CONCAT_VECTORS operation can have legal types is when
3157 // two 64-bit vectors are concatenated to a 128-bit vector.
3158 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3159 "unexpected CONCAT_VECTORS");
3160 DebugLoc dl = Op.getDebugLoc();
3161 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3162 SDValue Op0 = Op.getOperand(0);
3163 SDValue Op1 = Op.getOperand(1);
3164 if (Op0.getOpcode() != ISD::UNDEF)
3165 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3166 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3167 DAG.getIntPtrConstant(0));
3168 if (Op1.getOpcode() != ISD::UNDEF)
3169 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3170 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3171 DAG.getIntPtrConstant(1));
3172 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3175 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3176 switch (Op.getOpcode()) {
3177 default: llvm_unreachable("Don't know how to custom lower this!");
3178 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3179 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3180 case ISD::GlobalAddress:
3181 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3182 LowerGlobalAddressELF(Op, DAG);
3183 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3184 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3185 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3186 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3187 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3188 case ISD::VASTART: return LowerVASTART(Op, DAG);
3189 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3190 case ISD::SINT_TO_FP:
3191 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3192 case ISD::FP_TO_SINT:
3193 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3194 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3195 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3196 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3197 case ISD::STACKADDR: return LowerSTACKADDR(Op, DAG);
3198 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3199 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3200 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3201 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3203 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3206 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3207 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3208 case ISD::SRL_PARTS:
3209 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3210 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3211 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3212 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3213 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3214 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3215 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3220 /// ReplaceNodeResults - Replace the results of node with an illegal result
3221 /// type with new values built out of custom code.
3222 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3223 SmallVectorImpl<SDValue>&Results,
3224 SelectionDAG &DAG) const {
3226 switch (N->getOpcode()) {
3228 llvm_unreachable("Don't know how to custom expand this!");
3230 case ISD::BIT_CONVERT:
3231 Res = ExpandBIT_CONVERT(N, DAG);
3235 Res = LowerShift(N, DAG, Subtarget);
3239 Results.push_back(Res);
3242 //===----------------------------------------------------------------------===//
3243 // ARM Scheduler Hooks
3244 //===----------------------------------------------------------------------===//
3247 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3248 MachineBasicBlock *BB,
3249 unsigned Size) const {
3250 unsigned dest = MI->getOperand(0).getReg();
3251 unsigned ptr = MI->getOperand(1).getReg();
3252 unsigned oldval = MI->getOperand(2).getReg();
3253 unsigned newval = MI->getOperand(3).getReg();
3254 unsigned scratch = BB->getParent()->getRegInfo()
3255 .createVirtualRegister(ARM::GPRRegisterClass);
3256 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3257 DebugLoc dl = MI->getDebugLoc();
3258 bool isThumb2 = Subtarget->isThumb2();
3260 unsigned ldrOpc, strOpc;
3262 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3264 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3265 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3268 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3269 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3272 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3273 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3277 MachineFunction *MF = BB->getParent();
3278 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3279 MachineFunction::iterator It = BB;
3280 ++It; // insert the new blocks after the current block
3282 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3283 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3284 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3285 MF->insert(It, loop1MBB);
3286 MF->insert(It, loop2MBB);
3287 MF->insert(It, exitMBB);
3288 exitMBB->transferSuccessors(BB);
3292 // fallthrough --> loop1MBB
3293 BB->addSuccessor(loop1MBB);
3296 // ldrex dest, [ptr]
3300 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3301 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3302 .addReg(dest).addReg(oldval));
3303 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3304 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3305 BB->addSuccessor(loop2MBB);
3306 BB->addSuccessor(exitMBB);
3309 // strex scratch, newval, [ptr]
3313 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3315 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3316 .addReg(scratch).addImm(0));
3317 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3318 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3319 BB->addSuccessor(loop1MBB);
3320 BB->addSuccessor(exitMBB);
3326 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3332 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3333 unsigned Size, unsigned BinOpcode) const {
3334 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3335 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3337 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3338 MachineFunction *MF = BB->getParent();
3339 MachineFunction::iterator It = BB;
3342 unsigned dest = MI->getOperand(0).getReg();
3343 unsigned ptr = MI->getOperand(1).getReg();
3344 unsigned incr = MI->getOperand(2).getReg();
3345 DebugLoc dl = MI->getDebugLoc();
3347 bool isThumb2 = Subtarget->isThumb2();
3348 unsigned ldrOpc, strOpc;
3350 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3352 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3353 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3356 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3357 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3360 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3361 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3365 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3366 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3367 MF->insert(It, loopMBB);
3368 MF->insert(It, exitMBB);
3369 exitMBB->transferSuccessors(BB);
3371 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3372 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3373 unsigned scratch2 = (!BinOpcode) ? incr :
3374 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3378 // fallthrough --> loopMBB
3379 BB->addSuccessor(loopMBB);
3383 // <binop> scratch2, dest, incr
3384 // strex scratch, scratch2, ptr
3387 // fallthrough --> exitMBB
3389 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3391 // operand order needs to go the other way for NAND
3392 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3393 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3394 addReg(incr).addReg(dest)).addReg(0);
3396 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3397 addReg(dest).addReg(incr)).addReg(0);
3400 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3402 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3403 .addReg(scratch).addImm(0));
3404 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3405 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3407 BB->addSuccessor(loopMBB);
3408 BB->addSuccessor(exitMBB);
3414 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3420 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3421 MachineBasicBlock *BB) const {
3422 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3423 DebugLoc dl = MI->getDebugLoc();
3424 bool isThumb2 = Subtarget->isThumb2();
3425 switch (MI->getOpcode()) {
3428 llvm_unreachable("Unexpected instr type to insert");
3430 case ARM::ATOMIC_LOAD_ADD_I8:
3431 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3432 case ARM::ATOMIC_LOAD_ADD_I16:
3433 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3434 case ARM::ATOMIC_LOAD_ADD_I32:
3435 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3437 case ARM::ATOMIC_LOAD_AND_I8:
3438 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3439 case ARM::ATOMIC_LOAD_AND_I16:
3440 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3441 case ARM::ATOMIC_LOAD_AND_I32:
3442 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3444 case ARM::ATOMIC_LOAD_OR_I8:
3445 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3446 case ARM::ATOMIC_LOAD_OR_I16:
3447 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3448 case ARM::ATOMIC_LOAD_OR_I32:
3449 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3451 case ARM::ATOMIC_LOAD_XOR_I8:
3452 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3453 case ARM::ATOMIC_LOAD_XOR_I16:
3454 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3455 case ARM::ATOMIC_LOAD_XOR_I32:
3456 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3458 case ARM::ATOMIC_LOAD_NAND_I8:
3459 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3460 case ARM::ATOMIC_LOAD_NAND_I16:
3461 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3462 case ARM::ATOMIC_LOAD_NAND_I32:
3463 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3465 case ARM::ATOMIC_LOAD_SUB_I8:
3466 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3467 case ARM::ATOMIC_LOAD_SUB_I16:
3468 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3469 case ARM::ATOMIC_LOAD_SUB_I32:
3470 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3472 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3473 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3474 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3476 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3477 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3478 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3480 case ARM::tMOVCCr_pseudo: {
3481 // To "insert" a SELECT_CC instruction, we actually have to insert the
3482 // diamond control-flow pattern. The incoming instruction knows the
3483 // destination vreg to set, the condition code register to branch on, the
3484 // true/false values to select between, and a branch opcode to use.
3485 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3486 MachineFunction::iterator It = BB;
3492 // cmpTY ccX, r1, r2
3494 // fallthrough --> copy0MBB
3495 MachineBasicBlock *thisMBB = BB;
3496 MachineFunction *F = BB->getParent();
3497 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3498 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3499 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3500 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3501 F->insert(It, copy0MBB);
3502 F->insert(It, sinkMBB);
3503 // Update machine-CFG edges by first adding all successors of the current
3504 // block to the new block which will contain the Phi node for the select.
3505 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
3506 E = BB->succ_end(); I != E; ++I)
3507 sinkMBB->addSuccessor(*I);
3508 // Next, remove all successors of the current block, and add the true
3509 // and fallthrough blocks as its successors.
3510 while (!BB->succ_empty())
3511 BB->removeSuccessor(BB->succ_begin());
3512 BB->addSuccessor(copy0MBB);
3513 BB->addSuccessor(sinkMBB);
3516 // %FalseValue = ...
3517 // # fallthrough to sinkMBB
3520 // Update machine-CFG edges
3521 BB->addSuccessor(sinkMBB);
3524 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3527 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
3528 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3529 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3531 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3538 case ARM::t2SUBrSPi_:
3539 case ARM::t2SUBrSPi12_:
3540 case ARM::t2SUBrSPs_: {
3541 MachineFunction *MF = BB->getParent();
3542 unsigned DstReg = MI->getOperand(0).getReg();
3543 unsigned SrcReg = MI->getOperand(1).getReg();
3544 bool DstIsDead = MI->getOperand(0).isDead();
3545 bool SrcIsKill = MI->getOperand(1).isKill();
3547 if (SrcReg != ARM::SP) {
3548 // Copy the source to SP from virtual register.
3549 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
3550 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3551 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
3552 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
3553 .addReg(SrcReg, getKillRegState(SrcIsKill));
3557 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
3558 switch (MI->getOpcode()) {
3560 llvm_unreachable("Unexpected pseudo instruction!");
3566 OpOpc = ARM::tADDspr;
3569 OpOpc = ARM::tSUBspi;
3571 case ARM::t2SUBrSPi_:
3572 OpOpc = ARM::t2SUBrSPi;
3573 NeedPred = true; NeedCC = true;
3575 case ARM::t2SUBrSPi12_:
3576 OpOpc = ARM::t2SUBrSPi12;
3579 case ARM::t2SUBrSPs_:
3580 OpOpc = ARM::t2SUBrSPs;
3581 NeedPred = true; NeedCC = true; NeedOp3 = true;
3584 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
3585 if (OpOpc == ARM::tAND)
3586 AddDefaultT1CC(MIB);
3587 MIB.addReg(ARM::SP);
3588 MIB.addOperand(MI->getOperand(2));
3590 MIB.addOperand(MI->getOperand(3));
3592 AddDefaultPred(MIB);
3596 // Copy the result from SP to virtual register.
3597 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
3598 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3599 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
3600 BuildMI(BB, dl, TII->get(CopyOpc))
3601 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
3603 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3609 //===----------------------------------------------------------------------===//
3610 // ARM Optimization Hooks
3611 //===----------------------------------------------------------------------===//
3614 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
3615 TargetLowering::DAGCombinerInfo &DCI) {
3616 SelectionDAG &DAG = DCI.DAG;
3617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3618 EVT VT = N->getValueType(0);
3619 unsigned Opc = N->getOpcode();
3620 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
3621 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
3622 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
3623 ISD::CondCode CC = ISD::SETCC_INVALID;
3626 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
3628 SDValue CCOp = Slct.getOperand(0);
3629 if (CCOp.getOpcode() == ISD::SETCC)
3630 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
3633 bool DoXform = false;
3635 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
3638 if (LHS.getOpcode() == ISD::Constant &&
3639 cast<ConstantSDNode>(LHS)->isNullValue()) {
3641 } else if (CC != ISD::SETCC_INVALID &&
3642 RHS.getOpcode() == ISD::Constant &&
3643 cast<ConstantSDNode>(RHS)->isNullValue()) {
3644 std::swap(LHS, RHS);
3645 SDValue Op0 = Slct.getOperand(0);
3646 EVT OpVT = isSlctCC ? Op0.getValueType() :
3647 Op0.getOperand(0).getValueType();
3648 bool isInt = OpVT.isInteger();
3649 CC = ISD::getSetCCInverse(CC, isInt);
3651 if (!TLI.isCondCodeLegal(CC, OpVT))
3652 return SDValue(); // Inverse operator isn't legal.
3659 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
3661 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
3662 Slct.getOperand(0), Slct.getOperand(1), CC);
3663 SDValue CCOp = Slct.getOperand(0);
3665 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
3666 CCOp.getOperand(0), CCOp.getOperand(1), CC);
3667 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3668 CCOp, OtherOp, Result);
3673 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3674 static SDValue PerformADDCombine(SDNode *N,
3675 TargetLowering::DAGCombinerInfo &DCI) {
3676 // added by evan in r37685 with no testcase.
3677 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3679 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
3680 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
3681 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
3682 if (Result.getNode()) return Result;
3684 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3685 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3686 if (Result.getNode()) return Result;
3692 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
3693 static SDValue PerformSUBCombine(SDNode *N,
3694 TargetLowering::DAGCombinerInfo &DCI) {
3695 // added by evan in r37685 with no testcase.
3696 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3698 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
3699 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3700 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3701 if (Result.getNode()) return Result;
3707 static SDValue PerformMULCombine(SDNode *N,
3708 TargetLowering::DAGCombinerInfo &DCI,
3709 const ARMSubtarget *Subtarget) {
3710 SelectionDAG &DAG = DCI.DAG;
3712 if (Subtarget->isThumb1Only())
3715 if (DAG.getMachineFunction().
3716 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
3719 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
3722 EVT VT = N->getValueType(0);
3726 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
3730 uint64_t MulAmt = C->getZExtValue();
3731 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
3732 ShiftAmt = ShiftAmt & (32 - 1);
3733 SDValue V = N->getOperand(0);
3734 DebugLoc DL = N->getDebugLoc();
3737 MulAmt >>= ShiftAmt;
3738 if (isPowerOf2_32(MulAmt - 1)) {
3739 // (mul x, 2^N + 1) => (add (shl x, N), x)
3740 Res = DAG.getNode(ISD::ADD, DL, VT,
3741 V, DAG.getNode(ISD::SHL, DL, VT,
3742 V, DAG.getConstant(Log2_32(MulAmt-1),
3744 } else if (isPowerOf2_32(MulAmt + 1)) {
3745 // (mul x, 2^N - 1) => (sub (shl x, N), x)
3746 Res = DAG.getNode(ISD::SUB, DL, VT,
3747 DAG.getNode(ISD::SHL, DL, VT,
3748 V, DAG.getConstant(Log2_32(MulAmt+1),
3755 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
3756 DAG.getConstant(ShiftAmt, MVT::i32));
3758 // Do not add new nodes to DAG combiner worklist.
3759 DCI.CombineTo(N, Res, false);
3763 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
3764 /// ARMISD::VMOVRRD.
3765 static SDValue PerformVMOVRRDCombine(SDNode *N,
3766 TargetLowering::DAGCombinerInfo &DCI) {
3767 // fmrrd(fmdrr x, y) -> x,y
3768 SDValue InDouble = N->getOperand(0);
3769 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
3770 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
3774 /// getVShiftImm - Check if this is a valid build_vector for the immediate
3775 /// operand of a vector shift operation, where all the elements of the
3776 /// build_vector must have the same constant integer value.
3777 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3778 // Ignore bit_converts.
3779 while (Op.getOpcode() == ISD::BIT_CONVERT)
3780 Op = Op.getOperand(0);
3781 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3782 APInt SplatBits, SplatUndef;
3783 unsigned SplatBitSize;
3785 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3786 HasAnyUndefs, ElementBits) ||
3787 SplatBitSize > ElementBits)
3789 Cnt = SplatBits.getSExtValue();
3793 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
3794 /// operand of a vector shift left operation. That value must be in the range:
3795 /// 0 <= Value < ElementBits for a left shift; or
3796 /// 0 <= Value <= ElementBits for a long left shift.
3797 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
3798 assert(VT.isVector() && "vector shift count is not a vector type");
3799 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3800 if (! getVShiftImm(Op, ElementBits, Cnt))
3802 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
3805 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
3806 /// operand of a vector shift right operation. For a shift opcode, the value
3807 /// is positive, but for an intrinsic the value count must be negative. The
3808 /// absolute value must be in the range:
3809 /// 1 <= |Value| <= ElementBits for a right shift; or
3810 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
3811 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
3813 assert(VT.isVector() && "vector shift count is not a vector type");
3814 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3815 if (! getVShiftImm(Op, ElementBits, Cnt))
3819 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
3822 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
3823 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
3824 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3827 // Don't do anything for most intrinsics.
3830 // Vector shifts: check for immediate versions and lower them.
3831 // Note: This is done during DAG combining instead of DAG legalizing because
3832 // the build_vectors for 64-bit vector element shift counts are generally
3833 // not legal, and it is hard to see their values after they get legalized to
3834 // loads from a constant pool.
3835 case Intrinsic::arm_neon_vshifts:
3836 case Intrinsic::arm_neon_vshiftu:
3837 case Intrinsic::arm_neon_vshiftls:
3838 case Intrinsic::arm_neon_vshiftlu:
3839 case Intrinsic::arm_neon_vshiftn:
3840 case Intrinsic::arm_neon_vrshifts:
3841 case Intrinsic::arm_neon_vrshiftu:
3842 case Intrinsic::arm_neon_vrshiftn:
3843 case Intrinsic::arm_neon_vqshifts:
3844 case Intrinsic::arm_neon_vqshiftu:
3845 case Intrinsic::arm_neon_vqshiftsu:
3846 case Intrinsic::arm_neon_vqshiftns:
3847 case Intrinsic::arm_neon_vqshiftnu:
3848 case Intrinsic::arm_neon_vqshiftnsu:
3849 case Intrinsic::arm_neon_vqrshiftns:
3850 case Intrinsic::arm_neon_vqrshiftnu:
3851 case Intrinsic::arm_neon_vqrshiftnsu: {
3852 EVT VT = N->getOperand(1).getValueType();
3854 unsigned VShiftOpc = 0;
3857 case Intrinsic::arm_neon_vshifts:
3858 case Intrinsic::arm_neon_vshiftu:
3859 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
3860 VShiftOpc = ARMISD::VSHL;
3863 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
3864 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
3865 ARMISD::VSHRs : ARMISD::VSHRu);
3870 case Intrinsic::arm_neon_vshiftls:
3871 case Intrinsic::arm_neon_vshiftlu:
3872 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
3874 llvm_unreachable("invalid shift count for vshll intrinsic");
3876 case Intrinsic::arm_neon_vrshifts:
3877 case Intrinsic::arm_neon_vrshiftu:
3878 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
3882 case Intrinsic::arm_neon_vqshifts:
3883 case Intrinsic::arm_neon_vqshiftu:
3884 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3888 case Intrinsic::arm_neon_vqshiftsu:
3889 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3891 llvm_unreachable("invalid shift count for vqshlu intrinsic");
3893 case Intrinsic::arm_neon_vshiftn:
3894 case Intrinsic::arm_neon_vrshiftn:
3895 case Intrinsic::arm_neon_vqshiftns:
3896 case Intrinsic::arm_neon_vqshiftnu:
3897 case Intrinsic::arm_neon_vqshiftnsu:
3898 case Intrinsic::arm_neon_vqrshiftns:
3899 case Intrinsic::arm_neon_vqrshiftnu:
3900 case Intrinsic::arm_neon_vqrshiftnsu:
3901 // Narrowing shifts require an immediate right shift.
3902 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
3904 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
3907 llvm_unreachable("unhandled vector shift");
3911 case Intrinsic::arm_neon_vshifts:
3912 case Intrinsic::arm_neon_vshiftu:
3913 // Opcode already set above.
3915 case Intrinsic::arm_neon_vshiftls:
3916 case Intrinsic::arm_neon_vshiftlu:
3917 if (Cnt == VT.getVectorElementType().getSizeInBits())
3918 VShiftOpc = ARMISD::VSHLLi;
3920 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
3921 ARMISD::VSHLLs : ARMISD::VSHLLu);
3923 case Intrinsic::arm_neon_vshiftn:
3924 VShiftOpc = ARMISD::VSHRN; break;
3925 case Intrinsic::arm_neon_vrshifts:
3926 VShiftOpc = ARMISD::VRSHRs; break;
3927 case Intrinsic::arm_neon_vrshiftu:
3928 VShiftOpc = ARMISD::VRSHRu; break;
3929 case Intrinsic::arm_neon_vrshiftn:
3930 VShiftOpc = ARMISD::VRSHRN; break;
3931 case Intrinsic::arm_neon_vqshifts:
3932 VShiftOpc = ARMISD::VQSHLs; break;
3933 case Intrinsic::arm_neon_vqshiftu:
3934 VShiftOpc = ARMISD::VQSHLu; break;
3935 case Intrinsic::arm_neon_vqshiftsu:
3936 VShiftOpc = ARMISD::VQSHLsu; break;
3937 case Intrinsic::arm_neon_vqshiftns:
3938 VShiftOpc = ARMISD::VQSHRNs; break;
3939 case Intrinsic::arm_neon_vqshiftnu:
3940 VShiftOpc = ARMISD::VQSHRNu; break;
3941 case Intrinsic::arm_neon_vqshiftnsu:
3942 VShiftOpc = ARMISD::VQSHRNsu; break;
3943 case Intrinsic::arm_neon_vqrshiftns:
3944 VShiftOpc = ARMISD::VQRSHRNs; break;
3945 case Intrinsic::arm_neon_vqrshiftnu:
3946 VShiftOpc = ARMISD::VQRSHRNu; break;
3947 case Intrinsic::arm_neon_vqrshiftnsu:
3948 VShiftOpc = ARMISD::VQRSHRNsu; break;
3951 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3952 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
3955 case Intrinsic::arm_neon_vshiftins: {
3956 EVT VT = N->getOperand(1).getValueType();
3958 unsigned VShiftOpc = 0;
3960 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
3961 VShiftOpc = ARMISD::VSLI;
3962 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
3963 VShiftOpc = ARMISD::VSRI;
3965 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
3968 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3969 N->getOperand(1), N->getOperand(2),
3970 DAG.getConstant(Cnt, MVT::i32));
3973 case Intrinsic::arm_neon_vqrshifts:
3974 case Intrinsic::arm_neon_vqrshiftu:
3975 // No immediate versions of these to check for.
3982 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
3983 /// lowers them. As with the vector shift intrinsics, this is done during DAG
3984 /// combining instead of DAG legalizing because the build_vectors for 64-bit
3985 /// vector element shift counts are generally not legal, and it is hard to see
3986 /// their values after they get legalized to loads from a constant pool.
3987 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3988 const ARMSubtarget *ST) {
3989 EVT VT = N->getValueType(0);
3991 // Nothing to be done for scalar shifts.
3992 if (! VT.isVector())
3995 assert(ST->hasNEON() && "unexpected vector shift");
3998 switch (N->getOpcode()) {
3999 default: llvm_unreachable("unexpected shift opcode");
4002 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4003 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4004 DAG.getConstant(Cnt, MVT::i32));
4009 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4010 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4011 ARMISD::VSHRs : ARMISD::VSHRu);
4012 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4013 DAG.getConstant(Cnt, MVT::i32));
4019 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4020 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4021 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4022 const ARMSubtarget *ST) {
4023 SDValue N0 = N->getOperand(0);
4025 // Check for sign- and zero-extensions of vector extract operations of 8-
4026 // and 16-bit vector elements. NEON supports these directly. They are
4027 // handled during DAG combining because type legalization will promote them
4028 // to 32-bit types and it is messy to recognize the operations after that.
4029 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4030 SDValue Vec = N0.getOperand(0);
4031 SDValue Lane = N0.getOperand(1);
4032 EVT VT = N->getValueType(0);
4033 EVT EltVT = N0.getValueType();
4034 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4036 if (VT == MVT::i32 &&
4037 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4038 TLI.isTypeLegal(Vec.getValueType())) {
4041 switch (N->getOpcode()) {
4042 default: llvm_unreachable("unexpected opcode");
4043 case ISD::SIGN_EXTEND:
4044 Opc = ARMISD::VGETLANEs;
4046 case ISD::ZERO_EXTEND:
4047 case ISD::ANY_EXTEND:
4048 Opc = ARMISD::VGETLANEu;
4051 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4058 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4059 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4060 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4061 const ARMSubtarget *ST) {
4062 // If the target supports NEON, try to use vmax/vmin instructions for f32
4063 // selects like "x < y ? x : y". Unless the FiniteOnlyFPMath option is set,
4064 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4065 // a NaN; only do the transformation when it matches that behavior.
4067 // For now only do this when using NEON for FP operations; if using VFP, it
4068 // is not obvious that the benefit outweighs the cost of switching to the
4070 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4071 N->getValueType(0) != MVT::f32)
4074 SDValue CondLHS = N->getOperand(0);
4075 SDValue CondRHS = N->getOperand(1);
4076 SDValue LHS = N->getOperand(2);
4077 SDValue RHS = N->getOperand(3);
4078 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4080 unsigned Opcode = 0;
4082 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4083 IsReversed = false; // x CC y ? x : y
4084 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4085 IsReversed = true ; // x CC y ? y : x
4099 // If LHS is NaN, an ordered comparison will be false and the result will
4100 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4101 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4102 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4103 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4105 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4106 // will return -0, so vmin can only be used for unsafe math or if one of
4107 // the operands is known to be nonzero.
4108 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4110 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4112 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4121 // If LHS is NaN, an ordered comparison will be false and the result will
4122 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4123 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4124 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4125 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4127 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4128 // will return +0, so vmax can only be used for unsafe math or if one of
4129 // the operands is known to be nonzero.
4130 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4132 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4134 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4140 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4143 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4144 DAGCombinerInfo &DCI) const {
4145 switch (N->getOpcode()) {
4147 case ISD::ADD: return PerformADDCombine(N, DCI);
4148 case ISD::SUB: return PerformSUBCombine(N, DCI);
4149 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4150 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4151 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4154 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4155 case ISD::SIGN_EXTEND:
4156 case ISD::ZERO_EXTEND:
4157 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4158 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4163 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4164 if (!Subtarget->hasV6Ops())
4165 // Pre-v6 does not support unaligned mem access.
4168 // v6+ may or may not support unaligned mem access depending on the system
4170 // FIXME: This is pretty conservative. Should we provide cmdline option to
4171 // control the behaviour?
4172 if (!Subtarget->isTargetDarwin())
4176 switch (VT.getSimpleVT().SimpleTy) {
4183 // FIXME: VLD1 etc with standard alignment is legal.
4187 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4192 switch (VT.getSimpleVT().SimpleTy) {
4193 default: return false;
4208 if ((V & (Scale - 1)) != 0)
4211 return V == (V & ((1LL << 5) - 1));
4214 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4215 const ARMSubtarget *Subtarget) {
4222 switch (VT.getSimpleVT().SimpleTy) {
4223 default: return false;
4228 // + imm12 or - imm8
4230 return V == (V & ((1LL << 8) - 1));
4231 return V == (V & ((1LL << 12) - 1));
4234 // Same as ARM mode. FIXME: NEON?
4235 if (!Subtarget->hasVFP2())
4240 return V == (V & ((1LL << 8) - 1));
4244 /// isLegalAddressImmediate - Return true if the integer value can be used
4245 /// as the offset of the target addressing mode for load / store of the
4247 static bool isLegalAddressImmediate(int64_t V, EVT VT,
4248 const ARMSubtarget *Subtarget) {
4255 if (Subtarget->isThumb1Only())
4256 return isLegalT1AddressImmediate(V, VT);
4257 else if (Subtarget->isThumb2())
4258 return isLegalT2AddressImmediate(V, VT, Subtarget);
4263 switch (VT.getSimpleVT().SimpleTy) {
4264 default: return false;
4269 return V == (V & ((1LL << 12) - 1));
4272 return V == (V & ((1LL << 8) - 1));
4275 if (!Subtarget->hasVFP2()) // FIXME: NEON?
4280 return V == (V & ((1LL << 8) - 1));
4284 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
4286 int Scale = AM.Scale;
4290 switch (VT.getSimpleVT().SimpleTy) {
4291 default: return false;
4300 return Scale == 2 || Scale == 4 || Scale == 8;
4303 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4307 // Note, we allow "void" uses (basically, uses that aren't loads or
4308 // stores), because arm allows folding a scale into many arithmetic
4309 // operations. This should be made more precise and revisited later.
4311 // Allow r << imm, but the imm has to be a multiple of two.
4312 if (Scale & 1) return false;
4313 return isPowerOf2_32(Scale);
4317 /// isLegalAddressingMode - Return true if the addressing mode represented
4318 /// by AM is legal for this target, for a load/store of the specified type.
4319 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4320 const Type *Ty) const {
4321 EVT VT = getValueType(Ty, true);
4322 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4325 // Can never fold addr of global into load/store.
4330 case 0: // no scale reg, must be "r+i" or "r", or "i".
4333 if (Subtarget->isThumb1Only())
4337 // ARM doesn't support any R+R*scale+imm addr modes.
4344 if (Subtarget->isThumb2())
4345 return isLegalT2ScaledAddressingMode(AM, VT);
4347 int Scale = AM.Scale;
4348 switch (VT.getSimpleVT().SimpleTy) {
4349 default: return false;
4353 if (Scale < 0) Scale = -Scale;
4357 return isPowerOf2_32(Scale & ~1);
4361 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4366 // Note, we allow "void" uses (basically, uses that aren't loads or
4367 // stores), because arm allows folding a scale into many arithmetic
4368 // operations. This should be made more precise and revisited later.
4370 // Allow r << imm, but the imm has to be a multiple of two.
4371 if (Scale & 1) return false;
4372 return isPowerOf2_32(Scale);
4379 /// isLegalICmpImmediate - Return true if the specified immediate is legal
4380 /// icmp immediate, that is the target has icmp instructions which can compare
4381 /// a register against the immediate without having to materialize the
4382 /// immediate into a register.
4383 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4384 if (!Subtarget->isThumb())
4385 return ARM_AM::getSOImmVal(Imm) != -1;
4386 if (Subtarget->isThumb2())
4387 return ARM_AM::getT2SOImmVal(Imm) != -1;
4388 return Imm >= 0 && Imm <= 255;
4391 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
4392 bool isSEXTLoad, SDValue &Base,
4393 SDValue &Offset, bool &isInc,
4394 SelectionDAG &DAG) {
4395 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4398 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
4400 Base = Ptr->getOperand(0);
4401 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4402 int RHSC = (int)RHS->getZExtValue();
4403 if (RHSC < 0 && RHSC > -256) {
4404 assert(Ptr->getOpcode() == ISD::ADD);
4406 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4410 isInc = (Ptr->getOpcode() == ISD::ADD);
4411 Offset = Ptr->getOperand(1);
4413 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
4415 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4416 int RHSC = (int)RHS->getZExtValue();
4417 if (RHSC < 0 && RHSC > -0x1000) {
4418 assert(Ptr->getOpcode() == ISD::ADD);
4420 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4421 Base = Ptr->getOperand(0);
4426 if (Ptr->getOpcode() == ISD::ADD) {
4428 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4429 if (ShOpcVal != ARM_AM::no_shift) {
4430 Base = Ptr->getOperand(1);
4431 Offset = Ptr->getOperand(0);
4433 Base = Ptr->getOperand(0);
4434 Offset = Ptr->getOperand(1);
4439 isInc = (Ptr->getOpcode() == ISD::ADD);
4440 Base = Ptr->getOperand(0);
4441 Offset = Ptr->getOperand(1);
4445 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
4449 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
4450 bool isSEXTLoad, SDValue &Base,
4451 SDValue &Offset, bool &isInc,
4452 SelectionDAG &DAG) {
4453 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4456 Base = Ptr->getOperand(0);
4457 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4458 int RHSC = (int)RHS->getZExtValue();
4459 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
4460 assert(Ptr->getOpcode() == ISD::ADD);
4462 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4464 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
4465 isInc = Ptr->getOpcode() == ISD::ADD;
4466 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
4474 /// getPreIndexedAddressParts - returns true by value, base pointer and
4475 /// offset pointer and addressing mode by reference if the node's address
4476 /// can be legally represented as pre-indexed load / store address.
4478 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
4480 ISD::MemIndexedMode &AM,
4481 SelectionDAG &DAG) const {
4482 if (Subtarget->isThumb1Only())
4487 bool isSEXTLoad = false;
4488 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4489 Ptr = LD->getBasePtr();
4490 VT = LD->getMemoryVT();
4491 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4492 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4493 Ptr = ST->getBasePtr();
4494 VT = ST->getMemoryVT();
4499 bool isLegal = false;
4500 if (Subtarget->isThumb2())
4501 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4502 Offset, isInc, DAG);
4504 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4505 Offset, isInc, DAG);
4509 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
4513 /// getPostIndexedAddressParts - returns true by value, base pointer and
4514 /// offset pointer and addressing mode by reference if this node can be
4515 /// combined with a load / store to form a post-indexed load / store.
4516 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
4519 ISD::MemIndexedMode &AM,
4520 SelectionDAG &DAG) const {
4521 if (Subtarget->isThumb1Only())
4526 bool isSEXTLoad = false;
4527 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4528 VT = LD->getMemoryVT();
4529 Ptr = LD->getBasePtr();
4530 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4531 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4532 VT = ST->getMemoryVT();
4533 Ptr = ST->getBasePtr();
4538 bool isLegal = false;
4539 if (Subtarget->isThumb2())
4540 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4543 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4549 // Swap base ptr and offset to catch more post-index load / store when
4550 // it's legal. In Thumb2 mode, offset must be an immediate.
4551 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
4552 !Subtarget->isThumb2())
4553 std::swap(Base, Offset);
4555 // Post-indexed load / store update the base pointer.
4560 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
4564 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4568 const SelectionDAG &DAG,
4569 unsigned Depth) const {
4570 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4571 switch (Op.getOpcode()) {
4573 case ARMISD::CMOV: {
4574 // Bits are known zero/one if known on the LHS and RHS.
4575 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
4576 if (KnownZero == 0 && KnownOne == 0) return;
4578 APInt KnownZeroRHS, KnownOneRHS;
4579 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
4580 KnownZeroRHS, KnownOneRHS, Depth+1);
4581 KnownZero &= KnownZeroRHS;
4582 KnownOne &= KnownOneRHS;
4588 //===----------------------------------------------------------------------===//
4589 // ARM Inline Assembly Support
4590 //===----------------------------------------------------------------------===//
4592 /// getConstraintType - Given a constraint letter, return the type of
4593 /// constraint it is for this target.
4594 ARMTargetLowering::ConstraintType
4595 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
4596 if (Constraint.size() == 1) {
4597 switch (Constraint[0]) {
4599 case 'l': return C_RegisterClass;
4600 case 'w': return C_RegisterClass;
4603 return TargetLowering::getConstraintType(Constraint);
4606 std::pair<unsigned, const TargetRegisterClass*>
4607 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4609 if (Constraint.size() == 1) {
4610 // GCC ARM Constraint Letters
4611 switch (Constraint[0]) {
4613 if (Subtarget->isThumb())
4614 return std::make_pair(0U, ARM::tGPRRegisterClass);
4616 return std::make_pair(0U, ARM::GPRRegisterClass);
4618 return std::make_pair(0U, ARM::GPRRegisterClass);
4621 return std::make_pair(0U, ARM::SPRRegisterClass);
4622 if (VT.getSizeInBits() == 64)
4623 return std::make_pair(0U, ARM::DPRRegisterClass);
4624 if (VT.getSizeInBits() == 128)
4625 return std::make_pair(0U, ARM::QPRRegisterClass);
4629 if (StringRef("{cc}").equals_lower(Constraint))
4630 return std::make_pair(0U, ARM::CCRRegisterClass);
4632 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4635 std::vector<unsigned> ARMTargetLowering::
4636 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4638 if (Constraint.size() != 1)
4639 return std::vector<unsigned>();
4641 switch (Constraint[0]) { // GCC ARM Constraint Letters
4644 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4645 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4648 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4649 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4650 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
4651 ARM::R12, ARM::LR, 0);
4654 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
4655 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
4656 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
4657 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
4658 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
4659 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
4660 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
4661 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
4662 if (VT.getSizeInBits() == 64)
4663 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
4664 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
4665 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
4666 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
4667 if (VT.getSizeInBits() == 128)
4668 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
4669 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
4673 return std::vector<unsigned>();
4676 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4677 /// vector. If it is invalid, don't add anything to Ops.
4678 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4681 std::vector<SDValue>&Ops,
4682 SelectionDAG &DAG) const {
4683 SDValue Result(0, 0);
4685 switch (Constraint) {
4687 case 'I': case 'J': case 'K': case 'L':
4688 case 'M': case 'N': case 'O':
4689 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4693 int64_t CVal64 = C->getSExtValue();
4694 int CVal = (int) CVal64;
4695 // None of these constraints allow values larger than 32 bits. Check
4696 // that the value fits in an int.
4700 switch (Constraint) {
4702 if (Subtarget->isThumb1Only()) {
4703 // This must be a constant between 0 and 255, for ADD
4705 if (CVal >= 0 && CVal <= 255)
4707 } else if (Subtarget->isThumb2()) {
4708 // A constant that can be used as an immediate value in a
4709 // data-processing instruction.
4710 if (ARM_AM::getT2SOImmVal(CVal) != -1)
4713 // A constant that can be used as an immediate value in a
4714 // data-processing instruction.
4715 if (ARM_AM::getSOImmVal(CVal) != -1)
4721 if (Subtarget->isThumb()) { // FIXME thumb2
4722 // This must be a constant between -255 and -1, for negated ADD
4723 // immediates. This can be used in GCC with an "n" modifier that
4724 // prints the negated value, for use with SUB instructions. It is
4725 // not useful otherwise but is implemented for compatibility.
4726 if (CVal >= -255 && CVal <= -1)
4729 // This must be a constant between -4095 and 4095. It is not clear
4730 // what this constraint is intended for. Implemented for
4731 // compatibility with GCC.
4732 if (CVal >= -4095 && CVal <= 4095)
4738 if (Subtarget->isThumb1Only()) {
4739 // A 32-bit value where only one byte has a nonzero value. Exclude
4740 // zero to match GCC. This constraint is used by GCC internally for
4741 // constants that can be loaded with a move/shift combination.
4742 // It is not useful otherwise but is implemented for compatibility.
4743 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
4745 } else if (Subtarget->isThumb2()) {
4746 // A constant whose bitwise inverse can be used as an immediate
4747 // value in a data-processing instruction. This can be used in GCC
4748 // with a "B" modifier that prints the inverted value, for use with
4749 // BIC and MVN instructions. It is not useful otherwise but is
4750 // implemented for compatibility.
4751 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
4754 // A constant whose bitwise inverse can be used as an immediate
4755 // value in a data-processing instruction. This can be used in GCC
4756 // with a "B" modifier that prints the inverted value, for use with
4757 // BIC and MVN instructions. It is not useful otherwise but is
4758 // implemented for compatibility.
4759 if (ARM_AM::getSOImmVal(~CVal) != -1)
4765 if (Subtarget->isThumb1Only()) {
4766 // This must be a constant between -7 and 7,
4767 // for 3-operand ADD/SUB immediate instructions.
4768 if (CVal >= -7 && CVal < 7)
4770 } else if (Subtarget->isThumb2()) {
4771 // A constant whose negation can be used as an immediate value in a
4772 // data-processing instruction. This can be used in GCC with an "n"
4773 // modifier that prints the negated value, for use with SUB
4774 // instructions. It is not useful otherwise but is implemented for
4776 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
4779 // A constant whose negation can be used as an immediate value in a
4780 // data-processing instruction. This can be used in GCC with an "n"
4781 // modifier that prints the negated value, for use with SUB
4782 // instructions. It is not useful otherwise but is implemented for
4784 if (ARM_AM::getSOImmVal(-CVal) != -1)
4790 if (Subtarget->isThumb()) { // FIXME thumb2
4791 // This must be a multiple of 4 between 0 and 1020, for
4792 // ADD sp + immediate.
4793 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
4796 // A power of two or a constant between 0 and 32. This is used in
4797 // GCC for the shift amount on shifted register operands, but it is
4798 // useful in general for any shift amounts.
4799 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
4805 if (Subtarget->isThumb()) { // FIXME thumb2
4806 // This must be a constant between 0 and 31, for shift amounts.
4807 if (CVal >= 0 && CVal <= 31)
4813 if (Subtarget->isThumb()) { // FIXME thumb2
4814 // This must be a multiple of 4 between -508 and 508, for
4815 // ADD/SUB sp = sp + immediate.
4816 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
4821 Result = DAG.getTargetConstant(CVal, Op.getValueType());
4825 if (Result.getNode()) {
4826 Ops.push_back(Result);
4829 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
4834 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4835 // The ARM target isn't yet aware of offsets.
4839 int ARM::getVFPf32Imm(const APFloat &FPImm) {
4840 APInt Imm = FPImm.bitcastToAPInt();
4841 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
4842 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
4843 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
4845 // We can handle 4 bits of mantissa.
4846 // mantissa = (16+UInt(e:f:g:h))/16.
4847 if (Mantissa & 0x7ffff)
4850 if ((Mantissa & 0xf) != Mantissa)
4853 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4854 if (Exp < -3 || Exp > 4)
4856 Exp = ((Exp+3) & 0x7) ^ 4;
4858 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4861 int ARM::getVFPf64Imm(const APFloat &FPImm) {
4862 APInt Imm = FPImm.bitcastToAPInt();
4863 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
4864 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
4865 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
4867 // We can handle 4 bits of mantissa.
4868 // mantissa = (16+UInt(e:f:g:h))/16.
4869 if (Mantissa & 0xffffffffffffLL)
4872 if ((Mantissa & 0xf) != Mantissa)
4875 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4876 if (Exp < -3 || Exp > 4)
4878 Exp = ((Exp+3) & 0x7) ^ 4;
4880 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4883 /// isFPImmLegal - Returns true if the target can instruction select the
4884 /// specified FP immediate natively. If false, the legalizer will
4885 /// materialize the FP immediate as a load from a constant pool.
4886 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4887 if (!Subtarget->hasVFP3())
4890 return ARM::getVFPf32Imm(Imm) != -1;
4892 return ARM::getVFPf64Imm(Imm) != -1;