1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instruction.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineBasicBlock.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/VectorExtras.h"
39 #include "llvm/Support/MathExtras.h"
42 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
43 CCValAssign::LocInfo &LocInfo,
44 ISD::ArgFlagsTy &ArgFlags,
46 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
51 CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags,
54 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
55 CCValAssign::LocInfo &LocInfo,
56 ISD::ArgFlagsTy &ArgFlags,
59 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
60 MVT PromotedBitwiseVT) {
61 if (VT != PromotedLdStVT) {
62 setOperationAction(ISD::LOAD, VT, Promote);
63 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
65 setOperationAction(ISD::STORE, VT, Promote);
66 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
69 MVT ElemTy = VT.getVectorElementType();
70 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
71 setOperationAction(ISD::VSETCC, VT, Custom);
72 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
73 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
74 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
75 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
76 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
77 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
79 setOperationAction(ISD::SHL, VT, Custom);
80 setOperationAction(ISD::SRA, VT, Custom);
81 setOperationAction(ISD::SRL, VT, Custom);
84 // Promote all bit-wise operations.
85 if (VT.isInteger() && VT != PromotedBitwiseVT) {
86 setOperationAction(ISD::AND, VT, Promote);
87 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
88 setOperationAction(ISD::OR, VT, Promote);
89 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
90 setOperationAction(ISD::XOR, VT, Promote);
91 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
95 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
96 addRegisterClass(VT, ARM::DPRRegisterClass);
97 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
100 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
101 addRegisterClass(VT, ARM::QPRRegisterClass);
102 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
105 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
106 : TargetLowering(TM), ARMPCLabelIndex(0) {
107 Subtarget = &TM.getSubtarget<ARMSubtarget>();
109 if (Subtarget->isTargetDarwin()) {
110 // Uses VFP for Thumb libfuncs if available.
111 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
112 // Single-precision floating-point arithmetic.
113 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
114 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
115 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
116 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
118 // Double-precision floating-point arithmetic.
119 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
120 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
121 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
122 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
124 // Single-precision comparisons.
125 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
126 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
127 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
128 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
129 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
130 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
131 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
132 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
134 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
135 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
136 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
137 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
138 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
139 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
140 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
141 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
143 // Double-precision comparisons.
144 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
145 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
146 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
147 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
148 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
149 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
150 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
151 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
153 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
154 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
155 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
156 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
157 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
158 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
159 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
160 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
162 // Floating-point to integer conversions.
163 // i64 conversions are done via library routines even when generating VFP
164 // instructions, so use the same ones.
165 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
166 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
167 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
168 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
170 // Conversions between floating types.
171 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
172 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
174 // Integer to floating-point conversions.
175 // i64 conversions are done via library routines even when generating VFP
176 // instructions, so use the same ones.
177 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
178 // e.g., __floatunsidf vs. __floatunssidfvfp.
179 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
180 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
181 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
182 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
186 // These libcalls are not available in 32-bit.
187 setLibcallName(RTLIB::SHL_I128, 0);
188 setLibcallName(RTLIB::SRL_I128, 0);
189 setLibcallName(RTLIB::SRA_I128, 0);
191 if (Subtarget->isThumb())
192 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
194 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
195 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
196 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
197 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
199 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
202 if (Subtarget->hasNEON()) {
203 addDRTypeForNEON(MVT::v2f32);
204 addDRTypeForNEON(MVT::v8i8);
205 addDRTypeForNEON(MVT::v4i16);
206 addDRTypeForNEON(MVT::v2i32);
207 addDRTypeForNEON(MVT::v1i64);
209 addQRTypeForNEON(MVT::v4f32);
210 addQRTypeForNEON(MVT::v2f64);
211 addQRTypeForNEON(MVT::v16i8);
212 addQRTypeForNEON(MVT::v8i16);
213 addQRTypeForNEON(MVT::v4i32);
214 addQRTypeForNEON(MVT::v2i64);
216 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
217 setTargetDAGCombine(ISD::SHL);
218 setTargetDAGCombine(ISD::SRL);
219 setTargetDAGCombine(ISD::SRA);
220 setTargetDAGCombine(ISD::SIGN_EXTEND);
221 setTargetDAGCombine(ISD::ZERO_EXTEND);
222 setTargetDAGCombine(ISD::ANY_EXTEND);
225 computeRegisterProperties();
227 // ARM does not have f32 extending load.
228 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
230 // ARM does not have i1 sign extending load.
231 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
233 // ARM supports all 4 flavors of integer indexed load / store.
234 if (!Subtarget->isThumb1Only()) {
235 for (unsigned im = (unsigned)ISD::PRE_INC;
236 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
237 setIndexedLoadAction(im, MVT::i1, Legal);
238 setIndexedLoadAction(im, MVT::i8, Legal);
239 setIndexedLoadAction(im, MVT::i16, Legal);
240 setIndexedLoadAction(im, MVT::i32, Legal);
241 setIndexedStoreAction(im, MVT::i1, Legal);
242 setIndexedStoreAction(im, MVT::i8, Legal);
243 setIndexedStoreAction(im, MVT::i16, Legal);
244 setIndexedStoreAction(im, MVT::i32, Legal);
248 // i64 operation support.
249 if (Subtarget->isThumb1Only()) {
250 setOperationAction(ISD::MUL, MVT::i64, Expand);
251 setOperationAction(ISD::MULHU, MVT::i32, Expand);
252 setOperationAction(ISD::MULHS, MVT::i32, Expand);
253 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
254 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
256 setOperationAction(ISD::MUL, MVT::i64, Expand);
257 setOperationAction(ISD::MULHU, MVT::i32, Expand);
258 if (!Subtarget->isThumb() && !Subtarget->hasV6Ops())
259 setOperationAction(ISD::MULHS, MVT::i32, Expand);
261 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
262 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
263 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
264 setOperationAction(ISD::SRL, MVT::i64, Custom);
265 setOperationAction(ISD::SRA, MVT::i64, Custom);
267 // ARM does not have ROTL.
268 setOperationAction(ISD::ROTL, MVT::i32, Expand);
269 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
270 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
271 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
272 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
274 // Only ARMv6 has BSWAP.
275 if (!Subtarget->hasV6Ops())
276 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
278 // These are expanded into libcalls.
279 setOperationAction(ISD::SDIV, MVT::i32, Expand);
280 setOperationAction(ISD::UDIV, MVT::i32, Expand);
281 setOperationAction(ISD::SREM, MVT::i32, Expand);
282 setOperationAction(ISD::UREM, MVT::i32, Expand);
283 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
284 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
286 // Support label based line numbers.
287 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
288 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
290 setOperationAction(ISD::RET, MVT::Other, Custom);
291 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
292 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
293 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
294 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
296 // Use the default implementation.
297 setOperationAction(ISD::VASTART, MVT::Other, Custom);
298 setOperationAction(ISD::VAARG, MVT::Other, Expand);
299 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
300 setOperationAction(ISD::VAEND, MVT::Other, Expand);
301 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
302 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
303 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
304 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
306 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
310 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
312 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
313 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
314 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
316 // We want to custom lower some of our intrinsics.
317 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
319 setOperationAction(ISD::SETCC, MVT::i32, Expand);
320 setOperationAction(ISD::SETCC, MVT::f32, Expand);
321 setOperationAction(ISD::SETCC, MVT::f64, Expand);
322 setOperationAction(ISD::SELECT, MVT::i32, Expand);
323 setOperationAction(ISD::SELECT, MVT::f32, Expand);
324 setOperationAction(ISD::SELECT, MVT::f64, Expand);
325 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
326 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
327 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
329 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
330 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
331 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
332 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
333 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
335 // We don't support sin/cos/fmod/copysign/pow
336 setOperationAction(ISD::FSIN, MVT::f64, Expand);
337 setOperationAction(ISD::FSIN, MVT::f32, Expand);
338 setOperationAction(ISD::FCOS, MVT::f32, Expand);
339 setOperationAction(ISD::FCOS, MVT::f64, Expand);
340 setOperationAction(ISD::FREM, MVT::f64, Expand);
341 setOperationAction(ISD::FREM, MVT::f32, Expand);
342 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
343 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
344 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
346 setOperationAction(ISD::FPOW, MVT::f64, Expand);
347 setOperationAction(ISD::FPOW, MVT::f32, Expand);
349 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
350 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
351 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
352 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
353 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
354 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
357 // We have target-specific dag combine patterns for the following nodes:
358 // ARMISD::FMRRD - No need to call setTargetDAGCombine
359 setTargetDAGCombine(ISD::ADD);
360 setTargetDAGCombine(ISD::SUB);
362 setStackPointerRegisterToSaveRestore(ARM::SP);
363 setSchedulingPreference(SchedulingForRegPressure);
364 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
365 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
367 if (!Subtarget->isThumb()) {
368 // Use branch latency information to determine if-conversion limits.
369 // FIXME: If-converter should use instruction latency of the branch being
370 // eliminated to compute the threshold. For ARMv6, the branch "latency"
371 // varies depending on whether it's dynamically or statically predicted
372 // and on whether the destination is in the prefetch buffer.
373 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
374 const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData();
375 unsigned Latency= InstrItins.getLatency(TII->get(ARM::Bcc).getSchedClass());
377 setIfCvtBlockSizeLimit(Latency-1);
379 setIfCvtDupBlockSizeLimit(Latency-2);
381 setIfCvtBlockSizeLimit(10);
382 setIfCvtDupBlockSizeLimit(2);
386 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
387 // Do not enable CodePlacementOpt for now: it currently runs after the
388 // ARMConstantIslandPass and messes up branch relaxation and placement
389 // of constant islands.
390 // benefitFromCodePlacementOpt = true;
393 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
396 case ARMISD::Wrapper: return "ARMISD::Wrapper";
397 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
398 case ARMISD::CALL: return "ARMISD::CALL";
399 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
400 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
401 case ARMISD::tCALL: return "ARMISD::tCALL";
402 case ARMISD::BRCOND: return "ARMISD::BRCOND";
403 case ARMISD::BR_JT: return "ARMISD::BR_JT";
404 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
405 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
406 case ARMISD::CMP: return "ARMISD::CMP";
407 case ARMISD::CMPZ: return "ARMISD::CMPZ";
408 case ARMISD::CMPFP: return "ARMISD::CMPFP";
409 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
410 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
411 case ARMISD::CMOV: return "ARMISD::CMOV";
412 case ARMISD::CNEG: return "ARMISD::CNEG";
414 case ARMISD::FTOSI: return "ARMISD::FTOSI";
415 case ARMISD::FTOUI: return "ARMISD::FTOUI";
416 case ARMISD::SITOF: return "ARMISD::SITOF";
417 case ARMISD::UITOF: return "ARMISD::UITOF";
419 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
420 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
421 case ARMISD::RRX: return "ARMISD::RRX";
423 case ARMISD::FMRRD: return "ARMISD::FMRRD";
424 case ARMISD::FMDRR: return "ARMISD::FMDRR";
426 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
428 case ARMISD::VCEQ: return "ARMISD::VCEQ";
429 case ARMISD::VCGE: return "ARMISD::VCGE";
430 case ARMISD::VCGEU: return "ARMISD::VCGEU";
431 case ARMISD::VCGT: return "ARMISD::VCGT";
432 case ARMISD::VCGTU: return "ARMISD::VCGTU";
433 case ARMISD::VTST: return "ARMISD::VTST";
435 case ARMISD::VSHL: return "ARMISD::VSHL";
436 case ARMISD::VSHRs: return "ARMISD::VSHRs";
437 case ARMISD::VSHRu: return "ARMISD::VSHRu";
438 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
439 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
440 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
441 case ARMISD::VSHRN: return "ARMISD::VSHRN";
442 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
443 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
444 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
445 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
446 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
447 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
448 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
449 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
450 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
451 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
452 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
453 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
454 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
455 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
456 case ARMISD::VDUPLANEQ: return "ARMISD::VDUPLANEQ";
460 /// getFunctionAlignment - Return the Log2 alignment of this function.
461 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
462 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
465 //===----------------------------------------------------------------------===//
467 //===----------------------------------------------------------------------===//
469 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
470 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
472 default: assert(0 && "Unknown condition code!");
473 case ISD::SETNE: return ARMCC::NE;
474 case ISD::SETEQ: return ARMCC::EQ;
475 case ISD::SETGT: return ARMCC::GT;
476 case ISD::SETGE: return ARMCC::GE;
477 case ISD::SETLT: return ARMCC::LT;
478 case ISD::SETLE: return ARMCC::LE;
479 case ISD::SETUGT: return ARMCC::HI;
480 case ISD::SETUGE: return ARMCC::HS;
481 case ISD::SETULT: return ARMCC::LO;
482 case ISD::SETULE: return ARMCC::LS;
486 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
487 /// returns true if the operands should be inverted to form the proper
489 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
490 ARMCC::CondCodes &CondCode2) {
492 CondCode2 = ARMCC::AL;
494 default: assert(0 && "Unknown FP condition!");
496 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
498 case ISD::SETOGT: CondCode = ARMCC::GT; break;
500 case ISD::SETOGE: CondCode = ARMCC::GE; break;
501 case ISD::SETOLT: CondCode = ARMCC::MI; break;
502 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
503 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
504 case ISD::SETO: CondCode = ARMCC::VC; break;
505 case ISD::SETUO: CondCode = ARMCC::VS; break;
506 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
507 case ISD::SETUGT: CondCode = ARMCC::HI; break;
508 case ISD::SETUGE: CondCode = ARMCC::PL; break;
510 case ISD::SETULT: CondCode = ARMCC::LT; break;
512 case ISD::SETULE: CondCode = ARMCC::LE; break;
514 case ISD::SETUNE: CondCode = ARMCC::NE; break;
519 //===----------------------------------------------------------------------===//
520 // Calling Convention Implementation
522 // The lower operations present on calling convention works on this order:
523 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
524 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
525 // LowerRET (virt regs --> phys regs)
526 // LowerCALL (phys regs --> virt regs)
528 //===----------------------------------------------------------------------===//
530 #include "ARMGenCallingConv.inc"
532 // APCS f64 is in register pairs, possibly split to stack
533 static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
534 CCValAssign::LocInfo &LocInfo,
535 CCState &State, bool CanFail) {
536 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
538 // Try to get the first register.
539 if (unsigned Reg = State.AllocateReg(RegList, 4))
540 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
542 // For the 2nd half of a v2f64, do not fail.
546 // Put the whole thing on the stack.
547 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
548 State.AllocateStack(8, 4),
553 // Try to get the second register.
554 if (unsigned Reg = State.AllocateReg(RegList, 4))
555 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
557 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
558 State.AllocateStack(4, 4),
563 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
564 CCValAssign::LocInfo &LocInfo,
565 ISD::ArgFlagsTy &ArgFlags,
567 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
569 if (LocVT == MVT::v2f64 &&
570 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
572 return true; // we handled it
575 // AAPCS f64 is in aligned register pairs
576 static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
577 CCValAssign::LocInfo &LocInfo,
578 CCState &State, bool CanFail) {
579 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
580 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
582 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
584 // For the 2nd half of a v2f64, do not just fail.
588 // Put the whole thing on the stack.
589 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
590 State.AllocateStack(8, 8),
596 for (i = 0; i < 2; ++i)
597 if (HiRegList[i] == Reg)
600 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
601 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
606 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
607 CCValAssign::LocInfo &LocInfo,
608 ISD::ArgFlagsTy &ArgFlags,
610 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
612 if (LocVT == MVT::v2f64 &&
613 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
615 return true; // we handled it
618 static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
619 CCValAssign::LocInfo &LocInfo, CCState &State) {
620 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
621 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
623 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
625 return false; // we didn't handle it
628 for (i = 0; i < 2; ++i)
629 if (HiRegList[i] == Reg)
632 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
633 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
638 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
639 CCValAssign::LocInfo &LocInfo,
640 ISD::ArgFlagsTy &ArgFlags,
642 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
644 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
646 return true; // we handled it
649 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
650 CCValAssign::LocInfo &LocInfo,
651 ISD::ArgFlagsTy &ArgFlags,
653 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
657 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
658 /// given CallingConvention value.
659 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
663 assert(0 && "Unsupported calling convention");
665 case CallingConv::Fast:
666 // Use target triple & subtarget features to do actual dispatch.
667 if (Subtarget->isAAPCS_ABI()) {
668 if (Subtarget->hasVFP2() &&
669 FloatABIType == FloatABI::Hard)
670 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
672 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
674 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
675 case CallingConv::ARM_AAPCS_VFP:
676 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
677 case CallingConv::ARM_AAPCS:
678 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
679 case CallingConv::ARM_APCS:
680 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
684 /// LowerCallResult - Lower the result values of an ISD::CALL into the
685 /// appropriate copies out of appropriate physical registers. This assumes that
686 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
687 /// being lowered. The returns a SDNode with the same number of values as the
689 SDNode *ARMTargetLowering::
690 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
691 unsigned CallingConv, SelectionDAG &DAG) {
693 DebugLoc dl = TheCall->getDebugLoc();
694 // Assign locations to each value returned by this call.
695 SmallVector<CCValAssign, 16> RVLocs;
696 bool isVarArg = TheCall->isVarArg();
697 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
698 CCInfo.AnalyzeCallResult(TheCall,
699 CCAssignFnForNode(CallingConv, /* Return*/ true));
701 SmallVector<SDValue, 8> ResultVals;
703 // Copy all of the result registers out of their specified physreg.
704 for (unsigned i = 0; i != RVLocs.size(); ++i) {
705 CCValAssign VA = RVLocs[i];
708 if (VA.needsCustom()) {
709 // Handle f64 or half of a v2f64.
710 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
712 Chain = Lo.getValue(1);
713 InFlag = Lo.getValue(2);
714 VA = RVLocs[++i]; // skip ahead to next loc
715 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
717 Chain = Hi.getValue(1);
718 InFlag = Hi.getValue(2);
719 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
721 if (VA.getLocVT() == MVT::v2f64) {
722 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
723 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
724 DAG.getConstant(0, MVT::i32));
726 VA = RVLocs[++i]; // skip ahead to next loc
727 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
728 Chain = Lo.getValue(1);
729 InFlag = Lo.getValue(2);
730 VA = RVLocs[++i]; // skip ahead to next loc
731 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
732 Chain = Hi.getValue(1);
733 InFlag = Hi.getValue(2);
734 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
735 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
736 DAG.getConstant(1, MVT::i32));
739 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
741 Chain = Val.getValue(1);
742 InFlag = Val.getValue(2);
745 switch (VA.getLocInfo()) {
746 default: assert(0 && "Unknown loc info!");
747 case CCValAssign::Full: break;
748 case CCValAssign::BCvt:
749 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
753 ResultVals.push_back(Val);
756 // Merge everything together with a MERGE_VALUES node.
757 ResultVals.push_back(Chain);
758 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
759 &ResultVals[0], ResultVals.size()).getNode();
762 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
763 /// by "Src" to address "Dst" of size "Size". Alignment information is
764 /// specified by the specific parameter attribute. The copy will be passed as
765 /// a byval function parameter.
766 /// Sometimes what we are copying is the end of a larger object, the part that
767 /// does not fit in registers.
769 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
770 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
772 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
773 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
774 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
777 /// LowerMemOpCallTo - Store the argument to the stack.
779 ARMTargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
780 const SDValue &StackPtr,
781 const CCValAssign &VA, SDValue Chain,
782 SDValue Arg, ISD::ArgFlagsTy Flags) {
783 DebugLoc dl = TheCall->getDebugLoc();
784 unsigned LocMemOffset = VA.getLocMemOffset();
785 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
786 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
787 if (Flags.isByVal()) {
788 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
790 return DAG.getStore(Chain, dl, Arg, PtrOff,
791 PseudoSourceValue::getStack(), LocMemOffset);
794 void ARMTargetLowering::PassF64ArgInRegs(CallSDNode *TheCall, SelectionDAG &DAG,
795 SDValue Chain, SDValue &Arg,
796 RegsToPassVector &RegsToPass,
797 CCValAssign &VA, CCValAssign &NextVA,
799 SmallVector<SDValue, 8> &MemOpChains,
800 ISD::ArgFlagsTy Flags) {
801 DebugLoc dl = TheCall->getDebugLoc();
803 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
804 DAG.getVTList(MVT::i32, MVT::i32), Arg);
805 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
807 if (NextVA.isRegLoc())
808 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
810 assert(NextVA.isMemLoc());
811 if (StackPtr.getNode() == 0)
812 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
814 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, NextVA,
815 Chain, fmrrd.getValue(1), Flags));
819 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
820 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
822 SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
823 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
824 MVT RetVT = TheCall->getRetValType(0);
825 SDValue Chain = TheCall->getChain();
826 unsigned CC = TheCall->getCallingConv();
827 bool isVarArg = TheCall->isVarArg();
828 SDValue Callee = TheCall->getCallee();
829 DebugLoc dl = TheCall->getDebugLoc();
831 // Analyze operands of the call, assigning locations to each operand.
832 SmallVector<CCValAssign, 16> ArgLocs;
833 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
834 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC, /* Return*/ false));
836 // Get a count of how many bytes are to be pushed on the stack.
837 unsigned NumBytes = CCInfo.getNextStackOffset();
839 // Adjust the stack pointer for the new arguments...
840 // These operations are automatically eliminated by the prolog/epilog pass
841 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
843 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
845 RegsToPassVector RegsToPass;
846 SmallVector<SDValue, 8> MemOpChains;
848 // Walk the register/memloc assignments, inserting copies/loads. In the case
849 // of tail call optimization, arguments are handled later.
850 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
853 CCValAssign &VA = ArgLocs[i];
854 SDValue Arg = TheCall->getArg(realArgIdx);
855 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(realArgIdx);
857 // Promote the value if needed.
858 switch (VA.getLocInfo()) {
859 default: assert(0 && "Unknown loc info!");
860 case CCValAssign::Full: break;
861 case CCValAssign::SExt:
862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
864 case CCValAssign::ZExt:
865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
867 case CCValAssign::AExt:
868 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
870 case CCValAssign::BCvt:
871 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
875 // f64 and v2f64 are passed in i32 pairs and must be split into pieces
876 if (VA.needsCustom()) {
877 if (VA.getLocVT() == MVT::v2f64) {
878 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
879 DAG.getConstant(0, MVT::i32));
880 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
881 DAG.getConstant(1, MVT::i32));
883 PassF64ArgInRegs(TheCall, DAG, Chain, Op0, RegsToPass,
884 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
886 VA = ArgLocs[++i]; // skip ahead to next loc
888 PassF64ArgInRegs(TheCall, DAG, Chain, Op1, RegsToPass,
889 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
891 assert(VA.isMemLoc());
892 if (StackPtr.getNode() == 0)
893 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
895 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
899 PassF64ArgInRegs(TheCall, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
900 StackPtr, MemOpChains, Flags);
902 } else if (VA.isRegLoc()) {
903 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
905 assert(VA.isMemLoc());
906 if (StackPtr.getNode() == 0)
907 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
909 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
914 if (!MemOpChains.empty())
915 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
916 &MemOpChains[0], MemOpChains.size());
918 // Build a sequence of copy-to-reg nodes chained together with token chain
919 // and flag operands which copy the outgoing args into the appropriate regs.
921 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
922 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
923 RegsToPass[i].second, InFlag);
924 InFlag = Chain.getValue(1);
927 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
928 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
929 // node so that legalize doesn't hack it.
930 bool isDirect = false;
931 bool isARMFunc = false;
932 bool isLocalARMFunc = false;
933 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
934 GlobalValue *GV = G->getGlobal();
936 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
937 GV->hasLinkOnceLinkage());
938 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
939 getTargetMachine().getRelocationModel() != Reloc::Static;
940 isARMFunc = !Subtarget->isThumb() || isStub;
941 // ARM call to a local ARM function is predicable.
942 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
943 // tBX takes a register source operand.
944 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
945 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
947 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
948 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
949 Callee = DAG.getLoad(getPointerTy(), dl,
950 DAG.getEntryNode(), CPAddr, NULL, 0);
951 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
952 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
953 getPointerTy(), Callee, PICLabel);
955 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
956 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
958 bool isStub = Subtarget->isTargetDarwin() &&
959 getTargetMachine().getRelocationModel() != Reloc::Static;
960 isARMFunc = !Subtarget->isThumb() || isStub;
961 // tBX takes a register source operand.
962 const char *Sym = S->getSymbol();
963 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
964 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
966 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
967 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
968 Callee = DAG.getLoad(getPointerTy(), dl,
969 DAG.getEntryNode(), CPAddr, NULL, 0);
970 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
971 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
972 getPointerTy(), Callee, PICLabel);
974 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
977 // FIXME: handle tail calls differently.
979 if (Subtarget->isThumb()) {
980 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
981 CallOpc = ARMISD::CALL_NOLINK;
983 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
985 CallOpc = (isDirect || Subtarget->hasV5TOps())
986 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
987 : ARMISD::CALL_NOLINK;
989 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
990 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
991 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
992 InFlag = Chain.getValue(1);
995 std::vector<SDValue> Ops;
996 Ops.push_back(Chain);
997 Ops.push_back(Callee);
999 // Add argument registers to the end of the list so that they are known live
1001 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1002 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1003 RegsToPass[i].second.getValueType()));
1005 if (InFlag.getNode())
1006 Ops.push_back(InFlag);
1007 // Returns a chain and a flag for retval copy to use.
1008 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1009 &Ops[0], Ops.size());
1010 InFlag = Chain.getValue(1);
1012 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1013 DAG.getIntPtrConstant(0, true), InFlag);
1014 if (RetVT != MVT::Other)
1015 InFlag = Chain.getValue(1);
1017 // Handle result values, copying them out of physregs into vregs that we
1019 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1023 SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1024 // The chain is always operand #0
1025 SDValue Chain = Op.getOperand(0);
1026 DebugLoc dl = Op.getDebugLoc();
1028 // CCValAssign - represent the assignment of the return value to a location.
1029 SmallVector<CCValAssign, 16> RVLocs;
1030 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1031 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1033 // CCState - Info about the registers and stack slots.
1034 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
1036 // Analyze return values of ISD::RET.
1037 CCInfo.AnalyzeReturn(Op.getNode(), CCAssignFnForNode(CC, /* Return */ true));
1039 // If this is the first return lowered for this function, add
1040 // the regs to the liveout set for the function.
1041 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1042 for (unsigned i = 0; i != RVLocs.size(); ++i)
1043 if (RVLocs[i].isRegLoc())
1044 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1049 // Copy the result values into the output registers.
1050 for (unsigned i = 0, realRVLocIdx = 0;
1052 ++i, ++realRVLocIdx) {
1053 CCValAssign &VA = RVLocs[i];
1054 assert(VA.isRegLoc() && "Can only return in registers!");
1056 // ISD::RET => ret chain, (regnum1,val1), ...
1057 // So i*2+1 index only the regnums
1058 SDValue Arg = Op.getOperand(realRVLocIdx*2+1);
1060 switch (VA.getLocInfo()) {
1061 default: assert(0 && "Unknown loc info!");
1062 case CCValAssign::Full: break;
1063 case CCValAssign::BCvt:
1064 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1068 if (VA.needsCustom()) {
1069 if (VA.getLocVT() == MVT::v2f64) {
1070 // Extract the first half and return it in two registers.
1071 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1072 DAG.getConstant(0, MVT::i32));
1073 SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
1074 DAG.getVTList(MVT::i32, MVT::i32), Half);
1076 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1077 Flag = Chain.getValue(1);
1078 VA = RVLocs[++i]; // skip ahead to next loc
1079 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1080 HalfGPRs.getValue(1), Flag);
1081 Flag = Chain.getValue(1);
1082 VA = RVLocs[++i]; // skip ahead to next loc
1084 // Extract the 2nd half and fall through to handle it as an f64 value.
1085 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1086 DAG.getConstant(1, MVT::i32));
1088 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1090 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
1091 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1092 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1093 Flag = Chain.getValue(1);
1094 VA = RVLocs[++i]; // skip ahead to next loc
1095 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1098 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1100 // Guarantee that all emitted copies are
1101 // stuck together, avoiding something bad.
1102 Flag = Chain.getValue(1);
1107 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1109 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1114 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1115 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
1116 // one of the above mentioned nodes. It has to be wrapped because otherwise
1117 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1118 // be used to form addressing mode. These wrapped nodes will be selected
1120 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1121 MVT PtrVT = Op.getValueType();
1122 // FIXME there is no actual debug info here
1123 DebugLoc dl = Op.getDebugLoc();
1124 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1126 if (CP->isMachineConstantPoolEntry())
1127 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1128 CP->getAlignment());
1130 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1131 CP->getAlignment());
1132 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1135 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1137 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1138 SelectionDAG &DAG) {
1139 DebugLoc dl = GA->getDebugLoc();
1140 MVT PtrVT = getPointerTy();
1141 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1142 ARMConstantPoolValue *CPV =
1143 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1144 PCAdj, "tlsgd", true);
1145 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1146 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1147 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
1148 SDValue Chain = Argument.getValue(1);
1150 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1151 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1153 // call __tls_get_addr.
1156 Entry.Node = Argument;
1157 Entry.Ty = (const Type *) Type::Int32Ty;
1158 Args.push_back(Entry);
1159 // FIXME: is there useful debug info available here?
1160 std::pair<SDValue, SDValue> CallResult =
1161 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
1162 0, CallingConv::C, false,
1163 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1164 return CallResult.first;
1167 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1168 // "local exec" model.
1170 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1171 SelectionDAG &DAG) {
1172 GlobalValue *GV = GA->getGlobal();
1173 DebugLoc dl = GA->getDebugLoc();
1175 SDValue Chain = DAG.getEntryNode();
1176 MVT PtrVT = getPointerTy();
1177 // Get the Thread Pointer
1178 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1180 if (GV->isDeclaration()){
1181 // initial exec model
1182 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1183 ARMConstantPoolValue *CPV =
1184 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1185 PCAdj, "gottpoff", true);
1186 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1187 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1188 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1189 Chain = Offset.getValue(1);
1191 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1192 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1194 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1197 ARMConstantPoolValue *CPV =
1198 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
1199 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1200 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1201 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1204 // The address of the thread local variable is the add of the thread
1205 // pointer with the offset of the variable.
1206 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1210 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1211 // TODO: implement the "local dynamic" model
1212 assert(Subtarget->isTargetELF() &&
1213 "TLS not implemented for non-ELF targets");
1214 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1215 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1216 // otherwise use the "Local Exec" TLS Model
1217 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1218 return LowerToTLSGeneralDynamicModel(GA, DAG);
1220 return LowerToTLSExecModels(GA, DAG);
1223 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1224 SelectionDAG &DAG) {
1225 MVT PtrVT = getPointerTy();
1226 DebugLoc dl = Op.getDebugLoc();
1227 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1228 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1229 if (RelocM == Reloc::PIC_) {
1230 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1231 ARMConstantPoolValue *CPV =
1232 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
1233 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1234 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1235 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1237 SDValue Chain = Result.getValue(1);
1238 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1239 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1241 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1244 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1245 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1246 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1250 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
1251 /// even in non-static mode.
1252 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
1253 // If symbol visibility is hidden, the extra load is not needed if
1254 // the symbol is definitely defined in the current translation unit.
1255 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
1256 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
1258 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
1261 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1262 SelectionDAG &DAG) {
1263 MVT PtrVT = getPointerTy();
1264 DebugLoc dl = Op.getDebugLoc();
1265 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1266 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1267 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
1269 if (RelocM == Reloc::Static)
1270 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1272 unsigned PCAdj = (RelocM != Reloc::PIC_)
1273 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1274 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1276 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1278 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1280 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1282 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1283 SDValue Chain = Result.getValue(1);
1285 if (RelocM == Reloc::PIC_) {
1286 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1287 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1290 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1295 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1297 assert(Subtarget->isTargetELF() &&
1298 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1299 MVT PtrVT = getPointerTy();
1300 DebugLoc dl = Op.getDebugLoc();
1301 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1302 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
1304 ARMCP::CPValue, PCAdj);
1305 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1306 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1307 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1308 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1309 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1313 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1314 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1315 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1316 DebugLoc dl = Op.getDebugLoc();
1318 default: return SDValue(); // Don't custom lower most intrinsics.
1319 case Intrinsic::arm_thread_pointer:
1320 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1321 case Intrinsic::eh_sjlj_setjmp:
1322 SDValue Res = DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32,
1328 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1329 unsigned VarArgsFrameIndex) {
1330 // vastart just stores the address of the VarArgsFrameIndex slot into the
1331 // memory location argument.
1332 DebugLoc dl = Op.getDebugLoc();
1333 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1334 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1335 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1336 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1340 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1341 SDValue &Root, SelectionDAG &DAG,
1343 MachineFunction &MF = DAG.getMachineFunction();
1344 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1346 TargetRegisterClass *RC;
1347 if (AFI->isThumbFunction())
1348 RC = ARM::tGPRRegisterClass;
1350 RC = ARM::GPRRegisterClass;
1352 // Transform the arguments stored in physical registers into virtual ones.
1353 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1354 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1357 if (NextVA.isMemLoc()) {
1358 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1359 MachineFrameInfo *MFI = MF.getFrameInfo();
1360 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset());
1362 // Create load node to retrieve arguments from the stack.
1363 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1364 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1366 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1367 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1370 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
1374 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1375 MachineFunction &MF = DAG.getMachineFunction();
1376 MachineFrameInfo *MFI = MF.getFrameInfo();
1378 SDValue Root = Op.getOperand(0);
1379 DebugLoc dl = Op.getDebugLoc();
1380 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1381 unsigned CC = MF.getFunction()->getCallingConv();
1382 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1384 // Assign locations to all of the incoming arguments.
1385 SmallVector<CCValAssign, 16> ArgLocs;
1386 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1387 CCInfo.AnalyzeFormalArguments(Op.getNode(),
1388 CCAssignFnForNode(CC, /* Return*/ false));
1390 SmallVector<SDValue, 16> ArgValues;
1392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1393 CCValAssign &VA = ArgLocs[i];
1395 // Arguments stored in registers.
1396 if (VA.isRegLoc()) {
1397 MVT RegVT = VA.getLocVT();
1400 if (VA.needsCustom()) {
1401 // f64 and vector types are split up into multiple registers or
1402 // combinations of registers and stack slots.
1405 if (VA.getLocVT() == MVT::v2f64) {
1406 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1408 VA = ArgLocs[++i]; // skip ahead to next loc
1409 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1411 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1412 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1413 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1414 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1415 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1417 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Root, DAG, dl);
1420 TargetRegisterClass *RC;
1421 if (FloatABIType == FloatABI::Hard && RegVT == MVT::f32)
1422 RC = ARM::SPRRegisterClass;
1423 else if (FloatABIType == FloatABI::Hard && RegVT == MVT::f64)
1424 RC = ARM::DPRRegisterClass;
1425 else if (AFI->isThumbFunction())
1426 RC = ARM::tGPRRegisterClass;
1428 RC = ARM::GPRRegisterClass;
1430 assert((RegVT == MVT::i32 || RegVT == MVT::f32 ||
1431 (FloatABIType == FloatABI::Hard && RegVT == MVT::f64)) &&
1432 "RegVT not supported by FORMAL_ARGUMENTS Lowering");
1434 // Transform the arguments in physical registers into virtual ones.
1435 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1436 ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1439 // If this is an 8 or 16-bit value, it is really passed promoted
1440 // to 32 bits. Insert an assert[sz]ext to capture this, then
1441 // truncate to the right size.
1442 switch (VA.getLocInfo()) {
1443 default: assert(0 && "Unknown loc info!");
1444 case CCValAssign::Full: break;
1445 case CCValAssign::BCvt:
1446 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1448 case CCValAssign::SExt:
1449 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1450 DAG.getValueType(VA.getValVT()));
1451 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1453 case CCValAssign::ZExt:
1454 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1455 DAG.getValueType(VA.getValVT()));
1456 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1460 ArgValues.push_back(ArgValue);
1462 } else { // VA.isRegLoc()
1465 assert(VA.isMemLoc());
1466 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1468 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1469 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1471 // Create load nodes to retrieve arguments from the stack.
1472 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1473 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1479 static const unsigned GPRArgRegs[] = {
1480 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1483 unsigned NumGPRs = CCInfo.getFirstUnallocated
1484 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1486 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1487 unsigned VARegSize = (4 - NumGPRs) * 4;
1488 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1489 unsigned ArgOffset = 0;
1490 if (VARegSaveSize) {
1491 // If this function is vararg, store any remaining integer argument regs
1492 // to their spots on the stack so that they may be loaded by deferencing
1493 // the result of va_next.
1494 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1495 ArgOffset = CCInfo.getNextStackOffset();
1496 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1497 VARegSaveSize - VARegSize);
1498 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1500 SmallVector<SDValue, 4> MemOps;
1501 for (; NumGPRs < 4; ++NumGPRs) {
1502 TargetRegisterClass *RC;
1503 if (AFI->isThumbFunction())
1504 RC = ARM::tGPRRegisterClass;
1506 RC = ARM::GPRRegisterClass;
1508 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1509 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1510 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1511 MemOps.push_back(Store);
1512 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1513 DAG.getConstant(4, getPointerTy()));
1515 if (!MemOps.empty())
1516 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1517 &MemOps[0], MemOps.size());
1519 // This will point to the next argument passed via stack.
1520 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1523 ArgValues.push_back(Root);
1525 // Return the new list of results.
1526 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1527 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1530 /// isFloatingPointZero - Return true if this is +0.0.
1531 static bool isFloatingPointZero(SDValue Op) {
1532 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1533 return CFP->getValueAPF().isPosZero();
1534 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1535 // Maybe this has already been legalized into the constant pool?
1536 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1537 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1538 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1539 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1540 return CFP->getValueAPF().isPosZero();
1546 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1547 return ( isThumb && (C & ~255U) == 0) ||
1548 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1551 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1552 /// the given operands.
1553 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1554 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb,
1556 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1557 unsigned C = RHSC->getZExtValue();
1558 if (!isLegalCmpImmediate(C, isThumb)) {
1559 // Constant does not fit, try adjusting it by one?
1564 if (isLegalCmpImmediate(C-1, isThumb)) {
1565 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1566 RHS = DAG.getConstant(C-1, MVT::i32);
1571 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1572 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1573 RHS = DAG.getConstant(C-1, MVT::i32);
1578 if (isLegalCmpImmediate(C+1, isThumb)) {
1579 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1580 RHS = DAG.getConstant(C+1, MVT::i32);
1585 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1586 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1587 RHS = DAG.getConstant(C+1, MVT::i32);
1594 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1595 ARMISD::NodeType CompareType;
1598 CompareType = ARMISD::CMP;
1603 CompareType = ARMISD::CMPZ;
1606 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1607 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1610 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1611 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1614 if (!isFloatingPointZero(RHS))
1615 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1617 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1618 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1621 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1622 const ARMSubtarget *ST) {
1623 MVT VT = Op.getValueType();
1624 SDValue LHS = Op.getOperand(0);
1625 SDValue RHS = Op.getOperand(1);
1626 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1627 SDValue TrueVal = Op.getOperand(2);
1628 SDValue FalseVal = Op.getOperand(3);
1629 DebugLoc dl = Op.getDebugLoc();
1631 if (LHS.getValueType() == MVT::i32) {
1633 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1634 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1635 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1638 ARMCC::CondCodes CondCode, CondCode2;
1639 if (FPCCToARMCC(CC, CondCode, CondCode2))
1640 std::swap(TrueVal, FalseVal);
1642 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1643 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1644 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1645 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1647 if (CondCode2 != ARMCC::AL) {
1648 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1649 // FIXME: Needs another CMP because flag can have but one use.
1650 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1651 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1652 Result, TrueVal, ARMCC2, CCR, Cmp2);
1657 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1658 const ARMSubtarget *ST) {
1659 SDValue Chain = Op.getOperand(0);
1660 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1661 SDValue LHS = Op.getOperand(2);
1662 SDValue RHS = Op.getOperand(3);
1663 SDValue Dest = Op.getOperand(4);
1664 DebugLoc dl = Op.getDebugLoc();
1666 if (LHS.getValueType() == MVT::i32) {
1668 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1669 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1670 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1671 Chain, Dest, ARMCC, CCR,Cmp);
1674 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1675 ARMCC::CondCodes CondCode, CondCode2;
1676 if (FPCCToARMCC(CC, CondCode, CondCode2))
1677 // Swap the LHS/RHS of the comparison if needed.
1678 std::swap(LHS, RHS);
1680 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1681 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1682 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1683 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1684 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1685 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1686 if (CondCode2 != ARMCC::AL) {
1687 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1688 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1689 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1694 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1695 SDValue Chain = Op.getOperand(0);
1696 SDValue Table = Op.getOperand(1);
1697 SDValue Index = Op.getOperand(2);
1698 DebugLoc dl = Op.getDebugLoc();
1700 MVT PTy = getPointerTy();
1701 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1702 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1703 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1704 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1705 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1706 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1707 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1708 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1709 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl,
1710 Chain, Addr, NULL, 0);
1711 Chain = Addr.getValue(1);
1713 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1714 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1717 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1718 DebugLoc dl = Op.getDebugLoc();
1720 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1721 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1722 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1725 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1726 MVT VT = Op.getValueType();
1727 DebugLoc dl = Op.getDebugLoc();
1729 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1731 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1732 return DAG.getNode(Opc, dl, VT, Op);
1735 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1736 // Implement fcopysign with a fabs and a conditional fneg.
1737 SDValue Tmp0 = Op.getOperand(0);
1738 SDValue Tmp1 = Op.getOperand(1);
1739 DebugLoc dl = Op.getDebugLoc();
1740 MVT VT = Op.getValueType();
1741 MVT SrcVT = Tmp1.getValueType();
1742 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1743 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1744 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1745 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1746 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1749 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1750 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1751 MFI->setFrameAddressIsTaken(true);
1752 MVT VT = Op.getValueType();
1753 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1754 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1755 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1756 ? ARM::R7 : ARM::R11;
1757 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1759 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1764 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1766 SDValue Dst, SDValue Src,
1767 SDValue Size, unsigned Align,
1769 const Value *DstSV, uint64_t DstSVOff,
1770 const Value *SrcSV, uint64_t SrcSVOff){
1771 // Do repeated 4-byte loads and stores. To be improved.
1772 // This requires 4-byte alignment.
1773 if ((Align & 3) != 0)
1775 // This requires the copy size to be a constant, preferrably
1776 // within a subtarget-specific limit.
1777 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1780 uint64_t SizeVal = ConstantSize->getZExtValue();
1781 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1784 unsigned BytesLeft = SizeVal & 3;
1785 unsigned NumMemOps = SizeVal >> 2;
1786 unsigned EmittedNumMemOps = 0;
1788 unsigned VTSize = 4;
1790 const unsigned MAX_LOADS_IN_LDM = 6;
1791 SDValue TFOps[MAX_LOADS_IN_LDM];
1792 SDValue Loads[MAX_LOADS_IN_LDM];
1793 uint64_t SrcOff = 0, DstOff = 0;
1795 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1796 // same number of stores. The loads and stores will get combined into
1797 // ldm/stm later on.
1798 while (EmittedNumMemOps < NumMemOps) {
1800 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1801 Loads[i] = DAG.getLoad(VT, dl, Chain,
1802 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1803 DAG.getConstant(SrcOff, MVT::i32)),
1804 SrcSV, SrcSVOff + SrcOff);
1805 TFOps[i] = Loads[i].getValue(1);
1808 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1811 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1812 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1813 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1814 DAG.getConstant(DstOff, MVT::i32)),
1815 DstSV, DstSVOff + DstOff);
1818 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1820 EmittedNumMemOps += i;
1826 // Issue loads / stores for the trailing (1 - 3) bytes.
1827 unsigned BytesLeftSave = BytesLeft;
1830 if (BytesLeft >= 2) {
1838 Loads[i] = DAG.getLoad(VT, dl, Chain,
1839 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1840 DAG.getConstant(SrcOff, MVT::i32)),
1841 SrcSV, SrcSVOff + SrcOff);
1842 TFOps[i] = Loads[i].getValue(1);
1845 BytesLeft -= VTSize;
1847 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1850 BytesLeft = BytesLeftSave;
1852 if (BytesLeft >= 2) {
1860 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1861 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1862 DAG.getConstant(DstOff, MVT::i32)),
1863 DstSV, DstSVOff + DstOff);
1866 BytesLeft -= VTSize;
1868 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1871 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1872 SDValue Op = N->getOperand(0);
1873 DebugLoc dl = N->getDebugLoc();
1874 if (N->getValueType(0) == MVT::f64) {
1875 // Turn i64->f64 into FMDRR.
1876 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1877 DAG.getConstant(0, MVT::i32));
1878 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1879 DAG.getConstant(1, MVT::i32));
1880 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
1883 // Turn f64->i64 into FMRRD.
1884 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
1885 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
1887 // Merge the pieces into a single i64 value.
1888 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
1891 /// getZeroVector - Returns a vector of specified type with all zero elements.
1893 static SDValue getZeroVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
1894 assert(VT.isVector() && "Expected a vector type");
1896 // Zero vectors are used to represent vector negation and in those cases
1897 // will be implemented with the NEON VNEG instruction. However, VNEG does
1898 // not support i64 elements, so sometimes the zero vectors will need to be
1899 // explicitly constructed. For those cases, and potentially other uses in
1900 // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
1901 // to their dest type. This ensures they get CSE'd.
1903 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
1904 if (VT.getSizeInBits() == 64)
1905 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
1907 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
1909 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
1912 /// getOnesVector - Returns a vector of specified type with all bits set.
1914 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
1915 assert(VT.isVector() && "Expected a vector type");
1917 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
1918 // type. This ensures they get CSE'd.
1920 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
1921 if (VT.getSizeInBits() == 64)
1922 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
1924 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
1926 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
1929 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
1930 const ARMSubtarget *ST) {
1931 MVT VT = N->getValueType(0);
1932 DebugLoc dl = N->getDebugLoc();
1934 // Lower vector shifts on NEON to use VSHL.
1935 if (VT.isVector()) {
1936 assert(ST->hasNEON() && "unexpected vector shift");
1938 // Left shifts translate directly to the vshiftu intrinsic.
1939 if (N->getOpcode() == ISD::SHL)
1940 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
1941 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
1942 N->getOperand(0), N->getOperand(1));
1944 assert((N->getOpcode() == ISD::SRA ||
1945 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
1947 // NEON uses the same intrinsics for both left and right shifts. For
1948 // right shifts, the shift amounts are negative, so negate the vector of
1950 MVT ShiftVT = N->getOperand(1).getValueType();
1951 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
1952 getZeroVector(ShiftVT, DAG, dl),
1954 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
1955 Intrinsic::arm_neon_vshifts :
1956 Intrinsic::arm_neon_vshiftu);
1957 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
1958 DAG.getConstant(vshiftInt, MVT::i32),
1959 N->getOperand(0), NegatedCount);
1962 assert(VT == MVT::i64 &&
1963 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1964 "Unknown shift to lower!");
1966 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1967 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1968 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
1971 // If we are in thumb mode, we don't have RRX.
1972 if (ST->isThumb()) return SDValue();
1974 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1975 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1976 DAG.getConstant(0, MVT::i32));
1977 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1978 DAG.getConstant(1, MVT::i32));
1980 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1981 // captures the result into a carry flag.
1982 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1983 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1985 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1986 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
1988 // Merge the pieces into a single i64 value.
1989 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1992 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
1993 SDValue TmpOp0, TmpOp1;
1994 bool Invert = false;
1998 SDValue Op0 = Op.getOperand(0);
1999 SDValue Op1 = Op.getOperand(1);
2000 SDValue CC = Op.getOperand(2);
2001 MVT VT = Op.getValueType();
2002 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2003 DebugLoc dl = Op.getDebugLoc();
2005 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2006 switch (SetCCOpcode) {
2007 default: assert(0 && "Illegal FP comparison"); break;
2009 case ISD::SETNE: Invert = true; // Fallthrough
2011 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2013 case ISD::SETLT: Swap = true; // Fallthrough
2015 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2017 case ISD::SETLE: Swap = true; // Fallthrough
2019 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2020 case ISD::SETUGE: Swap = true; // Fallthrough
2021 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2022 case ISD::SETUGT: Swap = true; // Fallthrough
2023 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2024 case ISD::SETUEQ: Invert = true; // Fallthrough
2026 // Expand this to (OLT | OGT).
2030 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2031 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2033 case ISD::SETUO: Invert = true; // Fallthrough
2035 // Expand this to (OLT | OGE).
2039 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2040 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2044 // Integer comparisons.
2045 switch (SetCCOpcode) {
2046 default: assert(0 && "Illegal integer comparison"); break;
2047 case ISD::SETNE: Invert = true;
2048 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2049 case ISD::SETLT: Swap = true;
2050 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2051 case ISD::SETLE: Swap = true;
2052 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2053 case ISD::SETULT: Swap = true;
2054 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2055 case ISD::SETULE: Swap = true;
2056 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2059 // Detect VTST (Vector Test Bits) = vicmp ne (and (op0, op1), zero).
2060 if (Opc == ARMISD::VCEQ) {
2063 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2065 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2068 // Ignore bitconvert.
2069 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2070 AndOp = AndOp.getOperand(0);
2072 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2074 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2075 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2082 std::swap(Op0, Op1);
2084 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2087 Result = DAG.getNOT(dl, Result, VT);
2092 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2093 /// VMOV instruction, and if so, return the constant being splatted.
2094 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2095 unsigned SplatBitSize, SelectionDAG &DAG) {
2096 switch (SplatBitSize) {
2098 // Any 1-byte value is OK.
2099 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2100 return DAG.getTargetConstant(SplatBits, MVT::i8);
2103 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2104 if ((SplatBits & ~0xff) == 0 ||
2105 (SplatBits & ~0xff00) == 0)
2106 return DAG.getTargetConstant(SplatBits, MVT::i16);
2110 // NEON's 32-bit VMOV supports splat values where:
2111 // * only one byte is nonzero, or
2112 // * the least significant byte is 0xff and the second byte is nonzero, or
2113 // * the least significant 2 bytes are 0xff and the third is nonzero.
2114 if ((SplatBits & ~0xff) == 0 ||
2115 (SplatBits & ~0xff00) == 0 ||
2116 (SplatBits & ~0xff0000) == 0 ||
2117 (SplatBits & ~0xff000000) == 0)
2118 return DAG.getTargetConstant(SplatBits, MVT::i32);
2120 if ((SplatBits & ~0xffff) == 0 &&
2121 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2122 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2124 if ((SplatBits & ~0xffffff) == 0 &&
2125 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2126 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2128 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2129 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2130 // VMOV.I32. A (very) minor optimization would be to replicate the value
2131 // and fall through here to test for a valid 64-bit splat. But, then the
2132 // caller would also need to check and handle the change in size.
2136 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2137 uint64_t BitMask = 0xff;
2139 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2140 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2142 else if ((SplatBits & BitMask) != 0)
2146 return DAG.getTargetConstant(Val, MVT::i64);
2150 assert(0 && "unexpected size for isVMOVSplat");
2157 /// getVMOVImm - If this is a build_vector of constants which can be
2158 /// formed by using a VMOV instruction of the specified element size,
2159 /// return the constant being splatted. The ByteSize field indicates the
2160 /// number of bytes of each element [1248].
2161 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2162 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2163 APInt SplatBits, SplatUndef;
2164 unsigned SplatBitSize;
2166 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2167 HasAnyUndefs, ByteSize * 8))
2170 if (SplatBitSize > ByteSize * 8)
2173 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2177 static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) {
2178 // Canonicalize all-zeros and all-ones vectors.
2179 ConstantSDNode *ConstVal = dyn_cast<ConstantSDNode>(Val.getNode());
2180 if (ConstVal->isNullValue())
2181 return getZeroVector(VT, DAG, dl);
2182 if (ConstVal->isAllOnesValue())
2183 return getOnesVector(VT, DAG, dl);
2186 if (VT.is64BitVector()) {
2187 switch (Val.getValueType().getSizeInBits()) {
2188 case 8: CanonicalVT = MVT::v8i8; break;
2189 case 16: CanonicalVT = MVT::v4i16; break;
2190 case 32: CanonicalVT = MVT::v2i32; break;
2191 case 64: CanonicalVT = MVT::v1i64; break;
2192 default: assert(0 && "unexpected splat element type"); break;
2195 assert(VT.is128BitVector() && "unknown splat vector size");
2196 switch (Val.getValueType().getSizeInBits()) {
2197 case 8: CanonicalVT = MVT::v16i8; break;
2198 case 16: CanonicalVT = MVT::v8i16; break;
2199 case 32: CanonicalVT = MVT::v4i32; break;
2200 case 64: CanonicalVT = MVT::v2i64; break;
2201 default: assert(0 && "unexpected splat element type"); break;
2205 // Build a canonical splat for this value.
2206 SmallVector<SDValue, 8> Ops;
2207 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2208 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2210 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2213 // If this is a case we can't handle, return null and let the default
2214 // expansion code take care of it.
2215 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2216 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2217 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
2218 DebugLoc dl = Op.getDebugLoc();
2220 APInt SplatBits, SplatUndef;
2221 unsigned SplatBitSize;
2223 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2224 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2225 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2227 return BuildSplat(Val, Op.getValueType(), DAG, dl);
2233 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2237 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
2241 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2242 MVT VT = Op.getValueType();
2243 DebugLoc dl = Op.getDebugLoc();
2244 assert((VT == MVT::i8 || VT == MVT::i16) &&
2245 "unexpected type for custom-lowering vector extract");
2246 SDValue Vec = Op.getOperand(0);
2247 SDValue Lane = Op.getOperand(1);
2248 Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2249 Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
2250 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
2253 static SDValue LowerCONCAT_VECTORS(SDValue Op) {
2254 if (Op.getValueType().is128BitVector() && Op.getNumOperands() == 2)
2259 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2260 switch (Op.getOpcode()) {
2261 default: assert(0 && "Don't know how to custom lower this!"); abort();
2262 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2263 case ISD::GlobalAddress:
2264 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2265 LowerGlobalAddressELF(Op, DAG);
2266 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2267 case ISD::CALL: return LowerCALL(Op, DAG);
2268 case ISD::RET: return LowerRET(Op, DAG);
2269 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
2270 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
2271 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2272 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2273 case ISD::SINT_TO_FP:
2274 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
2275 case ISD::FP_TO_SINT:
2276 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
2277 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
2278 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
2279 case ISD::RETURNADDR: break;
2280 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2281 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2282 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2283 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
2286 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
2287 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
2288 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2289 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2290 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2291 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2292 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op);
2297 /// ReplaceNodeResults - Replace the results of node with an illegal result
2298 /// type with new values built out of custom code.
2299 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2300 SmallVectorImpl<SDValue>&Results,
2301 SelectionDAG &DAG) {
2302 switch (N->getOpcode()) {
2304 assert(0 && "Don't know how to custom expand this!");
2306 case ISD::BIT_CONVERT:
2307 Results.push_back(ExpandBIT_CONVERT(N, DAG));
2311 SDValue Res = LowerShift(N, DAG, Subtarget);
2313 Results.push_back(Res);
2319 //===----------------------------------------------------------------------===//
2320 // ARM Scheduler Hooks
2321 //===----------------------------------------------------------------------===//
2324 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2325 MachineBasicBlock *BB) const {
2326 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2327 DebugLoc dl = MI->getDebugLoc();
2328 switch (MI->getOpcode()) {
2329 default: assert(false && "Unexpected instr type to insert");
2330 case ARM::tMOVCCr: {
2331 // To "insert" a SELECT_CC instruction, we actually have to insert the
2332 // diamond control-flow pattern. The incoming instruction knows the
2333 // destination vreg to set, the condition code register to branch on, the
2334 // true/false values to select between, and a branch opcode to use.
2335 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2336 MachineFunction::iterator It = BB;
2342 // cmpTY ccX, r1, r2
2344 // fallthrough --> copy0MBB
2345 MachineBasicBlock *thisMBB = BB;
2346 MachineFunction *F = BB->getParent();
2347 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2348 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2349 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2350 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2351 F->insert(It, copy0MBB);
2352 F->insert(It, sinkMBB);
2353 // Update machine-CFG edges by first adding all successors of the current
2354 // block to the new block which will contain the Phi node for the select.
2355 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2356 e = BB->succ_end(); i != e; ++i)
2357 sinkMBB->addSuccessor(*i);
2358 // Next, remove all successors of the current block, and add the true
2359 // and fallthrough blocks as its successors.
2360 while(!BB->succ_empty())
2361 BB->removeSuccessor(BB->succ_begin());
2362 BB->addSuccessor(copy0MBB);
2363 BB->addSuccessor(sinkMBB);
2366 // %FalseValue = ...
2367 // # fallthrough to sinkMBB
2370 // Update machine-CFG edges
2371 BB->addSuccessor(sinkMBB);
2374 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2377 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2378 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2379 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2381 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2387 //===----------------------------------------------------------------------===//
2388 // ARM Optimization Hooks
2389 //===----------------------------------------------------------------------===//
2392 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
2393 TargetLowering::DAGCombinerInfo &DCI) {
2394 SelectionDAG &DAG = DCI.DAG;
2395 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2396 MVT VT = N->getValueType(0);
2397 unsigned Opc = N->getOpcode();
2398 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
2399 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
2400 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
2401 ISD::CondCode CC = ISD::SETCC_INVALID;
2404 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
2406 SDValue CCOp = Slct.getOperand(0);
2407 if (CCOp.getOpcode() == ISD::SETCC)
2408 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
2411 bool DoXform = false;
2413 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
2416 if (LHS.getOpcode() == ISD::Constant &&
2417 cast<ConstantSDNode>(LHS)->isNullValue()) {
2419 } else if (CC != ISD::SETCC_INVALID &&
2420 RHS.getOpcode() == ISD::Constant &&
2421 cast<ConstantSDNode>(RHS)->isNullValue()) {
2422 std::swap(LHS, RHS);
2423 SDValue Op0 = Slct.getOperand(0);
2424 MVT OpVT = isSlctCC ? Op0.getValueType() :
2425 Op0.getOperand(0).getValueType();
2426 bool isInt = OpVT.isInteger();
2427 CC = ISD::getSetCCInverse(CC, isInt);
2429 if (!TLI.isCondCodeLegal(CC, OpVT))
2430 return SDValue(); // Inverse operator isn't legal.
2437 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
2439 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
2440 Slct.getOperand(0), Slct.getOperand(1), CC);
2441 SDValue CCOp = Slct.getOperand(0);
2443 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
2444 CCOp.getOperand(0), CCOp.getOperand(1), CC);
2445 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
2446 CCOp, OtherOp, Result);
2451 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
2452 static SDValue PerformADDCombine(SDNode *N,
2453 TargetLowering::DAGCombinerInfo &DCI) {
2454 // added by evan in r37685 with no testcase.
2455 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2457 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
2458 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
2459 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
2460 if (Result.getNode()) return Result;
2462 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2463 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2464 if (Result.getNode()) return Result;
2470 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
2471 static SDValue PerformSUBCombine(SDNode *N,
2472 TargetLowering::DAGCombinerInfo &DCI) {
2473 // added by evan in r37685 with no testcase.
2474 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2476 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
2477 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2478 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2479 if (Result.getNode()) return Result;
2486 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
2487 static SDValue PerformFMRRDCombine(SDNode *N,
2488 TargetLowering::DAGCombinerInfo &DCI) {
2489 // fmrrd(fmdrr x, y) -> x,y
2490 SDValue InDouble = N->getOperand(0);
2491 if (InDouble.getOpcode() == ARMISD::FMDRR)
2492 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
2496 /// getVShiftImm - Check if this is a valid build_vector for the immediate
2497 /// operand of a vector shift operation, where all the elements of the
2498 /// build_vector must have the same constant integer value.
2499 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
2500 // Ignore bit_converts.
2501 while (Op.getOpcode() == ISD::BIT_CONVERT)
2502 Op = Op.getOperand(0);
2503 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2504 APInt SplatBits, SplatUndef;
2505 unsigned SplatBitSize;
2507 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2508 HasAnyUndefs, ElementBits) ||
2509 SplatBitSize > ElementBits)
2511 Cnt = SplatBits.getSExtValue();
2515 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
2516 /// operand of a vector shift left operation. That value must be in the range:
2517 /// 0 <= Value < ElementBits for a left shift; or
2518 /// 0 <= Value <= ElementBits for a long left shift.
2519 static bool isVShiftLImm(SDValue Op, MVT VT, bool isLong, int64_t &Cnt) {
2520 assert(VT.isVector() && "vector shift count is not a vector type");
2521 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2522 if (! getVShiftImm(Op, ElementBits, Cnt))
2524 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
2527 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
2528 /// operand of a vector shift right operation. For a shift opcode, the value
2529 /// is positive, but for an intrinsic the value count must be negative. The
2530 /// absolute value must be in the range:
2531 /// 1 <= |Value| <= ElementBits for a right shift; or
2532 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
2533 static bool isVShiftRImm(SDValue Op, MVT VT, bool isNarrow, bool isIntrinsic,
2535 assert(VT.isVector() && "vector shift count is not a vector type");
2536 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2537 if (! getVShiftImm(Op, ElementBits, Cnt))
2541 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
2544 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
2545 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
2546 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2549 // Don't do anything for most intrinsics.
2552 // Vector shifts: check for immediate versions and lower them.
2553 // Note: This is done during DAG combining instead of DAG legalizing because
2554 // the build_vectors for 64-bit vector element shift counts are generally
2555 // not legal, and it is hard to see their values after they get legalized to
2556 // loads from a constant pool.
2557 case Intrinsic::arm_neon_vshifts:
2558 case Intrinsic::arm_neon_vshiftu:
2559 case Intrinsic::arm_neon_vshiftls:
2560 case Intrinsic::arm_neon_vshiftlu:
2561 case Intrinsic::arm_neon_vshiftn:
2562 case Intrinsic::arm_neon_vrshifts:
2563 case Intrinsic::arm_neon_vrshiftu:
2564 case Intrinsic::arm_neon_vrshiftn:
2565 case Intrinsic::arm_neon_vqshifts:
2566 case Intrinsic::arm_neon_vqshiftu:
2567 case Intrinsic::arm_neon_vqshiftsu:
2568 case Intrinsic::arm_neon_vqshiftns:
2569 case Intrinsic::arm_neon_vqshiftnu:
2570 case Intrinsic::arm_neon_vqshiftnsu:
2571 case Intrinsic::arm_neon_vqrshiftns:
2572 case Intrinsic::arm_neon_vqrshiftnu:
2573 case Intrinsic::arm_neon_vqrshiftnsu: {
2574 MVT VT = N->getOperand(1).getValueType();
2576 unsigned VShiftOpc = 0;
2579 case Intrinsic::arm_neon_vshifts:
2580 case Intrinsic::arm_neon_vshiftu:
2581 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
2582 VShiftOpc = ARMISD::VSHL;
2585 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
2586 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
2587 ARMISD::VSHRs : ARMISD::VSHRu);
2592 case Intrinsic::arm_neon_vshiftls:
2593 case Intrinsic::arm_neon_vshiftlu:
2594 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
2596 assert(0 && "invalid shift count for vshll intrinsic");
2599 case Intrinsic::arm_neon_vrshifts:
2600 case Intrinsic::arm_neon_vrshiftu:
2601 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
2605 case Intrinsic::arm_neon_vqshifts:
2606 case Intrinsic::arm_neon_vqshiftu:
2607 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2611 case Intrinsic::arm_neon_vqshiftsu:
2612 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2614 assert(0 && "invalid shift count for vqshlu intrinsic");
2617 case Intrinsic::arm_neon_vshiftn:
2618 case Intrinsic::arm_neon_vrshiftn:
2619 case Intrinsic::arm_neon_vqshiftns:
2620 case Intrinsic::arm_neon_vqshiftnu:
2621 case Intrinsic::arm_neon_vqshiftnsu:
2622 case Intrinsic::arm_neon_vqrshiftns:
2623 case Intrinsic::arm_neon_vqrshiftnu:
2624 case Intrinsic::arm_neon_vqrshiftnsu:
2625 // Narrowing shifts require an immediate right shift.
2626 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
2628 assert(0 && "invalid shift count for narrowing vector shift intrinsic");
2632 assert(0 && "unhandled vector shift");
2636 case Intrinsic::arm_neon_vshifts:
2637 case Intrinsic::arm_neon_vshiftu:
2638 // Opcode already set above.
2640 case Intrinsic::arm_neon_vshiftls:
2641 case Intrinsic::arm_neon_vshiftlu:
2642 if (Cnt == VT.getVectorElementType().getSizeInBits())
2643 VShiftOpc = ARMISD::VSHLLi;
2645 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
2646 ARMISD::VSHLLs : ARMISD::VSHLLu);
2648 case Intrinsic::arm_neon_vshiftn:
2649 VShiftOpc = ARMISD::VSHRN; break;
2650 case Intrinsic::arm_neon_vrshifts:
2651 VShiftOpc = ARMISD::VRSHRs; break;
2652 case Intrinsic::arm_neon_vrshiftu:
2653 VShiftOpc = ARMISD::VRSHRu; break;
2654 case Intrinsic::arm_neon_vrshiftn:
2655 VShiftOpc = ARMISD::VRSHRN; break;
2656 case Intrinsic::arm_neon_vqshifts:
2657 VShiftOpc = ARMISD::VQSHLs; break;
2658 case Intrinsic::arm_neon_vqshiftu:
2659 VShiftOpc = ARMISD::VQSHLu; break;
2660 case Intrinsic::arm_neon_vqshiftsu:
2661 VShiftOpc = ARMISD::VQSHLsu; break;
2662 case Intrinsic::arm_neon_vqshiftns:
2663 VShiftOpc = ARMISD::VQSHRNs; break;
2664 case Intrinsic::arm_neon_vqshiftnu:
2665 VShiftOpc = ARMISD::VQSHRNu; break;
2666 case Intrinsic::arm_neon_vqshiftnsu:
2667 VShiftOpc = ARMISD::VQSHRNsu; break;
2668 case Intrinsic::arm_neon_vqrshiftns:
2669 VShiftOpc = ARMISD::VQRSHRNs; break;
2670 case Intrinsic::arm_neon_vqrshiftnu:
2671 VShiftOpc = ARMISD::VQRSHRNu; break;
2672 case Intrinsic::arm_neon_vqrshiftnsu:
2673 VShiftOpc = ARMISD::VQRSHRNsu; break;
2676 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2677 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
2680 case Intrinsic::arm_neon_vshiftins: {
2681 MVT VT = N->getOperand(1).getValueType();
2683 unsigned VShiftOpc = 0;
2685 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
2686 VShiftOpc = ARMISD::VSLI;
2687 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
2688 VShiftOpc = ARMISD::VSRI;
2690 assert(0 && "invalid shift count for vsli/vsri intrinsic");
2694 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2695 N->getOperand(1), N->getOperand(2),
2696 DAG.getConstant(Cnt, MVT::i32));
2699 case Intrinsic::arm_neon_vqrshifts:
2700 case Intrinsic::arm_neon_vqrshiftu:
2701 // No immediate versions of these to check for.
2708 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
2709 /// lowers them. As with the vector shift intrinsics, this is done during DAG
2710 /// combining instead of DAG legalizing because the build_vectors for 64-bit
2711 /// vector element shift counts are generally not legal, and it is hard to see
2712 /// their values after they get legalized to loads from a constant pool.
2713 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
2714 const ARMSubtarget *ST) {
2715 MVT VT = N->getValueType(0);
2717 // Nothing to be done for scalar shifts.
2718 if (! VT.isVector())
2721 assert(ST->hasNEON() && "unexpected vector shift");
2724 switch (N->getOpcode()) {
2725 default: assert(0 && "unexpected shift opcode");
2728 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
2729 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
2730 DAG.getConstant(Cnt, MVT::i32));
2735 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
2736 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
2737 ARMISD::VSHRs : ARMISD::VSHRu);
2738 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
2739 DAG.getConstant(Cnt, MVT::i32));
2745 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
2746 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
2747 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
2748 const ARMSubtarget *ST) {
2749 SDValue N0 = N->getOperand(0);
2751 // Check for sign- and zero-extensions of vector extract operations of 8-
2752 // and 16-bit vector elements. NEON supports these directly. They are
2753 // handled during DAG combining because type legalization will promote them
2754 // to 32-bit types and it is messy to recognize the operations after that.
2755 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
2756 SDValue Vec = N0.getOperand(0);
2757 SDValue Lane = N0.getOperand(1);
2758 MVT VT = N->getValueType(0);
2759 MVT EltVT = N0.getValueType();
2760 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2762 if (VT == MVT::i32 &&
2763 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
2764 TLI.isTypeLegal(Vec.getValueType())) {
2767 switch (N->getOpcode()) {
2768 default: assert(0 && "unexpected opcode");
2769 case ISD::SIGN_EXTEND:
2770 Opc = ARMISD::VGETLANEs;
2772 case ISD::ZERO_EXTEND:
2773 case ISD::ANY_EXTEND:
2774 Opc = ARMISD::VGETLANEu;
2777 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
2784 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
2785 DAGCombinerInfo &DCI) const {
2786 switch (N->getOpcode()) {
2788 case ISD::ADD: return PerformADDCombine(N, DCI);
2789 case ISD::SUB: return PerformSUBCombine(N, DCI);
2790 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
2791 case ISD::INTRINSIC_WO_CHAIN:
2792 return PerformIntrinsicCombine(N, DCI.DAG);
2796 return PerformShiftCombine(N, DCI.DAG, Subtarget);
2797 case ISD::SIGN_EXTEND:
2798 case ISD::ZERO_EXTEND:
2799 case ISD::ANY_EXTEND:
2800 return PerformExtendCombine(N, DCI.DAG, Subtarget);
2805 /// isLegalAddressImmediate - Return true if the integer value can be used
2806 /// as the offset of the target addressing mode for load / store of the
2808 static bool isLegalAddressImmediate(int64_t V, MVT VT,
2809 const ARMSubtarget *Subtarget) {
2816 if (Subtarget->isThumb()) {
2821 switch (VT.getSimpleVT()) {
2822 default: return false;
2837 if ((V & (Scale - 1)) != 0)
2840 return V == (V & ((1LL << 5) - 1));
2845 switch (VT.getSimpleVT()) {
2846 default: return false;
2851 return V == (V & ((1LL << 12) - 1));
2854 return V == (V & ((1LL << 8) - 1));
2857 if (!Subtarget->hasVFP2())
2862 return V == (V & ((1LL << 8) - 1));
2866 /// isLegalAddressingMode - Return true if the addressing mode represented
2867 /// by AM is legal for this target, for a load/store of the specified type.
2868 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
2869 const Type *Ty) const {
2870 MVT VT = getValueType(Ty, true);
2871 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
2874 // Can never fold addr of global into load/store.
2879 case 0: // no scale reg, must be "r+i" or "r", or "i".
2882 if (Subtarget->isThumb())
2886 // ARM doesn't support any R+R*scale+imm addr modes.
2893 int Scale = AM.Scale;
2894 switch (VT.getSimpleVT()) {
2895 default: return false;
2900 // This assumes i64 is legalized to a pair of i32. If not (i.e.
2901 // ldrd / strd are used, then its address mode is same as i16.
2903 if (Scale < 0) Scale = -Scale;
2907 return isPowerOf2_32(Scale & ~1);
2910 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
2915 // Note, we allow "void" uses (basically, uses that aren't loads or
2916 // stores), because arm allows folding a scale into many arithmetic
2917 // operations. This should be made more precise and revisited later.
2919 // Allow r << imm, but the imm has to be a multiple of two.
2920 if (AM.Scale & 1) return false;
2921 return isPowerOf2_32(AM.Scale);
2928 static bool getARMIndexedAddressParts(SDNode *Ptr, MVT VT,
2929 bool isSEXTLoad, SDValue &Base,
2930 SDValue &Offset, bool &isInc,
2931 SelectionDAG &DAG) {
2932 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
2935 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
2937 Base = Ptr->getOperand(0);
2938 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
2939 int RHSC = (int)RHS->getZExtValue();
2940 if (RHSC < 0 && RHSC > -256) {
2941 assert(Ptr->getOpcode() == ISD::ADD);
2943 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
2947 isInc = (Ptr->getOpcode() == ISD::ADD);
2948 Offset = Ptr->getOperand(1);
2950 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
2952 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
2953 int RHSC = (int)RHS->getZExtValue();
2954 if (RHSC < 0 && RHSC > -0x1000) {
2955 assert(Ptr->getOpcode() == ISD::ADD);
2957 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
2958 Base = Ptr->getOperand(0);
2963 if (Ptr->getOpcode() == ISD::ADD) {
2965 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
2966 if (ShOpcVal != ARM_AM::no_shift) {
2967 Base = Ptr->getOperand(1);
2968 Offset = Ptr->getOperand(0);
2970 Base = Ptr->getOperand(0);
2971 Offset = Ptr->getOperand(1);
2976 isInc = (Ptr->getOpcode() == ISD::ADD);
2977 Base = Ptr->getOperand(0);
2978 Offset = Ptr->getOperand(1);
2982 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
2986 static bool getT2IndexedAddressParts(SDNode *Ptr, MVT VT,
2987 bool isSEXTLoad, SDValue &Base,
2988 SDValue &Offset, bool &isInc,
2989 SelectionDAG &DAG) {
2990 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
2993 Base = Ptr->getOperand(0);
2994 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
2995 int RHSC = (int)RHS->getZExtValue();
2996 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
2997 assert(Ptr->getOpcode() == ISD::ADD);
2999 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3001 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
3002 isInc = Ptr->getOpcode() == ISD::ADD;
3003 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
3011 /// getPreIndexedAddressParts - returns true by value, base pointer and
3012 /// offset pointer and addressing mode by reference if the node's address
3013 /// can be legally represented as pre-indexed load / store address.
3015 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3017 ISD::MemIndexedMode &AM,
3018 SelectionDAG &DAG) const {
3019 if (Subtarget->isThumb1Only())
3024 bool isSEXTLoad = false;
3025 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3026 Ptr = LD->getBasePtr();
3027 VT = LD->getMemoryVT();
3028 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3029 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3030 Ptr = ST->getBasePtr();
3031 VT = ST->getMemoryVT();
3036 bool isLegal = false;
3037 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3038 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3039 Offset, isInc, DAG);
3041 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3042 Offset, isInc, DAG);
3046 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3050 /// getPostIndexedAddressParts - returns true by value, base pointer and
3051 /// offset pointer and addressing mode by reference if this node can be
3052 /// combined with a load / store to form a post-indexed load / store.
3053 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3056 ISD::MemIndexedMode &AM,
3057 SelectionDAG &DAG) const {
3058 if (Subtarget->isThumb1Only())
3063 bool isSEXTLoad = false;
3064 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3065 VT = LD->getMemoryVT();
3066 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3067 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3068 VT = ST->getMemoryVT();
3073 bool isLegal = false;
3074 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3075 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3078 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3083 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3087 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3091 const SelectionDAG &DAG,
3092 unsigned Depth) const {
3093 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3094 switch (Op.getOpcode()) {
3096 case ARMISD::CMOV: {
3097 // Bits are known zero/one if known on the LHS and RHS.
3098 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3099 if (KnownZero == 0 && KnownOne == 0) return;
3101 APInt KnownZeroRHS, KnownOneRHS;
3102 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3103 KnownZeroRHS, KnownOneRHS, Depth+1);
3104 KnownZero &= KnownZeroRHS;
3105 KnownOne &= KnownOneRHS;
3111 //===----------------------------------------------------------------------===//
3112 // ARM Inline Assembly Support
3113 //===----------------------------------------------------------------------===//
3115 /// getConstraintType - Given a constraint letter, return the type of
3116 /// constraint it is for this target.
3117 ARMTargetLowering::ConstraintType
3118 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3119 if (Constraint.size() == 1) {
3120 switch (Constraint[0]) {
3122 case 'l': return C_RegisterClass;
3123 case 'w': return C_RegisterClass;
3126 return TargetLowering::getConstraintType(Constraint);
3129 std::pair<unsigned, const TargetRegisterClass*>
3130 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3132 if (Constraint.size() == 1) {
3133 // GCC RS6000 Constraint Letters
3134 switch (Constraint[0]) {
3136 if (Subtarget->isThumb())
3137 return std::make_pair(0U, ARM::tGPRRegisterClass);
3139 return std::make_pair(0U, ARM::GPRRegisterClass);
3141 return std::make_pair(0U, ARM::GPRRegisterClass);
3144 return std::make_pair(0U, ARM::SPRRegisterClass);
3146 return std::make_pair(0U, ARM::DPRRegisterClass);
3150 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3153 std::vector<unsigned> ARMTargetLowering::
3154 getRegClassForInlineAsmConstraint(const std::string &Constraint,
3156 if (Constraint.size() != 1)
3157 return std::vector<unsigned>();
3159 switch (Constraint[0]) { // GCC ARM Constraint Letters
3162 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3163 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3166 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3167 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3168 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3169 ARM::R12, ARM::LR, 0);
3172 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3173 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3174 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3175 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3176 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3177 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3178 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3179 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3181 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3182 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3183 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3184 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3188 return std::vector<unsigned>();
3191 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3192 /// vector. If it is invalid, don't add anything to Ops.
3193 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3196 std::vector<SDValue>&Ops,
3197 SelectionDAG &DAG) const {
3198 SDValue Result(0, 0);
3200 switch (Constraint) {
3202 case 'I': case 'J': case 'K': case 'L':
3203 case 'M': case 'N': case 'O':
3204 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3208 int64_t CVal64 = C->getSExtValue();
3209 int CVal = (int) CVal64;
3210 // None of these constraints allow values larger than 32 bits. Check
3211 // that the value fits in an int.
3215 switch (Constraint) {
3217 if (Subtarget->isThumb()) {
3218 // This must be a constant between 0 and 255, for ADD immediates.
3219 if (CVal >= 0 && CVal <= 255)
3222 // A constant that can be used as an immediate value in a
3223 // data-processing instruction.
3224 if (ARM_AM::getSOImmVal(CVal) != -1)
3230 if (Subtarget->isThumb()) {
3231 // This must be a constant between -255 and -1, for negated ADD
3232 // immediates. This can be used in GCC with an "n" modifier that
3233 // prints the negated value, for use with SUB instructions. It is
3234 // not useful otherwise but is implemented for compatibility.
3235 if (CVal >= -255 && CVal <= -1)
3238 // This must be a constant between -4095 and 4095. It is not clear
3239 // what this constraint is intended for. Implemented for
3240 // compatibility with GCC.
3241 if (CVal >= -4095 && CVal <= 4095)
3247 if (Subtarget->isThumb()) {
3248 // A 32-bit value where only one byte has a nonzero value. Exclude
3249 // zero to match GCC. This constraint is used by GCC internally for
3250 // constants that can be loaded with a move/shift combination.
3251 // It is not useful otherwise but is implemented for compatibility.
3252 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
3255 // A constant whose bitwise inverse can be used as an immediate
3256 // value in a data-processing instruction. This can be used in GCC
3257 // with a "B" modifier that prints the inverted value, for use with
3258 // BIC and MVN instructions. It is not useful otherwise but is
3259 // implemented for compatibility.
3260 if (ARM_AM::getSOImmVal(~CVal) != -1)
3266 if (Subtarget->isThumb()) {
3267 // This must be a constant between -7 and 7,
3268 // for 3-operand ADD/SUB immediate instructions.
3269 if (CVal >= -7 && CVal < 7)
3272 // A constant whose negation can be used as an immediate value in a
3273 // data-processing instruction. This can be used in GCC with an "n"
3274 // modifier that prints the negated value, for use with SUB
3275 // instructions. It is not useful otherwise but is implemented for
3277 if (ARM_AM::getSOImmVal(-CVal) != -1)
3283 if (Subtarget->isThumb()) {
3284 // This must be a multiple of 4 between 0 and 1020, for
3285 // ADD sp + immediate.
3286 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
3289 // A power of two or a constant between 0 and 32. This is used in
3290 // GCC for the shift amount on shifted register operands, but it is
3291 // useful in general for any shift amounts.
3292 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
3298 if (Subtarget->isThumb()) {
3299 // This must be a constant between 0 and 31, for shift amounts.
3300 if (CVal >= 0 && CVal <= 31)
3306 if (Subtarget->isThumb()) {
3307 // This must be a multiple of 4 between -508 and 508, for
3308 // ADD/SUB sp = sp + immediate.
3309 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
3314 Result = DAG.getTargetConstant(CVal, Op.getValueType());
3318 if (Result.getNode()) {
3319 Ops.push_back(Result);
3322 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,