1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Instruction.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Type.h"
33 #include "llvm/CodeGen/CallingConvLower.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/MC/MCSectionMachO.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/ADT/VectorExtras.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
52 STATISTIC(NumTailCalls, "Number of tail calls");
54 // This option should go away when tail calls fully work.
56 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
57 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions"),
66 ARMInterworking("arm-interworking", cl::Hidden,
67 cl::desc("Enable / disable ARM interworking (for debugging only)"),
71 EnableARMCodePlacement("arm-code-placement", cl::Hidden,
72 cl::desc("Enable code placement pass for ARM"),
75 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
76 CCValAssign::LocInfo &LocInfo,
77 ISD::ArgFlagsTy &ArgFlags,
79 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
80 CCValAssign::LocInfo &LocInfo,
81 ISD::ArgFlagsTy &ArgFlags,
83 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
84 CCValAssign::LocInfo &LocInfo,
85 ISD::ArgFlagsTy &ArgFlags,
87 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
88 CCValAssign::LocInfo &LocInfo,
89 ISD::ArgFlagsTy &ArgFlags,
92 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
93 EVT PromotedBitwiseVT) {
94 if (VT != PromotedLdStVT) {
95 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
96 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
97 PromotedLdStVT.getSimpleVT());
99 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
101 PromotedLdStVT.getSimpleVT());
104 EVT ElemTy = VT.getVectorElementType();
105 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
106 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
107 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
108 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
109 if (ElemTy != MVT::i32) {
110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
111 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
112 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
116 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
117 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
118 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
119 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
120 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
121 if (VT.isInteger()) {
122 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
123 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
124 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
127 // Promote all bit-wise operations.
128 if (VT.isInteger() && VT != PromotedBitwiseVT) {
129 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
130 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
131 PromotedBitwiseVT.getSimpleVT());
132 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
133 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
134 PromotedBitwiseVT.getSimpleVT());
135 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
136 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
137 PromotedBitwiseVT.getSimpleVT());
140 // Neon does not support vector divide/remainder operations.
141 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
142 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
143 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
144 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
145 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
146 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
149 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
150 addRegisterClass(VT, ARM::DPRRegisterClass);
151 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
154 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
155 addRegisterClass(VT, ARM::QPRRegisterClass);
156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
159 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
160 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
161 return new TargetLoweringObjectFileMachO();
163 return new ARMElfTargetObjectFile();
166 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
167 : TargetLowering(TM, createTLOF(TM)) {
168 Subtarget = &TM.getSubtarget<ARMSubtarget>();
170 if (Subtarget->isTargetDarwin()) {
171 // Uses VFP for Thumb libfuncs if available.
172 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
173 // Single-precision floating-point arithmetic.
174 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
175 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
176 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
177 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
179 // Double-precision floating-point arithmetic.
180 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
181 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
182 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
183 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
185 // Single-precision comparisons.
186 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
187 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
188 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
189 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
190 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
191 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
192 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
193 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
195 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
204 // Double-precision comparisons.
205 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
206 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
207 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
208 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
209 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
210 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
211 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
212 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
214 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
220 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
221 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
223 // Floating-point to integer conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
227 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
228 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
229 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
231 // Conversions between floating types.
232 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
233 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
235 // Integer to floating-point conversions.
236 // i64 conversions are done via library routines even when generating VFP
237 // instructions, so use the same ones.
238 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
239 // e.g., __floatunsidf vs. __floatunssidfvfp.
240 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
241 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
242 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
243 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
247 // These libcalls are not available in 32-bit.
248 setLibcallName(RTLIB::SHL_I128, 0);
249 setLibcallName(RTLIB::SRL_I128, 0);
250 setLibcallName(RTLIB::SRA_I128, 0);
252 // Libcalls should use the AAPCS base standard ABI, even if hard float
253 // is in effect, as per the ARM RTABI specification, section 4.1.2.
254 if (Subtarget->isAAPCS_ABI()) {
255 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
256 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
257 CallingConv::ARM_AAPCS);
261 if (Subtarget->isThumb1Only())
262 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
264 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
266 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
267 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
269 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
272 if (Subtarget->hasNEON()) {
273 addDRTypeForNEON(MVT::v2f32);
274 addDRTypeForNEON(MVT::v8i8);
275 addDRTypeForNEON(MVT::v4i16);
276 addDRTypeForNEON(MVT::v2i32);
277 addDRTypeForNEON(MVT::v1i64);
279 addQRTypeForNEON(MVT::v4f32);
280 addQRTypeForNEON(MVT::v2f64);
281 addQRTypeForNEON(MVT::v16i8);
282 addQRTypeForNEON(MVT::v8i16);
283 addQRTypeForNEON(MVT::v4i32);
284 addQRTypeForNEON(MVT::v2i64);
286 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
287 // neither Neon nor VFP support any arithmetic operations on it.
288 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
289 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
290 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
291 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
292 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
293 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
294 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
295 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
296 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
297 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
298 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
299 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
300 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
301 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
302 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
303 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
304 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
305 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
306 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
307 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
308 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
309 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
310 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
311 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
313 // Neon does not support some operations on v1i64 and v2i64 types.
314 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
315 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
316 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
317 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
319 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
320 setTargetDAGCombine(ISD::SHL);
321 setTargetDAGCombine(ISD::SRL);
322 setTargetDAGCombine(ISD::SRA);
323 setTargetDAGCombine(ISD::SIGN_EXTEND);
324 setTargetDAGCombine(ISD::ZERO_EXTEND);
325 setTargetDAGCombine(ISD::ANY_EXTEND);
326 setTargetDAGCombine(ISD::SELECT_CC);
329 computeRegisterProperties();
331 // ARM does not have f32 extending load.
332 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
334 // ARM does not have i1 sign extending load.
335 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
337 // ARM supports all 4 flavors of integer indexed load / store.
338 if (!Subtarget->isThumb1Only()) {
339 for (unsigned im = (unsigned)ISD::PRE_INC;
340 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
341 setIndexedLoadAction(im, MVT::i1, Legal);
342 setIndexedLoadAction(im, MVT::i8, Legal);
343 setIndexedLoadAction(im, MVT::i16, Legal);
344 setIndexedLoadAction(im, MVT::i32, Legal);
345 setIndexedStoreAction(im, MVT::i1, Legal);
346 setIndexedStoreAction(im, MVT::i8, Legal);
347 setIndexedStoreAction(im, MVT::i16, Legal);
348 setIndexedStoreAction(im, MVT::i32, Legal);
352 // i64 operation support.
353 if (Subtarget->isThumb1Only()) {
354 setOperationAction(ISD::MUL, MVT::i64, Expand);
355 setOperationAction(ISD::MULHU, MVT::i32, Expand);
356 setOperationAction(ISD::MULHS, MVT::i32, Expand);
357 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
358 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
360 setOperationAction(ISD::MUL, MVT::i64, Expand);
361 setOperationAction(ISD::MULHU, MVT::i32, Expand);
362 if (!Subtarget->hasV6Ops())
363 setOperationAction(ISD::MULHS, MVT::i32, Expand);
365 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
366 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
367 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
368 setOperationAction(ISD::SRL, MVT::i64, Custom);
369 setOperationAction(ISD::SRA, MVT::i64, Custom);
371 // ARM does not have ROTL.
372 setOperationAction(ISD::ROTL, MVT::i32, Expand);
373 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
374 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
375 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
376 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
378 // Only ARMv6 has BSWAP.
379 if (!Subtarget->hasV6Ops())
380 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
382 // These are expanded into libcalls.
383 if (!Subtarget->hasDivide()) {
384 // v7M has a hardware divider
385 setOperationAction(ISD::SDIV, MVT::i32, Expand);
386 setOperationAction(ISD::UDIV, MVT::i32, Expand);
388 setOperationAction(ISD::SREM, MVT::i32, Expand);
389 setOperationAction(ISD::UREM, MVT::i32, Expand);
390 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
391 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
393 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
394 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
395 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
396 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
397 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // Use the default implementation.
402 setOperationAction(ISD::VASTART, MVT::Other, Custom);
403 setOperationAction(ISD::VAARG, MVT::Other, Expand);
404 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
405 setOperationAction(ISD::VAEND, MVT::Other, Expand);
406 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
407 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
408 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
409 // FIXME: Shouldn't need this, since no register is used, but the legalizer
410 // doesn't yet know how to not do that for SjLj.
411 setExceptionSelectorRegister(ARM::R0);
412 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
413 // Handle atomics directly for ARMv[67] (except for Thumb1), otherwise
414 // use the default expansion.
415 bool canHandleAtomics =
416 (Subtarget->hasV7Ops() ||
417 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only()));
418 if (canHandleAtomics) {
419 // membarrier needs custom lowering; the rest are legal and handled
421 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
423 // Set them all for expansion, which will force libcalls.
424 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
425 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
426 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
427 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
428 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
429 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
430 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
431 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
432 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
433 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
434 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
435 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
436 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
437 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
438 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
439 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
440 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
441 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
442 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
443 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
444 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
445 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
446 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
447 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
448 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
449 // Since the libcalls include locking, fold in the fences
450 setShouldFoldAtomicFences(true);
452 // 64-bit versions are always libcalls (for now)
453 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
454 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
455 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
456 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
457 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
458 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
459 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
460 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
462 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
463 if (!Subtarget->hasV6Ops()) {
464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
469 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
470 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
471 // iff target supports vfp2.
472 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
474 // We want to custom lower some of our intrinsics.
475 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
476 if (Subtarget->isTargetDarwin()) {
477 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
478 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
481 setOperationAction(ISD::SETCC, MVT::i32, Expand);
482 setOperationAction(ISD::SETCC, MVT::f32, Expand);
483 setOperationAction(ISD::SETCC, MVT::f64, Expand);
484 setOperationAction(ISD::SELECT, MVT::i32, Expand);
485 setOperationAction(ISD::SELECT, MVT::f32, Expand);
486 setOperationAction(ISD::SELECT, MVT::f64, Expand);
487 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
488 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
489 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
491 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
492 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
493 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
494 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
495 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
497 // We don't support sin/cos/fmod/copysign/pow
498 setOperationAction(ISD::FSIN, MVT::f64, Expand);
499 setOperationAction(ISD::FSIN, MVT::f32, Expand);
500 setOperationAction(ISD::FCOS, MVT::f32, Expand);
501 setOperationAction(ISD::FCOS, MVT::f64, Expand);
502 setOperationAction(ISD::FREM, MVT::f64, Expand);
503 setOperationAction(ISD::FREM, MVT::f32, Expand);
504 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
505 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
506 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
508 setOperationAction(ISD::FPOW, MVT::f64, Expand);
509 setOperationAction(ISD::FPOW, MVT::f32, Expand);
511 // Various VFP goodness
512 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
513 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
514 if (Subtarget->hasVFP2()) {
515 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
516 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
517 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
518 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
520 // Special handling for half-precision FP.
521 if (!Subtarget->hasFP16()) {
522 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
523 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
527 // We have target-specific dag combine patterns for the following nodes:
528 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
529 setTargetDAGCombine(ISD::ADD);
530 setTargetDAGCombine(ISD::SUB);
531 setTargetDAGCombine(ISD::MUL);
533 if (Subtarget->hasV6T2Ops())
534 setTargetDAGCombine(ISD::OR);
536 setStackPointerRegisterToSaveRestore(ARM::SP);
538 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
539 setSchedulingPreference(Sched::RegPressure);
541 setSchedulingPreference(Sched::Hybrid);
543 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
545 // On ARM arguments smaller than 4 bytes are extended, so all arguments
546 // are at least 4 bytes aligned.
547 setMinStackArgumentAlignment(4);
549 if (EnableARMCodePlacement)
550 benefitFromCodePlacementOpt = true;
553 const TargetRegisterClass *
554 ARMTargetLowering::findRepresentativeClass(const TargetRegisterClass *RC) const{
555 switch (RC->getID()) {
558 case ARM::tGPRRegClassID:
559 case ARM::GPRRegClassID:
560 return ARM::GPRRegisterClass;
561 case ARM::SPRRegClassID:
562 case ARM::DPRRegClassID:
563 return ARM::DPRRegisterClass;
564 case ARM::QPRRegClassID:
565 return ARM::QPRRegisterClass;
569 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
572 case ARMISD::Wrapper: return "ARMISD::Wrapper";
573 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
574 case ARMISD::CALL: return "ARMISD::CALL";
575 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
576 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
577 case ARMISD::tCALL: return "ARMISD::tCALL";
578 case ARMISD::BRCOND: return "ARMISD::BRCOND";
579 case ARMISD::BR_JT: return "ARMISD::BR_JT";
580 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
581 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
582 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
583 case ARMISD::CMP: return "ARMISD::CMP";
584 case ARMISD::CMPZ: return "ARMISD::CMPZ";
585 case ARMISD::CMPFP: return "ARMISD::CMPFP";
586 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
587 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
588 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
589 case ARMISD::CMOV: return "ARMISD::CMOV";
590 case ARMISD::CNEG: return "ARMISD::CNEG";
592 case ARMISD::RBIT: return "ARMISD::RBIT";
594 case ARMISD::FTOSI: return "ARMISD::FTOSI";
595 case ARMISD::FTOUI: return "ARMISD::FTOUI";
596 case ARMISD::SITOF: return "ARMISD::SITOF";
597 case ARMISD::UITOF: return "ARMISD::UITOF";
599 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
600 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
601 case ARMISD::RRX: return "ARMISD::RRX";
603 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
604 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
606 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
607 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
609 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
611 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
613 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
615 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
616 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
618 case ARMISD::VCEQ: return "ARMISD::VCEQ";
619 case ARMISD::VCGE: return "ARMISD::VCGE";
620 case ARMISD::VCGEU: return "ARMISD::VCGEU";
621 case ARMISD::VCGT: return "ARMISD::VCGT";
622 case ARMISD::VCGTU: return "ARMISD::VCGTU";
623 case ARMISD::VTST: return "ARMISD::VTST";
625 case ARMISD::VSHL: return "ARMISD::VSHL";
626 case ARMISD::VSHRs: return "ARMISD::VSHRs";
627 case ARMISD::VSHRu: return "ARMISD::VSHRu";
628 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
629 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
630 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
631 case ARMISD::VSHRN: return "ARMISD::VSHRN";
632 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
633 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
634 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
635 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
636 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
637 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
638 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
639 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
640 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
641 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
642 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
643 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
644 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
645 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
646 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
647 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
648 case ARMISD::VDUP: return "ARMISD::VDUP";
649 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
650 case ARMISD::VEXT: return "ARMISD::VEXT";
651 case ARMISD::VREV64: return "ARMISD::VREV64";
652 case ARMISD::VREV32: return "ARMISD::VREV32";
653 case ARMISD::VREV16: return "ARMISD::VREV16";
654 case ARMISD::VZIP: return "ARMISD::VZIP";
655 case ARMISD::VUZP: return "ARMISD::VUZP";
656 case ARMISD::VTRN: return "ARMISD::VTRN";
657 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
658 case ARMISD::FMAX: return "ARMISD::FMAX";
659 case ARMISD::FMIN: return "ARMISD::FMIN";
660 case ARMISD::BFI: return "ARMISD::BFI";
664 /// getRegClassFor - Return the register class that should be used for the
665 /// specified value type.
666 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
667 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
668 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
669 // load / store 4 to 8 consecutive D registers.
670 if (Subtarget->hasNEON()) {
671 if (VT == MVT::v4i64)
672 return ARM::QQPRRegisterClass;
673 else if (VT == MVT::v8i64)
674 return ARM::QQQQPRRegisterClass;
676 return TargetLowering::getRegClassFor(VT);
679 /// getFunctionAlignment - Return the Log2 alignment of this function.
680 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
681 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
684 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
685 unsigned NumVals = N->getNumValues();
687 return Sched::RegPressure;
689 for (unsigned i = 0; i != NumVals; ++i) {
690 EVT VT = N->getValueType(i);
691 if (VT.isFloatingPoint() || VT.isVector())
692 return Sched::Latency;
695 if (!N->isMachineOpcode())
696 return Sched::RegPressure;
698 // Load are scheduled for latency even if there instruction itinerary
700 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
701 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
703 return Sched::Latency;
705 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
706 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
707 return Sched::Latency;
708 return Sched::RegPressure;
711 //===----------------------------------------------------------------------===//
713 //===----------------------------------------------------------------------===//
715 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
716 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
718 default: llvm_unreachable("Unknown condition code!");
719 case ISD::SETNE: return ARMCC::NE;
720 case ISD::SETEQ: return ARMCC::EQ;
721 case ISD::SETGT: return ARMCC::GT;
722 case ISD::SETGE: return ARMCC::GE;
723 case ISD::SETLT: return ARMCC::LT;
724 case ISD::SETLE: return ARMCC::LE;
725 case ISD::SETUGT: return ARMCC::HI;
726 case ISD::SETUGE: return ARMCC::HS;
727 case ISD::SETULT: return ARMCC::LO;
728 case ISD::SETULE: return ARMCC::LS;
732 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
733 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
734 ARMCC::CondCodes &CondCode2) {
735 CondCode2 = ARMCC::AL;
737 default: llvm_unreachable("Unknown FP condition!");
739 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
741 case ISD::SETOGT: CondCode = ARMCC::GT; break;
743 case ISD::SETOGE: CondCode = ARMCC::GE; break;
744 case ISD::SETOLT: CondCode = ARMCC::MI; break;
745 case ISD::SETOLE: CondCode = ARMCC::LS; break;
746 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
747 case ISD::SETO: CondCode = ARMCC::VC; break;
748 case ISD::SETUO: CondCode = ARMCC::VS; break;
749 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
750 case ISD::SETUGT: CondCode = ARMCC::HI; break;
751 case ISD::SETUGE: CondCode = ARMCC::PL; break;
753 case ISD::SETULT: CondCode = ARMCC::LT; break;
755 case ISD::SETULE: CondCode = ARMCC::LE; break;
757 case ISD::SETUNE: CondCode = ARMCC::NE; break;
761 //===----------------------------------------------------------------------===//
762 // Calling Convention Implementation
763 //===----------------------------------------------------------------------===//
765 #include "ARMGenCallingConv.inc"
767 // APCS f64 is in register pairs, possibly split to stack
768 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
769 CCValAssign::LocInfo &LocInfo,
770 CCState &State, bool CanFail) {
771 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
773 // Try to get the first register.
774 if (unsigned Reg = State.AllocateReg(RegList, 4))
775 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
777 // For the 2nd half of a v2f64, do not fail.
781 // Put the whole thing on the stack.
782 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
783 State.AllocateStack(8, 4),
788 // Try to get the second register.
789 if (unsigned Reg = State.AllocateReg(RegList, 4))
790 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
792 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
793 State.AllocateStack(4, 4),
798 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
799 CCValAssign::LocInfo &LocInfo,
800 ISD::ArgFlagsTy &ArgFlags,
802 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
804 if (LocVT == MVT::v2f64 &&
805 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
807 return true; // we handled it
810 // AAPCS f64 is in aligned register pairs
811 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
812 CCValAssign::LocInfo &LocInfo,
813 CCState &State, bool CanFail) {
814 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
815 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
817 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
819 // For the 2nd half of a v2f64, do not just fail.
823 // Put the whole thing on the stack.
824 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
825 State.AllocateStack(8, 8),
831 for (i = 0; i < 2; ++i)
832 if (HiRegList[i] == Reg)
835 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
836 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
841 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
842 CCValAssign::LocInfo &LocInfo,
843 ISD::ArgFlagsTy &ArgFlags,
845 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
847 if (LocVT == MVT::v2f64 &&
848 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
850 return true; // we handled it
853 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
854 CCValAssign::LocInfo &LocInfo, CCState &State) {
855 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
856 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
858 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
860 return false; // we didn't handle it
863 for (i = 0; i < 2; ++i)
864 if (HiRegList[i] == Reg)
867 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
868 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
873 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
874 CCValAssign::LocInfo &LocInfo,
875 ISD::ArgFlagsTy &ArgFlags,
877 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
879 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
881 return true; // we handled it
884 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
885 CCValAssign::LocInfo &LocInfo,
886 ISD::ArgFlagsTy &ArgFlags,
888 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
892 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
893 /// given CallingConvention value.
894 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
896 bool isVarArg) const {
899 llvm_unreachable("Unsupported calling convention");
901 case CallingConv::Fast:
902 // Use target triple & subtarget features to do actual dispatch.
903 if (Subtarget->isAAPCS_ABI()) {
904 if (Subtarget->hasVFP2() &&
905 FloatABIType == FloatABI::Hard && !isVarArg)
906 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
908 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
910 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
911 case CallingConv::ARM_AAPCS_VFP:
912 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
913 case CallingConv::ARM_AAPCS:
914 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
915 case CallingConv::ARM_APCS:
916 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
920 /// LowerCallResult - Lower the result values of a call into the
921 /// appropriate copies out of appropriate physical registers.
923 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
924 CallingConv::ID CallConv, bool isVarArg,
925 const SmallVectorImpl<ISD::InputArg> &Ins,
926 DebugLoc dl, SelectionDAG &DAG,
927 SmallVectorImpl<SDValue> &InVals) const {
929 // Assign locations to each value returned by this call.
930 SmallVector<CCValAssign, 16> RVLocs;
931 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
932 RVLocs, *DAG.getContext());
933 CCInfo.AnalyzeCallResult(Ins,
934 CCAssignFnForNode(CallConv, /* Return*/ true,
937 // Copy all of the result registers out of their specified physreg.
938 for (unsigned i = 0; i != RVLocs.size(); ++i) {
939 CCValAssign VA = RVLocs[i];
942 if (VA.needsCustom()) {
943 // Handle f64 or half of a v2f64.
944 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
946 Chain = Lo.getValue(1);
947 InFlag = Lo.getValue(2);
948 VA = RVLocs[++i]; // skip ahead to next loc
949 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
951 Chain = Hi.getValue(1);
952 InFlag = Hi.getValue(2);
953 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
955 if (VA.getLocVT() == MVT::v2f64) {
956 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
957 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
958 DAG.getConstant(0, MVT::i32));
960 VA = RVLocs[++i]; // skip ahead to next loc
961 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
962 Chain = Lo.getValue(1);
963 InFlag = Lo.getValue(2);
964 VA = RVLocs[++i]; // skip ahead to next loc
965 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
966 Chain = Hi.getValue(1);
967 InFlag = Hi.getValue(2);
968 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
969 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
970 DAG.getConstant(1, MVT::i32));
973 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
975 Chain = Val.getValue(1);
976 InFlag = Val.getValue(2);
979 switch (VA.getLocInfo()) {
980 default: llvm_unreachable("Unknown loc info!");
981 case CCValAssign::Full: break;
982 case CCValAssign::BCvt:
983 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
987 InVals.push_back(Val);
993 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
994 /// by "Src" to address "Dst" of size "Size". Alignment information is
995 /// specified by the specific parameter attribute. The copy will be passed as
996 /// a byval function parameter.
997 /// Sometimes what we are copying is the end of a larger object, the part that
998 /// does not fit in registers.
1000 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1001 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1003 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1004 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1005 /*isVolatile=*/false, /*AlwaysInline=*/false,
1009 /// LowerMemOpCallTo - Store the argument to the stack.
1011 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1012 SDValue StackPtr, SDValue Arg,
1013 DebugLoc dl, SelectionDAG &DAG,
1014 const CCValAssign &VA,
1015 ISD::ArgFlagsTy Flags) const {
1016 unsigned LocMemOffset = VA.getLocMemOffset();
1017 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1018 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1019 if (Flags.isByVal()) {
1020 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1022 return DAG.getStore(Chain, dl, Arg, PtrOff,
1023 PseudoSourceValue::getStack(), LocMemOffset,
1027 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1028 SDValue Chain, SDValue &Arg,
1029 RegsToPassVector &RegsToPass,
1030 CCValAssign &VA, CCValAssign &NextVA,
1032 SmallVector<SDValue, 8> &MemOpChains,
1033 ISD::ArgFlagsTy Flags) const {
1035 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1036 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1037 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1039 if (NextVA.isRegLoc())
1040 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1042 assert(NextVA.isMemLoc());
1043 if (StackPtr.getNode() == 0)
1044 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1046 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1052 /// LowerCall - Lowering a call into a callseq_start <-
1053 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1056 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1057 CallingConv::ID CallConv, bool isVarArg,
1059 const SmallVectorImpl<ISD::OutputArg> &Outs,
1060 const SmallVectorImpl<SDValue> &OutVals,
1061 const SmallVectorImpl<ISD::InputArg> &Ins,
1062 DebugLoc dl, SelectionDAG &DAG,
1063 SmallVectorImpl<SDValue> &InVals) const {
1064 MachineFunction &MF = DAG.getMachineFunction();
1065 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1066 bool IsSibCall = false;
1067 // Temporarily disable tail calls so things don't break.
1068 if (!EnableARMTailCalls)
1071 // Check if it's really possible to do a tail call.
1072 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1073 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1074 Outs, OutVals, Ins, DAG);
1075 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1076 // detected sibcalls.
1083 // Analyze operands of the call, assigning locations to each operand.
1084 SmallVector<CCValAssign, 16> ArgLocs;
1085 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1087 CCInfo.AnalyzeCallOperands(Outs,
1088 CCAssignFnForNode(CallConv, /* Return*/ false,
1091 // Get a count of how many bytes are to be pushed on the stack.
1092 unsigned NumBytes = CCInfo.getNextStackOffset();
1094 // For tail calls, memory operands are available in our caller's stack.
1098 // Adjust the stack pointer for the new arguments...
1099 // These operations are automatically eliminated by the prolog/epilog pass
1101 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1103 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1105 RegsToPassVector RegsToPass;
1106 SmallVector<SDValue, 8> MemOpChains;
1108 // Walk the register/memloc assignments, inserting copies/loads. In the case
1109 // of tail call optimization, arguments are handled later.
1110 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1112 ++i, ++realArgIdx) {
1113 CCValAssign &VA = ArgLocs[i];
1114 SDValue Arg = OutVals[realArgIdx];
1115 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1117 // Promote the value if needed.
1118 switch (VA.getLocInfo()) {
1119 default: llvm_unreachable("Unknown loc info!");
1120 case CCValAssign::Full: break;
1121 case CCValAssign::SExt:
1122 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1124 case CCValAssign::ZExt:
1125 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1127 case CCValAssign::AExt:
1128 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1130 case CCValAssign::BCvt:
1131 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1135 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1136 if (VA.needsCustom()) {
1137 if (VA.getLocVT() == MVT::v2f64) {
1138 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1139 DAG.getConstant(0, MVT::i32));
1140 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1141 DAG.getConstant(1, MVT::i32));
1143 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1144 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1146 VA = ArgLocs[++i]; // skip ahead to next loc
1147 if (VA.isRegLoc()) {
1148 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1149 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1151 assert(VA.isMemLoc());
1153 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1154 dl, DAG, VA, Flags));
1157 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1158 StackPtr, MemOpChains, Flags);
1160 } else if (VA.isRegLoc()) {
1161 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1162 } else if (!IsSibCall) {
1163 assert(VA.isMemLoc());
1165 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1166 dl, DAG, VA, Flags));
1170 if (!MemOpChains.empty())
1171 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1172 &MemOpChains[0], MemOpChains.size());
1174 // Build a sequence of copy-to-reg nodes chained together with token chain
1175 // and flag operands which copy the outgoing args into the appropriate regs.
1177 // Tail call byval lowering might overwrite argument registers so in case of
1178 // tail call optimization the copies to registers are lowered later.
1180 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1181 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1182 RegsToPass[i].second, InFlag);
1183 InFlag = Chain.getValue(1);
1186 // For tail calls lower the arguments to the 'real' stack slot.
1188 // Force all the incoming stack arguments to be loaded from the stack
1189 // before any new outgoing arguments are stored to the stack, because the
1190 // outgoing stack slots may alias the incoming argument stack slots, and
1191 // the alias isn't otherwise explicit. This is slightly more conservative
1192 // than necessary, because it means that each store effectively depends
1193 // on every argument instead of just those arguments it would clobber.
1195 // Do not flag preceeding copytoreg stuff together with the following stuff.
1197 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1198 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1199 RegsToPass[i].second, InFlag);
1200 InFlag = Chain.getValue(1);
1205 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1206 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1207 // node so that legalize doesn't hack it.
1208 bool isDirect = false;
1209 bool isARMFunc = false;
1210 bool isLocalARMFunc = false;
1211 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1213 if (EnableARMLongCalls) {
1214 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1215 && "long-calls with non-static relocation model!");
1216 // Handle a global address or an external symbol. If it's not one of
1217 // those, the target's already in a register, so we don't need to do
1219 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1220 const GlobalValue *GV = G->getGlobal();
1221 // Create a constant pool entry for the callee address
1222 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1223 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1226 // Get the address of the callee into a register
1227 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1228 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1229 Callee = DAG.getLoad(getPointerTy(), dl,
1230 DAG.getEntryNode(), CPAddr,
1231 PseudoSourceValue::getConstantPool(), 0,
1233 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1234 const char *Sym = S->getSymbol();
1236 // Create a constant pool entry for the callee address
1237 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1238 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1239 Sym, ARMPCLabelIndex, 0);
1240 // Get the address of the callee into a register
1241 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1242 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1243 Callee = DAG.getLoad(getPointerTy(), dl,
1244 DAG.getEntryNode(), CPAddr,
1245 PseudoSourceValue::getConstantPool(), 0,
1248 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1249 const GlobalValue *GV = G->getGlobal();
1251 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1252 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1253 getTargetMachine().getRelocationModel() != Reloc::Static;
1254 isARMFunc = !Subtarget->isThumb() || isStub;
1255 // ARM call to a local ARM function is predicable.
1256 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1257 // tBX takes a register source operand.
1258 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1259 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1260 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1263 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1264 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1265 Callee = DAG.getLoad(getPointerTy(), dl,
1266 DAG.getEntryNode(), CPAddr,
1267 PseudoSourceValue::getConstantPool(), 0,
1269 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1270 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1271 getPointerTy(), Callee, PICLabel);
1273 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1274 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1276 bool isStub = Subtarget->isTargetDarwin() &&
1277 getTargetMachine().getRelocationModel() != Reloc::Static;
1278 isARMFunc = !Subtarget->isThumb() || isStub;
1279 // tBX takes a register source operand.
1280 const char *Sym = S->getSymbol();
1281 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1282 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1283 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1284 Sym, ARMPCLabelIndex, 4);
1285 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1286 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1287 Callee = DAG.getLoad(getPointerTy(), dl,
1288 DAG.getEntryNode(), CPAddr,
1289 PseudoSourceValue::getConstantPool(), 0,
1291 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1292 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1293 getPointerTy(), Callee, PICLabel);
1295 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1298 // FIXME: handle tail calls differently.
1300 if (Subtarget->isThumb()) {
1301 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1302 CallOpc = ARMISD::CALL_NOLINK;
1304 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1306 CallOpc = (isDirect || Subtarget->hasV5TOps())
1307 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1308 : ARMISD::CALL_NOLINK;
1311 std::vector<SDValue> Ops;
1312 Ops.push_back(Chain);
1313 Ops.push_back(Callee);
1315 // Add argument registers to the end of the list so that they are known live
1317 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1318 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1319 RegsToPass[i].second.getValueType()));
1321 if (InFlag.getNode())
1322 Ops.push_back(InFlag);
1324 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1326 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1328 // Returns a chain and a flag for retval copy to use.
1329 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1330 InFlag = Chain.getValue(1);
1332 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1333 DAG.getIntPtrConstant(0, true), InFlag);
1335 InFlag = Chain.getValue(1);
1337 // Handle result values, copying them out of physregs into vregs that we
1339 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1343 /// MatchingStackOffset - Return true if the given stack call argument is
1344 /// already available in the same position (relatively) of the caller's
1345 /// incoming argument stack.
1347 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1348 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1349 const ARMInstrInfo *TII) {
1350 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1352 if (Arg.getOpcode() == ISD::CopyFromReg) {
1353 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1354 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1356 MachineInstr *Def = MRI->getVRegDef(VR);
1359 if (!Flags.isByVal()) {
1360 if (!TII->isLoadFromStackSlot(Def, FI))
1365 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1366 if (Flags.isByVal())
1367 // ByVal argument is passed in as a pointer but it's now being
1368 // dereferenced. e.g.
1369 // define @foo(%struct.X* %A) {
1370 // tail call @bar(%struct.X* byval %A)
1373 SDValue Ptr = Ld->getBasePtr();
1374 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1377 FI = FINode->getIndex();
1381 assert(FI != INT_MAX);
1382 if (!MFI->isFixedObjectIndex(FI))
1384 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1387 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1388 /// for tail call optimization. Targets which want to do tail call
1389 /// optimization should implement this function.
1391 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1392 CallingConv::ID CalleeCC,
1394 bool isCalleeStructRet,
1395 bool isCallerStructRet,
1396 const SmallVectorImpl<ISD::OutputArg> &Outs,
1397 const SmallVectorImpl<SDValue> &OutVals,
1398 const SmallVectorImpl<ISD::InputArg> &Ins,
1399 SelectionDAG& DAG) const {
1400 const Function *CallerF = DAG.getMachineFunction().getFunction();
1401 CallingConv::ID CallerCC = CallerF->getCallingConv();
1402 bool CCMatch = CallerCC == CalleeCC;
1404 // Look for obvious safe cases to perform tail call optimization that do not
1405 // require ABI changes. This is what gcc calls sibcall.
1407 // Do not sibcall optimize vararg calls unless the call site is not passing
1409 if (isVarArg && !Outs.empty())
1412 // Also avoid sibcall optimization if either caller or callee uses struct
1413 // return semantics.
1414 if (isCalleeStructRet || isCallerStructRet)
1417 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1418 // emitEpilogue is not ready for them.
1419 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1420 // LR. This means if we need to reload LR, it takes an extra instructions,
1421 // which outweighs the value of the tail call; but here we don't know yet
1422 // whether LR is going to be used. Probably the right approach is to
1423 // generate the tail call here and turn it back into CALL/RET in
1424 // emitEpilogue if LR is used.
1425 if (Subtarget->isThumb1Only())
1428 // For the moment, we can only do this to functions defined in this
1429 // compilation, or to indirect calls. A Thumb B to an ARM function,
1430 // or vice versa, is not easily fixed up in the linker unlike BL.
1431 // (We could do this by loading the address of the callee into a register;
1432 // that is an extra instruction over the direct call and burns a register
1433 // as well, so is not likely to be a win.)
1435 // It might be safe to remove this restriction on non-Darwin.
1437 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1438 // but we need to make sure there are enough registers; the only valid
1439 // registers are the 4 used for parameters. We don't currently do this
1441 if (isa<ExternalSymbolSDNode>(Callee))
1444 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1445 const GlobalValue *GV = G->getGlobal();
1446 if (GV->isDeclaration() || GV->isWeakForLinker())
1450 // If the calling conventions do not match, then we'd better make sure the
1451 // results are returned in the same way as what the caller expects.
1453 SmallVector<CCValAssign, 16> RVLocs1;
1454 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1455 RVLocs1, *DAG.getContext());
1456 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1458 SmallVector<CCValAssign, 16> RVLocs2;
1459 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1460 RVLocs2, *DAG.getContext());
1461 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1463 if (RVLocs1.size() != RVLocs2.size())
1465 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1466 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1468 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1470 if (RVLocs1[i].isRegLoc()) {
1471 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1474 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1480 // If the callee takes no arguments then go on to check the results of the
1482 if (!Outs.empty()) {
1483 // Check if stack adjustment is needed. For now, do not do this if any
1484 // argument is passed on the stack.
1485 SmallVector<CCValAssign, 16> ArgLocs;
1486 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1487 ArgLocs, *DAG.getContext());
1488 CCInfo.AnalyzeCallOperands(Outs,
1489 CCAssignFnForNode(CalleeCC, false, isVarArg));
1490 if (CCInfo.getNextStackOffset()) {
1491 MachineFunction &MF = DAG.getMachineFunction();
1493 // Check if the arguments are already laid out in the right way as
1494 // the caller's fixed stack objects.
1495 MachineFrameInfo *MFI = MF.getFrameInfo();
1496 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1497 const ARMInstrInfo *TII =
1498 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1499 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1501 ++i, ++realArgIdx) {
1502 CCValAssign &VA = ArgLocs[i];
1503 EVT RegVT = VA.getLocVT();
1504 SDValue Arg = OutVals[realArgIdx];
1505 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1506 if (VA.getLocInfo() == CCValAssign::Indirect)
1508 if (VA.needsCustom()) {
1509 // f64 and vector types are split into multiple registers or
1510 // register/stack-slot combinations. The types will not match
1511 // the registers; give up on memory f64 refs until we figure
1512 // out what to do about this.
1515 if (!ArgLocs[++i].isRegLoc())
1517 if (RegVT == MVT::v2f64) {
1518 if (!ArgLocs[++i].isRegLoc())
1520 if (!ArgLocs[++i].isRegLoc())
1523 } else if (!VA.isRegLoc()) {
1524 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1536 ARMTargetLowering::LowerReturn(SDValue Chain,
1537 CallingConv::ID CallConv, bool isVarArg,
1538 const SmallVectorImpl<ISD::OutputArg> &Outs,
1539 const SmallVectorImpl<SDValue> &OutVals,
1540 DebugLoc dl, SelectionDAG &DAG) const {
1542 // CCValAssign - represent the assignment of the return value to a location.
1543 SmallVector<CCValAssign, 16> RVLocs;
1545 // CCState - Info about the registers and stack slots.
1546 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1549 // Analyze outgoing return values.
1550 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1553 // If this is the first return lowered for this function, add
1554 // the regs to the liveout set for the function.
1555 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1556 for (unsigned i = 0; i != RVLocs.size(); ++i)
1557 if (RVLocs[i].isRegLoc())
1558 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1563 // Copy the result values into the output registers.
1564 for (unsigned i = 0, realRVLocIdx = 0;
1566 ++i, ++realRVLocIdx) {
1567 CCValAssign &VA = RVLocs[i];
1568 assert(VA.isRegLoc() && "Can only return in registers!");
1570 SDValue Arg = OutVals[realRVLocIdx];
1572 switch (VA.getLocInfo()) {
1573 default: llvm_unreachable("Unknown loc info!");
1574 case CCValAssign::Full: break;
1575 case CCValAssign::BCvt:
1576 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1580 if (VA.needsCustom()) {
1581 if (VA.getLocVT() == MVT::v2f64) {
1582 // Extract the first half and return it in two registers.
1583 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1584 DAG.getConstant(0, MVT::i32));
1585 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1586 DAG.getVTList(MVT::i32, MVT::i32), Half);
1588 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1589 Flag = Chain.getValue(1);
1590 VA = RVLocs[++i]; // skip ahead to next loc
1591 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1592 HalfGPRs.getValue(1), Flag);
1593 Flag = Chain.getValue(1);
1594 VA = RVLocs[++i]; // skip ahead to next loc
1596 // Extract the 2nd half and fall through to handle it as an f64 value.
1597 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1598 DAG.getConstant(1, MVT::i32));
1600 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1602 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1603 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1604 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1605 Flag = Chain.getValue(1);
1606 VA = RVLocs[++i]; // skip ahead to next loc
1607 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1610 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1612 // Guarantee that all emitted copies are
1613 // stuck together, avoiding something bad.
1614 Flag = Chain.getValue(1);
1619 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1621 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1626 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1627 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1628 // one of the above mentioned nodes. It has to be wrapped because otherwise
1629 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1630 // be used to form addressing mode. These wrapped nodes will be selected
1632 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1633 EVT PtrVT = Op.getValueType();
1634 // FIXME there is no actual debug info here
1635 DebugLoc dl = Op.getDebugLoc();
1636 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1638 if (CP->isMachineConstantPoolEntry())
1639 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1640 CP->getAlignment());
1642 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1643 CP->getAlignment());
1644 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1647 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1648 return MachineJumpTableInfo::EK_Inline;
1651 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1652 SelectionDAG &DAG) const {
1653 MachineFunction &MF = DAG.getMachineFunction();
1654 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1655 unsigned ARMPCLabelIndex = 0;
1656 DebugLoc DL = Op.getDebugLoc();
1657 EVT PtrVT = getPointerTy();
1658 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1659 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1661 if (RelocM == Reloc::Static) {
1662 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1664 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1665 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1666 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1667 ARMCP::CPBlockAddress,
1669 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1671 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1672 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1673 PseudoSourceValue::getConstantPool(), 0,
1675 if (RelocM == Reloc::Static)
1677 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1678 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1681 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1683 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1684 SelectionDAG &DAG) const {
1685 DebugLoc dl = GA->getDebugLoc();
1686 EVT PtrVT = getPointerTy();
1687 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1688 MachineFunction &MF = DAG.getMachineFunction();
1689 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1690 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1691 ARMConstantPoolValue *CPV =
1692 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1693 ARMCP::CPValue, PCAdj, "tlsgd", true);
1694 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1695 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1696 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1697 PseudoSourceValue::getConstantPool(), 0,
1699 SDValue Chain = Argument.getValue(1);
1701 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1702 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1704 // call __tls_get_addr.
1707 Entry.Node = Argument;
1708 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1709 Args.push_back(Entry);
1710 // FIXME: is there useful debug info available here?
1711 std::pair<SDValue, SDValue> CallResult =
1712 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1713 false, false, false, false,
1714 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1715 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1716 return CallResult.first;
1719 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1720 // "local exec" model.
1722 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1723 SelectionDAG &DAG) const {
1724 const GlobalValue *GV = GA->getGlobal();
1725 DebugLoc dl = GA->getDebugLoc();
1727 SDValue Chain = DAG.getEntryNode();
1728 EVT PtrVT = getPointerTy();
1729 // Get the Thread Pointer
1730 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1732 if (GV->isDeclaration()) {
1733 MachineFunction &MF = DAG.getMachineFunction();
1734 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1735 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1736 // Initial exec model.
1737 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1738 ARMConstantPoolValue *CPV =
1739 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1740 ARMCP::CPValue, PCAdj, "gottpoff", true);
1741 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1742 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1743 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1744 PseudoSourceValue::getConstantPool(), 0,
1746 Chain = Offset.getValue(1);
1748 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1749 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1751 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1752 PseudoSourceValue::getConstantPool(), 0,
1756 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1757 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1758 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1759 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1760 PseudoSourceValue::getConstantPool(), 0,
1764 // The address of the thread local variable is the add of the thread
1765 // pointer with the offset of the variable.
1766 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1770 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1771 // TODO: implement the "local dynamic" model
1772 assert(Subtarget->isTargetELF() &&
1773 "TLS not implemented for non-ELF targets");
1774 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1775 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1776 // otherwise use the "Local Exec" TLS Model
1777 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1778 return LowerToTLSGeneralDynamicModel(GA, DAG);
1780 return LowerToTLSExecModels(GA, DAG);
1783 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1784 SelectionDAG &DAG) const {
1785 EVT PtrVT = getPointerTy();
1786 DebugLoc dl = Op.getDebugLoc();
1787 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1788 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1789 if (RelocM == Reloc::PIC_) {
1790 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1791 ARMConstantPoolValue *CPV =
1792 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1793 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1794 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1795 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1797 PseudoSourceValue::getConstantPool(), 0,
1799 SDValue Chain = Result.getValue(1);
1800 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1801 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1803 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1804 PseudoSourceValue::getGOT(), 0,
1808 // If we have T2 ops, we can materialize the address directly via movt/movw
1809 // pair. This is always cheaper.
1810 if (Subtarget->useMovt()) {
1811 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1812 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1814 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1815 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1816 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1817 PseudoSourceValue::getConstantPool(), 0,
1823 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1824 SelectionDAG &DAG) const {
1825 MachineFunction &MF = DAG.getMachineFunction();
1826 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1827 unsigned ARMPCLabelIndex = 0;
1828 EVT PtrVT = getPointerTy();
1829 DebugLoc dl = Op.getDebugLoc();
1830 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1831 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1833 if (RelocM == Reloc::Static)
1834 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1836 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1837 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1838 ARMConstantPoolValue *CPV =
1839 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1840 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1842 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1844 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1845 PseudoSourceValue::getConstantPool(), 0,
1847 SDValue Chain = Result.getValue(1);
1849 if (RelocM == Reloc::PIC_) {
1850 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1851 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1854 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1855 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1856 PseudoSourceValue::getGOT(), 0,
1862 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1863 SelectionDAG &DAG) const {
1864 assert(Subtarget->isTargetELF() &&
1865 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1866 MachineFunction &MF = DAG.getMachineFunction();
1867 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1868 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1869 EVT PtrVT = getPointerTy();
1870 DebugLoc dl = Op.getDebugLoc();
1871 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1872 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1873 "_GLOBAL_OFFSET_TABLE_",
1874 ARMPCLabelIndex, PCAdj);
1875 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1876 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1877 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1878 PseudoSourceValue::getConstantPool(), 0,
1880 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1881 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1885 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1886 DebugLoc dl = Op.getDebugLoc();
1887 SDValue Val = DAG.getConstant(0, MVT::i32);
1888 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1889 Op.getOperand(1), Val);
1893 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1894 DebugLoc dl = Op.getDebugLoc();
1895 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1896 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1900 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1901 const ARMSubtarget *Subtarget) const {
1902 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1903 DebugLoc dl = Op.getDebugLoc();
1905 default: return SDValue(); // Don't custom lower most intrinsics.
1906 case Intrinsic::arm_thread_pointer: {
1907 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1908 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1910 case Intrinsic::eh_sjlj_lsda: {
1911 MachineFunction &MF = DAG.getMachineFunction();
1912 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1913 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1914 EVT PtrVT = getPointerTy();
1915 DebugLoc dl = Op.getDebugLoc();
1916 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1918 unsigned PCAdj = (RelocM != Reloc::PIC_)
1919 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1920 ARMConstantPoolValue *CPV =
1921 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1922 ARMCP::CPLSDA, PCAdj);
1923 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1924 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1926 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1927 PseudoSourceValue::getConstantPool(), 0,
1930 if (RelocM == Reloc::PIC_) {
1931 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1932 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1939 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1940 const ARMSubtarget *Subtarget) {
1941 DebugLoc dl = Op.getDebugLoc();
1942 SDValue Op5 = Op.getOperand(5);
1943 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1944 // v6 and v7 can both handle barriers directly, but need handled a bit
1945 // differently. Thumb1 and pre-v6 ARM mode use a libcall instead and should
1947 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER;
1948 if (Subtarget->hasV7Ops())
1949 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0));
1950 else if (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())
1951 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0),
1952 DAG.getConstant(0, MVT::i32));
1953 assert(0 && "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
1957 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
1958 MachineFunction &MF = DAG.getMachineFunction();
1959 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
1961 // vastart just stores the address of the VarArgsFrameIndex slot into the
1962 // memory location argument.
1963 DebugLoc dl = Op.getDebugLoc();
1964 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1965 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1966 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1967 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1972 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1973 SelectionDAG &DAG) const {
1974 SDNode *Node = Op.getNode();
1975 DebugLoc dl = Node->getDebugLoc();
1976 EVT VT = Node->getValueType(0);
1977 SDValue Chain = Op.getOperand(0);
1978 SDValue Size = Op.getOperand(1);
1979 SDValue Align = Op.getOperand(2);
1981 // Chain the dynamic stack allocation so that it doesn't modify the stack
1982 // pointer when other instructions are using the stack.
1983 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1985 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1986 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1987 if (AlignVal > StackAlign)
1988 // Do this now since selection pass cannot introduce new target
1989 // independent node.
1990 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1992 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1993 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1994 // do even more horrible hack later.
1995 MachineFunction &MF = DAG.getMachineFunction();
1996 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1997 if (AFI->isThumb1OnlyFunction()) {
1999 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
2001 uint32_t Val = C->getZExtValue();
2002 if (Val <= 508 && ((Val & 3) == 0))
2006 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
2009 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2010 SDValue Ops1[] = { Chain, Size, Align };
2011 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
2012 Chain = Res.getValue(1);
2013 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
2014 DAG.getIntPtrConstant(0, true), SDValue());
2015 SDValue Ops2[] = { Res, Chain };
2016 return DAG.getMergeValues(Ops2, 2, dl);
2020 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2021 SDValue &Root, SelectionDAG &DAG,
2022 DebugLoc dl) const {
2023 MachineFunction &MF = DAG.getMachineFunction();
2024 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2026 TargetRegisterClass *RC;
2027 if (AFI->isThumb1OnlyFunction())
2028 RC = ARM::tGPRRegisterClass;
2030 RC = ARM::GPRRegisterClass;
2032 // Transform the arguments stored in physical registers into virtual ones.
2033 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2034 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2037 if (NextVA.isMemLoc()) {
2038 MachineFrameInfo *MFI = MF.getFrameInfo();
2039 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2041 // Create load node to retrieve arguments from the stack.
2042 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2043 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2044 PseudoSourceValue::getFixedStack(FI), 0,
2047 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2048 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2051 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2055 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2056 CallingConv::ID CallConv, bool isVarArg,
2057 const SmallVectorImpl<ISD::InputArg>
2059 DebugLoc dl, SelectionDAG &DAG,
2060 SmallVectorImpl<SDValue> &InVals)
2063 MachineFunction &MF = DAG.getMachineFunction();
2064 MachineFrameInfo *MFI = MF.getFrameInfo();
2066 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2068 // Assign locations to all of the incoming arguments.
2069 SmallVector<CCValAssign, 16> ArgLocs;
2070 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2072 CCInfo.AnalyzeFormalArguments(Ins,
2073 CCAssignFnForNode(CallConv, /* Return*/ false,
2076 SmallVector<SDValue, 16> ArgValues;
2078 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2079 CCValAssign &VA = ArgLocs[i];
2081 // Arguments stored in registers.
2082 if (VA.isRegLoc()) {
2083 EVT RegVT = VA.getLocVT();
2086 if (VA.needsCustom()) {
2087 // f64 and vector types are split up into multiple registers or
2088 // combinations of registers and stack slots.
2089 if (VA.getLocVT() == MVT::v2f64) {
2090 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2092 VA = ArgLocs[++i]; // skip ahead to next loc
2094 if (VA.isMemLoc()) {
2095 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2096 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2097 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2098 PseudoSourceValue::getFixedStack(FI), 0,
2101 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2104 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2105 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2106 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2107 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2108 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2110 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2113 TargetRegisterClass *RC;
2115 if (RegVT == MVT::f32)
2116 RC = ARM::SPRRegisterClass;
2117 else if (RegVT == MVT::f64)
2118 RC = ARM::DPRRegisterClass;
2119 else if (RegVT == MVT::v2f64)
2120 RC = ARM::QPRRegisterClass;
2121 else if (RegVT == MVT::i32)
2122 RC = (AFI->isThumb1OnlyFunction() ?
2123 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2125 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2127 // Transform the arguments in physical registers into virtual ones.
2128 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2129 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2132 // If this is an 8 or 16-bit value, it is really passed promoted
2133 // to 32 bits. Insert an assert[sz]ext to capture this, then
2134 // truncate to the right size.
2135 switch (VA.getLocInfo()) {
2136 default: llvm_unreachable("Unknown loc info!");
2137 case CCValAssign::Full: break;
2138 case CCValAssign::BCvt:
2139 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2141 case CCValAssign::SExt:
2142 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2143 DAG.getValueType(VA.getValVT()));
2144 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2146 case CCValAssign::ZExt:
2147 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2148 DAG.getValueType(VA.getValVT()));
2149 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2153 InVals.push_back(ArgValue);
2155 } else { // VA.isRegLoc()
2158 assert(VA.isMemLoc());
2159 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2161 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2162 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2164 // Create load nodes to retrieve arguments from the stack.
2165 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2166 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2167 PseudoSourceValue::getFixedStack(FI), 0,
2174 static const unsigned GPRArgRegs[] = {
2175 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2178 unsigned NumGPRs = CCInfo.getFirstUnallocated
2179 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2181 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2182 unsigned VARegSize = (4 - NumGPRs) * 4;
2183 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2184 unsigned ArgOffset = CCInfo.getNextStackOffset();
2185 if (VARegSaveSize) {
2186 // If this function is vararg, store any remaining integer argument regs
2187 // to their spots on the stack so that they may be loaded by deferencing
2188 // the result of va_next.
2189 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2190 AFI->setVarArgsFrameIndex(
2191 MFI->CreateFixedObject(VARegSaveSize,
2192 ArgOffset + VARegSaveSize - VARegSize,
2194 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2197 SmallVector<SDValue, 4> MemOps;
2198 for (; NumGPRs < 4; ++NumGPRs) {
2199 TargetRegisterClass *RC;
2200 if (AFI->isThumb1OnlyFunction())
2201 RC = ARM::tGPRRegisterClass;
2203 RC = ARM::GPRRegisterClass;
2205 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2206 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2208 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2209 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()),
2210 0, false, false, 0);
2211 MemOps.push_back(Store);
2212 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2213 DAG.getConstant(4, getPointerTy()));
2215 if (!MemOps.empty())
2216 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2217 &MemOps[0], MemOps.size());
2219 // This will point to the next argument passed via stack.
2220 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2226 /// isFloatingPointZero - Return true if this is +0.0.
2227 static bool isFloatingPointZero(SDValue Op) {
2228 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2229 return CFP->getValueAPF().isPosZero();
2230 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2231 // Maybe this has already been legalized into the constant pool?
2232 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2233 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2234 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2235 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2236 return CFP->getValueAPF().isPosZero();
2242 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2243 /// the given operands.
2245 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2246 SDValue &ARMcc, SelectionDAG &DAG,
2247 DebugLoc dl) const {
2248 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2249 unsigned C = RHSC->getZExtValue();
2250 if (!isLegalICmpImmediate(C)) {
2251 // Constant does not fit, try adjusting it by one?
2256 if (isLegalICmpImmediate(C-1)) {
2257 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2258 RHS = DAG.getConstant(C-1, MVT::i32);
2263 if (C > 0 && isLegalICmpImmediate(C-1)) {
2264 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2265 RHS = DAG.getConstant(C-1, MVT::i32);
2270 if (isLegalICmpImmediate(C+1)) {
2271 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2272 RHS = DAG.getConstant(C+1, MVT::i32);
2277 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
2278 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2279 RHS = DAG.getConstant(C+1, MVT::i32);
2286 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2287 ARMISD::NodeType CompareType;
2290 CompareType = ARMISD::CMP;
2295 CompareType = ARMISD::CMPZ;
2298 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2299 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2302 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2304 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2305 DebugLoc dl) const {
2307 if (!isFloatingPointZero(RHS))
2308 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2310 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2311 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2314 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2315 EVT VT = Op.getValueType();
2316 SDValue LHS = Op.getOperand(0);
2317 SDValue RHS = Op.getOperand(1);
2318 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2319 SDValue TrueVal = Op.getOperand(2);
2320 SDValue FalseVal = Op.getOperand(3);
2321 DebugLoc dl = Op.getDebugLoc();
2323 if (LHS.getValueType() == MVT::i32) {
2325 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2326 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2327 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2330 ARMCC::CondCodes CondCode, CondCode2;
2331 FPCCToARMCC(CC, CondCode, CondCode2);
2333 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2334 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2335 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2336 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2338 if (CondCode2 != ARMCC::AL) {
2339 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2340 // FIXME: Needs another CMP because flag can have but one use.
2341 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2342 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2343 Result, TrueVal, ARMcc2, CCR, Cmp2);
2348 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2349 /// to morph to an integer compare sequence.
2350 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2351 const ARMSubtarget *Subtarget) {
2352 SDNode *N = Op.getNode();
2353 if (!N->hasOneUse())
2354 // Otherwise it requires moving the value from fp to integer registers.
2356 if (!N->getNumValues())
2358 EVT VT = Op.getValueType();
2359 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2360 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2361 // vmrs are very slow, e.g. cortex-a8.
2364 if (isFloatingPointZero(Op)) {
2368 return ISD::isNormalLoad(N);
2371 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2372 if (isFloatingPointZero(Op))
2373 return DAG.getConstant(0, MVT::i32);
2375 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2376 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2377 Ld->getChain(), Ld->getBasePtr(),
2378 Ld->getSrcValue(), Ld->getSrcValueOffset(),
2379 Ld->isVolatile(), Ld->isNonTemporal(),
2380 Ld->getAlignment());
2382 llvm_unreachable("Unknown VFP cmp argument!");
2385 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2386 SDValue &RetVal1, SDValue &RetVal2) {
2387 if (isFloatingPointZero(Op)) {
2388 RetVal1 = DAG.getConstant(0, MVT::i32);
2389 RetVal2 = DAG.getConstant(0, MVT::i32);
2393 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2394 SDValue Ptr = Ld->getBasePtr();
2395 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2396 Ld->getChain(), Ptr,
2397 Ld->getSrcValue(), Ld->getSrcValueOffset(),
2398 Ld->isVolatile(), Ld->isNonTemporal(),
2399 Ld->getAlignment());
2401 EVT PtrType = Ptr.getValueType();
2402 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2403 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2404 PtrType, Ptr, DAG.getConstant(4, PtrType));
2405 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2406 Ld->getChain(), NewPtr,
2407 Ld->getSrcValue(), Ld->getSrcValueOffset() + 4,
2408 Ld->isVolatile(), Ld->isNonTemporal(),
2413 llvm_unreachable("Unknown VFP cmp argument!");
2416 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2417 /// f32 and even f64 comparisons to integer ones.
2419 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2420 SDValue Chain = Op.getOperand(0);
2421 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2422 SDValue LHS = Op.getOperand(2);
2423 SDValue RHS = Op.getOperand(3);
2424 SDValue Dest = Op.getOperand(4);
2425 DebugLoc dl = Op.getDebugLoc();
2427 bool SeenZero = false;
2428 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2429 canChangeToInt(RHS, SeenZero, Subtarget) &&
2430 // If one of the operand is zero, it's safe to ignore the NaN case since
2431 // we only care about equality comparisons.
2432 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2433 // If unsafe fp math optimization is enabled and there are no othter uses of
2434 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2435 // to an integer comparison.
2436 if (CC == ISD::SETOEQ)
2438 else if (CC == ISD::SETUNE)
2442 if (LHS.getValueType() == MVT::f32) {
2443 LHS = bitcastf32Toi32(LHS, DAG);
2444 RHS = bitcastf32Toi32(RHS, DAG);
2445 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2446 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2447 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2448 Chain, Dest, ARMcc, CCR, Cmp);
2453 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2454 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2455 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2456 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2457 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2458 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2459 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2465 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2466 SDValue Chain = Op.getOperand(0);
2467 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2468 SDValue LHS = Op.getOperand(2);
2469 SDValue RHS = Op.getOperand(3);
2470 SDValue Dest = Op.getOperand(4);
2471 DebugLoc dl = Op.getDebugLoc();
2473 if (LHS.getValueType() == MVT::i32) {
2475 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2476 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2477 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2478 Chain, Dest, ARMcc, CCR, Cmp);
2481 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2484 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2485 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2486 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2487 if (Result.getNode())
2491 ARMCC::CondCodes CondCode, CondCode2;
2492 FPCCToARMCC(CC, CondCode, CondCode2);
2494 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2495 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2496 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2497 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2498 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2499 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2500 if (CondCode2 != ARMCC::AL) {
2501 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2502 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2503 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2508 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2509 SDValue Chain = Op.getOperand(0);
2510 SDValue Table = Op.getOperand(1);
2511 SDValue Index = Op.getOperand(2);
2512 DebugLoc dl = Op.getDebugLoc();
2514 EVT PTy = getPointerTy();
2515 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2516 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2517 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2518 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2519 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2520 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2521 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2522 if (Subtarget->isThumb2()) {
2523 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2524 // which does another jump to the destination. This also makes it easier
2525 // to translate it to TBB / TBH later.
2526 // FIXME: This might not work if the function is extremely large.
2527 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2528 Addr, Op.getOperand(2), JTI, UId);
2530 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2531 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2532 PseudoSourceValue::getJumpTable(), 0,
2534 Chain = Addr.getValue(1);
2535 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2536 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2538 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2539 PseudoSourceValue::getJumpTable(), 0, false, false, 0);
2540 Chain = Addr.getValue(1);
2541 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2545 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2546 DebugLoc dl = Op.getDebugLoc();
2549 switch (Op.getOpcode()) {
2551 assert(0 && "Invalid opcode!");
2552 case ISD::FP_TO_SINT:
2553 Opc = ARMISD::FTOSI;
2555 case ISD::FP_TO_UINT:
2556 Opc = ARMISD::FTOUI;
2559 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2560 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2563 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2564 EVT VT = Op.getValueType();
2565 DebugLoc dl = Op.getDebugLoc();
2568 switch (Op.getOpcode()) {
2570 assert(0 && "Invalid opcode!");
2571 case ISD::SINT_TO_FP:
2572 Opc = ARMISD::SITOF;
2574 case ISD::UINT_TO_FP:
2575 Opc = ARMISD::UITOF;
2579 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2580 return DAG.getNode(Opc, dl, VT, Op);
2583 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2584 // Implement fcopysign with a fabs and a conditional fneg.
2585 SDValue Tmp0 = Op.getOperand(0);
2586 SDValue Tmp1 = Op.getOperand(1);
2587 DebugLoc dl = Op.getDebugLoc();
2588 EVT VT = Op.getValueType();
2589 EVT SrcVT = Tmp1.getValueType();
2590 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2591 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2592 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2593 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2594 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2595 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2598 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2599 MachineFunction &MF = DAG.getMachineFunction();
2600 MachineFrameInfo *MFI = MF.getFrameInfo();
2601 MFI->setReturnAddressIsTaken(true);
2603 EVT VT = Op.getValueType();
2604 DebugLoc dl = Op.getDebugLoc();
2605 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2607 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2608 SDValue Offset = DAG.getConstant(4, MVT::i32);
2609 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2610 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2611 NULL, 0, false, false, 0);
2614 // Return LR, which contains the return address. Mark it an implicit live-in.
2615 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
2616 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2619 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2620 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2621 MFI->setFrameAddressIsTaken(true);
2623 EVT VT = Op.getValueType();
2624 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2625 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2626 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2627 ? ARM::R7 : ARM::R11;
2628 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2630 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
2635 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2636 /// expand a bit convert where either the source or destination type is i64 to
2637 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2638 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2639 /// vectors), since the legalizer won't know what to do with that.
2640 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2641 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2642 DebugLoc dl = N->getDebugLoc();
2643 SDValue Op = N->getOperand(0);
2645 // This function is only supposed to be called for i64 types, either as the
2646 // source or destination of the bit convert.
2647 EVT SrcVT = Op.getValueType();
2648 EVT DstVT = N->getValueType(0);
2649 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2650 "ExpandBIT_CONVERT called for non-i64 type");
2652 // Turn i64->f64 into VMOVDRR.
2653 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2654 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2655 DAG.getConstant(0, MVT::i32));
2656 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2657 DAG.getConstant(1, MVT::i32));
2658 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2659 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2662 // Turn f64->i64 into VMOVRRD.
2663 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2664 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2665 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2666 // Merge the pieces into a single i64 value.
2667 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2673 /// getZeroVector - Returns a vector of specified type with all zero elements.
2674 /// Zero vectors are used to represent vector negation and in those cases
2675 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2676 /// not support i64 elements, so sometimes the zero vectors will need to be
2677 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2679 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2680 assert(VT.isVector() && "Expected a vector type");
2681 // The canonical modified immediate encoding of a zero vector is....0!
2682 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2683 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2684 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2685 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2688 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2689 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2690 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2691 SelectionDAG &DAG) const {
2692 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2693 EVT VT = Op.getValueType();
2694 unsigned VTBits = VT.getSizeInBits();
2695 DebugLoc dl = Op.getDebugLoc();
2696 SDValue ShOpLo = Op.getOperand(0);
2697 SDValue ShOpHi = Op.getOperand(1);
2698 SDValue ShAmt = Op.getOperand(2);
2700 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2702 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2704 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2705 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2706 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2707 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2708 DAG.getConstant(VTBits, MVT::i32));
2709 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2710 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2711 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2713 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2714 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2716 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2717 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2720 SDValue Ops[2] = { Lo, Hi };
2721 return DAG.getMergeValues(Ops, 2, dl);
2724 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2725 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2726 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2727 SelectionDAG &DAG) const {
2728 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2729 EVT VT = Op.getValueType();
2730 unsigned VTBits = VT.getSizeInBits();
2731 DebugLoc dl = Op.getDebugLoc();
2732 SDValue ShOpLo = Op.getOperand(0);
2733 SDValue ShOpHi = Op.getOperand(1);
2734 SDValue ShAmt = Op.getOperand(2);
2737 assert(Op.getOpcode() == ISD::SHL_PARTS);
2738 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2739 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2740 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2741 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2742 DAG.getConstant(VTBits, MVT::i32));
2743 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2744 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2746 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2747 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2748 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2750 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2751 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2754 SDValue Ops[2] = { Lo, Hi };
2755 return DAG.getMergeValues(Ops, 2, dl);
2758 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2759 const ARMSubtarget *ST) {
2760 EVT VT = N->getValueType(0);
2761 DebugLoc dl = N->getDebugLoc();
2763 if (!ST->hasV6T2Ops())
2766 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2767 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2770 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2771 const ARMSubtarget *ST) {
2772 EVT VT = N->getValueType(0);
2773 DebugLoc dl = N->getDebugLoc();
2775 // Lower vector shifts on NEON to use VSHL.
2776 if (VT.isVector()) {
2777 assert(ST->hasNEON() && "unexpected vector shift");
2779 // Left shifts translate directly to the vshiftu intrinsic.
2780 if (N->getOpcode() == ISD::SHL)
2781 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2782 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2783 N->getOperand(0), N->getOperand(1));
2785 assert((N->getOpcode() == ISD::SRA ||
2786 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2788 // NEON uses the same intrinsics for both left and right shifts. For
2789 // right shifts, the shift amounts are negative, so negate the vector of
2791 EVT ShiftVT = N->getOperand(1).getValueType();
2792 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2793 getZeroVector(ShiftVT, DAG, dl),
2795 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2796 Intrinsic::arm_neon_vshifts :
2797 Intrinsic::arm_neon_vshiftu);
2798 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2799 DAG.getConstant(vshiftInt, MVT::i32),
2800 N->getOperand(0), NegatedCount);
2803 // We can get here for a node like i32 = ISD::SHL i32, i64
2807 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2808 "Unknown shift to lower!");
2810 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2811 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2812 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2815 // If we are in thumb mode, we don't have RRX.
2816 if (ST->isThumb1Only()) return SDValue();
2818 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2819 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2820 DAG.getConstant(0, MVT::i32));
2821 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2822 DAG.getConstant(1, MVT::i32));
2824 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2825 // captures the result into a carry flag.
2826 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2827 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2829 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2830 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2832 // Merge the pieces into a single i64 value.
2833 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2836 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2837 SDValue TmpOp0, TmpOp1;
2838 bool Invert = false;
2842 SDValue Op0 = Op.getOperand(0);
2843 SDValue Op1 = Op.getOperand(1);
2844 SDValue CC = Op.getOperand(2);
2845 EVT VT = Op.getValueType();
2846 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2847 DebugLoc dl = Op.getDebugLoc();
2849 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2850 switch (SetCCOpcode) {
2851 default: llvm_unreachable("Illegal FP comparison"); break;
2853 case ISD::SETNE: Invert = true; // Fallthrough
2855 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2857 case ISD::SETLT: Swap = true; // Fallthrough
2859 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2861 case ISD::SETLE: Swap = true; // Fallthrough
2863 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2864 case ISD::SETUGE: Swap = true; // Fallthrough
2865 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2866 case ISD::SETUGT: Swap = true; // Fallthrough
2867 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2868 case ISD::SETUEQ: Invert = true; // Fallthrough
2870 // Expand this to (OLT | OGT).
2874 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2875 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2877 case ISD::SETUO: Invert = true; // Fallthrough
2879 // Expand this to (OLT | OGE).
2883 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2884 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2888 // Integer comparisons.
2889 switch (SetCCOpcode) {
2890 default: llvm_unreachable("Illegal integer comparison"); break;
2891 case ISD::SETNE: Invert = true;
2892 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2893 case ISD::SETLT: Swap = true;
2894 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2895 case ISD::SETLE: Swap = true;
2896 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2897 case ISD::SETULT: Swap = true;
2898 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2899 case ISD::SETULE: Swap = true;
2900 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2903 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2904 if (Opc == ARMISD::VCEQ) {
2907 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2909 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2912 // Ignore bitconvert.
2913 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2914 AndOp = AndOp.getOperand(0);
2916 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2918 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2919 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2926 std::swap(Op0, Op1);
2928 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2931 Result = DAG.getNOT(dl, Result, VT);
2936 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
2937 /// valid vector constant for a NEON instruction with a "modified immediate"
2938 /// operand (e.g., VMOV). If so, return the encoded value.
2939 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
2940 unsigned SplatBitSize, SelectionDAG &DAG,
2941 EVT &VT, bool is128Bits, bool isVMOV) {
2942 unsigned OpCmode, Imm;
2944 // SplatBitSize is set to the smallest size that splats the vector, so a
2945 // zero vector will always have SplatBitSize == 8. However, NEON modified
2946 // immediate instructions others than VMOV do not support the 8-bit encoding
2947 // of a zero vector, and the default encoding of zero is supposed to be the
2952 switch (SplatBitSize) {
2956 // Any 1-byte value is OK. Op=0, Cmode=1110.
2957 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2960 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
2964 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2965 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
2966 if ((SplatBits & ~0xff) == 0) {
2967 // Value = 0x00nn: Op=x, Cmode=100x.
2972 if ((SplatBits & ~0xff00) == 0) {
2973 // Value = 0xnn00: Op=x, Cmode=101x.
2975 Imm = SplatBits >> 8;
2981 // NEON's 32-bit VMOV supports splat values where:
2982 // * only one byte is nonzero, or
2983 // * the least significant byte is 0xff and the second byte is nonzero, or
2984 // * the least significant 2 bytes are 0xff and the third is nonzero.
2985 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
2986 if ((SplatBits & ~0xff) == 0) {
2987 // Value = 0x000000nn: Op=x, Cmode=000x.
2992 if ((SplatBits & ~0xff00) == 0) {
2993 // Value = 0x0000nn00: Op=x, Cmode=001x.
2995 Imm = SplatBits >> 8;
2998 if ((SplatBits & ~0xff0000) == 0) {
2999 // Value = 0x00nn0000: Op=x, Cmode=010x.
3001 Imm = SplatBits >> 16;
3004 if ((SplatBits & ~0xff000000) == 0) {
3005 // Value = 0xnn000000: Op=x, Cmode=011x.
3007 Imm = SplatBits >> 24;
3011 if ((SplatBits & ~0xffff) == 0 &&
3012 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3013 // Value = 0x0000nnff: Op=x, Cmode=1100.
3015 Imm = SplatBits >> 8;
3020 if ((SplatBits & ~0xffffff) == 0 &&
3021 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3022 // Value = 0x00nnffff: Op=x, Cmode=1101.
3024 Imm = SplatBits >> 16;
3025 SplatBits |= 0xffff;
3029 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3030 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3031 // VMOV.I32. A (very) minor optimization would be to replicate the value
3032 // and fall through here to test for a valid 64-bit splat. But, then the
3033 // caller would also need to check and handle the change in size.
3039 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3040 uint64_t BitMask = 0xff;
3042 unsigned ImmMask = 1;
3044 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3045 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3048 } else if ((SplatBits & BitMask) != 0) {
3054 // Op=1, Cmode=1110.
3057 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3062 llvm_unreachable("unexpected size for isNEONModifiedImm");
3066 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3067 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3070 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3071 bool &ReverseVEXT, unsigned &Imm) {
3072 unsigned NumElts = VT.getVectorNumElements();
3073 ReverseVEXT = false;
3076 // If this is a VEXT shuffle, the immediate value is the index of the first
3077 // element. The other shuffle indices must be the successive elements after
3079 unsigned ExpectedElt = Imm;
3080 for (unsigned i = 1; i < NumElts; ++i) {
3081 // Increment the expected index. If it wraps around, it may still be
3082 // a VEXT but the source vectors must be swapped.
3084 if (ExpectedElt == NumElts * 2) {
3089 if (ExpectedElt != static_cast<unsigned>(M[i]))
3093 // Adjust the index value if the source operands will be swapped.
3100 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3101 /// instruction with the specified blocksize. (The order of the elements
3102 /// within each block of the vector is reversed.)
3103 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3104 unsigned BlockSize) {
3105 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3106 "Only possible block sizes for VREV are: 16, 32, 64");
3108 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3112 unsigned NumElts = VT.getVectorNumElements();
3113 unsigned BlockElts = M[0] + 1;
3115 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3118 for (unsigned i = 0; i < NumElts; ++i) {
3119 if ((unsigned) M[i] !=
3120 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3127 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3128 unsigned &WhichResult) {
3129 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3133 unsigned NumElts = VT.getVectorNumElements();
3134 WhichResult = (M[0] == 0 ? 0 : 1);
3135 for (unsigned i = 0; i < NumElts; i += 2) {
3136 if ((unsigned) M[i] != i + WhichResult ||
3137 (unsigned) M[i+1] != i + NumElts + WhichResult)
3143 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3144 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3145 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3146 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3147 unsigned &WhichResult) {
3148 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3152 unsigned NumElts = VT.getVectorNumElements();
3153 WhichResult = (M[0] == 0 ? 0 : 1);
3154 for (unsigned i = 0; i < NumElts; i += 2) {
3155 if ((unsigned) M[i] != i + WhichResult ||
3156 (unsigned) M[i+1] != i + WhichResult)
3162 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3163 unsigned &WhichResult) {
3164 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3168 unsigned NumElts = VT.getVectorNumElements();
3169 WhichResult = (M[0] == 0 ? 0 : 1);
3170 for (unsigned i = 0; i != NumElts; ++i) {
3171 if ((unsigned) M[i] != 2 * i + WhichResult)
3175 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3176 if (VT.is64BitVector() && EltSz == 32)
3182 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3183 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3184 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3185 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3186 unsigned &WhichResult) {
3187 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3191 unsigned Half = VT.getVectorNumElements() / 2;
3192 WhichResult = (M[0] == 0 ? 0 : 1);
3193 for (unsigned j = 0; j != 2; ++j) {
3194 unsigned Idx = WhichResult;
3195 for (unsigned i = 0; i != Half; ++i) {
3196 if ((unsigned) M[i + j * Half] != Idx)
3202 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3203 if (VT.is64BitVector() && EltSz == 32)
3209 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3210 unsigned &WhichResult) {
3211 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3215 unsigned NumElts = VT.getVectorNumElements();
3216 WhichResult = (M[0] == 0 ? 0 : 1);
3217 unsigned Idx = WhichResult * NumElts / 2;
3218 for (unsigned i = 0; i != NumElts; i += 2) {
3219 if ((unsigned) M[i] != Idx ||
3220 (unsigned) M[i+1] != Idx + NumElts)
3225 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3226 if (VT.is64BitVector() && EltSz == 32)
3232 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3233 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3234 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3235 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3236 unsigned &WhichResult) {
3237 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3241 unsigned NumElts = VT.getVectorNumElements();
3242 WhichResult = (M[0] == 0 ? 0 : 1);
3243 unsigned Idx = WhichResult * NumElts / 2;
3244 for (unsigned i = 0; i != NumElts; i += 2) {
3245 if ((unsigned) M[i] != Idx ||
3246 (unsigned) M[i+1] != Idx)
3251 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3252 if (VT.is64BitVector() && EltSz == 32)
3258 // If this is a case we can't handle, return null and let the default
3259 // expansion code take care of it.
3260 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3261 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3262 DebugLoc dl = Op.getDebugLoc();
3263 EVT VT = Op.getValueType();
3265 APInt SplatBits, SplatUndef;
3266 unsigned SplatBitSize;
3268 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3269 if (SplatBitSize <= 64) {
3270 // Check if an immediate VMOV works.
3272 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3273 SplatUndef.getZExtValue(), SplatBitSize,
3274 DAG, VmovVT, VT.is128BitVector(), true);
3275 if (Val.getNode()) {
3276 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3277 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3280 // Try an immediate VMVN.
3281 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3282 ((1LL << SplatBitSize) - 1));
3283 Val = isNEONModifiedImm(NegatedImm,
3284 SplatUndef.getZExtValue(), SplatBitSize,
3285 DAG, VmovVT, VT.is128BitVector(), false);
3286 if (Val.getNode()) {
3287 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3288 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3293 // Scan through the operands to see if only one value is used.
3294 unsigned NumElts = VT.getVectorNumElements();
3295 bool isOnlyLowElement = true;
3296 bool usesOnlyOneValue = true;
3297 bool isConstant = true;
3299 for (unsigned i = 0; i < NumElts; ++i) {
3300 SDValue V = Op.getOperand(i);
3301 if (V.getOpcode() == ISD::UNDEF)
3304 isOnlyLowElement = false;
3305 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3308 if (!Value.getNode())
3310 else if (V != Value)
3311 usesOnlyOneValue = false;
3314 if (!Value.getNode())
3315 return DAG.getUNDEF(VT);
3317 if (isOnlyLowElement)
3318 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3320 // If all elements are constants, fall back to the default expansion, which
3321 // will generate a load from the constant pool.
3325 // Use VDUP for non-constant splats.
3326 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3327 if (usesOnlyOneValue && EltSize <= 32)
3328 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3330 // Vectors with 32- or 64-bit elements can be built by directly assigning
3331 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3332 // will be legalized.
3333 if (EltSize >= 32) {
3334 // Do the expansion with floating-point types, since that is what the VFP
3335 // registers are defined to use, and since i64 is not legal.
3336 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3337 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3338 SmallVector<SDValue, 8> Ops;
3339 for (unsigned i = 0; i < NumElts; ++i)
3340 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3341 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3342 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3348 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3349 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3350 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3351 /// are assumed to be legal.
3353 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3355 if (VT.getVectorNumElements() == 4 &&
3356 (VT.is128BitVector() || VT.is64BitVector())) {
3357 unsigned PFIndexes[4];
3358 for (unsigned i = 0; i != 4; ++i) {
3362 PFIndexes[i] = M[i];
3365 // Compute the index in the perfect shuffle table.
3366 unsigned PFTableIndex =
3367 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3368 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3369 unsigned Cost = (PFEntry >> 30);
3376 unsigned Imm, WhichResult;
3378 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3379 return (EltSize >= 32 ||
3380 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3381 isVREVMask(M, VT, 64) ||
3382 isVREVMask(M, VT, 32) ||
3383 isVREVMask(M, VT, 16) ||
3384 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3385 isVTRNMask(M, VT, WhichResult) ||
3386 isVUZPMask(M, VT, WhichResult) ||
3387 isVZIPMask(M, VT, WhichResult) ||
3388 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3389 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3390 isVZIP_v_undef_Mask(M, VT, WhichResult));
3393 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3394 /// the specified operations to build the shuffle.
3395 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3396 SDValue RHS, SelectionDAG &DAG,
3398 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3399 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3400 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3403 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3412 OP_VUZPL, // VUZP, left result
3413 OP_VUZPR, // VUZP, right result
3414 OP_VZIPL, // VZIP, left result
3415 OP_VZIPR, // VZIP, right result
3416 OP_VTRNL, // VTRN, left result
3417 OP_VTRNR // VTRN, right result
3420 if (OpNum == OP_COPY) {
3421 if (LHSID == (1*9+2)*9+3) return LHS;
3422 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3426 SDValue OpLHS, OpRHS;
3427 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3428 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3429 EVT VT = OpLHS.getValueType();
3432 default: llvm_unreachable("Unknown shuffle opcode!");
3434 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3439 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3440 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3444 return DAG.getNode(ARMISD::VEXT, dl, VT,
3446 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3449 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3450 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3453 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3454 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3457 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3458 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3462 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3463 SDValue V1 = Op.getOperand(0);
3464 SDValue V2 = Op.getOperand(1);
3465 DebugLoc dl = Op.getDebugLoc();
3466 EVT VT = Op.getValueType();
3467 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3468 SmallVector<int, 8> ShuffleMask;
3470 // Convert shuffles that are directly supported on NEON to target-specific
3471 // DAG nodes, instead of keeping them as shuffles and matching them again
3472 // during code selection. This is more efficient and avoids the possibility
3473 // of inconsistencies between legalization and selection.
3474 // FIXME: floating-point vectors should be canonicalized to integer vectors
3475 // of the same time so that they get CSEd properly.
3476 SVN->getMask(ShuffleMask);
3478 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3479 if (EltSize <= 32) {
3480 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3481 int Lane = SVN->getSplatIndex();
3482 // If this is undef splat, generate it via "just" vdup, if possible.
3483 if (Lane == -1) Lane = 0;
3485 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3486 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3488 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3489 DAG.getConstant(Lane, MVT::i32));
3494 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3497 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3498 DAG.getConstant(Imm, MVT::i32));
3501 if (isVREVMask(ShuffleMask, VT, 64))
3502 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3503 if (isVREVMask(ShuffleMask, VT, 32))
3504 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3505 if (isVREVMask(ShuffleMask, VT, 16))
3506 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3508 // Check for Neon shuffles that modify both input vectors in place.
3509 // If both results are used, i.e., if there are two shuffles with the same
3510 // source operands and with masks corresponding to both results of one of
3511 // these operations, DAG memoization will ensure that a single node is
3512 // used for both shuffles.
3513 unsigned WhichResult;
3514 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3515 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3516 V1, V2).getValue(WhichResult);
3517 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3518 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3519 V1, V2).getValue(WhichResult);
3520 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3521 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3522 V1, V2).getValue(WhichResult);
3524 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3525 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3526 V1, V1).getValue(WhichResult);
3527 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3528 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3529 V1, V1).getValue(WhichResult);
3530 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3531 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3532 V1, V1).getValue(WhichResult);
3535 // If the shuffle is not directly supported and it has 4 elements, use
3536 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3537 unsigned NumElts = VT.getVectorNumElements();
3539 unsigned PFIndexes[4];
3540 for (unsigned i = 0; i != 4; ++i) {
3541 if (ShuffleMask[i] < 0)
3544 PFIndexes[i] = ShuffleMask[i];
3547 // Compute the index in the perfect shuffle table.
3548 unsigned PFTableIndex =
3549 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3550 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3551 unsigned Cost = (PFEntry >> 30);
3554 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3557 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3558 if (EltSize >= 32) {
3559 // Do the expansion with floating-point types, since that is what the VFP
3560 // registers are defined to use, and since i64 is not legal.
3561 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3562 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3563 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3564 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3565 SmallVector<SDValue, 8> Ops;
3566 for (unsigned i = 0; i < NumElts; ++i) {
3567 if (ShuffleMask[i] < 0)
3568 Ops.push_back(DAG.getUNDEF(EltVT));
3570 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3571 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3572 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3575 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3576 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3582 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3583 EVT VT = Op.getValueType();
3584 DebugLoc dl = Op.getDebugLoc();
3585 SDValue Vec = Op.getOperand(0);
3586 SDValue Lane = Op.getOperand(1);
3587 assert(VT == MVT::i32 &&
3588 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3589 "unexpected type for custom-lowering vector extract");
3590 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3593 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3594 // The only time a CONCAT_VECTORS operation can have legal types is when
3595 // two 64-bit vectors are concatenated to a 128-bit vector.
3596 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3597 "unexpected CONCAT_VECTORS");
3598 DebugLoc dl = Op.getDebugLoc();
3599 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3600 SDValue Op0 = Op.getOperand(0);
3601 SDValue Op1 = Op.getOperand(1);
3602 if (Op0.getOpcode() != ISD::UNDEF)
3603 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3604 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3605 DAG.getIntPtrConstant(0));
3606 if (Op1.getOpcode() != ISD::UNDEF)
3607 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3608 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3609 DAG.getIntPtrConstant(1));
3610 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3613 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3614 switch (Op.getOpcode()) {
3615 default: llvm_unreachable("Don't know how to custom lower this!");
3616 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3617 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3618 case ISD::GlobalAddress:
3619 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3620 LowerGlobalAddressELF(Op, DAG);
3621 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3622 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3623 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3624 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3625 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3626 case ISD::VASTART: return LowerVASTART(Op, DAG);
3627 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3628 case ISD::SINT_TO_FP:
3629 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3630 case ISD::FP_TO_SINT:
3631 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3632 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3633 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3634 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3635 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3636 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3637 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3638 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3640 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3643 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3644 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3645 case ISD::SRL_PARTS:
3646 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3647 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3648 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3649 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3650 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3651 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3652 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3657 /// ReplaceNodeResults - Replace the results of node with an illegal result
3658 /// type with new values built out of custom code.
3659 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3660 SmallVectorImpl<SDValue>&Results,
3661 SelectionDAG &DAG) const {
3663 switch (N->getOpcode()) {
3665 llvm_unreachable("Don't know how to custom expand this!");
3667 case ISD::BIT_CONVERT:
3668 Res = ExpandBIT_CONVERT(N, DAG);
3672 Res = LowerShift(N, DAG, Subtarget);
3676 Results.push_back(Res);
3679 //===----------------------------------------------------------------------===//
3680 // ARM Scheduler Hooks
3681 //===----------------------------------------------------------------------===//
3684 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3685 MachineBasicBlock *BB,
3686 unsigned Size) const {
3687 unsigned dest = MI->getOperand(0).getReg();
3688 unsigned ptr = MI->getOperand(1).getReg();
3689 unsigned oldval = MI->getOperand(2).getReg();
3690 unsigned newval = MI->getOperand(3).getReg();
3691 unsigned scratch = BB->getParent()->getRegInfo()
3692 .createVirtualRegister(ARM::GPRRegisterClass);
3693 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3694 DebugLoc dl = MI->getDebugLoc();
3695 bool isThumb2 = Subtarget->isThumb2();
3697 unsigned ldrOpc, strOpc;
3699 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3701 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3702 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3705 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3706 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3709 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3710 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3714 MachineFunction *MF = BB->getParent();
3715 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3716 MachineFunction::iterator It = BB;
3717 ++It; // insert the new blocks after the current block
3719 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3720 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3721 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3722 MF->insert(It, loop1MBB);
3723 MF->insert(It, loop2MBB);
3724 MF->insert(It, exitMBB);
3726 // Transfer the remainder of BB and its successor edges to exitMBB.
3727 exitMBB->splice(exitMBB->begin(), BB,
3728 llvm::next(MachineBasicBlock::iterator(MI)),
3730 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3734 // fallthrough --> loop1MBB
3735 BB->addSuccessor(loop1MBB);
3738 // ldrex dest, [ptr]
3742 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3743 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3744 .addReg(dest).addReg(oldval));
3745 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3746 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3747 BB->addSuccessor(loop2MBB);
3748 BB->addSuccessor(exitMBB);
3751 // strex scratch, newval, [ptr]
3755 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3757 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3758 .addReg(scratch).addImm(0));
3759 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3760 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3761 BB->addSuccessor(loop1MBB);
3762 BB->addSuccessor(exitMBB);
3768 MI->eraseFromParent(); // The instruction is gone now.
3774 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3775 unsigned Size, unsigned BinOpcode) const {
3776 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3777 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3779 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3780 MachineFunction *MF = BB->getParent();
3781 MachineFunction::iterator It = BB;
3784 unsigned dest = MI->getOperand(0).getReg();
3785 unsigned ptr = MI->getOperand(1).getReg();
3786 unsigned incr = MI->getOperand(2).getReg();
3787 DebugLoc dl = MI->getDebugLoc();
3789 bool isThumb2 = Subtarget->isThumb2();
3790 unsigned ldrOpc, strOpc;
3792 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3794 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3795 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3798 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3799 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3802 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3803 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3807 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3808 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3809 MF->insert(It, loopMBB);
3810 MF->insert(It, exitMBB);
3812 // Transfer the remainder of BB and its successor edges to exitMBB.
3813 exitMBB->splice(exitMBB->begin(), BB,
3814 llvm::next(MachineBasicBlock::iterator(MI)),
3816 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3818 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3819 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3820 unsigned scratch2 = (!BinOpcode) ? incr :
3821 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3825 // fallthrough --> loopMBB
3826 BB->addSuccessor(loopMBB);
3830 // <binop> scratch2, dest, incr
3831 // strex scratch, scratch2, ptr
3834 // fallthrough --> exitMBB
3836 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3838 // operand order needs to go the other way for NAND
3839 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3840 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3841 addReg(incr).addReg(dest)).addReg(0);
3843 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3844 addReg(dest).addReg(incr)).addReg(0);
3847 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3849 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3850 .addReg(scratch).addImm(0));
3851 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3852 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3854 BB->addSuccessor(loopMBB);
3855 BB->addSuccessor(exitMBB);
3861 MI->eraseFromParent(); // The instruction is gone now.
3867 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
3868 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
3869 E = MBB->succ_end(); I != E; ++I)
3872 llvm_unreachable("Expecting a BB with two successors!");
3876 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3877 MachineBasicBlock *BB) const {
3878 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3879 DebugLoc dl = MI->getDebugLoc();
3880 bool isThumb2 = Subtarget->isThumb2();
3881 switch (MI->getOpcode()) {
3884 llvm_unreachable("Unexpected instr type to insert");
3886 case ARM::ATOMIC_LOAD_ADD_I8:
3887 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3888 case ARM::ATOMIC_LOAD_ADD_I16:
3889 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3890 case ARM::ATOMIC_LOAD_ADD_I32:
3891 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3893 case ARM::ATOMIC_LOAD_AND_I8:
3894 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3895 case ARM::ATOMIC_LOAD_AND_I16:
3896 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3897 case ARM::ATOMIC_LOAD_AND_I32:
3898 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3900 case ARM::ATOMIC_LOAD_OR_I8:
3901 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3902 case ARM::ATOMIC_LOAD_OR_I16:
3903 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3904 case ARM::ATOMIC_LOAD_OR_I32:
3905 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3907 case ARM::ATOMIC_LOAD_XOR_I8:
3908 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3909 case ARM::ATOMIC_LOAD_XOR_I16:
3910 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3911 case ARM::ATOMIC_LOAD_XOR_I32:
3912 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3914 case ARM::ATOMIC_LOAD_NAND_I8:
3915 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3916 case ARM::ATOMIC_LOAD_NAND_I16:
3917 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3918 case ARM::ATOMIC_LOAD_NAND_I32:
3919 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3921 case ARM::ATOMIC_LOAD_SUB_I8:
3922 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3923 case ARM::ATOMIC_LOAD_SUB_I16:
3924 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3925 case ARM::ATOMIC_LOAD_SUB_I32:
3926 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3928 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3929 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3930 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3932 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3933 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3934 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3936 case ARM::tMOVCCr_pseudo: {
3937 // To "insert" a SELECT_CC instruction, we actually have to insert the
3938 // diamond control-flow pattern. The incoming instruction knows the
3939 // destination vreg to set, the condition code register to branch on, the
3940 // true/false values to select between, and a branch opcode to use.
3941 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3942 MachineFunction::iterator It = BB;
3948 // cmpTY ccX, r1, r2
3950 // fallthrough --> copy0MBB
3951 MachineBasicBlock *thisMBB = BB;
3952 MachineFunction *F = BB->getParent();
3953 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3954 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3955 F->insert(It, copy0MBB);
3956 F->insert(It, sinkMBB);
3958 // Transfer the remainder of BB and its successor edges to sinkMBB.
3959 sinkMBB->splice(sinkMBB->begin(), BB,
3960 llvm::next(MachineBasicBlock::iterator(MI)),
3962 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3964 BB->addSuccessor(copy0MBB);
3965 BB->addSuccessor(sinkMBB);
3967 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3968 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3971 // %FalseValue = ...
3972 // # fallthrough to sinkMBB
3975 // Update machine-CFG edges
3976 BB->addSuccessor(sinkMBB);
3979 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3982 BuildMI(*BB, BB->begin(), dl,
3983 TII->get(ARM::PHI), MI->getOperand(0).getReg())
3984 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3985 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3987 MI->eraseFromParent(); // The pseudo instruction is gone now.
3992 case ARM::BCCZi64: {
3993 // Compare both parts that make up the double comparison separately for
3995 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
3997 unsigned LHS1 = MI->getOperand(1).getReg();
3998 unsigned LHS2 = MI->getOperand(2).getReg();
4000 AddDefaultPred(BuildMI(BB, dl,
4001 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4002 .addReg(LHS1).addImm(0));
4003 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4004 .addReg(LHS2).addImm(0)
4005 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4007 unsigned RHS1 = MI->getOperand(3).getReg();
4008 unsigned RHS2 = MI->getOperand(4).getReg();
4009 AddDefaultPred(BuildMI(BB, dl,
4010 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4011 .addReg(LHS1).addReg(RHS1));
4012 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4013 .addReg(LHS2).addReg(RHS2)
4014 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4017 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4018 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4019 if (MI->getOperand(0).getImm() == ARMCC::NE)
4020 std::swap(destMBB, exitMBB);
4022 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4023 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4024 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4027 MI->eraseFromParent(); // The pseudo instruction is gone now.
4034 case ARM::t2SUBrSPi_:
4035 case ARM::t2SUBrSPi12_:
4036 case ARM::t2SUBrSPs_: {
4037 MachineFunction *MF = BB->getParent();
4038 unsigned DstReg = MI->getOperand(0).getReg();
4039 unsigned SrcReg = MI->getOperand(1).getReg();
4040 bool DstIsDead = MI->getOperand(0).isDead();
4041 bool SrcIsKill = MI->getOperand(1).isKill();
4043 if (SrcReg != ARM::SP) {
4044 // Copy the source to SP from virtual register.
4045 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
4046 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
4047 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
4048 BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP)
4049 .addReg(SrcReg, getKillRegState(SrcIsKill));
4053 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
4054 switch (MI->getOpcode()) {
4056 llvm_unreachable("Unexpected pseudo instruction!");
4062 OpOpc = ARM::tADDspr;
4065 OpOpc = ARM::tSUBspi;
4067 case ARM::t2SUBrSPi_:
4068 OpOpc = ARM::t2SUBrSPi;
4069 NeedPred = true; NeedCC = true;
4071 case ARM::t2SUBrSPi12_:
4072 OpOpc = ARM::t2SUBrSPi12;
4075 case ARM::t2SUBrSPs_:
4076 OpOpc = ARM::t2SUBrSPs;
4077 NeedPred = true; NeedCC = true; NeedOp3 = true;
4080 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP);
4081 if (OpOpc == ARM::tAND)
4082 AddDefaultT1CC(MIB);
4083 MIB.addReg(ARM::SP);
4084 MIB.addOperand(MI->getOperand(2));
4086 MIB.addOperand(MI->getOperand(3));
4088 AddDefaultPred(MIB);
4092 // Copy the result from SP to virtual register.
4093 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
4094 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
4095 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
4096 BuildMI(*BB, MI, dl, TII->get(CopyOpc))
4097 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
4099 MI->eraseFromParent(); // The pseudo instruction is gone now.
4105 //===----------------------------------------------------------------------===//
4106 // ARM Optimization Hooks
4107 //===----------------------------------------------------------------------===//
4110 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4111 TargetLowering::DAGCombinerInfo &DCI) {
4112 SelectionDAG &DAG = DCI.DAG;
4113 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4114 EVT VT = N->getValueType(0);
4115 unsigned Opc = N->getOpcode();
4116 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4117 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4118 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4119 ISD::CondCode CC = ISD::SETCC_INVALID;
4122 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4124 SDValue CCOp = Slct.getOperand(0);
4125 if (CCOp.getOpcode() == ISD::SETCC)
4126 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4129 bool DoXform = false;
4131 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4134 if (LHS.getOpcode() == ISD::Constant &&
4135 cast<ConstantSDNode>(LHS)->isNullValue()) {
4137 } else if (CC != ISD::SETCC_INVALID &&
4138 RHS.getOpcode() == ISD::Constant &&
4139 cast<ConstantSDNode>(RHS)->isNullValue()) {
4140 std::swap(LHS, RHS);
4141 SDValue Op0 = Slct.getOperand(0);
4142 EVT OpVT = isSlctCC ? Op0.getValueType() :
4143 Op0.getOperand(0).getValueType();
4144 bool isInt = OpVT.isInteger();
4145 CC = ISD::getSetCCInverse(CC, isInt);
4147 if (!TLI.isCondCodeLegal(CC, OpVT))
4148 return SDValue(); // Inverse operator isn't legal.
4155 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4157 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4158 Slct.getOperand(0), Slct.getOperand(1), CC);
4159 SDValue CCOp = Slct.getOperand(0);
4161 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4162 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4163 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4164 CCOp, OtherOp, Result);
4169 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4170 static SDValue PerformADDCombine(SDNode *N,
4171 TargetLowering::DAGCombinerInfo &DCI) {
4172 // added by evan in r37685 with no testcase.
4173 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4175 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4176 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4177 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4178 if (Result.getNode()) return Result;
4180 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4181 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4182 if (Result.getNode()) return Result;
4188 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4189 static SDValue PerformSUBCombine(SDNode *N,
4190 TargetLowering::DAGCombinerInfo &DCI) {
4191 // added by evan in r37685 with no testcase.
4192 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4194 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4195 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4196 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4197 if (Result.getNode()) return Result;
4203 static SDValue PerformMULCombine(SDNode *N,
4204 TargetLowering::DAGCombinerInfo &DCI,
4205 const ARMSubtarget *Subtarget) {
4206 SelectionDAG &DAG = DCI.DAG;
4208 if (Subtarget->isThumb1Only())
4211 if (DAG.getMachineFunction().
4212 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
4215 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4218 EVT VT = N->getValueType(0);
4222 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4226 uint64_t MulAmt = C->getZExtValue();
4227 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4228 ShiftAmt = ShiftAmt & (32 - 1);
4229 SDValue V = N->getOperand(0);
4230 DebugLoc DL = N->getDebugLoc();
4233 MulAmt >>= ShiftAmt;
4234 if (isPowerOf2_32(MulAmt - 1)) {
4235 // (mul x, 2^N + 1) => (add (shl x, N), x)
4236 Res = DAG.getNode(ISD::ADD, DL, VT,
4237 V, DAG.getNode(ISD::SHL, DL, VT,
4238 V, DAG.getConstant(Log2_32(MulAmt-1),
4240 } else if (isPowerOf2_32(MulAmt + 1)) {
4241 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4242 Res = DAG.getNode(ISD::SUB, DL, VT,
4243 DAG.getNode(ISD::SHL, DL, VT,
4244 V, DAG.getConstant(Log2_32(MulAmt+1),
4251 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4252 DAG.getConstant(ShiftAmt, MVT::i32));
4254 // Do not add new nodes to DAG combiner worklist.
4255 DCI.CombineTo(N, Res, false);
4259 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4260 static SDValue PerformORCombine(SDNode *N,
4261 TargetLowering::DAGCombinerInfo &DCI,
4262 const ARMSubtarget *Subtarget) {
4263 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4266 // BFI is only available on V6T2+
4267 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4270 SelectionDAG &DAG = DCI.DAG;
4271 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4272 DebugLoc DL = N->getDebugLoc();
4273 // 1) or (and A, mask), val => ARMbfi A, val, mask
4274 // iff (val & mask) == val
4276 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4277 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4278 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4279 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4280 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4281 // (i.e., copy a bitfield value into another bitfield of the same width)
4282 if (N0.getOpcode() != ISD::AND)
4285 EVT VT = N->getValueType(0);
4290 // The value and the mask need to be constants so we can verify this is
4291 // actually a bitfield set. If the mask is 0xffff, we can do better
4292 // via a movt instruction, so don't use BFI in that case.
4293 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4296 unsigned Mask = C->getZExtValue();
4300 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4301 if ((C = dyn_cast<ConstantSDNode>(N1))) {
4302 unsigned Val = C->getZExtValue();
4303 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
4305 Val >>= CountTrailingZeros_32(~Mask);
4307 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
4308 DAG.getConstant(Val, MVT::i32),
4309 DAG.getConstant(Mask, MVT::i32));
4311 // Do not add new nodes to DAG combiner worklist.
4312 DCI.CombineTo(N, Res, false);
4313 } else if (N1.getOpcode() == ISD::AND) {
4314 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4315 C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4318 unsigned Mask2 = C->getZExtValue();
4320 if (ARM::isBitFieldInvertedMask(Mask) &&
4321 ARM::isBitFieldInvertedMask(~Mask2) &&
4322 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4323 // The pack halfword instruction works better for masks that fit it,
4324 // so use that when it's available.
4325 if (Subtarget->hasT2ExtractPack() &&
4326 (Mask == 0xffff || Mask == 0xffff0000))
4329 unsigned lsb = CountTrailingZeros_32(Mask2);
4330 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4331 DAG.getConstant(lsb, MVT::i32));
4332 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
4333 DAG.getConstant(Mask, MVT::i32));
4334 // Do not add new nodes to DAG combiner worklist.
4335 DCI.CombineTo(N, Res, false);
4336 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4337 ARM::isBitFieldInvertedMask(Mask2) &&
4338 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4339 // The pack halfword instruction works better for masks that fit it,
4340 // so use that when it's available.
4341 if (Subtarget->hasT2ExtractPack() &&
4342 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4345 unsigned lsb = CountTrailingZeros_32(Mask);
4346 Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4347 DAG.getConstant(lsb, MVT::i32));
4348 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4349 DAG.getConstant(Mask2, MVT::i32));
4350 // Do not add new nodes to DAG combiner worklist.
4351 DCI.CombineTo(N, Res, false);
4358 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4359 /// ARMISD::VMOVRRD.
4360 static SDValue PerformVMOVRRDCombine(SDNode *N,
4361 TargetLowering::DAGCombinerInfo &DCI) {
4362 // fmrrd(fmdrr x, y) -> x,y
4363 SDValue InDouble = N->getOperand(0);
4364 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4365 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4369 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4370 /// ARMISD::VDUPLANE.
4371 static SDValue PerformVDUPLANECombine(SDNode *N,
4372 TargetLowering::DAGCombinerInfo &DCI) {
4373 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4375 SDValue Op = N->getOperand(0);
4376 EVT VT = N->getValueType(0);
4378 // Ignore bit_converts.
4379 while (Op.getOpcode() == ISD::BIT_CONVERT)
4380 Op = Op.getOperand(0);
4381 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4384 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4385 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4386 // The canonical VMOV for a zero vector uses a 32-bit element size.
4387 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4389 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4391 if (EltSize > VT.getVectorElementType().getSizeInBits())
4394 SDValue Res = DCI.DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
4395 return DCI.CombineTo(N, Res, false);
4398 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4399 /// operand of a vector shift operation, where all the elements of the
4400 /// build_vector must have the same constant integer value.
4401 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4402 // Ignore bit_converts.
4403 while (Op.getOpcode() == ISD::BIT_CONVERT)
4404 Op = Op.getOperand(0);
4405 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4406 APInt SplatBits, SplatUndef;
4407 unsigned SplatBitSize;
4409 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4410 HasAnyUndefs, ElementBits) ||
4411 SplatBitSize > ElementBits)
4413 Cnt = SplatBits.getSExtValue();
4417 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4418 /// operand of a vector shift left operation. That value must be in the range:
4419 /// 0 <= Value < ElementBits for a left shift; or
4420 /// 0 <= Value <= ElementBits for a long left shift.
4421 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4422 assert(VT.isVector() && "vector shift count is not a vector type");
4423 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4424 if (! getVShiftImm(Op, ElementBits, Cnt))
4426 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4429 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4430 /// operand of a vector shift right operation. For a shift opcode, the value
4431 /// is positive, but for an intrinsic the value count must be negative. The
4432 /// absolute value must be in the range:
4433 /// 1 <= |Value| <= ElementBits for a right shift; or
4434 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4435 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4437 assert(VT.isVector() && "vector shift count is not a vector type");
4438 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4439 if (! getVShiftImm(Op, ElementBits, Cnt))
4443 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4446 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4447 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4448 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4451 // Don't do anything for most intrinsics.
4454 // Vector shifts: check for immediate versions and lower them.
4455 // Note: This is done during DAG combining instead of DAG legalizing because
4456 // the build_vectors for 64-bit vector element shift counts are generally
4457 // not legal, and it is hard to see their values after they get legalized to
4458 // loads from a constant pool.
4459 case Intrinsic::arm_neon_vshifts:
4460 case Intrinsic::arm_neon_vshiftu:
4461 case Intrinsic::arm_neon_vshiftls:
4462 case Intrinsic::arm_neon_vshiftlu:
4463 case Intrinsic::arm_neon_vshiftn:
4464 case Intrinsic::arm_neon_vrshifts:
4465 case Intrinsic::arm_neon_vrshiftu:
4466 case Intrinsic::arm_neon_vrshiftn:
4467 case Intrinsic::arm_neon_vqshifts:
4468 case Intrinsic::arm_neon_vqshiftu:
4469 case Intrinsic::arm_neon_vqshiftsu:
4470 case Intrinsic::arm_neon_vqshiftns:
4471 case Intrinsic::arm_neon_vqshiftnu:
4472 case Intrinsic::arm_neon_vqshiftnsu:
4473 case Intrinsic::arm_neon_vqrshiftns:
4474 case Intrinsic::arm_neon_vqrshiftnu:
4475 case Intrinsic::arm_neon_vqrshiftnsu: {
4476 EVT VT = N->getOperand(1).getValueType();
4478 unsigned VShiftOpc = 0;
4481 case Intrinsic::arm_neon_vshifts:
4482 case Intrinsic::arm_neon_vshiftu:
4483 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4484 VShiftOpc = ARMISD::VSHL;
4487 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4488 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4489 ARMISD::VSHRs : ARMISD::VSHRu);
4494 case Intrinsic::arm_neon_vshiftls:
4495 case Intrinsic::arm_neon_vshiftlu:
4496 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4498 llvm_unreachable("invalid shift count for vshll intrinsic");
4500 case Intrinsic::arm_neon_vrshifts:
4501 case Intrinsic::arm_neon_vrshiftu:
4502 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4506 case Intrinsic::arm_neon_vqshifts:
4507 case Intrinsic::arm_neon_vqshiftu:
4508 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4512 case Intrinsic::arm_neon_vqshiftsu:
4513 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4515 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4517 case Intrinsic::arm_neon_vshiftn:
4518 case Intrinsic::arm_neon_vrshiftn:
4519 case Intrinsic::arm_neon_vqshiftns:
4520 case Intrinsic::arm_neon_vqshiftnu:
4521 case Intrinsic::arm_neon_vqshiftnsu:
4522 case Intrinsic::arm_neon_vqrshiftns:
4523 case Intrinsic::arm_neon_vqrshiftnu:
4524 case Intrinsic::arm_neon_vqrshiftnsu:
4525 // Narrowing shifts require an immediate right shift.
4526 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4528 llvm_unreachable("invalid shift count for narrowing vector shift "
4532 llvm_unreachable("unhandled vector shift");
4536 case Intrinsic::arm_neon_vshifts:
4537 case Intrinsic::arm_neon_vshiftu:
4538 // Opcode already set above.
4540 case Intrinsic::arm_neon_vshiftls:
4541 case Intrinsic::arm_neon_vshiftlu:
4542 if (Cnt == VT.getVectorElementType().getSizeInBits())
4543 VShiftOpc = ARMISD::VSHLLi;
4545 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4546 ARMISD::VSHLLs : ARMISD::VSHLLu);
4548 case Intrinsic::arm_neon_vshiftn:
4549 VShiftOpc = ARMISD::VSHRN; break;
4550 case Intrinsic::arm_neon_vrshifts:
4551 VShiftOpc = ARMISD::VRSHRs; break;
4552 case Intrinsic::arm_neon_vrshiftu:
4553 VShiftOpc = ARMISD::VRSHRu; break;
4554 case Intrinsic::arm_neon_vrshiftn:
4555 VShiftOpc = ARMISD::VRSHRN; break;
4556 case Intrinsic::arm_neon_vqshifts:
4557 VShiftOpc = ARMISD::VQSHLs; break;
4558 case Intrinsic::arm_neon_vqshiftu:
4559 VShiftOpc = ARMISD::VQSHLu; break;
4560 case Intrinsic::arm_neon_vqshiftsu:
4561 VShiftOpc = ARMISD::VQSHLsu; break;
4562 case Intrinsic::arm_neon_vqshiftns:
4563 VShiftOpc = ARMISD::VQSHRNs; break;
4564 case Intrinsic::arm_neon_vqshiftnu:
4565 VShiftOpc = ARMISD::VQSHRNu; break;
4566 case Intrinsic::arm_neon_vqshiftnsu:
4567 VShiftOpc = ARMISD::VQSHRNsu; break;
4568 case Intrinsic::arm_neon_vqrshiftns:
4569 VShiftOpc = ARMISD::VQRSHRNs; break;
4570 case Intrinsic::arm_neon_vqrshiftnu:
4571 VShiftOpc = ARMISD::VQRSHRNu; break;
4572 case Intrinsic::arm_neon_vqrshiftnsu:
4573 VShiftOpc = ARMISD::VQRSHRNsu; break;
4576 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4577 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4580 case Intrinsic::arm_neon_vshiftins: {
4581 EVT VT = N->getOperand(1).getValueType();
4583 unsigned VShiftOpc = 0;
4585 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4586 VShiftOpc = ARMISD::VSLI;
4587 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4588 VShiftOpc = ARMISD::VSRI;
4590 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4593 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4594 N->getOperand(1), N->getOperand(2),
4595 DAG.getConstant(Cnt, MVT::i32));
4598 case Intrinsic::arm_neon_vqrshifts:
4599 case Intrinsic::arm_neon_vqrshiftu:
4600 // No immediate versions of these to check for.
4607 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4608 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4609 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4610 /// vector element shift counts are generally not legal, and it is hard to see
4611 /// their values after they get legalized to loads from a constant pool.
4612 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4613 const ARMSubtarget *ST) {
4614 EVT VT = N->getValueType(0);
4616 // Nothing to be done for scalar shifts.
4617 if (! VT.isVector())
4620 assert(ST->hasNEON() && "unexpected vector shift");
4623 switch (N->getOpcode()) {
4624 default: llvm_unreachable("unexpected shift opcode");
4627 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4628 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4629 DAG.getConstant(Cnt, MVT::i32));
4634 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4635 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4636 ARMISD::VSHRs : ARMISD::VSHRu);
4637 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4638 DAG.getConstant(Cnt, MVT::i32));
4644 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4645 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4646 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4647 const ARMSubtarget *ST) {
4648 SDValue N0 = N->getOperand(0);
4650 // Check for sign- and zero-extensions of vector extract operations of 8-
4651 // and 16-bit vector elements. NEON supports these directly. They are
4652 // handled during DAG combining because type legalization will promote them
4653 // to 32-bit types and it is messy to recognize the operations after that.
4654 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4655 SDValue Vec = N0.getOperand(0);
4656 SDValue Lane = N0.getOperand(1);
4657 EVT VT = N->getValueType(0);
4658 EVT EltVT = N0.getValueType();
4659 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4661 if (VT == MVT::i32 &&
4662 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4663 TLI.isTypeLegal(Vec.getValueType())) {
4666 switch (N->getOpcode()) {
4667 default: llvm_unreachable("unexpected opcode");
4668 case ISD::SIGN_EXTEND:
4669 Opc = ARMISD::VGETLANEs;
4671 case ISD::ZERO_EXTEND:
4672 case ISD::ANY_EXTEND:
4673 Opc = ARMISD::VGETLANEu;
4676 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4683 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4684 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4685 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4686 const ARMSubtarget *ST) {
4687 // If the target supports NEON, try to use vmax/vmin instructions for f32
4688 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
4689 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4690 // a NaN; only do the transformation when it matches that behavior.
4692 // For now only do this when using NEON for FP operations; if using VFP, it
4693 // is not obvious that the benefit outweighs the cost of switching to the
4695 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4696 N->getValueType(0) != MVT::f32)
4699 SDValue CondLHS = N->getOperand(0);
4700 SDValue CondRHS = N->getOperand(1);
4701 SDValue LHS = N->getOperand(2);
4702 SDValue RHS = N->getOperand(3);
4703 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4705 unsigned Opcode = 0;
4707 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4708 IsReversed = false; // x CC y ? x : y
4709 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4710 IsReversed = true ; // x CC y ? y : x
4724 // If LHS is NaN, an ordered comparison will be false and the result will
4725 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4726 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4727 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4728 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4730 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4731 // will return -0, so vmin can only be used for unsafe math or if one of
4732 // the operands is known to be nonzero.
4733 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4735 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4737 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4746 // If LHS is NaN, an ordered comparison will be false and the result will
4747 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4748 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4749 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4750 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4752 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4753 // will return +0, so vmax can only be used for unsafe math or if one of
4754 // the operands is known to be nonzero.
4755 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4757 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4759 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4765 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4768 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4769 DAGCombinerInfo &DCI) const {
4770 switch (N->getOpcode()) {
4772 case ISD::ADD: return PerformADDCombine(N, DCI);
4773 case ISD::SUB: return PerformSUBCombine(N, DCI);
4774 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4775 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
4776 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4777 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
4778 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4781 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4782 case ISD::SIGN_EXTEND:
4783 case ISD::ZERO_EXTEND:
4784 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4785 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4790 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4791 if (!Subtarget->hasV6Ops())
4792 // Pre-v6 does not support unaligned mem access.
4795 // v6+ may or may not support unaligned mem access depending on the system
4797 // FIXME: This is pretty conservative. Should we provide cmdline option to
4798 // control the behaviour?
4799 if (!Subtarget->isTargetDarwin())
4802 switch (VT.getSimpleVT().SimpleTy) {
4809 // FIXME: VLD1 etc with standard alignment is legal.
4813 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4818 switch (VT.getSimpleVT().SimpleTy) {
4819 default: return false;
4834 if ((V & (Scale - 1)) != 0)
4837 return V == (V & ((1LL << 5) - 1));
4840 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4841 const ARMSubtarget *Subtarget) {
4848 switch (VT.getSimpleVT().SimpleTy) {
4849 default: return false;
4854 // + imm12 or - imm8
4856 return V == (V & ((1LL << 8) - 1));
4857 return V == (V & ((1LL << 12) - 1));
4860 // Same as ARM mode. FIXME: NEON?
4861 if (!Subtarget->hasVFP2())
4866 return V == (V & ((1LL << 8) - 1));
4870 /// isLegalAddressImmediate - Return true if the integer value can be used
4871 /// as the offset of the target addressing mode for load / store of the
4873 static bool isLegalAddressImmediate(int64_t V, EVT VT,
4874 const ARMSubtarget *Subtarget) {
4881 if (Subtarget->isThumb1Only())
4882 return isLegalT1AddressImmediate(V, VT);
4883 else if (Subtarget->isThumb2())
4884 return isLegalT2AddressImmediate(V, VT, Subtarget);
4889 switch (VT.getSimpleVT().SimpleTy) {
4890 default: return false;
4895 return V == (V & ((1LL << 12) - 1));
4898 return V == (V & ((1LL << 8) - 1));
4901 if (!Subtarget->hasVFP2()) // FIXME: NEON?
4906 return V == (V & ((1LL << 8) - 1));
4910 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
4912 int Scale = AM.Scale;
4916 switch (VT.getSimpleVT().SimpleTy) {
4917 default: return false;
4926 return Scale == 2 || Scale == 4 || Scale == 8;
4929 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4933 // Note, we allow "void" uses (basically, uses that aren't loads or
4934 // stores), because arm allows folding a scale into many arithmetic
4935 // operations. This should be made more precise and revisited later.
4937 // Allow r << imm, but the imm has to be a multiple of two.
4938 if (Scale & 1) return false;
4939 return isPowerOf2_32(Scale);
4943 /// isLegalAddressingMode - Return true if the addressing mode represented
4944 /// by AM is legal for this target, for a load/store of the specified type.
4945 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4946 const Type *Ty) const {
4947 EVT VT = getValueType(Ty, true);
4948 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4951 // Can never fold addr of global into load/store.
4956 case 0: // no scale reg, must be "r+i" or "r", or "i".
4959 if (Subtarget->isThumb1Only())
4963 // ARM doesn't support any R+R*scale+imm addr modes.
4970 if (Subtarget->isThumb2())
4971 return isLegalT2ScaledAddressingMode(AM, VT);
4973 int Scale = AM.Scale;
4974 switch (VT.getSimpleVT().SimpleTy) {
4975 default: return false;
4979 if (Scale < 0) Scale = -Scale;
4983 return isPowerOf2_32(Scale & ~1);
4987 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4992 // Note, we allow "void" uses (basically, uses that aren't loads or
4993 // stores), because arm allows folding a scale into many arithmetic
4994 // operations. This should be made more precise and revisited later.
4996 // Allow r << imm, but the imm has to be a multiple of two.
4997 if (Scale & 1) return false;
4998 return isPowerOf2_32(Scale);
5005 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5006 /// icmp immediate, that is the target has icmp instructions which can compare
5007 /// a register against the immediate without having to materialize the
5008 /// immediate into a register.
5009 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5010 if (!Subtarget->isThumb())
5011 return ARM_AM::getSOImmVal(Imm) != -1;
5012 if (Subtarget->isThumb2())
5013 return ARM_AM::getT2SOImmVal(Imm) != -1;
5014 return Imm >= 0 && Imm <= 255;
5017 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5018 bool isSEXTLoad, SDValue &Base,
5019 SDValue &Offset, bool &isInc,
5020 SelectionDAG &DAG) {
5021 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5024 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5026 Base = Ptr->getOperand(0);
5027 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5028 int RHSC = (int)RHS->getZExtValue();
5029 if (RHSC < 0 && RHSC > -256) {
5030 assert(Ptr->getOpcode() == ISD::ADD);
5032 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5036 isInc = (Ptr->getOpcode() == ISD::ADD);
5037 Offset = Ptr->getOperand(1);
5039 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5041 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5042 int RHSC = (int)RHS->getZExtValue();
5043 if (RHSC < 0 && RHSC > -0x1000) {
5044 assert(Ptr->getOpcode() == ISD::ADD);
5046 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5047 Base = Ptr->getOperand(0);
5052 if (Ptr->getOpcode() == ISD::ADD) {
5054 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5055 if (ShOpcVal != ARM_AM::no_shift) {
5056 Base = Ptr->getOperand(1);
5057 Offset = Ptr->getOperand(0);
5059 Base = Ptr->getOperand(0);
5060 Offset = Ptr->getOperand(1);
5065 isInc = (Ptr->getOpcode() == ISD::ADD);
5066 Base = Ptr->getOperand(0);
5067 Offset = Ptr->getOperand(1);
5071 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5075 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5076 bool isSEXTLoad, SDValue &Base,
5077 SDValue &Offset, bool &isInc,
5078 SelectionDAG &DAG) {
5079 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5082 Base = Ptr->getOperand(0);
5083 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5084 int RHSC = (int)RHS->getZExtValue();
5085 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5086 assert(Ptr->getOpcode() == ISD::ADD);
5088 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5090 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5091 isInc = Ptr->getOpcode() == ISD::ADD;
5092 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5100 /// getPreIndexedAddressParts - returns true by value, base pointer and
5101 /// offset pointer and addressing mode by reference if the node's address
5102 /// can be legally represented as pre-indexed load / store address.
5104 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5106 ISD::MemIndexedMode &AM,
5107 SelectionDAG &DAG) const {
5108 if (Subtarget->isThumb1Only())
5113 bool isSEXTLoad = false;
5114 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5115 Ptr = LD->getBasePtr();
5116 VT = LD->getMemoryVT();
5117 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5118 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5119 Ptr = ST->getBasePtr();
5120 VT = ST->getMemoryVT();
5125 bool isLegal = false;
5126 if (Subtarget->isThumb2())
5127 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5128 Offset, isInc, DAG);
5130 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5131 Offset, isInc, DAG);
5135 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5139 /// getPostIndexedAddressParts - returns true by value, base pointer and
5140 /// offset pointer and addressing mode by reference if this node can be
5141 /// combined with a load / store to form a post-indexed load / store.
5142 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5145 ISD::MemIndexedMode &AM,
5146 SelectionDAG &DAG) const {
5147 if (Subtarget->isThumb1Only())
5152 bool isSEXTLoad = false;
5153 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5154 VT = LD->getMemoryVT();
5155 Ptr = LD->getBasePtr();
5156 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5157 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5158 VT = ST->getMemoryVT();
5159 Ptr = ST->getBasePtr();
5164 bool isLegal = false;
5165 if (Subtarget->isThumb2())
5166 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5169 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5175 // Swap base ptr and offset to catch more post-index load / store when
5176 // it's legal. In Thumb2 mode, offset must be an immediate.
5177 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5178 !Subtarget->isThumb2())
5179 std::swap(Base, Offset);
5181 // Post-indexed load / store update the base pointer.
5186 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5190 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5194 const SelectionDAG &DAG,
5195 unsigned Depth) const {
5196 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5197 switch (Op.getOpcode()) {
5199 case ARMISD::CMOV: {
5200 // Bits are known zero/one if known on the LHS and RHS.
5201 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5202 if (KnownZero == 0 && KnownOne == 0) return;
5204 APInt KnownZeroRHS, KnownOneRHS;
5205 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5206 KnownZeroRHS, KnownOneRHS, Depth+1);
5207 KnownZero &= KnownZeroRHS;
5208 KnownOne &= KnownOneRHS;
5214 //===----------------------------------------------------------------------===//
5215 // ARM Inline Assembly Support
5216 //===----------------------------------------------------------------------===//
5218 /// getConstraintType - Given a constraint letter, return the type of
5219 /// constraint it is for this target.
5220 ARMTargetLowering::ConstraintType
5221 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5222 if (Constraint.size() == 1) {
5223 switch (Constraint[0]) {
5225 case 'l': return C_RegisterClass;
5226 case 'w': return C_RegisterClass;
5229 return TargetLowering::getConstraintType(Constraint);
5232 std::pair<unsigned, const TargetRegisterClass*>
5233 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5235 if (Constraint.size() == 1) {
5236 // GCC ARM Constraint Letters
5237 switch (Constraint[0]) {
5239 if (Subtarget->isThumb())
5240 return std::make_pair(0U, ARM::tGPRRegisterClass);
5242 return std::make_pair(0U, ARM::GPRRegisterClass);
5244 return std::make_pair(0U, ARM::GPRRegisterClass);
5247 return std::make_pair(0U, ARM::SPRRegisterClass);
5248 if (VT.getSizeInBits() == 64)
5249 return std::make_pair(0U, ARM::DPRRegisterClass);
5250 if (VT.getSizeInBits() == 128)
5251 return std::make_pair(0U, ARM::QPRRegisterClass);
5255 if (StringRef("{cc}").equals_lower(Constraint))
5256 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5258 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5261 std::vector<unsigned> ARMTargetLowering::
5262 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5264 if (Constraint.size() != 1)
5265 return std::vector<unsigned>();
5267 switch (Constraint[0]) { // GCC ARM Constraint Letters
5270 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5271 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5274 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5275 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5276 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5277 ARM::R12, ARM::LR, 0);
5280 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5281 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5282 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5283 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5284 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5285 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5286 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5287 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5288 if (VT.getSizeInBits() == 64)
5289 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5290 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5291 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5292 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5293 if (VT.getSizeInBits() == 128)
5294 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5295 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5299 return std::vector<unsigned>();
5302 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5303 /// vector. If it is invalid, don't add anything to Ops.
5304 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5306 std::vector<SDValue>&Ops,
5307 SelectionDAG &DAG) const {
5308 SDValue Result(0, 0);
5310 switch (Constraint) {
5312 case 'I': case 'J': case 'K': case 'L':
5313 case 'M': case 'N': case 'O':
5314 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5318 int64_t CVal64 = C->getSExtValue();
5319 int CVal = (int) CVal64;
5320 // None of these constraints allow values larger than 32 bits. Check
5321 // that the value fits in an int.
5325 switch (Constraint) {
5327 if (Subtarget->isThumb1Only()) {
5328 // This must be a constant between 0 and 255, for ADD
5330 if (CVal >= 0 && CVal <= 255)
5332 } else if (Subtarget->isThumb2()) {
5333 // A constant that can be used as an immediate value in a
5334 // data-processing instruction.
5335 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5338 // A constant that can be used as an immediate value in a
5339 // data-processing instruction.
5340 if (ARM_AM::getSOImmVal(CVal) != -1)
5346 if (Subtarget->isThumb()) { // FIXME thumb2
5347 // This must be a constant between -255 and -1, for negated ADD
5348 // immediates. This can be used in GCC with an "n" modifier that
5349 // prints the negated value, for use with SUB instructions. It is
5350 // not useful otherwise but is implemented for compatibility.
5351 if (CVal >= -255 && CVal <= -1)
5354 // This must be a constant between -4095 and 4095. It is not clear
5355 // what this constraint is intended for. Implemented for
5356 // compatibility with GCC.
5357 if (CVal >= -4095 && CVal <= 4095)
5363 if (Subtarget->isThumb1Only()) {
5364 // A 32-bit value where only one byte has a nonzero value. Exclude
5365 // zero to match GCC. This constraint is used by GCC internally for
5366 // constants that can be loaded with a move/shift combination.
5367 // It is not useful otherwise but is implemented for compatibility.
5368 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5370 } else if (Subtarget->isThumb2()) {
5371 // A constant whose bitwise inverse can be used as an immediate
5372 // value in a data-processing instruction. This can be used in GCC
5373 // with a "B" modifier that prints the inverted value, for use with
5374 // BIC and MVN instructions. It is not useful otherwise but is
5375 // implemented for compatibility.
5376 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5379 // A constant whose bitwise inverse can be used as an immediate
5380 // value in a data-processing instruction. This can be used in GCC
5381 // with a "B" modifier that prints the inverted value, for use with
5382 // BIC and MVN instructions. It is not useful otherwise but is
5383 // implemented for compatibility.
5384 if (ARM_AM::getSOImmVal(~CVal) != -1)
5390 if (Subtarget->isThumb1Only()) {
5391 // This must be a constant between -7 and 7,
5392 // for 3-operand ADD/SUB immediate instructions.
5393 if (CVal >= -7 && CVal < 7)
5395 } else if (Subtarget->isThumb2()) {
5396 // A constant whose negation can be used as an immediate value in a
5397 // data-processing instruction. This can be used in GCC with an "n"
5398 // modifier that prints the negated value, for use with SUB
5399 // instructions. It is not useful otherwise but is implemented for
5401 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5404 // A constant whose negation can be used as an immediate value in a
5405 // data-processing instruction. This can be used in GCC with an "n"
5406 // modifier that prints the negated value, for use with SUB
5407 // instructions. It is not useful otherwise but is implemented for
5409 if (ARM_AM::getSOImmVal(-CVal) != -1)
5415 if (Subtarget->isThumb()) { // FIXME thumb2
5416 // This must be a multiple of 4 between 0 and 1020, for
5417 // ADD sp + immediate.
5418 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5421 // A power of two or a constant between 0 and 32. This is used in
5422 // GCC for the shift amount on shifted register operands, but it is
5423 // useful in general for any shift amounts.
5424 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5430 if (Subtarget->isThumb()) { // FIXME thumb2
5431 // This must be a constant between 0 and 31, for shift amounts.
5432 if (CVal >= 0 && CVal <= 31)
5438 if (Subtarget->isThumb()) { // FIXME thumb2
5439 // This must be a multiple of 4 between -508 and 508, for
5440 // ADD/SUB sp = sp + immediate.
5441 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5446 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5450 if (Result.getNode()) {
5451 Ops.push_back(Result);
5454 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5458 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5459 // The ARM target isn't yet aware of offsets.
5463 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5464 APInt Imm = FPImm.bitcastToAPInt();
5465 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5466 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5467 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5469 // We can handle 4 bits of mantissa.
5470 // mantissa = (16+UInt(e:f:g:h))/16.
5471 if (Mantissa & 0x7ffff)
5474 if ((Mantissa & 0xf) != Mantissa)
5477 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5478 if (Exp < -3 || Exp > 4)
5480 Exp = ((Exp+3) & 0x7) ^ 4;
5482 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5485 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5486 APInt Imm = FPImm.bitcastToAPInt();
5487 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5488 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5489 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5491 // We can handle 4 bits of mantissa.
5492 // mantissa = (16+UInt(e:f:g:h))/16.
5493 if (Mantissa & 0xffffffffffffLL)
5496 if ((Mantissa & 0xf) != Mantissa)
5499 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5500 if (Exp < -3 || Exp > 4)
5502 Exp = ((Exp+3) & 0x7) ^ 4;
5504 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5507 bool ARM::isBitFieldInvertedMask(unsigned v) {
5508 if (v == 0xffffffff)
5510 // there can be 1's on either or both "outsides", all the "inside"
5512 unsigned int lsb = 0, msb = 31;
5513 while (v & (1 << msb)) --msb;
5514 while (v & (1 << lsb)) ++lsb;
5515 for (unsigned int i = lsb; i <= msb; ++i) {
5522 /// isFPImmLegal - Returns true if the target can instruction select the
5523 /// specified FP immediate natively. If false, the legalizer will
5524 /// materialize the FP immediate as a load from a constant pool.
5525 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5526 if (!Subtarget->hasVFP3())
5529 return ARM::getVFPf32Imm(Imm) != -1;
5531 return ARM::getVFPf64Imm(Imm) != -1;