1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
75 // The APCS parameter registers.
76 static const unsigned GPRArgRegs[] = {
77 ARM::R0, ARM::R1, ARM::R2, ARM::R3
80 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
81 EVT PromotedBitwiseVT) {
82 if (VT != PromotedLdStVT) {
83 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
84 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
85 PromotedLdStVT.getSimpleVT());
87 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
88 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
89 PromotedLdStVT.getSimpleVT());
92 EVT ElemTy = VT.getVectorElementType();
93 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
94 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
96 if (ElemTy != MVT::i32) {
97 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
98 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
100 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
104 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
105 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
106 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
107 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
108 if (VT.isInteger()) {
109 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
112 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
113 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
114 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
115 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
116 setTruncStoreAction(VT.getSimpleVT(),
117 (MVT::SimpleValueType)InnerVT, Expand);
119 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
121 // Promote all bit-wise operations.
122 if (VT.isInteger() && VT != PromotedBitwiseVT) {
123 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
124 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
125 PromotedBitwiseVT.getSimpleVT());
126 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
127 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
128 PromotedBitwiseVT.getSimpleVT());
129 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
130 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
131 PromotedBitwiseVT.getSimpleVT());
134 // Neon does not support vector divide/remainder operations.
135 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
136 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
137 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
138 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
139 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
140 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
143 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
144 addRegisterClass(VT, ARM::DPRRegisterClass);
145 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
148 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
149 addRegisterClass(VT, ARM::QPRRegisterClass);
150 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
153 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
154 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
155 return new TargetLoweringObjectFileMachO();
157 return new ARMElfTargetObjectFile();
160 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
161 : TargetLowering(TM, createTLOF(TM)) {
162 Subtarget = &TM.getSubtarget<ARMSubtarget>();
163 RegInfo = TM.getRegisterInfo();
164 Itins = TM.getInstrItineraryData();
166 if (Subtarget->isTargetDarwin()) {
167 // Uses VFP for Thumb libfuncs if available.
168 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
169 // Single-precision floating-point arithmetic.
170 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
171 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
172 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
173 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
175 // Double-precision floating-point arithmetic.
176 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
177 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
178 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
179 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
181 // Single-precision comparisons.
182 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
183 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
184 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
185 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
186 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
187 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
188 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
189 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
191 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
193 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
194 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
195 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
200 // Double-precision comparisons.
201 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
202 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
203 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
204 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
205 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
206 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
207 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
208 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
210 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
219 // Floating-point to integer conversions.
220 // i64 conversions are done via library routines even when generating VFP
221 // instructions, so use the same ones.
222 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
223 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
224 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
225 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
227 // Conversions between floating types.
228 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
229 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
231 // Integer to floating-point conversions.
232 // i64 conversions are done via library routines even when generating VFP
233 // instructions, so use the same ones.
234 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
235 // e.g., __floatunsidf vs. __floatunssidfvfp.
236 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
237 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
238 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
239 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
243 // These libcalls are not available in 32-bit.
244 setLibcallName(RTLIB::SHL_I128, 0);
245 setLibcallName(RTLIB::SRL_I128, 0);
246 setLibcallName(RTLIB::SRA_I128, 0);
248 if (Subtarget->isAAPCS_ABI()) {
249 // Double-precision floating-point arithmetic helper functions
250 // RTABI chapter 4.1.2, Table 2
251 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
252 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
253 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
254 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
255 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
256 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
257 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
258 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
260 // Double-precision floating-point comparison helper functions
261 // RTABI chapter 4.1.2, Table 3
262 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
263 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
264 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
265 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
266 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
267 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
268 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
269 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
270 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
271 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
272 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
273 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
274 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
275 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
276 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
277 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
278 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
279 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
280 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
281 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
282 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
283 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
284 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
285 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
287 // Single-precision floating-point arithmetic helper functions
288 // RTABI chapter 4.1.2, Table 4
289 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
290 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
291 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
292 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
293 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
294 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
295 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
298 // Single-precision floating-point comparison helper functions
299 // RTABI chapter 4.1.2, Table 5
300 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
301 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
302 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
303 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
304 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
305 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
306 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
307 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
308 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
309 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
310 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
311 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
312 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
313 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
314 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
315 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
316 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
317 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
318 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
319 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
320 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
321 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
322 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
323 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
325 // Floating-point to integer conversions.
326 // RTABI chapter 4.1.2, Table 6
327 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
328 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
329 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
330 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
331 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
332 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
333 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
334 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
335 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
339 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
340 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
342 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
344 // Conversions between floating types.
345 // RTABI chapter 4.1.2, Table 7
346 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
347 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
348 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
349 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
351 // Integer to floating-point conversions.
352 // RTABI chapter 4.1.2, Table 8
353 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
354 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
355 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
356 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
357 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
358 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
359 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
360 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
361 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
362 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
363 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
364 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
365 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
366 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
367 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
368 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
370 // Long long helper functions
371 // RTABI chapter 4.2, Table 9
372 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
373 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
374 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
375 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
376 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
377 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
378 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
383 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
385 // Integer division functions
386 // RTABI chapter 4.3.1
387 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
388 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
389 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
390 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
391 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
392 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
393 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
394 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
395 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
396 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
398 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
401 // RTABI chapter 4.3.4
402 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
403 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
404 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
407 if (Subtarget->isThumb1Only())
408 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
410 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
411 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
412 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
413 if (!Subtarget->isFPOnlySP())
414 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
416 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
419 if (Subtarget->hasNEON()) {
420 addDRTypeForNEON(MVT::v2f32);
421 addDRTypeForNEON(MVT::v8i8);
422 addDRTypeForNEON(MVT::v4i16);
423 addDRTypeForNEON(MVT::v2i32);
424 addDRTypeForNEON(MVT::v1i64);
426 addQRTypeForNEON(MVT::v4f32);
427 addQRTypeForNEON(MVT::v2f64);
428 addQRTypeForNEON(MVT::v16i8);
429 addQRTypeForNEON(MVT::v8i16);
430 addQRTypeForNEON(MVT::v4i32);
431 addQRTypeForNEON(MVT::v2i64);
433 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
434 // neither Neon nor VFP support any arithmetic operations on it.
435 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
436 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
437 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
438 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
439 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
440 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
441 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
442 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
443 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
444 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
445 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
446 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
447 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
448 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
449 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
450 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
451 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
452 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
453 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
454 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
455 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
456 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
457 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
458 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
460 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
462 // Neon does not support some operations on v1i64 and v2i64 types.
463 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
464 // Custom handling for some quad-vector types to detect VMULL.
465 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
466 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
467 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
468 // Custom handling for some vector types to avoid expensive expansions
469 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
470 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
471 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
472 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
473 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
474 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
475 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
476 // a destination type that is wider than the source.
477 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
478 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
480 setTargetDAGCombine(ISD::INTRINSIC_VOID);
481 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
482 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
483 setTargetDAGCombine(ISD::SHL);
484 setTargetDAGCombine(ISD::SRL);
485 setTargetDAGCombine(ISD::SRA);
486 setTargetDAGCombine(ISD::SIGN_EXTEND);
487 setTargetDAGCombine(ISD::ZERO_EXTEND);
488 setTargetDAGCombine(ISD::ANY_EXTEND);
489 setTargetDAGCombine(ISD::SELECT_CC);
490 setTargetDAGCombine(ISD::BUILD_VECTOR);
491 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
492 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
493 setTargetDAGCombine(ISD::STORE);
496 computeRegisterProperties();
498 // ARM does not have f32 extending load.
499 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
501 // ARM does not have i1 sign extending load.
502 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
504 // ARM supports all 4 flavors of integer indexed load / store.
505 if (!Subtarget->isThumb1Only()) {
506 for (unsigned im = (unsigned)ISD::PRE_INC;
507 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
508 setIndexedLoadAction(im, MVT::i1, Legal);
509 setIndexedLoadAction(im, MVT::i8, Legal);
510 setIndexedLoadAction(im, MVT::i16, Legal);
511 setIndexedLoadAction(im, MVT::i32, Legal);
512 setIndexedStoreAction(im, MVT::i1, Legal);
513 setIndexedStoreAction(im, MVT::i8, Legal);
514 setIndexedStoreAction(im, MVT::i16, Legal);
515 setIndexedStoreAction(im, MVT::i32, Legal);
519 // i64 operation support.
520 setOperationAction(ISD::MUL, MVT::i64, Expand);
521 setOperationAction(ISD::MULHU, MVT::i32, Expand);
522 if (Subtarget->isThumb1Only()) {
523 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
524 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
526 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops())
527 setOperationAction(ISD::MULHS, MVT::i32, Expand);
529 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
530 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
531 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
532 setOperationAction(ISD::SRL, MVT::i64, Custom);
533 setOperationAction(ISD::SRA, MVT::i64, Custom);
535 // ARM does not have ROTL.
536 setOperationAction(ISD::ROTL, MVT::i32, Expand);
537 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
538 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
539 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
540 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
542 // Only ARMv6 has BSWAP.
543 if (!Subtarget->hasV6Ops())
544 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
546 // These are expanded into libcalls.
547 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
548 // v7M has a hardware divider
549 setOperationAction(ISD::SDIV, MVT::i32, Expand);
550 setOperationAction(ISD::UDIV, MVT::i32, Expand);
552 setOperationAction(ISD::SREM, MVT::i32, Expand);
553 setOperationAction(ISD::UREM, MVT::i32, Expand);
554 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
555 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
557 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
558 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
559 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
560 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
561 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
563 setOperationAction(ISD::TRAP, MVT::Other, Legal);
565 // Use the default implementation.
566 setOperationAction(ISD::VASTART, MVT::Other, Custom);
567 setOperationAction(ISD::VAARG, MVT::Other, Expand);
568 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
569 setOperationAction(ISD::VAEND, MVT::Other, Expand);
570 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
571 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
572 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
573 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
574 setExceptionPointerRegister(ARM::R0);
575 setExceptionSelectorRegister(ARM::R1);
577 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
578 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
579 // the default expansion.
580 if (Subtarget->hasDataBarrier() ||
581 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
582 // membarrier needs custom lowering; the rest are legal and handled
584 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
586 // Set them all for expansion, which will force libcalls.
587 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
588 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
589 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
590 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
591 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
592 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
593 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
600 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
601 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
602 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
603 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
604 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
605 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
606 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
607 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
608 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
609 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
610 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
611 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
612 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i8, Expand);
613 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i16, Expand);
614 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
615 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i8, Expand);
616 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i16, Expand);
617 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
618 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i8, Expand);
619 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i16, Expand);
620 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i8, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i16, Expand);
623 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
624 // Since the libcalls include locking, fold in the fences
625 setShouldFoldAtomicFences(true);
627 // 64-bit versions are always libcalls (for now)
628 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
629 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
630 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
631 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
632 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
633 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
634 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
635 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
637 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
639 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
640 if (!Subtarget->hasV6Ops()) {
641 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
642 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
644 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
646 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
647 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
648 // iff target supports vfp2.
649 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
650 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
653 // We want to custom lower some of our intrinsics.
654 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
655 if (Subtarget->isTargetDarwin()) {
656 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
657 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
658 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
661 setOperationAction(ISD::SETCC, MVT::i32, Expand);
662 setOperationAction(ISD::SETCC, MVT::f32, Expand);
663 setOperationAction(ISD::SETCC, MVT::f64, Expand);
664 setOperationAction(ISD::SELECT, MVT::i32, Custom);
665 setOperationAction(ISD::SELECT, MVT::f32, Custom);
666 setOperationAction(ISD::SELECT, MVT::f64, Custom);
667 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
668 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
669 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
671 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
672 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
673 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
674 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
675 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
677 // We don't support sin/cos/fmod/copysign/pow
678 setOperationAction(ISD::FSIN, MVT::f64, Expand);
679 setOperationAction(ISD::FSIN, MVT::f32, Expand);
680 setOperationAction(ISD::FCOS, MVT::f32, Expand);
681 setOperationAction(ISD::FCOS, MVT::f64, Expand);
682 setOperationAction(ISD::FREM, MVT::f64, Expand);
683 setOperationAction(ISD::FREM, MVT::f32, Expand);
684 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
685 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
686 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
688 setOperationAction(ISD::FPOW, MVT::f64, Expand);
689 setOperationAction(ISD::FPOW, MVT::f32, Expand);
691 // Various VFP goodness
692 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
693 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
694 if (Subtarget->hasVFP2()) {
695 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
696 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
697 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
698 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
700 // Special handling for half-precision FP.
701 if (!Subtarget->hasFP16()) {
702 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
703 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
707 // We have target-specific dag combine patterns for the following nodes:
708 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
709 setTargetDAGCombine(ISD::ADD);
710 setTargetDAGCombine(ISD::SUB);
711 setTargetDAGCombine(ISD::MUL);
713 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
714 setTargetDAGCombine(ISD::OR);
715 if (Subtarget->hasNEON())
716 setTargetDAGCombine(ISD::AND);
718 setStackPointerRegisterToSaveRestore(ARM::SP);
720 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
721 setSchedulingPreference(Sched::RegPressure);
723 setSchedulingPreference(Sched::Hybrid);
725 //// temporary - rewrite interface to use type
726 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
728 // On ARM arguments smaller than 4 bytes are extended, so all arguments
729 // are at least 4 bytes aligned.
730 setMinStackArgumentAlignment(4);
732 benefitFromCodePlacementOpt = true;
734 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
737 // FIXME: It might make sense to define the representative register class as the
738 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
739 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
740 // SPR's representative would be DPR_VFP2. This should work well if register
741 // pressure tracking were modified such that a register use would increment the
742 // pressure of the register class's representative and all of it's super
743 // classes' representatives transitively. We have not implemented this because
744 // of the difficulty prior to coalescing of modeling operand register classes
745 // due to the common occurrence of cross class copies and subregister insertions
747 std::pair<const TargetRegisterClass*, uint8_t>
748 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
749 const TargetRegisterClass *RRC = 0;
751 switch (VT.getSimpleVT().SimpleTy) {
753 return TargetLowering::findRepresentativeClass(VT);
754 // Use DPR as representative register class for all floating point
755 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
756 // the cost is 1 for both f32 and f64.
757 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
758 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
759 RRC = ARM::DPRRegisterClass;
760 // When NEON is used for SP, only half of the register file is available
761 // because operations that define both SP and DP results will be constrained
762 // to the VFP2 class (D0-D15). We currently model this constraint prior to
763 // coalescing by double-counting the SP regs. See the FIXME above.
764 if (Subtarget->useNEONForSinglePrecisionFP())
767 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
768 case MVT::v4f32: case MVT::v2f64:
769 RRC = ARM::DPRRegisterClass;
773 RRC = ARM::DPRRegisterClass;
777 RRC = ARM::DPRRegisterClass;
781 return std::make_pair(RRC, Cost);
784 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
787 case ARMISD::Wrapper: return "ARMISD::Wrapper";
788 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
789 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
790 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
791 case ARMISD::CALL: return "ARMISD::CALL";
792 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
793 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
794 case ARMISD::tCALL: return "ARMISD::tCALL";
795 case ARMISD::BRCOND: return "ARMISD::BRCOND";
796 case ARMISD::BR_JT: return "ARMISD::BR_JT";
797 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
798 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
799 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
800 case ARMISD::CMP: return "ARMISD::CMP";
801 case ARMISD::CMPZ: return "ARMISD::CMPZ";
802 case ARMISD::CMPFP: return "ARMISD::CMPFP";
803 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
804 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
805 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
806 case ARMISD::CMOV: return "ARMISD::CMOV";
808 case ARMISD::RBIT: return "ARMISD::RBIT";
810 case ARMISD::FTOSI: return "ARMISD::FTOSI";
811 case ARMISD::FTOUI: return "ARMISD::FTOUI";
812 case ARMISD::SITOF: return "ARMISD::SITOF";
813 case ARMISD::UITOF: return "ARMISD::UITOF";
815 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
816 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
817 case ARMISD::RRX: return "ARMISD::RRX";
819 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
820 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
822 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
823 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
824 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
826 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
828 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
830 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
832 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
833 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
835 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
837 case ARMISD::VCEQ: return "ARMISD::VCEQ";
838 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
839 case ARMISD::VCGE: return "ARMISD::VCGE";
840 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
841 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
842 case ARMISD::VCGEU: return "ARMISD::VCGEU";
843 case ARMISD::VCGT: return "ARMISD::VCGT";
844 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
845 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
846 case ARMISD::VCGTU: return "ARMISD::VCGTU";
847 case ARMISD::VTST: return "ARMISD::VTST";
849 case ARMISD::VSHL: return "ARMISD::VSHL";
850 case ARMISD::VSHRs: return "ARMISD::VSHRs";
851 case ARMISD::VSHRu: return "ARMISD::VSHRu";
852 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
853 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
854 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
855 case ARMISD::VSHRN: return "ARMISD::VSHRN";
856 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
857 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
858 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
859 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
860 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
861 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
862 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
863 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
864 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
865 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
866 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
867 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
868 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
869 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
870 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
871 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
872 case ARMISD::VDUP: return "ARMISD::VDUP";
873 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
874 case ARMISD::VEXT: return "ARMISD::VEXT";
875 case ARMISD::VREV64: return "ARMISD::VREV64";
876 case ARMISD::VREV32: return "ARMISD::VREV32";
877 case ARMISD::VREV16: return "ARMISD::VREV16";
878 case ARMISD::VZIP: return "ARMISD::VZIP";
879 case ARMISD::VUZP: return "ARMISD::VUZP";
880 case ARMISD::VTRN: return "ARMISD::VTRN";
881 case ARMISD::VTBL1: return "ARMISD::VTBL1";
882 case ARMISD::VTBL2: return "ARMISD::VTBL2";
883 case ARMISD::VMULLs: return "ARMISD::VMULLs";
884 case ARMISD::VMULLu: return "ARMISD::VMULLu";
885 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
886 case ARMISD::FMAX: return "ARMISD::FMAX";
887 case ARMISD::FMIN: return "ARMISD::FMIN";
888 case ARMISD::BFI: return "ARMISD::BFI";
889 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
890 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
891 case ARMISD::VBSL: return "ARMISD::VBSL";
892 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
893 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
894 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
895 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
896 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
897 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
898 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
899 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
900 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
901 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
902 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
903 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
904 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
905 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
906 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
907 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
908 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
909 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
910 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
911 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
915 /// getRegClassFor - Return the register class that should be used for the
916 /// specified value type.
917 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
918 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
919 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
920 // load / store 4 to 8 consecutive D registers.
921 if (Subtarget->hasNEON()) {
922 if (VT == MVT::v4i64)
923 return ARM::QQPRRegisterClass;
924 else if (VT == MVT::v8i64)
925 return ARM::QQQQPRRegisterClass;
927 return TargetLowering::getRegClassFor(VT);
930 // Create a fast isel object.
932 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
933 return ARM::createFastISel(funcInfo);
936 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
937 /// be used for loads / stores from the global.
938 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
939 return (Subtarget->isThumb1Only() ? 127 : 4095);
942 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
943 unsigned NumVals = N->getNumValues();
945 return Sched::RegPressure;
947 for (unsigned i = 0; i != NumVals; ++i) {
948 EVT VT = N->getValueType(i);
949 if (VT == MVT::Glue || VT == MVT::Other)
951 if (VT.isFloatingPoint() || VT.isVector())
952 return Sched::Latency;
955 if (!N->isMachineOpcode())
956 return Sched::RegPressure;
958 // Load are scheduled for latency even if there instruction itinerary
960 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
961 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
963 if (TID.getNumDefs() == 0)
964 return Sched::RegPressure;
965 if (!Itins->isEmpty() &&
966 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
967 return Sched::Latency;
969 return Sched::RegPressure;
972 //===----------------------------------------------------------------------===//
974 //===----------------------------------------------------------------------===//
976 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
977 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
979 default: llvm_unreachable("Unknown condition code!");
980 case ISD::SETNE: return ARMCC::NE;
981 case ISD::SETEQ: return ARMCC::EQ;
982 case ISD::SETGT: return ARMCC::GT;
983 case ISD::SETGE: return ARMCC::GE;
984 case ISD::SETLT: return ARMCC::LT;
985 case ISD::SETLE: return ARMCC::LE;
986 case ISD::SETUGT: return ARMCC::HI;
987 case ISD::SETUGE: return ARMCC::HS;
988 case ISD::SETULT: return ARMCC::LO;
989 case ISD::SETULE: return ARMCC::LS;
993 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
994 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
995 ARMCC::CondCodes &CondCode2) {
996 CondCode2 = ARMCC::AL;
998 default: llvm_unreachable("Unknown FP condition!");
1000 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1002 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1004 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1005 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1006 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1007 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1008 case ISD::SETO: CondCode = ARMCC::VC; break;
1009 case ISD::SETUO: CondCode = ARMCC::VS; break;
1010 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1011 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1012 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1014 case ISD::SETULT: CondCode = ARMCC::LT; break;
1016 case ISD::SETULE: CondCode = ARMCC::LE; break;
1018 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1022 //===----------------------------------------------------------------------===//
1023 // Calling Convention Implementation
1024 //===----------------------------------------------------------------------===//
1026 #include "ARMGenCallingConv.inc"
1028 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1029 /// given CallingConvention value.
1030 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1032 bool isVarArg) const {
1035 llvm_unreachable("Unsupported calling convention");
1036 case CallingConv::Fast:
1037 if (Subtarget->hasVFP2() && !isVarArg) {
1038 if (!Subtarget->isAAPCS_ABI())
1039 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1040 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1041 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1044 case CallingConv::C: {
1045 // Use target triple & subtarget features to do actual dispatch.
1046 if (!Subtarget->isAAPCS_ABI())
1047 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1048 else if (Subtarget->hasVFP2() &&
1049 FloatABIType == FloatABI::Hard && !isVarArg)
1050 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1051 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1053 case CallingConv::ARM_AAPCS_VFP:
1054 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1055 case CallingConv::ARM_AAPCS:
1056 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1057 case CallingConv::ARM_APCS:
1058 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1062 /// LowerCallResult - Lower the result values of a call into the
1063 /// appropriate copies out of appropriate physical registers.
1065 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1066 CallingConv::ID CallConv, bool isVarArg,
1067 const SmallVectorImpl<ISD::InputArg> &Ins,
1068 DebugLoc dl, SelectionDAG &DAG,
1069 SmallVectorImpl<SDValue> &InVals) const {
1071 // Assign locations to each value returned by this call.
1072 SmallVector<CCValAssign, 16> RVLocs;
1073 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1074 RVLocs, *DAG.getContext());
1075 CCInfo.AnalyzeCallResult(Ins,
1076 CCAssignFnForNode(CallConv, /* Return*/ true,
1079 // Copy all of the result registers out of their specified physreg.
1080 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1081 CCValAssign VA = RVLocs[i];
1084 if (VA.needsCustom()) {
1085 // Handle f64 or half of a v2f64.
1086 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1088 Chain = Lo.getValue(1);
1089 InFlag = Lo.getValue(2);
1090 VA = RVLocs[++i]; // skip ahead to next loc
1091 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1093 Chain = Hi.getValue(1);
1094 InFlag = Hi.getValue(2);
1095 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1097 if (VA.getLocVT() == MVT::v2f64) {
1098 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1099 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1100 DAG.getConstant(0, MVT::i32));
1102 VA = RVLocs[++i]; // skip ahead to next loc
1103 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1104 Chain = Lo.getValue(1);
1105 InFlag = Lo.getValue(2);
1106 VA = RVLocs[++i]; // skip ahead to next loc
1107 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1108 Chain = Hi.getValue(1);
1109 InFlag = Hi.getValue(2);
1110 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1111 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1112 DAG.getConstant(1, MVT::i32));
1115 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1117 Chain = Val.getValue(1);
1118 InFlag = Val.getValue(2);
1121 switch (VA.getLocInfo()) {
1122 default: llvm_unreachable("Unknown loc info!");
1123 case CCValAssign::Full: break;
1124 case CCValAssign::BCvt:
1125 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1129 InVals.push_back(Val);
1135 /// LowerMemOpCallTo - Store the argument to the stack.
1137 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1138 SDValue StackPtr, SDValue Arg,
1139 DebugLoc dl, SelectionDAG &DAG,
1140 const CCValAssign &VA,
1141 ISD::ArgFlagsTy Flags) const {
1142 unsigned LocMemOffset = VA.getLocMemOffset();
1143 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1144 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1145 return DAG.getStore(Chain, dl, Arg, PtrOff,
1146 MachinePointerInfo::getStack(LocMemOffset),
1150 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1151 SDValue Chain, SDValue &Arg,
1152 RegsToPassVector &RegsToPass,
1153 CCValAssign &VA, CCValAssign &NextVA,
1155 SmallVector<SDValue, 8> &MemOpChains,
1156 ISD::ArgFlagsTy Flags) const {
1158 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1159 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1160 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1162 if (NextVA.isRegLoc())
1163 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1165 assert(NextVA.isMemLoc());
1166 if (StackPtr.getNode() == 0)
1167 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1169 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1175 /// LowerCall - Lowering a call into a callseq_start <-
1176 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1179 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1180 CallingConv::ID CallConv, bool isVarArg,
1182 const SmallVectorImpl<ISD::OutputArg> &Outs,
1183 const SmallVectorImpl<SDValue> &OutVals,
1184 const SmallVectorImpl<ISD::InputArg> &Ins,
1185 DebugLoc dl, SelectionDAG &DAG,
1186 SmallVectorImpl<SDValue> &InVals) const {
1187 MachineFunction &MF = DAG.getMachineFunction();
1188 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1189 bool IsSibCall = false;
1190 // Temporarily disable tail calls so things don't break.
1191 if (!EnableARMTailCalls)
1194 // Check if it's really possible to do a tail call.
1195 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1196 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1197 Outs, OutVals, Ins, DAG);
1198 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1199 // detected sibcalls.
1206 // Analyze operands of the call, assigning locations to each operand.
1207 SmallVector<CCValAssign, 16> ArgLocs;
1208 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1210 CCInfo.setCallOrPrologue(Call);
1211 CCInfo.AnalyzeCallOperands(Outs,
1212 CCAssignFnForNode(CallConv, /* Return*/ false,
1215 // Get a count of how many bytes are to be pushed on the stack.
1216 unsigned NumBytes = CCInfo.getNextStackOffset();
1218 // For tail calls, memory operands are available in our caller's stack.
1222 // Adjust the stack pointer for the new arguments...
1223 // These operations are automatically eliminated by the prolog/epilog pass
1225 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1227 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1229 RegsToPassVector RegsToPass;
1230 SmallVector<SDValue, 8> MemOpChains;
1232 // Walk the register/memloc assignments, inserting copies/loads. In the case
1233 // of tail call optimization, arguments are handled later.
1234 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1236 ++i, ++realArgIdx) {
1237 CCValAssign &VA = ArgLocs[i];
1238 SDValue Arg = OutVals[realArgIdx];
1239 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1240 bool isByVal = Flags.isByVal();
1242 // Promote the value if needed.
1243 switch (VA.getLocInfo()) {
1244 default: llvm_unreachable("Unknown loc info!");
1245 case CCValAssign::Full: break;
1246 case CCValAssign::SExt:
1247 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1249 case CCValAssign::ZExt:
1250 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1252 case CCValAssign::AExt:
1253 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1255 case CCValAssign::BCvt:
1256 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1260 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1261 if (VA.needsCustom()) {
1262 if (VA.getLocVT() == MVT::v2f64) {
1263 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1264 DAG.getConstant(0, MVT::i32));
1265 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1266 DAG.getConstant(1, MVT::i32));
1268 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1269 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1271 VA = ArgLocs[++i]; // skip ahead to next loc
1272 if (VA.isRegLoc()) {
1273 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1274 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1276 assert(VA.isMemLoc());
1278 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1279 dl, DAG, VA, Flags));
1282 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1283 StackPtr, MemOpChains, Flags);
1285 } else if (VA.isRegLoc()) {
1286 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1287 } else if (isByVal) {
1288 assert(VA.isMemLoc());
1289 unsigned offset = 0;
1291 // True if this byval aggregate will be split between registers
1293 if (CCInfo.isFirstByValRegValid()) {
1294 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1296 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1297 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1298 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1299 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1300 MachinePointerInfo(),
1302 MemOpChains.push_back(Load.getValue(1));
1303 RegsToPass.push_back(std::make_pair(j, Load));
1305 offset = ARM::R4 - CCInfo.getFirstByValReg();
1306 CCInfo.clearFirstByValReg();
1309 unsigned LocMemOffset = VA.getLocMemOffset();
1310 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1311 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1313 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1314 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1315 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1317 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
1318 Flags.getByValAlign(),
1319 /*isVolatile=*/false,
1320 /*AlwaysInline=*/false,
1321 MachinePointerInfo(0),
1322 MachinePointerInfo(0)));
1324 } else if (!IsSibCall) {
1325 assert(VA.isMemLoc());
1327 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1328 dl, DAG, VA, Flags));
1332 if (!MemOpChains.empty())
1333 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1334 &MemOpChains[0], MemOpChains.size());
1336 // Build a sequence of copy-to-reg nodes chained together with token chain
1337 // and flag operands which copy the outgoing args into the appropriate regs.
1339 // Tail call byval lowering might overwrite argument registers so in case of
1340 // tail call optimization the copies to registers are lowered later.
1342 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1343 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1344 RegsToPass[i].second, InFlag);
1345 InFlag = Chain.getValue(1);
1348 // For tail calls lower the arguments to the 'real' stack slot.
1350 // Force all the incoming stack arguments to be loaded from the stack
1351 // before any new outgoing arguments are stored to the stack, because the
1352 // outgoing stack slots may alias the incoming argument stack slots, and
1353 // the alias isn't otherwise explicit. This is slightly more conservative
1354 // than necessary, because it means that each store effectively depends
1355 // on every argument instead of just those arguments it would clobber.
1357 // Do not flag preceding copytoreg stuff together with the following stuff.
1359 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1360 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1361 RegsToPass[i].second, InFlag);
1362 InFlag = Chain.getValue(1);
1367 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1368 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1369 // node so that legalize doesn't hack it.
1370 bool isDirect = false;
1371 bool isARMFunc = false;
1372 bool isLocalARMFunc = false;
1373 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1375 if (EnableARMLongCalls) {
1376 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1377 && "long-calls with non-static relocation model!");
1378 // Handle a global address or an external symbol. If it's not one of
1379 // those, the target's already in a register, so we don't need to do
1381 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1382 const GlobalValue *GV = G->getGlobal();
1383 // Create a constant pool entry for the callee address
1384 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1385 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1388 // Get the address of the callee into a register
1389 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1390 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1391 Callee = DAG.getLoad(getPointerTy(), dl,
1392 DAG.getEntryNode(), CPAddr,
1393 MachinePointerInfo::getConstantPool(),
1395 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1396 const char *Sym = S->getSymbol();
1398 // Create a constant pool entry for the callee address
1399 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1400 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1401 Sym, ARMPCLabelIndex, 0);
1402 // Get the address of the callee into a register
1403 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1404 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1405 Callee = DAG.getLoad(getPointerTy(), dl,
1406 DAG.getEntryNode(), CPAddr,
1407 MachinePointerInfo::getConstantPool(),
1410 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1411 const GlobalValue *GV = G->getGlobal();
1413 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1414 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1415 getTargetMachine().getRelocationModel() != Reloc::Static;
1416 isARMFunc = !Subtarget->isThumb() || isStub;
1417 // ARM call to a local ARM function is predicable.
1418 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1419 // tBX takes a register source operand.
1420 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1421 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1422 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1425 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1426 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1427 Callee = DAG.getLoad(getPointerTy(), dl,
1428 DAG.getEntryNode(), CPAddr,
1429 MachinePointerInfo::getConstantPool(),
1431 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1432 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1433 getPointerTy(), Callee, PICLabel);
1435 // On ELF targets for PIC code, direct calls should go through the PLT
1436 unsigned OpFlags = 0;
1437 if (Subtarget->isTargetELF() &&
1438 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1439 OpFlags = ARMII::MO_PLT;
1440 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1442 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1444 bool isStub = Subtarget->isTargetDarwin() &&
1445 getTargetMachine().getRelocationModel() != Reloc::Static;
1446 isARMFunc = !Subtarget->isThumb() || isStub;
1447 // tBX takes a register source operand.
1448 const char *Sym = S->getSymbol();
1449 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1450 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1451 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1452 Sym, ARMPCLabelIndex, 4);
1453 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1454 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1455 Callee = DAG.getLoad(getPointerTy(), dl,
1456 DAG.getEntryNode(), CPAddr,
1457 MachinePointerInfo::getConstantPool(),
1459 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1460 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1461 getPointerTy(), Callee, PICLabel);
1463 unsigned OpFlags = 0;
1464 // On ELF targets for PIC code, direct calls should go through the PLT
1465 if (Subtarget->isTargetELF() &&
1466 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1467 OpFlags = ARMII::MO_PLT;
1468 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1472 // FIXME: handle tail calls differently.
1474 if (Subtarget->isThumb()) {
1475 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1476 CallOpc = ARMISD::CALL_NOLINK;
1478 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1480 CallOpc = (isDirect || Subtarget->hasV5TOps())
1481 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1482 : ARMISD::CALL_NOLINK;
1485 std::vector<SDValue> Ops;
1486 Ops.push_back(Chain);
1487 Ops.push_back(Callee);
1489 // Add argument registers to the end of the list so that they are known live
1491 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1492 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1493 RegsToPass[i].second.getValueType()));
1495 if (InFlag.getNode())
1496 Ops.push_back(InFlag);
1498 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1500 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1502 // Returns a chain and a flag for retval copy to use.
1503 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1504 InFlag = Chain.getValue(1);
1506 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1507 DAG.getIntPtrConstant(0, true), InFlag);
1509 InFlag = Chain.getValue(1);
1511 // Handle result values, copying them out of physregs into vregs that we
1513 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1517 /// HandleByVal - Every parameter *after* a byval parameter is passed
1518 /// on the stack. Remember the next parameter register to allocate,
1519 /// and then confiscate the rest of the parameter registers to insure
1522 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1523 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1524 assert((State->getCallOrPrologue() == Prologue ||
1525 State->getCallOrPrologue() == Call) &&
1526 "unhandled ParmContext");
1527 if ((!State->isFirstByValRegValid()) &&
1528 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1529 State->setFirstByValReg(reg);
1530 // At a call site, a byval parameter that is split between
1531 // registers and memory needs its size truncated here. In a
1532 // function prologue, such byval parameters are reassembled in
1533 // memory, and are not truncated.
1534 if (State->getCallOrPrologue() == Call) {
1535 unsigned excess = 4 * (ARM::R4 - reg);
1536 assert(size >= excess && "expected larger existing stack allocation");
1540 // Confiscate any remaining parameter registers to preclude their
1541 // assignment to subsequent parameters.
1542 while (State->AllocateReg(GPRArgRegs, 4))
1546 /// MatchingStackOffset - Return true if the given stack call argument is
1547 /// already available in the same position (relatively) of the caller's
1548 /// incoming argument stack.
1550 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1551 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1552 const ARMInstrInfo *TII) {
1553 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1555 if (Arg.getOpcode() == ISD::CopyFromReg) {
1556 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1557 if (!TargetRegisterInfo::isVirtualRegister(VR))
1559 MachineInstr *Def = MRI->getVRegDef(VR);
1562 if (!Flags.isByVal()) {
1563 if (!TII->isLoadFromStackSlot(Def, FI))
1568 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1569 if (Flags.isByVal())
1570 // ByVal argument is passed in as a pointer but it's now being
1571 // dereferenced. e.g.
1572 // define @foo(%struct.X* %A) {
1573 // tail call @bar(%struct.X* byval %A)
1576 SDValue Ptr = Ld->getBasePtr();
1577 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1580 FI = FINode->getIndex();
1584 assert(FI != INT_MAX);
1585 if (!MFI->isFixedObjectIndex(FI))
1587 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1590 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1591 /// for tail call optimization. Targets which want to do tail call
1592 /// optimization should implement this function.
1594 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1595 CallingConv::ID CalleeCC,
1597 bool isCalleeStructRet,
1598 bool isCallerStructRet,
1599 const SmallVectorImpl<ISD::OutputArg> &Outs,
1600 const SmallVectorImpl<SDValue> &OutVals,
1601 const SmallVectorImpl<ISD::InputArg> &Ins,
1602 SelectionDAG& DAG) const {
1603 const Function *CallerF = DAG.getMachineFunction().getFunction();
1604 CallingConv::ID CallerCC = CallerF->getCallingConv();
1605 bool CCMatch = CallerCC == CalleeCC;
1607 // Look for obvious safe cases to perform tail call optimization that do not
1608 // require ABI changes. This is what gcc calls sibcall.
1610 // Do not sibcall optimize vararg calls unless the call site is not passing
1612 if (isVarArg && !Outs.empty())
1615 // Also avoid sibcall optimization if either caller or callee uses struct
1616 // return semantics.
1617 if (isCalleeStructRet || isCallerStructRet)
1620 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1621 // emitEpilogue is not ready for them.
1622 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1623 // LR. This means if we need to reload LR, it takes an extra instructions,
1624 // which outweighs the value of the tail call; but here we don't know yet
1625 // whether LR is going to be used. Probably the right approach is to
1626 // generate the tail call here and turn it back into CALL/RET in
1627 // emitEpilogue if LR is used.
1629 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1630 // but we need to make sure there are enough registers; the only valid
1631 // registers are the 4 used for parameters. We don't currently do this
1633 if (Subtarget->isThumb1Only())
1636 // If the calling conventions do not match, then we'd better make sure the
1637 // results are returned in the same way as what the caller expects.
1639 SmallVector<CCValAssign, 16> RVLocs1;
1640 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1641 RVLocs1, *DAG.getContext());
1642 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1644 SmallVector<CCValAssign, 16> RVLocs2;
1645 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1646 RVLocs2, *DAG.getContext());
1647 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1649 if (RVLocs1.size() != RVLocs2.size())
1651 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1652 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1654 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1656 if (RVLocs1[i].isRegLoc()) {
1657 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1660 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1666 // If the callee takes no arguments then go on to check the results of the
1668 if (!Outs.empty()) {
1669 // Check if stack adjustment is needed. For now, do not do this if any
1670 // argument is passed on the stack.
1671 SmallVector<CCValAssign, 16> ArgLocs;
1672 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1673 ArgLocs, *DAG.getContext());
1674 CCInfo.AnalyzeCallOperands(Outs,
1675 CCAssignFnForNode(CalleeCC, false, isVarArg));
1676 if (CCInfo.getNextStackOffset()) {
1677 MachineFunction &MF = DAG.getMachineFunction();
1679 // Check if the arguments are already laid out in the right way as
1680 // the caller's fixed stack objects.
1681 MachineFrameInfo *MFI = MF.getFrameInfo();
1682 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1683 const ARMInstrInfo *TII =
1684 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1685 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1687 ++i, ++realArgIdx) {
1688 CCValAssign &VA = ArgLocs[i];
1689 EVT RegVT = VA.getLocVT();
1690 SDValue Arg = OutVals[realArgIdx];
1691 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1692 if (VA.getLocInfo() == CCValAssign::Indirect)
1694 if (VA.needsCustom()) {
1695 // f64 and vector types are split into multiple registers or
1696 // register/stack-slot combinations. The types will not match
1697 // the registers; give up on memory f64 refs until we figure
1698 // out what to do about this.
1701 if (!ArgLocs[++i].isRegLoc())
1703 if (RegVT == MVT::v2f64) {
1704 if (!ArgLocs[++i].isRegLoc())
1706 if (!ArgLocs[++i].isRegLoc())
1709 } else if (!VA.isRegLoc()) {
1710 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1722 ARMTargetLowering::LowerReturn(SDValue Chain,
1723 CallingConv::ID CallConv, bool isVarArg,
1724 const SmallVectorImpl<ISD::OutputArg> &Outs,
1725 const SmallVectorImpl<SDValue> &OutVals,
1726 DebugLoc dl, SelectionDAG &DAG) const {
1728 // CCValAssign - represent the assignment of the return value to a location.
1729 SmallVector<CCValAssign, 16> RVLocs;
1731 // CCState - Info about the registers and stack slots.
1732 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1735 // Analyze outgoing return values.
1736 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1739 // If this is the first return lowered for this function, add
1740 // the regs to the liveout set for the function.
1741 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1742 for (unsigned i = 0; i != RVLocs.size(); ++i)
1743 if (RVLocs[i].isRegLoc())
1744 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1749 // Copy the result values into the output registers.
1750 for (unsigned i = 0, realRVLocIdx = 0;
1752 ++i, ++realRVLocIdx) {
1753 CCValAssign &VA = RVLocs[i];
1754 assert(VA.isRegLoc() && "Can only return in registers!");
1756 SDValue Arg = OutVals[realRVLocIdx];
1758 switch (VA.getLocInfo()) {
1759 default: llvm_unreachable("Unknown loc info!");
1760 case CCValAssign::Full: break;
1761 case CCValAssign::BCvt:
1762 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1766 if (VA.needsCustom()) {
1767 if (VA.getLocVT() == MVT::v2f64) {
1768 // Extract the first half and return it in two registers.
1769 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1770 DAG.getConstant(0, MVT::i32));
1771 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1772 DAG.getVTList(MVT::i32, MVT::i32), Half);
1774 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1775 Flag = Chain.getValue(1);
1776 VA = RVLocs[++i]; // skip ahead to next loc
1777 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1778 HalfGPRs.getValue(1), Flag);
1779 Flag = Chain.getValue(1);
1780 VA = RVLocs[++i]; // skip ahead to next loc
1782 // Extract the 2nd half and fall through to handle it as an f64 value.
1783 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1784 DAG.getConstant(1, MVT::i32));
1786 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1788 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1789 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1790 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1791 Flag = Chain.getValue(1);
1792 VA = RVLocs[++i]; // skip ahead to next loc
1793 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1796 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1798 // Guarantee that all emitted copies are
1799 // stuck together, avoiding something bad.
1800 Flag = Chain.getValue(1);
1805 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1807 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1812 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1813 if (N->getNumValues() != 1)
1815 if (!N->hasNUsesOfValue(1, 0))
1818 unsigned NumCopies = 0;
1820 SDNode *Use = *N->use_begin();
1821 if (Use->getOpcode() == ISD::CopyToReg) {
1822 Copies[NumCopies++] = Use;
1823 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1824 // f64 returned in a pair of GPRs.
1825 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1827 if (UI->getOpcode() != ISD::CopyToReg)
1829 Copies[UI.getUse().getResNo()] = *UI;
1832 } else if (Use->getOpcode() == ISD::BITCAST) {
1833 // f32 returned in a single GPR.
1834 if (!Use->hasNUsesOfValue(1, 0))
1836 Use = *Use->use_begin();
1837 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1839 Copies[NumCopies++] = Use;
1844 if (NumCopies != 1 && NumCopies != 2)
1847 bool HasRet = false;
1848 for (unsigned i = 0; i < NumCopies; ++i) {
1849 SDNode *Copy = Copies[i];
1850 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1852 if (UI->getOpcode() == ISD::CopyToReg) {
1854 if (Use == Copies[0] || Use == Copies[1])
1858 if (UI->getOpcode() != ARMISD::RET_FLAG)
1867 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1868 if (!EnableARMTailCalls)
1871 if (!CI->isTailCall())
1874 return !Subtarget->isThumb1Only();
1877 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1878 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1879 // one of the above mentioned nodes. It has to be wrapped because otherwise
1880 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1881 // be used to form addressing mode. These wrapped nodes will be selected
1883 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1884 EVT PtrVT = Op.getValueType();
1885 // FIXME there is no actual debug info here
1886 DebugLoc dl = Op.getDebugLoc();
1887 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1889 if (CP->isMachineConstantPoolEntry())
1890 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1891 CP->getAlignment());
1893 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1894 CP->getAlignment());
1895 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1898 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1899 return MachineJumpTableInfo::EK_Inline;
1902 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1903 SelectionDAG &DAG) const {
1904 MachineFunction &MF = DAG.getMachineFunction();
1905 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1906 unsigned ARMPCLabelIndex = 0;
1907 DebugLoc DL = Op.getDebugLoc();
1908 EVT PtrVT = getPointerTy();
1909 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1910 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1912 if (RelocM == Reloc::Static) {
1913 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1915 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1916 ARMPCLabelIndex = AFI->createPICLabelUId();
1917 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1918 ARMCP::CPBlockAddress,
1920 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1922 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1923 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1924 MachinePointerInfo::getConstantPool(),
1926 if (RelocM == Reloc::Static)
1928 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1929 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1932 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1934 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1935 SelectionDAG &DAG) const {
1936 DebugLoc dl = GA->getDebugLoc();
1937 EVT PtrVT = getPointerTy();
1938 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1939 MachineFunction &MF = DAG.getMachineFunction();
1940 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1941 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1942 ARMConstantPoolValue *CPV =
1943 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1944 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1945 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1946 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1947 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1948 MachinePointerInfo::getConstantPool(),
1950 SDValue Chain = Argument.getValue(1);
1952 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1953 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1955 // call __tls_get_addr.
1958 Entry.Node = Argument;
1959 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1960 Args.push_back(Entry);
1961 // FIXME: is there useful debug info available here?
1962 std::pair<SDValue, SDValue> CallResult =
1963 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1964 false, false, false, false,
1965 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1966 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1967 return CallResult.first;
1970 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1971 // "local exec" model.
1973 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1974 SelectionDAG &DAG) const {
1975 const GlobalValue *GV = GA->getGlobal();
1976 DebugLoc dl = GA->getDebugLoc();
1978 SDValue Chain = DAG.getEntryNode();
1979 EVT PtrVT = getPointerTy();
1980 // Get the Thread Pointer
1981 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1983 if (GV->isDeclaration()) {
1984 MachineFunction &MF = DAG.getMachineFunction();
1985 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1986 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1987 // Initial exec model.
1988 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1989 ARMConstantPoolValue *CPV =
1990 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1991 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1992 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1993 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1994 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1995 MachinePointerInfo::getConstantPool(),
1997 Chain = Offset.getValue(1);
1999 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2000 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2002 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2003 MachinePointerInfo::getConstantPool(),
2007 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
2008 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2009 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2010 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2011 MachinePointerInfo::getConstantPool(),
2015 // The address of the thread local variable is the add of the thread
2016 // pointer with the offset of the variable.
2017 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2021 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2022 // TODO: implement the "local dynamic" model
2023 assert(Subtarget->isTargetELF() &&
2024 "TLS not implemented for non-ELF targets");
2025 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2026 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
2027 // otherwise use the "Local Exec" TLS Model
2028 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
2029 return LowerToTLSGeneralDynamicModel(GA, DAG);
2031 return LowerToTLSExecModels(GA, DAG);
2034 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2035 SelectionDAG &DAG) const {
2036 EVT PtrVT = getPointerTy();
2037 DebugLoc dl = Op.getDebugLoc();
2038 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2039 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2040 if (RelocM == Reloc::PIC_) {
2041 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2042 ARMConstantPoolValue *CPV =
2043 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2044 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2045 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2046 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2048 MachinePointerInfo::getConstantPool(),
2050 SDValue Chain = Result.getValue(1);
2051 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2052 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2054 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2055 MachinePointerInfo::getGOT(), false, false, 0);
2059 // If we have T2 ops, we can materialize the address directly via movt/movw
2060 // pair. This is always cheaper.
2061 if (Subtarget->useMovt()) {
2063 // FIXME: Once remat is capable of dealing with instructions with register
2064 // operands, expand this into two nodes.
2065 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2066 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2068 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2069 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2070 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2071 MachinePointerInfo::getConstantPool(),
2076 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2077 SelectionDAG &DAG) const {
2078 EVT PtrVT = getPointerTy();
2079 DebugLoc dl = Op.getDebugLoc();
2080 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2081 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2082 MachineFunction &MF = DAG.getMachineFunction();
2083 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2085 // FIXME: Enable this for static codegen when tool issues are fixed.
2086 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2088 // FIXME: Once remat is capable of dealing with instructions with register
2089 // operands, expand this into two nodes.
2090 if (RelocM == Reloc::Static)
2091 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2092 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2094 unsigned Wrapper = (RelocM == Reloc::PIC_)
2095 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2096 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2097 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2098 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2099 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2100 MachinePointerInfo::getGOT(), false, false, 0);
2104 unsigned ARMPCLabelIndex = 0;
2106 if (RelocM == Reloc::Static) {
2107 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2109 ARMPCLabelIndex = AFI->createPICLabelUId();
2110 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2111 ARMConstantPoolValue *CPV =
2112 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
2113 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2115 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2117 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2118 MachinePointerInfo::getConstantPool(),
2120 SDValue Chain = Result.getValue(1);
2122 if (RelocM == Reloc::PIC_) {
2123 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2124 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2127 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2128 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2134 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2135 SelectionDAG &DAG) const {
2136 assert(Subtarget->isTargetELF() &&
2137 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2138 MachineFunction &MF = DAG.getMachineFunction();
2139 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2140 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2141 EVT PtrVT = getPointerTy();
2142 DebugLoc dl = Op.getDebugLoc();
2143 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2144 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2145 "_GLOBAL_OFFSET_TABLE_",
2146 ARMPCLabelIndex, PCAdj);
2147 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2148 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2149 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2150 MachinePointerInfo::getConstantPool(),
2152 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2153 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2157 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2159 DebugLoc dl = Op.getDebugLoc();
2160 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2161 Op.getOperand(0), Op.getOperand(1));
2165 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2166 DebugLoc dl = Op.getDebugLoc();
2167 SDValue Val = DAG.getConstant(0, MVT::i32);
2168 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2169 Op.getOperand(1), Val);
2173 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2174 DebugLoc dl = Op.getDebugLoc();
2175 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2176 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2180 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2181 const ARMSubtarget *Subtarget) const {
2182 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2183 DebugLoc dl = Op.getDebugLoc();
2185 default: return SDValue(); // Don't custom lower most intrinsics.
2186 case Intrinsic::arm_thread_pointer: {
2187 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2188 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2190 case Intrinsic::eh_sjlj_lsda: {
2191 MachineFunction &MF = DAG.getMachineFunction();
2192 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2193 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2194 EVT PtrVT = getPointerTy();
2195 DebugLoc dl = Op.getDebugLoc();
2196 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2198 unsigned PCAdj = (RelocM != Reloc::PIC_)
2199 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2200 ARMConstantPoolValue *CPV =
2201 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2202 ARMCP::CPLSDA, PCAdj);
2203 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2204 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2206 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2207 MachinePointerInfo::getConstantPool(),
2210 if (RelocM == Reloc::PIC_) {
2211 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2212 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2216 case Intrinsic::arm_neon_vmulls:
2217 case Intrinsic::arm_neon_vmullu: {
2218 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2219 ? ARMISD::VMULLs : ARMISD::VMULLu;
2220 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2221 Op.getOperand(1), Op.getOperand(2));
2226 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2227 const ARMSubtarget *Subtarget) {
2228 DebugLoc dl = Op.getDebugLoc();
2229 if (!Subtarget->hasDataBarrier()) {
2230 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2231 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2233 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2234 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2235 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2236 DAG.getConstant(0, MVT::i32));
2239 SDValue Op5 = Op.getOperand(5);
2240 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2241 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2242 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2243 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2245 ARM_MB::MemBOpt DMBOpt;
2246 if (isDeviceBarrier)
2247 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2249 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2250 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2251 DAG.getConstant(DMBOpt, MVT::i32));
2254 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2255 const ARMSubtarget *Subtarget) {
2256 // ARM pre v5TE and Thumb1 does not have preload instructions.
2257 if (!(Subtarget->isThumb2() ||
2258 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2259 // Just preserve the chain.
2260 return Op.getOperand(0);
2262 DebugLoc dl = Op.getDebugLoc();
2263 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2265 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2266 // ARMv7 with MP extension has PLDW.
2267 return Op.getOperand(0);
2269 if (Subtarget->isThumb())
2271 isRead = ~isRead & 1;
2272 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2274 // Currently there is no intrinsic that matches pli.
2275 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2276 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2277 DAG.getConstant(isData, MVT::i32));
2280 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2281 MachineFunction &MF = DAG.getMachineFunction();
2282 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2284 // vastart just stores the address of the VarArgsFrameIndex slot into the
2285 // memory location argument.
2286 DebugLoc dl = Op.getDebugLoc();
2287 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2288 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2289 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2290 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2291 MachinePointerInfo(SV), false, false, 0);
2295 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2296 SDValue &Root, SelectionDAG &DAG,
2297 DebugLoc dl) const {
2298 MachineFunction &MF = DAG.getMachineFunction();
2299 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2301 TargetRegisterClass *RC;
2302 if (AFI->isThumb1OnlyFunction())
2303 RC = ARM::tGPRRegisterClass;
2305 RC = ARM::GPRRegisterClass;
2307 // Transform the arguments stored in physical registers into virtual ones.
2308 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2309 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2312 if (NextVA.isMemLoc()) {
2313 MachineFrameInfo *MFI = MF.getFrameInfo();
2314 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2316 // Create load node to retrieve arguments from the stack.
2317 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2318 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2319 MachinePointerInfo::getFixedStack(FI),
2322 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2323 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2326 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2330 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2331 unsigned &VARegSize, unsigned &VARegSaveSize)
2334 if (CCInfo.isFirstByValRegValid())
2335 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2337 unsigned int firstUnalloced;
2338 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2339 sizeof(GPRArgRegs) /
2340 sizeof(GPRArgRegs[0]));
2341 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2344 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2345 VARegSize = NumGPRs * 4;
2346 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2349 // The remaining GPRs hold either the beginning of variable-argument
2350 // data, or the beginning of an aggregate passed by value (usuall
2351 // byval). Either way, we allocate stack slots adjacent to the data
2352 // provided by our caller, and store the unallocated registers there.
2353 // If this is a variadic function, the va_list pointer will begin with
2354 // these values; otherwise, this reassembles a (byval) structure that
2355 // was split between registers and memory.
2357 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2358 DebugLoc dl, SDValue &Chain,
2359 unsigned ArgOffset) const {
2360 MachineFunction &MF = DAG.getMachineFunction();
2361 MachineFrameInfo *MFI = MF.getFrameInfo();
2362 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2363 unsigned firstRegToSaveIndex;
2364 if (CCInfo.isFirstByValRegValid())
2365 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2367 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2368 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2371 unsigned VARegSize, VARegSaveSize;
2372 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2373 if (VARegSaveSize) {
2374 // If this function is vararg, store any remaining integer argument regs
2375 // to their spots on the stack so that they may be loaded by deferencing
2376 // the result of va_next.
2377 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2378 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2379 ArgOffset + VARegSaveSize
2382 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2385 SmallVector<SDValue, 4> MemOps;
2386 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
2387 TargetRegisterClass *RC;
2388 if (AFI->isThumb1OnlyFunction())
2389 RC = ARM::tGPRRegisterClass;
2391 RC = ARM::GPRRegisterClass;
2393 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2394 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2396 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2397 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2399 MemOps.push_back(Store);
2400 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2401 DAG.getConstant(4, getPointerTy()));
2403 if (!MemOps.empty())
2404 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2405 &MemOps[0], MemOps.size());
2407 // This will point to the next argument passed via stack.
2408 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2412 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2413 CallingConv::ID CallConv, bool isVarArg,
2414 const SmallVectorImpl<ISD::InputArg>
2416 DebugLoc dl, SelectionDAG &DAG,
2417 SmallVectorImpl<SDValue> &InVals)
2419 MachineFunction &MF = DAG.getMachineFunction();
2420 MachineFrameInfo *MFI = MF.getFrameInfo();
2422 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2424 // Assign locations to all of the incoming arguments.
2425 SmallVector<CCValAssign, 16> ArgLocs;
2426 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2428 CCInfo.setCallOrPrologue(Prologue);
2429 CCInfo.AnalyzeFormalArguments(Ins,
2430 CCAssignFnForNode(CallConv, /* Return*/ false,
2433 SmallVector<SDValue, 16> ArgValues;
2434 int lastInsIndex = -1;
2437 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2438 CCValAssign &VA = ArgLocs[i];
2440 // Arguments stored in registers.
2441 if (VA.isRegLoc()) {
2442 EVT RegVT = VA.getLocVT();
2444 if (VA.needsCustom()) {
2445 // f64 and vector types are split up into multiple registers or
2446 // combinations of registers and stack slots.
2447 if (VA.getLocVT() == MVT::v2f64) {
2448 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2450 VA = ArgLocs[++i]; // skip ahead to next loc
2452 if (VA.isMemLoc()) {
2453 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2454 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2455 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2456 MachinePointerInfo::getFixedStack(FI),
2459 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2462 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2463 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2464 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2465 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2466 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2468 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2471 TargetRegisterClass *RC;
2473 if (RegVT == MVT::f32)
2474 RC = ARM::SPRRegisterClass;
2475 else if (RegVT == MVT::f64)
2476 RC = ARM::DPRRegisterClass;
2477 else if (RegVT == MVT::v2f64)
2478 RC = ARM::QPRRegisterClass;
2479 else if (RegVT == MVT::i32)
2480 RC = (AFI->isThumb1OnlyFunction() ?
2481 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2483 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2485 // Transform the arguments in physical registers into virtual ones.
2486 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2487 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2490 // If this is an 8 or 16-bit value, it is really passed promoted
2491 // to 32 bits. Insert an assert[sz]ext to capture this, then
2492 // truncate to the right size.
2493 switch (VA.getLocInfo()) {
2494 default: llvm_unreachable("Unknown loc info!");
2495 case CCValAssign::Full: break;
2496 case CCValAssign::BCvt:
2497 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2499 case CCValAssign::SExt:
2500 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2501 DAG.getValueType(VA.getValVT()));
2502 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2504 case CCValAssign::ZExt:
2505 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2506 DAG.getValueType(VA.getValVT()));
2507 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2511 InVals.push_back(ArgValue);
2513 } else { // VA.isRegLoc()
2516 assert(VA.isMemLoc());
2517 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2519 int index = ArgLocs[i].getValNo();
2521 // Some Ins[] entries become multiple ArgLoc[] entries.
2522 // Process them only once.
2523 if (index != lastInsIndex)
2525 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2526 // FIXME: For now, all byval parameter objects are marked mutable.
2527 // This can be changed with more analysis.
2528 // In case of tail call optimization mark all arguments mutable.
2529 // Since they could be overwritten by lowering of arguments in case of
2531 if (Flags.isByVal()) {
2532 unsigned VARegSize, VARegSaveSize;
2533 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2534 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0);
2535 unsigned Bytes = Flags.getByValSize() - VARegSize;
2536 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2537 int FI = MFI->CreateFixedObject(Bytes,
2538 VA.getLocMemOffset(), false);
2539 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2541 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2542 VA.getLocMemOffset(), true);
2544 // Create load nodes to retrieve arguments from the stack.
2545 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2546 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2547 MachinePointerInfo::getFixedStack(FI),
2550 lastInsIndex = index;
2557 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset());
2562 /// isFloatingPointZero - Return true if this is +0.0.
2563 static bool isFloatingPointZero(SDValue Op) {
2564 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2565 return CFP->getValueAPF().isPosZero();
2566 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2567 // Maybe this has already been legalized into the constant pool?
2568 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2569 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2570 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2571 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2572 return CFP->getValueAPF().isPosZero();
2578 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2579 /// the given operands.
2581 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2582 SDValue &ARMcc, SelectionDAG &DAG,
2583 DebugLoc dl) const {
2584 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2585 unsigned C = RHSC->getZExtValue();
2586 if (!isLegalICmpImmediate(C)) {
2587 // Constant does not fit, try adjusting it by one?
2592 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2593 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2594 RHS = DAG.getConstant(C-1, MVT::i32);
2599 if (C != 0 && isLegalICmpImmediate(C-1)) {
2600 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2601 RHS = DAG.getConstant(C-1, MVT::i32);
2606 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2607 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2608 RHS = DAG.getConstant(C+1, MVT::i32);
2613 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2614 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2615 RHS = DAG.getConstant(C+1, MVT::i32);
2622 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2623 ARMISD::NodeType CompareType;
2626 CompareType = ARMISD::CMP;
2631 CompareType = ARMISD::CMPZ;
2634 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2635 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2638 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2640 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2641 DebugLoc dl) const {
2643 if (!isFloatingPointZero(RHS))
2644 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2646 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2647 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2650 /// duplicateCmp - Glue values can have only one use, so this function
2651 /// duplicates a comparison node.
2653 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2654 unsigned Opc = Cmp.getOpcode();
2655 DebugLoc DL = Cmp.getDebugLoc();
2656 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2657 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2659 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2660 Cmp = Cmp.getOperand(0);
2661 Opc = Cmp.getOpcode();
2662 if (Opc == ARMISD::CMPFP)
2663 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2665 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2666 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2668 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2671 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2672 SDValue Cond = Op.getOperand(0);
2673 SDValue SelectTrue = Op.getOperand(1);
2674 SDValue SelectFalse = Op.getOperand(2);
2675 DebugLoc dl = Op.getDebugLoc();
2679 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2680 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2682 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2683 const ConstantSDNode *CMOVTrue =
2684 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2685 const ConstantSDNode *CMOVFalse =
2686 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2688 if (CMOVTrue && CMOVFalse) {
2689 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2690 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2694 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2696 False = SelectFalse;
2697 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2702 if (True.getNode() && False.getNode()) {
2703 EVT VT = Op.getValueType();
2704 SDValue ARMcc = Cond.getOperand(2);
2705 SDValue CCR = Cond.getOperand(3);
2706 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2707 assert(True.getValueType() == VT);
2708 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2713 return DAG.getSelectCC(dl, Cond,
2714 DAG.getConstant(0, Cond.getValueType()),
2715 SelectTrue, SelectFalse, ISD::SETNE);
2718 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2719 EVT VT = Op.getValueType();
2720 SDValue LHS = Op.getOperand(0);
2721 SDValue RHS = Op.getOperand(1);
2722 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2723 SDValue TrueVal = Op.getOperand(2);
2724 SDValue FalseVal = Op.getOperand(3);
2725 DebugLoc dl = Op.getDebugLoc();
2727 if (LHS.getValueType() == MVT::i32) {
2729 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2730 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2731 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2734 ARMCC::CondCodes CondCode, CondCode2;
2735 FPCCToARMCC(CC, CondCode, CondCode2);
2737 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2738 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2739 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2740 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2742 if (CondCode2 != ARMCC::AL) {
2743 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2744 // FIXME: Needs another CMP because flag can have but one use.
2745 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2746 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2747 Result, TrueVal, ARMcc2, CCR, Cmp2);
2752 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2753 /// to morph to an integer compare sequence.
2754 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2755 const ARMSubtarget *Subtarget) {
2756 SDNode *N = Op.getNode();
2757 if (!N->hasOneUse())
2758 // Otherwise it requires moving the value from fp to integer registers.
2760 if (!N->getNumValues())
2762 EVT VT = Op.getValueType();
2763 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2764 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2765 // vmrs are very slow, e.g. cortex-a8.
2768 if (isFloatingPointZero(Op)) {
2772 return ISD::isNormalLoad(N);
2775 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2776 if (isFloatingPointZero(Op))
2777 return DAG.getConstant(0, MVT::i32);
2779 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2780 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2781 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2782 Ld->isVolatile(), Ld->isNonTemporal(),
2783 Ld->getAlignment());
2785 llvm_unreachable("Unknown VFP cmp argument!");
2788 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2789 SDValue &RetVal1, SDValue &RetVal2) {
2790 if (isFloatingPointZero(Op)) {
2791 RetVal1 = DAG.getConstant(0, MVT::i32);
2792 RetVal2 = DAG.getConstant(0, MVT::i32);
2796 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2797 SDValue Ptr = Ld->getBasePtr();
2798 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2799 Ld->getChain(), Ptr,
2800 Ld->getPointerInfo(),
2801 Ld->isVolatile(), Ld->isNonTemporal(),
2802 Ld->getAlignment());
2804 EVT PtrType = Ptr.getValueType();
2805 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2806 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2807 PtrType, Ptr, DAG.getConstant(4, PtrType));
2808 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2809 Ld->getChain(), NewPtr,
2810 Ld->getPointerInfo().getWithOffset(4),
2811 Ld->isVolatile(), Ld->isNonTemporal(),
2816 llvm_unreachable("Unknown VFP cmp argument!");
2819 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2820 /// f32 and even f64 comparisons to integer ones.
2822 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2823 SDValue Chain = Op.getOperand(0);
2824 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2825 SDValue LHS = Op.getOperand(2);
2826 SDValue RHS = Op.getOperand(3);
2827 SDValue Dest = Op.getOperand(4);
2828 DebugLoc dl = Op.getDebugLoc();
2830 bool SeenZero = false;
2831 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2832 canChangeToInt(RHS, SeenZero, Subtarget) &&
2833 // If one of the operand is zero, it's safe to ignore the NaN case since
2834 // we only care about equality comparisons.
2835 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2836 // If unsafe fp math optimization is enabled and there are no other uses of
2837 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2838 // to an integer comparison.
2839 if (CC == ISD::SETOEQ)
2841 else if (CC == ISD::SETUNE)
2845 if (LHS.getValueType() == MVT::f32) {
2846 LHS = bitcastf32Toi32(LHS, DAG);
2847 RHS = bitcastf32Toi32(RHS, DAG);
2848 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2849 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2850 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2851 Chain, Dest, ARMcc, CCR, Cmp);
2856 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2857 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2858 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2859 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2860 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2861 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2862 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2868 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2869 SDValue Chain = Op.getOperand(0);
2870 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2871 SDValue LHS = Op.getOperand(2);
2872 SDValue RHS = Op.getOperand(3);
2873 SDValue Dest = Op.getOperand(4);
2874 DebugLoc dl = Op.getDebugLoc();
2876 if (LHS.getValueType() == MVT::i32) {
2878 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2879 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2880 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2881 Chain, Dest, ARMcc, CCR, Cmp);
2884 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2887 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2888 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2889 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2890 if (Result.getNode())
2894 ARMCC::CondCodes CondCode, CondCode2;
2895 FPCCToARMCC(CC, CondCode, CondCode2);
2897 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2898 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2899 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2900 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2901 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2902 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2903 if (CondCode2 != ARMCC::AL) {
2904 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2905 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2906 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2911 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2912 SDValue Chain = Op.getOperand(0);
2913 SDValue Table = Op.getOperand(1);
2914 SDValue Index = Op.getOperand(2);
2915 DebugLoc dl = Op.getDebugLoc();
2917 EVT PTy = getPointerTy();
2918 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2919 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2920 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2921 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2922 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2923 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2924 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2925 if (Subtarget->isThumb2()) {
2926 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2927 // which does another jump to the destination. This also makes it easier
2928 // to translate it to TBB / TBH later.
2929 // FIXME: This might not work if the function is extremely large.
2930 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2931 Addr, Op.getOperand(2), JTI, UId);
2933 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2934 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2935 MachinePointerInfo::getJumpTable(),
2937 Chain = Addr.getValue(1);
2938 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2939 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2941 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2942 MachinePointerInfo::getJumpTable(), false, false, 0);
2943 Chain = Addr.getValue(1);
2944 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2948 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2949 DebugLoc dl = Op.getDebugLoc();
2952 switch (Op.getOpcode()) {
2954 assert(0 && "Invalid opcode!");
2955 case ISD::FP_TO_SINT:
2956 Opc = ARMISD::FTOSI;
2958 case ISD::FP_TO_UINT:
2959 Opc = ARMISD::FTOUI;
2962 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2963 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2966 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2967 EVT VT = Op.getValueType();
2968 DebugLoc dl = Op.getDebugLoc();
2970 EVT OperandVT = Op.getOperand(0).getValueType();
2971 assert(OperandVT == MVT::v4i16 && "Invalid type for custom lowering!");
2972 if (VT != MVT::v4f32)
2973 return DAG.UnrollVectorOp(Op.getNode());
2977 switch (Op.getOpcode()) {
2979 assert(0 && "Invalid opcode!");
2980 case ISD::SINT_TO_FP:
2981 CastOpc = ISD::SIGN_EXTEND;
2982 Opc = ISD::SINT_TO_FP;
2984 case ISD::UINT_TO_FP:
2985 CastOpc = ISD::ZERO_EXTEND;
2986 Opc = ISD::UINT_TO_FP;
2990 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
2991 return DAG.getNode(Opc, dl, VT, Op);
2994 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2995 EVT VT = Op.getValueType();
2997 return LowerVectorINT_TO_FP(Op, DAG);
2999 DebugLoc dl = Op.getDebugLoc();
3002 switch (Op.getOpcode()) {
3004 assert(0 && "Invalid opcode!");
3005 case ISD::SINT_TO_FP:
3006 Opc = ARMISD::SITOF;
3008 case ISD::UINT_TO_FP:
3009 Opc = ARMISD::UITOF;
3013 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3014 return DAG.getNode(Opc, dl, VT, Op);
3017 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3018 // Implement fcopysign with a fabs and a conditional fneg.
3019 SDValue Tmp0 = Op.getOperand(0);
3020 SDValue Tmp1 = Op.getOperand(1);
3021 DebugLoc dl = Op.getDebugLoc();
3022 EVT VT = Op.getValueType();
3023 EVT SrcVT = Tmp1.getValueType();
3024 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3025 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3026 bool UseNEON = !InGPR && Subtarget->hasNEON();
3029 // Use VBSL to copy the sign bit.
3030 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3031 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3032 DAG.getTargetConstant(EncodedVal, MVT::i32));
3033 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3035 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3036 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3037 DAG.getConstant(32, MVT::i32));
3038 else /*if (VT == MVT::f32)*/
3039 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3040 if (SrcVT == MVT::f32) {
3041 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3043 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3044 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3045 DAG.getConstant(32, MVT::i32));
3046 } else if (VT == MVT::f32)
3047 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3048 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3049 DAG.getConstant(32, MVT::i32));
3050 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3051 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3053 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3055 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3056 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3057 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3059 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3060 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3061 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3062 if (VT == MVT::f32) {
3063 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3064 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3065 DAG.getConstant(0, MVT::i32));
3067 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3073 // Bitcast operand 1 to i32.
3074 if (SrcVT == MVT::f64)
3075 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3076 &Tmp1, 1).getValue(1);
3077 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3079 // Or in the signbit with integer operations.
3080 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3081 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3082 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3083 if (VT == MVT::f32) {
3084 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3085 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3086 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3087 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3090 // f64: Or the high part with signbit and then combine two parts.
3091 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3093 SDValue Lo = Tmp0.getValue(0);
3094 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3095 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3096 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3099 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3100 MachineFunction &MF = DAG.getMachineFunction();
3101 MachineFrameInfo *MFI = MF.getFrameInfo();
3102 MFI->setReturnAddressIsTaken(true);
3104 EVT VT = Op.getValueType();
3105 DebugLoc dl = Op.getDebugLoc();
3106 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3108 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3109 SDValue Offset = DAG.getConstant(4, MVT::i32);
3110 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3111 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3112 MachinePointerInfo(), false, false, 0);
3115 // Return LR, which contains the return address. Mark it an implicit live-in.
3116 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3117 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3120 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3121 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3122 MFI->setFrameAddressIsTaken(true);
3124 EVT VT = Op.getValueType();
3125 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3126 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3127 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3128 ? ARM::R7 : ARM::R11;
3129 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3131 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3132 MachinePointerInfo(),
3137 /// ExpandBITCAST - If the target supports VFP, this function is called to
3138 /// expand a bit convert where either the source or destination type is i64 to
3139 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3140 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3141 /// vectors), since the legalizer won't know what to do with that.
3142 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3143 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3144 DebugLoc dl = N->getDebugLoc();
3145 SDValue Op = N->getOperand(0);
3147 // This function is only supposed to be called for i64 types, either as the
3148 // source or destination of the bit convert.
3149 EVT SrcVT = Op.getValueType();
3150 EVT DstVT = N->getValueType(0);
3151 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3152 "ExpandBITCAST called for non-i64 type");
3154 // Turn i64->f64 into VMOVDRR.
3155 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3156 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3157 DAG.getConstant(0, MVT::i32));
3158 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3159 DAG.getConstant(1, MVT::i32));
3160 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3161 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3164 // Turn f64->i64 into VMOVRRD.
3165 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3166 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3167 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3168 // Merge the pieces into a single i64 value.
3169 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3175 /// getZeroVector - Returns a vector of specified type with all zero elements.
3176 /// Zero vectors are used to represent vector negation and in those cases
3177 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3178 /// not support i64 elements, so sometimes the zero vectors will need to be
3179 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3181 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3182 assert(VT.isVector() && "Expected a vector type");
3183 // The canonical modified immediate encoding of a zero vector is....0!
3184 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3185 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3186 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3187 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3190 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3191 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3192 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3193 SelectionDAG &DAG) const {
3194 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3195 EVT VT = Op.getValueType();
3196 unsigned VTBits = VT.getSizeInBits();
3197 DebugLoc dl = Op.getDebugLoc();
3198 SDValue ShOpLo = Op.getOperand(0);
3199 SDValue ShOpHi = Op.getOperand(1);
3200 SDValue ShAmt = Op.getOperand(2);
3202 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3204 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3206 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3207 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3208 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3209 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3210 DAG.getConstant(VTBits, MVT::i32));
3211 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3212 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3213 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3215 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3216 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3218 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3219 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3222 SDValue Ops[2] = { Lo, Hi };
3223 return DAG.getMergeValues(Ops, 2, dl);
3226 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3227 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3228 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3229 SelectionDAG &DAG) const {
3230 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3231 EVT VT = Op.getValueType();
3232 unsigned VTBits = VT.getSizeInBits();
3233 DebugLoc dl = Op.getDebugLoc();
3234 SDValue ShOpLo = Op.getOperand(0);
3235 SDValue ShOpHi = Op.getOperand(1);
3236 SDValue ShAmt = Op.getOperand(2);
3239 assert(Op.getOpcode() == ISD::SHL_PARTS);
3240 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3241 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3242 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3243 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3244 DAG.getConstant(VTBits, MVT::i32));
3245 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3246 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3248 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3249 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3250 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3252 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3253 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3256 SDValue Ops[2] = { Lo, Hi };
3257 return DAG.getMergeValues(Ops, 2, dl);
3260 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3261 SelectionDAG &DAG) const {
3262 // The rounding mode is in bits 23:22 of the FPSCR.
3263 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3264 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3265 // so that the shift + and get folded into a bitfield extract.
3266 DebugLoc dl = Op.getDebugLoc();
3267 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3268 DAG.getConstant(Intrinsic::arm_get_fpscr,
3270 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3271 DAG.getConstant(1U << 22, MVT::i32));
3272 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3273 DAG.getConstant(22, MVT::i32));
3274 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3275 DAG.getConstant(3, MVT::i32));
3278 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3279 const ARMSubtarget *ST) {
3280 EVT VT = N->getValueType(0);
3281 DebugLoc dl = N->getDebugLoc();
3283 if (!ST->hasV6T2Ops())
3286 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3287 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3290 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3291 const ARMSubtarget *ST) {
3292 EVT VT = N->getValueType(0);
3293 DebugLoc dl = N->getDebugLoc();
3298 // Lower vector shifts on NEON to use VSHL.
3299 assert(ST->hasNEON() && "unexpected vector shift");
3301 // Left shifts translate directly to the vshiftu intrinsic.
3302 if (N->getOpcode() == ISD::SHL)
3303 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3304 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3305 N->getOperand(0), N->getOperand(1));
3307 assert((N->getOpcode() == ISD::SRA ||
3308 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3310 // NEON uses the same intrinsics for both left and right shifts. For
3311 // right shifts, the shift amounts are negative, so negate the vector of
3313 EVT ShiftVT = N->getOperand(1).getValueType();
3314 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3315 getZeroVector(ShiftVT, DAG, dl),
3317 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3318 Intrinsic::arm_neon_vshifts :
3319 Intrinsic::arm_neon_vshiftu);
3320 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3321 DAG.getConstant(vshiftInt, MVT::i32),
3322 N->getOperand(0), NegatedCount);
3325 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3326 const ARMSubtarget *ST) {
3327 EVT VT = N->getValueType(0);
3328 DebugLoc dl = N->getDebugLoc();
3330 // We can get here for a node like i32 = ISD::SHL i32, i64
3334 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3335 "Unknown shift to lower!");
3337 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3338 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3339 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3342 // If we are in thumb mode, we don't have RRX.
3343 if (ST->isThumb1Only()) return SDValue();
3345 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3346 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3347 DAG.getConstant(0, MVT::i32));
3348 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3349 DAG.getConstant(1, MVT::i32));
3351 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3352 // captures the result into a carry flag.
3353 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3354 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3356 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3357 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3359 // Merge the pieces into a single i64 value.
3360 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3363 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3364 SDValue TmpOp0, TmpOp1;
3365 bool Invert = false;
3369 SDValue Op0 = Op.getOperand(0);
3370 SDValue Op1 = Op.getOperand(1);
3371 SDValue CC = Op.getOperand(2);
3372 EVT VT = Op.getValueType();
3373 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3374 DebugLoc dl = Op.getDebugLoc();
3376 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3377 switch (SetCCOpcode) {
3378 default: llvm_unreachable("Illegal FP comparison"); break;
3380 case ISD::SETNE: Invert = true; // Fallthrough
3382 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3384 case ISD::SETLT: Swap = true; // Fallthrough
3386 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3388 case ISD::SETLE: Swap = true; // Fallthrough
3390 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3391 case ISD::SETUGE: Swap = true; // Fallthrough
3392 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3393 case ISD::SETUGT: Swap = true; // Fallthrough
3394 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3395 case ISD::SETUEQ: Invert = true; // Fallthrough
3397 // Expand this to (OLT | OGT).
3401 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3402 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3404 case ISD::SETUO: Invert = true; // Fallthrough
3406 // Expand this to (OLT | OGE).
3410 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3411 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3415 // Integer comparisons.
3416 switch (SetCCOpcode) {
3417 default: llvm_unreachable("Illegal integer comparison"); break;
3418 case ISD::SETNE: Invert = true;
3419 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3420 case ISD::SETLT: Swap = true;
3421 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3422 case ISD::SETLE: Swap = true;
3423 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3424 case ISD::SETULT: Swap = true;
3425 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3426 case ISD::SETULE: Swap = true;
3427 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3430 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3431 if (Opc == ARMISD::VCEQ) {
3434 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3436 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3439 // Ignore bitconvert.
3440 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3441 AndOp = AndOp.getOperand(0);
3443 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3445 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3446 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3453 std::swap(Op0, Op1);
3455 // If one of the operands is a constant vector zero, attempt to fold the
3456 // comparison to a specialized compare-against-zero form.
3458 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3460 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3461 if (Opc == ARMISD::VCGE)
3462 Opc = ARMISD::VCLEZ;
3463 else if (Opc == ARMISD::VCGT)
3464 Opc = ARMISD::VCLTZ;
3469 if (SingleOp.getNode()) {
3472 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3474 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3476 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3478 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3480 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3482 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3485 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3489 Result = DAG.getNOT(dl, Result, VT);
3494 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3495 /// valid vector constant for a NEON instruction with a "modified immediate"
3496 /// operand (e.g., VMOV). If so, return the encoded value.
3497 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3498 unsigned SplatBitSize, SelectionDAG &DAG,
3499 EVT &VT, bool is128Bits, NEONModImmType type) {
3500 unsigned OpCmode, Imm;
3502 // SplatBitSize is set to the smallest size that splats the vector, so a
3503 // zero vector will always have SplatBitSize == 8. However, NEON modified
3504 // immediate instructions others than VMOV do not support the 8-bit encoding
3505 // of a zero vector, and the default encoding of zero is supposed to be the
3510 switch (SplatBitSize) {
3512 if (type != VMOVModImm)
3514 // Any 1-byte value is OK. Op=0, Cmode=1110.
3515 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3518 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3522 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3523 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3524 if ((SplatBits & ~0xff) == 0) {
3525 // Value = 0x00nn: Op=x, Cmode=100x.
3530 if ((SplatBits & ~0xff00) == 0) {
3531 // Value = 0xnn00: Op=x, Cmode=101x.
3533 Imm = SplatBits >> 8;
3539 // NEON's 32-bit VMOV supports splat values where:
3540 // * only one byte is nonzero, or
3541 // * the least significant byte is 0xff and the second byte is nonzero, or
3542 // * the least significant 2 bytes are 0xff and the third is nonzero.
3543 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3544 if ((SplatBits & ~0xff) == 0) {
3545 // Value = 0x000000nn: Op=x, Cmode=000x.
3550 if ((SplatBits & ~0xff00) == 0) {
3551 // Value = 0x0000nn00: Op=x, Cmode=001x.
3553 Imm = SplatBits >> 8;
3556 if ((SplatBits & ~0xff0000) == 0) {
3557 // Value = 0x00nn0000: Op=x, Cmode=010x.
3559 Imm = SplatBits >> 16;
3562 if ((SplatBits & ~0xff000000) == 0) {
3563 // Value = 0xnn000000: Op=x, Cmode=011x.
3565 Imm = SplatBits >> 24;
3569 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3570 if (type == OtherModImm) return SDValue();
3572 if ((SplatBits & ~0xffff) == 0 &&
3573 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3574 // Value = 0x0000nnff: Op=x, Cmode=1100.
3576 Imm = SplatBits >> 8;
3581 if ((SplatBits & ~0xffffff) == 0 &&
3582 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3583 // Value = 0x00nnffff: Op=x, Cmode=1101.
3585 Imm = SplatBits >> 16;
3586 SplatBits |= 0xffff;
3590 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3591 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3592 // VMOV.I32. A (very) minor optimization would be to replicate the value
3593 // and fall through here to test for a valid 64-bit splat. But, then the
3594 // caller would also need to check and handle the change in size.
3598 if (type != VMOVModImm)
3600 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3601 uint64_t BitMask = 0xff;
3603 unsigned ImmMask = 1;
3605 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3606 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3609 } else if ((SplatBits & BitMask) != 0) {
3615 // Op=1, Cmode=1110.
3618 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3623 llvm_unreachable("unexpected size for isNEONModifiedImm");
3627 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3628 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3631 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3632 bool &ReverseVEXT, unsigned &Imm) {
3633 unsigned NumElts = VT.getVectorNumElements();
3634 ReverseVEXT = false;
3636 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3642 // If this is a VEXT shuffle, the immediate value is the index of the first
3643 // element. The other shuffle indices must be the successive elements after
3645 unsigned ExpectedElt = Imm;
3646 for (unsigned i = 1; i < NumElts; ++i) {
3647 // Increment the expected index. If it wraps around, it may still be
3648 // a VEXT but the source vectors must be swapped.
3650 if (ExpectedElt == NumElts * 2) {
3655 if (M[i] < 0) continue; // ignore UNDEF indices
3656 if (ExpectedElt != static_cast<unsigned>(M[i]))
3660 // Adjust the index value if the source operands will be swapped.
3667 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3668 /// instruction with the specified blocksize. (The order of the elements
3669 /// within each block of the vector is reversed.)
3670 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3671 unsigned BlockSize) {
3672 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3673 "Only possible block sizes for VREV are: 16, 32, 64");
3675 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3679 unsigned NumElts = VT.getVectorNumElements();
3680 unsigned BlockElts = M[0] + 1;
3681 // If the first shuffle index is UNDEF, be optimistic.
3683 BlockElts = BlockSize / EltSz;
3685 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3688 for (unsigned i = 0; i < NumElts; ++i) {
3689 if (M[i] < 0) continue; // ignore UNDEF indices
3690 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3697 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3698 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3699 // range, then 0 is placed into the resulting vector. So pretty much any mask
3700 // of 8 elements can work here.
3701 return VT == MVT::v8i8 && M.size() == 8;
3704 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3705 unsigned &WhichResult) {
3706 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3710 unsigned NumElts = VT.getVectorNumElements();
3711 WhichResult = (M[0] == 0 ? 0 : 1);
3712 for (unsigned i = 0; i < NumElts; i += 2) {
3713 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3714 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3720 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3721 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3722 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3723 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3724 unsigned &WhichResult) {
3725 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3729 unsigned NumElts = VT.getVectorNumElements();
3730 WhichResult = (M[0] == 0 ? 0 : 1);
3731 for (unsigned i = 0; i < NumElts; i += 2) {
3732 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3733 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3739 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3740 unsigned &WhichResult) {
3741 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3745 unsigned NumElts = VT.getVectorNumElements();
3746 WhichResult = (M[0] == 0 ? 0 : 1);
3747 for (unsigned i = 0; i != NumElts; ++i) {
3748 if (M[i] < 0) continue; // ignore UNDEF indices
3749 if ((unsigned) M[i] != 2 * i + WhichResult)
3753 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3754 if (VT.is64BitVector() && EltSz == 32)
3760 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3761 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3762 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3763 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3764 unsigned &WhichResult) {
3765 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3769 unsigned Half = VT.getVectorNumElements() / 2;
3770 WhichResult = (M[0] == 0 ? 0 : 1);
3771 for (unsigned j = 0; j != 2; ++j) {
3772 unsigned Idx = WhichResult;
3773 for (unsigned i = 0; i != Half; ++i) {
3774 int MIdx = M[i + j * Half];
3775 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3781 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3782 if (VT.is64BitVector() && EltSz == 32)
3788 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3789 unsigned &WhichResult) {
3790 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3794 unsigned NumElts = VT.getVectorNumElements();
3795 WhichResult = (M[0] == 0 ? 0 : 1);
3796 unsigned Idx = WhichResult * NumElts / 2;
3797 for (unsigned i = 0; i != NumElts; i += 2) {
3798 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3799 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3804 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3805 if (VT.is64BitVector() && EltSz == 32)
3811 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3812 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3813 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3814 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3815 unsigned &WhichResult) {
3816 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3820 unsigned NumElts = VT.getVectorNumElements();
3821 WhichResult = (M[0] == 0 ? 0 : 1);
3822 unsigned Idx = WhichResult * NumElts / 2;
3823 for (unsigned i = 0; i != NumElts; i += 2) {
3824 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3825 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3830 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3831 if (VT.is64BitVector() && EltSz == 32)
3837 // If N is an integer constant that can be moved into a register in one
3838 // instruction, return an SDValue of such a constant (will become a MOV
3839 // instruction). Otherwise return null.
3840 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3841 const ARMSubtarget *ST, DebugLoc dl) {
3843 if (!isa<ConstantSDNode>(N))
3845 Val = cast<ConstantSDNode>(N)->getZExtValue();
3847 if (ST->isThumb1Only()) {
3848 if (Val <= 255 || ~Val <= 255)
3849 return DAG.getConstant(Val, MVT::i32);
3851 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3852 return DAG.getConstant(Val, MVT::i32);
3857 // If this is a case we can't handle, return null and let the default
3858 // expansion code take care of it.
3859 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3860 const ARMSubtarget *ST) const {
3861 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3862 DebugLoc dl = Op.getDebugLoc();
3863 EVT VT = Op.getValueType();
3865 APInt SplatBits, SplatUndef;
3866 unsigned SplatBitSize;
3868 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3869 if (SplatBitSize <= 64) {
3870 // Check if an immediate VMOV works.
3872 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3873 SplatUndef.getZExtValue(), SplatBitSize,
3874 DAG, VmovVT, VT.is128BitVector(),
3876 if (Val.getNode()) {
3877 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3878 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3881 // Try an immediate VMVN.
3882 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3883 ((1LL << SplatBitSize) - 1));
3884 Val = isNEONModifiedImm(NegatedImm,
3885 SplatUndef.getZExtValue(), SplatBitSize,
3886 DAG, VmovVT, VT.is128BitVector(),
3888 if (Val.getNode()) {
3889 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3890 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3895 // Scan through the operands to see if only one value is used.
3896 unsigned NumElts = VT.getVectorNumElements();
3897 bool isOnlyLowElement = true;
3898 bool usesOnlyOneValue = true;
3899 bool isConstant = true;
3901 for (unsigned i = 0; i < NumElts; ++i) {
3902 SDValue V = Op.getOperand(i);
3903 if (V.getOpcode() == ISD::UNDEF)
3906 isOnlyLowElement = false;
3907 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3910 if (!Value.getNode())
3912 else if (V != Value)
3913 usesOnlyOneValue = false;
3916 if (!Value.getNode())
3917 return DAG.getUNDEF(VT);
3919 if (isOnlyLowElement)
3920 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3922 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3924 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3925 // i32 and try again.
3926 if (usesOnlyOneValue && EltSize <= 32) {
3928 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3929 if (VT.getVectorElementType().isFloatingPoint()) {
3930 SmallVector<SDValue, 8> Ops;
3931 for (unsigned i = 0; i < NumElts; ++i)
3932 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3934 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3935 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3936 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3938 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3940 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3942 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3945 // If all elements are constants and the case above didn't get hit, fall back
3946 // to the default expansion, which will generate a load from the constant
3951 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
3953 SDValue shuffle = ReconstructShuffle(Op, DAG);
3954 if (shuffle != SDValue())
3958 // Vectors with 32- or 64-bit elements can be built by directly assigning
3959 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3960 // will be legalized.
3961 if (EltSize >= 32) {
3962 // Do the expansion with floating-point types, since that is what the VFP
3963 // registers are defined to use, and since i64 is not legal.
3964 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3965 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3966 SmallVector<SDValue, 8> Ops;
3967 for (unsigned i = 0; i < NumElts; ++i)
3968 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3969 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3970 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3976 // Gather data to see if the operation can be modelled as a
3977 // shuffle in combination with VEXTs.
3978 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
3979 SelectionDAG &DAG) const {
3980 DebugLoc dl = Op.getDebugLoc();
3981 EVT VT = Op.getValueType();
3982 unsigned NumElts = VT.getVectorNumElements();
3984 SmallVector<SDValue, 2> SourceVecs;
3985 SmallVector<unsigned, 2> MinElts;
3986 SmallVector<unsigned, 2> MaxElts;
3988 for (unsigned i = 0; i < NumElts; ++i) {
3989 SDValue V = Op.getOperand(i);
3990 if (V.getOpcode() == ISD::UNDEF)
3992 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
3993 // A shuffle can only come from building a vector from various
3994 // elements of other vectors.
3998 // Record this extraction against the appropriate vector if possible...
3999 SDValue SourceVec = V.getOperand(0);
4000 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4001 bool FoundSource = false;
4002 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4003 if (SourceVecs[j] == SourceVec) {
4004 if (MinElts[j] > EltNo)
4006 if (MaxElts[j] < EltNo)
4013 // Or record a new source if not...
4015 SourceVecs.push_back(SourceVec);
4016 MinElts.push_back(EltNo);
4017 MaxElts.push_back(EltNo);
4021 // Currently only do something sane when at most two source vectors
4023 if (SourceVecs.size() > 2)
4026 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4027 int VEXTOffsets[2] = {0, 0};
4029 // This loop extracts the usage patterns of the source vectors
4030 // and prepares appropriate SDValues for a shuffle if possible.
4031 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4032 if (SourceVecs[i].getValueType() == VT) {
4033 // No VEXT necessary
4034 ShuffleSrcs[i] = SourceVecs[i];
4037 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4038 // It probably isn't worth padding out a smaller vector just to
4039 // break it down again in a shuffle.
4043 // Since only 64-bit and 128-bit vectors are legal on ARM and
4044 // we've eliminated the other cases...
4045 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4046 "unexpected vector sizes in ReconstructShuffle");
4048 if (MaxElts[i] - MinElts[i] >= NumElts) {
4049 // Span too large for a VEXT to cope
4053 if (MinElts[i] >= NumElts) {
4054 // The extraction can just take the second half
4055 VEXTOffsets[i] = NumElts;
4056 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4058 DAG.getIntPtrConstant(NumElts));
4059 } else if (MaxElts[i] < NumElts) {
4060 // The extraction can just take the first half
4062 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4064 DAG.getIntPtrConstant(0));
4066 // An actual VEXT is needed
4067 VEXTOffsets[i] = MinElts[i];
4068 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4070 DAG.getIntPtrConstant(0));
4071 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4073 DAG.getIntPtrConstant(NumElts));
4074 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4075 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4079 SmallVector<int, 8> Mask;
4081 for (unsigned i = 0; i < NumElts; ++i) {
4082 SDValue Entry = Op.getOperand(i);
4083 if (Entry.getOpcode() == ISD::UNDEF) {
4088 SDValue ExtractVec = Entry.getOperand(0);
4089 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4090 .getOperand(1))->getSExtValue();
4091 if (ExtractVec == SourceVecs[0]) {
4092 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4094 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4098 // Final check before we try to produce nonsense...
4099 if (isShuffleMaskLegal(Mask, VT))
4100 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4106 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4107 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4108 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4109 /// are assumed to be legal.
4111 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4113 if (VT.getVectorNumElements() == 4 &&
4114 (VT.is128BitVector() || VT.is64BitVector())) {
4115 unsigned PFIndexes[4];
4116 for (unsigned i = 0; i != 4; ++i) {
4120 PFIndexes[i] = M[i];
4123 // Compute the index in the perfect shuffle table.
4124 unsigned PFTableIndex =
4125 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4126 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4127 unsigned Cost = (PFEntry >> 30);
4134 unsigned Imm, WhichResult;
4136 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4137 return (EltSize >= 32 ||
4138 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4139 isVREVMask(M, VT, 64) ||
4140 isVREVMask(M, VT, 32) ||
4141 isVREVMask(M, VT, 16) ||
4142 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4143 isVTBLMask(M, VT) ||
4144 isVTRNMask(M, VT, WhichResult) ||
4145 isVUZPMask(M, VT, WhichResult) ||
4146 isVZIPMask(M, VT, WhichResult) ||
4147 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4148 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4149 isVZIP_v_undef_Mask(M, VT, WhichResult));
4152 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4153 /// the specified operations to build the shuffle.
4154 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4155 SDValue RHS, SelectionDAG &DAG,
4157 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4158 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4159 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4162 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4171 OP_VUZPL, // VUZP, left result
4172 OP_VUZPR, // VUZP, right result
4173 OP_VZIPL, // VZIP, left result
4174 OP_VZIPR, // VZIP, right result
4175 OP_VTRNL, // VTRN, left result
4176 OP_VTRNR // VTRN, right result
4179 if (OpNum == OP_COPY) {
4180 if (LHSID == (1*9+2)*9+3) return LHS;
4181 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4185 SDValue OpLHS, OpRHS;
4186 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4187 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4188 EVT VT = OpLHS.getValueType();
4191 default: llvm_unreachable("Unknown shuffle opcode!");
4193 // VREV divides the vector in half and swaps within the half.
4194 if (VT.getVectorElementType() == MVT::i32 ||
4195 VT.getVectorElementType() == MVT::f32)
4196 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4197 // vrev <4 x i16> -> VREV32
4198 if (VT.getVectorElementType() == MVT::i16)
4199 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4200 // vrev <4 x i8> -> VREV16
4201 assert(VT.getVectorElementType() == MVT::i8);
4202 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4207 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4208 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4212 return DAG.getNode(ARMISD::VEXT, dl, VT,
4214 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4217 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4218 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4221 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4222 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4225 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4226 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4230 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4231 SmallVectorImpl<int> &ShuffleMask,
4232 SelectionDAG &DAG) {
4233 // Check to see if we can use the VTBL instruction.
4234 SDValue V1 = Op.getOperand(0);
4235 SDValue V2 = Op.getOperand(1);
4236 DebugLoc DL = Op.getDebugLoc();
4238 SmallVector<SDValue, 8> VTBLMask;
4239 for (SmallVectorImpl<int>::iterator
4240 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4241 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4243 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4244 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4245 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4248 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4249 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4253 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4254 SDValue V1 = Op.getOperand(0);
4255 SDValue V2 = Op.getOperand(1);
4256 DebugLoc dl = Op.getDebugLoc();
4257 EVT VT = Op.getValueType();
4258 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4259 SmallVector<int, 8> ShuffleMask;
4261 // Convert shuffles that are directly supported on NEON to target-specific
4262 // DAG nodes, instead of keeping them as shuffles and matching them again
4263 // during code selection. This is more efficient and avoids the possibility
4264 // of inconsistencies between legalization and selection.
4265 // FIXME: floating-point vectors should be canonicalized to integer vectors
4266 // of the same time so that they get CSEd properly.
4267 SVN->getMask(ShuffleMask);
4269 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4270 if (EltSize <= 32) {
4271 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4272 int Lane = SVN->getSplatIndex();
4273 // If this is undef splat, generate it via "just" vdup, if possible.
4274 if (Lane == -1) Lane = 0;
4276 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4277 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4279 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4280 DAG.getConstant(Lane, MVT::i32));
4285 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4288 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4289 DAG.getConstant(Imm, MVT::i32));
4292 if (isVREVMask(ShuffleMask, VT, 64))
4293 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4294 if (isVREVMask(ShuffleMask, VT, 32))
4295 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4296 if (isVREVMask(ShuffleMask, VT, 16))
4297 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4299 // Check for Neon shuffles that modify both input vectors in place.
4300 // If both results are used, i.e., if there are two shuffles with the same
4301 // source operands and with masks corresponding to both results of one of
4302 // these operations, DAG memoization will ensure that a single node is
4303 // used for both shuffles.
4304 unsigned WhichResult;
4305 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4306 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4307 V1, V2).getValue(WhichResult);
4308 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4309 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4310 V1, V2).getValue(WhichResult);
4311 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4312 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4313 V1, V2).getValue(WhichResult);
4315 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4316 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4317 V1, V1).getValue(WhichResult);
4318 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4319 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4320 V1, V1).getValue(WhichResult);
4321 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4322 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4323 V1, V1).getValue(WhichResult);
4326 // If the shuffle is not directly supported and it has 4 elements, use
4327 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4328 unsigned NumElts = VT.getVectorNumElements();
4330 unsigned PFIndexes[4];
4331 for (unsigned i = 0; i != 4; ++i) {
4332 if (ShuffleMask[i] < 0)
4335 PFIndexes[i] = ShuffleMask[i];
4338 // Compute the index in the perfect shuffle table.
4339 unsigned PFTableIndex =
4340 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4341 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4342 unsigned Cost = (PFEntry >> 30);
4345 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4348 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4349 if (EltSize >= 32) {
4350 // Do the expansion with floating-point types, since that is what the VFP
4351 // registers are defined to use, and since i64 is not legal.
4352 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4353 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4354 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4355 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4356 SmallVector<SDValue, 8> Ops;
4357 for (unsigned i = 0; i < NumElts; ++i) {
4358 if (ShuffleMask[i] < 0)
4359 Ops.push_back(DAG.getUNDEF(EltVT));
4361 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4362 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4363 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4366 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4367 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4370 if (VT == MVT::v8i8) {
4371 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4372 if (NewOp.getNode())
4379 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4380 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4381 SDValue Lane = Op.getOperand(1);
4382 if (!isa<ConstantSDNode>(Lane))
4385 SDValue Vec = Op.getOperand(0);
4386 if (Op.getValueType() == MVT::i32 &&
4387 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4388 DebugLoc dl = Op.getDebugLoc();
4389 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4395 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4396 // The only time a CONCAT_VECTORS operation can have legal types is when
4397 // two 64-bit vectors are concatenated to a 128-bit vector.
4398 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4399 "unexpected CONCAT_VECTORS");
4400 DebugLoc dl = Op.getDebugLoc();
4401 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4402 SDValue Op0 = Op.getOperand(0);
4403 SDValue Op1 = Op.getOperand(1);
4404 if (Op0.getOpcode() != ISD::UNDEF)
4405 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4406 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4407 DAG.getIntPtrConstant(0));
4408 if (Op1.getOpcode() != ISD::UNDEF)
4409 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4410 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4411 DAG.getIntPtrConstant(1));
4412 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4415 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4416 /// element has been zero/sign-extended, depending on the isSigned parameter,
4417 /// from an integer type half its size.
4418 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4420 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4421 EVT VT = N->getValueType(0);
4422 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4423 SDNode *BVN = N->getOperand(0).getNode();
4424 if (BVN->getValueType(0) != MVT::v4i32 ||
4425 BVN->getOpcode() != ISD::BUILD_VECTOR)
4427 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4428 unsigned HiElt = 1 - LoElt;
4429 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4430 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4431 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4432 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4433 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4436 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4437 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4440 if (Hi0->isNullValue() && Hi1->isNullValue())
4446 if (N->getOpcode() != ISD::BUILD_VECTOR)
4449 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4450 SDNode *Elt = N->getOperand(i).getNode();
4451 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4452 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4453 unsigned HalfSize = EltSize / 2;
4455 int64_t SExtVal = C->getSExtValue();
4456 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4459 if ((C->getZExtValue() >> HalfSize) != 0)
4470 /// isSignExtended - Check if a node is a vector value that is sign-extended
4471 /// or a constant BUILD_VECTOR with sign-extended elements.
4472 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4473 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4475 if (isExtendedBUILD_VECTOR(N, DAG, true))
4480 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4481 /// or a constant BUILD_VECTOR with zero-extended elements.
4482 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4483 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4485 if (isExtendedBUILD_VECTOR(N, DAG, false))
4490 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4491 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4492 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4493 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4494 return N->getOperand(0);
4495 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4496 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4497 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4498 LD->isNonTemporal(), LD->getAlignment());
4499 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4500 // have been legalized as a BITCAST from v4i32.
4501 if (N->getOpcode() == ISD::BITCAST) {
4502 SDNode *BVN = N->getOperand(0).getNode();
4503 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4504 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4505 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4506 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4507 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4509 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4510 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4511 EVT VT = N->getValueType(0);
4512 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4513 unsigned NumElts = VT.getVectorNumElements();
4514 MVT TruncVT = MVT::getIntegerVT(EltSize);
4515 SmallVector<SDValue, 8> Ops;
4516 for (unsigned i = 0; i != NumElts; ++i) {
4517 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4518 const APInt &CInt = C->getAPIntValue();
4519 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4521 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4522 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4525 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4526 unsigned Opcode = N->getOpcode();
4527 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4528 SDNode *N0 = N->getOperand(0).getNode();
4529 SDNode *N1 = N->getOperand(1).getNode();
4530 return N0->hasOneUse() && N1->hasOneUse() &&
4531 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4536 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4537 unsigned Opcode = N->getOpcode();
4538 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4539 SDNode *N0 = N->getOperand(0).getNode();
4540 SDNode *N1 = N->getOperand(1).getNode();
4541 return N0->hasOneUse() && N1->hasOneUse() &&
4542 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4547 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4548 // Multiplications are only custom-lowered for 128-bit vectors so that
4549 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4550 EVT VT = Op.getValueType();
4551 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4552 SDNode *N0 = Op.getOperand(0).getNode();
4553 SDNode *N1 = Op.getOperand(1).getNode();
4554 unsigned NewOpc = 0;
4556 bool isN0SExt = isSignExtended(N0, DAG);
4557 bool isN1SExt = isSignExtended(N1, DAG);
4558 if (isN0SExt && isN1SExt)
4559 NewOpc = ARMISD::VMULLs;
4561 bool isN0ZExt = isZeroExtended(N0, DAG);
4562 bool isN1ZExt = isZeroExtended(N1, DAG);
4563 if (isN0ZExt && isN1ZExt)
4564 NewOpc = ARMISD::VMULLu;
4565 else if (isN1SExt || isN1ZExt) {
4566 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4567 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4568 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4569 NewOpc = ARMISD::VMULLs;
4571 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4572 NewOpc = ARMISD::VMULLu;
4574 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4576 NewOpc = ARMISD::VMULLu;
4582 if (VT == MVT::v2i64)
4583 // Fall through to expand this. It is not legal.
4586 // Other vector multiplications are legal.
4591 // Legalize to a VMULL instruction.
4592 DebugLoc DL = Op.getDebugLoc();
4594 SDValue Op1 = SkipExtension(N1, DAG);
4596 Op0 = SkipExtension(N0, DAG);
4597 assert(Op0.getValueType().is64BitVector() &&
4598 Op1.getValueType().is64BitVector() &&
4599 "unexpected types for extended operands to VMULL");
4600 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4603 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4604 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4611 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4612 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4613 EVT Op1VT = Op1.getValueType();
4614 return DAG.getNode(N0->getOpcode(), DL, VT,
4615 DAG.getNode(NewOpc, DL, VT,
4616 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4617 DAG.getNode(NewOpc, DL, VT,
4618 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4622 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4624 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4625 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4626 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4627 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4628 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4629 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4630 // Get reciprocal estimate.
4631 // float4 recip = vrecpeq_f32(yf);
4632 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4633 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4634 // Because char has a smaller range than uchar, we can actually get away
4635 // without any newton steps. This requires that we use a weird bias
4636 // of 0xb000, however (again, this has been exhaustively tested).
4637 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4638 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4639 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4640 Y = DAG.getConstant(0xb000, MVT::i32);
4641 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4642 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4643 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4644 // Convert back to short.
4645 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4646 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4651 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4653 // Convert to float.
4654 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4655 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4656 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4657 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4658 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4659 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4661 // Use reciprocal estimate and one refinement step.
4662 // float4 recip = vrecpeq_f32(yf);
4663 // recip *= vrecpsq_f32(yf, recip);
4664 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4665 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4666 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4667 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4669 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4670 // Because short has a smaller range than ushort, we can actually get away
4671 // with only a single newton step. This requires that we use a weird bias
4672 // of 89, however (again, this has been exhaustively tested).
4673 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
4674 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4675 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4676 N1 = DAG.getConstant(0x89, MVT::i32);
4677 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4678 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4679 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4680 // Convert back to integer and return.
4681 // return vmovn_s32(vcvt_s32_f32(result));
4682 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4683 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4687 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4688 EVT VT = Op.getValueType();
4689 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4690 "unexpected type for custom-lowering ISD::SDIV");
4692 DebugLoc dl = Op.getDebugLoc();
4693 SDValue N0 = Op.getOperand(0);
4694 SDValue N1 = Op.getOperand(1);
4697 if (VT == MVT::v8i8) {
4698 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4699 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4701 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4702 DAG.getIntPtrConstant(4));
4703 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4704 DAG.getIntPtrConstant(4));
4705 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4706 DAG.getIntPtrConstant(0));
4707 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4708 DAG.getIntPtrConstant(0));
4710 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4711 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4713 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4714 N0 = LowerCONCAT_VECTORS(N0, DAG);
4716 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4719 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4722 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4723 EVT VT = Op.getValueType();
4724 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4725 "unexpected type for custom-lowering ISD::UDIV");
4727 DebugLoc dl = Op.getDebugLoc();
4728 SDValue N0 = Op.getOperand(0);
4729 SDValue N1 = Op.getOperand(1);
4732 if (VT == MVT::v8i8) {
4733 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4734 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4736 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4737 DAG.getIntPtrConstant(4));
4738 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4739 DAG.getIntPtrConstant(4));
4740 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4741 DAG.getIntPtrConstant(0));
4742 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4743 DAG.getIntPtrConstant(0));
4745 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4746 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4748 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4749 N0 = LowerCONCAT_VECTORS(N0, DAG);
4751 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4752 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4757 // v4i16 sdiv ... Convert to float.
4758 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4759 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4760 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4761 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4762 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4763 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4765 // Use reciprocal estimate and two refinement steps.
4766 // float4 recip = vrecpeq_f32(yf);
4767 // recip *= vrecpsq_f32(yf, recip);
4768 // recip *= vrecpsq_f32(yf, recip);
4769 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4770 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
4771 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4772 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4774 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4775 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4776 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4778 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4779 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4780 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4781 // and that it will never cause us to return an answer too large).
4782 // float4 result = as_float4(as_int4(xf*recip) + 2);
4783 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4784 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4785 N1 = DAG.getConstant(2, MVT::i32);
4786 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4787 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4788 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4789 // Convert back to integer and return.
4790 // return vmovn_u32(vcvt_s32_f32(result));
4791 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4792 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4796 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4797 switch (Op.getOpcode()) {
4798 default: llvm_unreachable("Don't know how to custom lower this!");
4799 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4800 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4801 case ISD::GlobalAddress:
4802 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4803 LowerGlobalAddressELF(Op, DAG);
4804 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4805 case ISD::SELECT: return LowerSELECT(Op, DAG);
4806 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4807 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4808 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4809 case ISD::VASTART: return LowerVASTART(Op, DAG);
4810 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4811 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4812 case ISD::SINT_TO_FP:
4813 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4814 case ISD::FP_TO_SINT:
4815 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4816 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4817 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4818 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4819 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4820 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4821 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4822 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4823 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4825 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4828 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4829 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4830 case ISD::SRL_PARTS:
4831 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4832 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4833 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4834 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4835 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4836 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4837 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4838 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4839 case ISD::MUL: return LowerMUL(Op, DAG);
4840 case ISD::SDIV: return LowerSDIV(Op, DAG);
4841 case ISD::UDIV: return LowerUDIV(Op, DAG);
4846 /// ReplaceNodeResults - Replace the results of node with an illegal result
4847 /// type with new values built out of custom code.
4848 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4849 SmallVectorImpl<SDValue>&Results,
4850 SelectionDAG &DAG) const {
4852 switch (N->getOpcode()) {
4854 llvm_unreachable("Don't know how to custom expand this!");
4857 Res = ExpandBITCAST(N, DAG);
4861 Res = Expand64BitShift(N, DAG, Subtarget);
4865 Results.push_back(Res);
4868 //===----------------------------------------------------------------------===//
4869 // ARM Scheduler Hooks
4870 //===----------------------------------------------------------------------===//
4873 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4874 MachineBasicBlock *BB,
4875 unsigned Size) const {
4876 unsigned dest = MI->getOperand(0).getReg();
4877 unsigned ptr = MI->getOperand(1).getReg();
4878 unsigned oldval = MI->getOperand(2).getReg();
4879 unsigned newval = MI->getOperand(3).getReg();
4880 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4881 DebugLoc dl = MI->getDebugLoc();
4882 bool isThumb2 = Subtarget->isThumb2();
4884 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4886 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
4887 : ARM::GPRRegisterClass);
4890 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
4891 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
4892 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
4895 unsigned ldrOpc, strOpc;
4897 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4899 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4900 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4903 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4904 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4907 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4908 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4912 MachineFunction *MF = BB->getParent();
4913 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4914 MachineFunction::iterator It = BB;
4915 ++It; // insert the new blocks after the current block
4917 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4918 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4919 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4920 MF->insert(It, loop1MBB);
4921 MF->insert(It, loop2MBB);
4922 MF->insert(It, exitMBB);
4924 // Transfer the remainder of BB and its successor edges to exitMBB.
4925 exitMBB->splice(exitMBB->begin(), BB,
4926 llvm::next(MachineBasicBlock::iterator(MI)),
4928 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4932 // fallthrough --> loop1MBB
4933 BB->addSuccessor(loop1MBB);
4936 // ldrex dest, [ptr]
4940 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4941 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4942 .addReg(dest).addReg(oldval));
4943 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4944 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4945 BB->addSuccessor(loop2MBB);
4946 BB->addSuccessor(exitMBB);
4949 // strex scratch, newval, [ptr]
4953 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4955 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4956 .addReg(scratch).addImm(0));
4957 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4958 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4959 BB->addSuccessor(loop1MBB);
4960 BB->addSuccessor(exitMBB);
4966 MI->eraseFromParent(); // The instruction is gone now.
4972 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4973 unsigned Size, unsigned BinOpcode) const {
4974 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4975 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4977 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4978 MachineFunction *MF = BB->getParent();
4979 MachineFunction::iterator It = BB;
4982 unsigned dest = MI->getOperand(0).getReg();
4983 unsigned ptr = MI->getOperand(1).getReg();
4984 unsigned incr = MI->getOperand(2).getReg();
4985 DebugLoc dl = MI->getDebugLoc();
4987 bool isThumb2 = Subtarget->isThumb2();
4988 unsigned ldrOpc, strOpc;
4990 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4992 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4993 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4996 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4997 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5000 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5001 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5005 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5006 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5007 MF->insert(It, loopMBB);
5008 MF->insert(It, exitMBB);
5010 // Transfer the remainder of BB and its successor edges to exitMBB.
5011 exitMBB->splice(exitMBB->begin(), BB,
5012 llvm::next(MachineBasicBlock::iterator(MI)),
5014 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5016 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5017 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
5018 unsigned scratch2 = (!BinOpcode) ? incr :
5019 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
5023 // fallthrough --> loopMBB
5024 BB->addSuccessor(loopMBB);
5028 // <binop> scratch2, dest, incr
5029 // strex scratch, scratch2, ptr
5032 // fallthrough --> exitMBB
5034 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
5036 // operand order needs to go the other way for NAND
5037 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5038 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5039 addReg(incr).addReg(dest)).addReg(0);
5041 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5042 addReg(dest).addReg(incr)).addReg(0);
5045 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
5047 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5048 .addReg(scratch).addImm(0));
5049 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5050 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5052 BB->addSuccessor(loopMBB);
5053 BB->addSuccessor(exitMBB);
5059 MI->eraseFromParent(); // The instruction is gone now.
5065 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5066 MachineBasicBlock *BB,
5069 ARMCC::CondCodes Cond) const {
5070 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5072 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5073 MachineFunction *MF = BB->getParent();
5074 MachineFunction::iterator It = BB;
5077 unsigned dest = MI->getOperand(0).getReg();
5078 unsigned ptr = MI->getOperand(1).getReg();
5079 unsigned incr = MI->getOperand(2).getReg();
5080 unsigned oldval = dest;
5081 DebugLoc dl = MI->getDebugLoc();
5083 bool isThumb2 = Subtarget->isThumb2();
5084 unsigned ldrOpc, strOpc, extendOpc;
5086 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5088 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5089 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5090 extendOpc = isThumb2 ? ARM::t2SXTBr : ARM::SXTBr;
5093 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5094 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5095 extendOpc = isThumb2 ? ARM::t2SXTHr : ARM::SXTHr;
5098 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5099 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5104 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5105 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5106 MF->insert(It, loopMBB);
5107 MF->insert(It, exitMBB);
5109 // Transfer the remainder of BB and its successor edges to exitMBB.
5110 exitMBB->splice(exitMBB->begin(), BB,
5111 llvm::next(MachineBasicBlock::iterator(MI)),
5113 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5115 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5116 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
5117 unsigned scratch2 = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
5121 // fallthrough --> loopMBB
5122 BB->addSuccessor(loopMBB);
5126 // (sign extend dest, if required)
5128 // cmov.cond scratch2, dest, incr
5129 // strex scratch, scratch2, ptr
5132 // fallthrough --> exitMBB
5134 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
5136 // Sign extend the value, if necessary.
5137 if (signExtend && extendOpc) {
5138 oldval = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
5139 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval).addReg(dest));
5142 // Build compare and cmov instructions.
5143 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5144 .addReg(oldval).addReg(incr));
5145 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5146 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
5148 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
5150 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5151 .addReg(scratch).addImm(0));
5152 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5153 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5155 BB->addSuccessor(loopMBB);
5156 BB->addSuccessor(exitMBB);
5162 MI->eraseFromParent(); // The instruction is gone now.
5168 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
5169 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
5170 E = MBB->succ_end(); I != E; ++I)
5173 llvm_unreachable("Expecting a BB with two successors!");
5176 // FIXME: This opcode table should obviously be expressed in the target
5177 // description. We probably just need a "machine opcode" value in the pseudo
5178 // instruction. But the ideal solution maybe to simply remove the "S" version
5179 // of the opcode altogether.
5180 struct AddSubFlagsOpcodePair {
5182 unsigned MachineOpc;
5185 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
5186 {ARM::ADCSri, ARM::ADCri},
5187 {ARM::ADCSrr, ARM::ADCrr},
5188 {ARM::ADCSrs, ARM::ADCrs},
5189 {ARM::SBCSri, ARM::SBCri},
5190 {ARM::SBCSrr, ARM::SBCrr},
5191 {ARM::SBCSrs, ARM::SBCrs},
5192 {ARM::RSBSri, ARM::RSBri},
5193 {ARM::RSBSrr, ARM::RSBrr},
5194 {ARM::RSBSrs, ARM::RSBrs},
5195 {ARM::RSCSri, ARM::RSCri},
5196 {ARM::RSCSrs, ARM::RSCrs},
5197 {ARM::t2ADCSri, ARM::t2ADCri},
5198 {ARM::t2ADCSrr, ARM::t2ADCrr},
5199 {ARM::t2ADCSrs, ARM::t2ADCrs},
5200 {ARM::t2SBCSri, ARM::t2SBCri},
5201 {ARM::t2SBCSrr, ARM::t2SBCrr},
5202 {ARM::t2SBCSrs, ARM::t2SBCrs},
5203 {ARM::t2RSBSri, ARM::t2RSBri},
5204 {ARM::t2RSBSrs, ARM::t2RSBrs},
5207 // Convert and Add or Subtract with Carry and Flags to a generic opcode with
5208 // CPSR<def> operand. e.g. ADCS (...) -> ADC (... CPSR<def>).
5210 // FIXME: Somewhere we should assert that CPSR<def> is in the correct
5211 // position to be recognized by the target descrition as the 'S' bit.
5212 bool ARMTargetLowering::RemapAddSubWithFlags(MachineInstr *MI,
5213 MachineBasicBlock *BB) const {
5214 unsigned OldOpc = MI->getOpcode();
5215 unsigned NewOpc = 0;
5217 // This is only called for instructions that need remapping, so iterating over
5218 // the tiny opcode table is not costly.
5219 static const int NPairs =
5220 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
5221 for (AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0],
5222 *End = &AddSubFlagsOpcodeMap[NPairs]; Pair != End; ++Pair) {
5223 if (OldOpc == Pair->PseudoOpc) {
5224 NewOpc = Pair->MachineOpc;
5231 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5232 DebugLoc dl = MI->getDebugLoc();
5233 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
5234 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
5235 MIB.addOperand(MI->getOperand(i));
5236 AddDefaultPred(MIB);
5237 MIB.addReg(ARM::CPSR, RegState::Define); // S bit
5238 MI->eraseFromParent();
5243 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5244 MachineBasicBlock *BB) const {
5245 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5246 DebugLoc dl = MI->getDebugLoc();
5247 bool isThumb2 = Subtarget->isThumb2();
5248 switch (MI->getOpcode()) {
5250 if (RemapAddSubWithFlags(MI, BB))
5254 llvm_unreachable("Unexpected instr type to insert");
5256 case ARM::ATOMIC_LOAD_ADD_I8:
5257 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5258 case ARM::ATOMIC_LOAD_ADD_I16:
5259 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5260 case ARM::ATOMIC_LOAD_ADD_I32:
5261 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5263 case ARM::ATOMIC_LOAD_AND_I8:
5264 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5265 case ARM::ATOMIC_LOAD_AND_I16:
5266 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5267 case ARM::ATOMIC_LOAD_AND_I32:
5268 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5270 case ARM::ATOMIC_LOAD_OR_I8:
5271 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5272 case ARM::ATOMIC_LOAD_OR_I16:
5273 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5274 case ARM::ATOMIC_LOAD_OR_I32:
5275 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5277 case ARM::ATOMIC_LOAD_XOR_I8:
5278 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5279 case ARM::ATOMIC_LOAD_XOR_I16:
5280 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5281 case ARM::ATOMIC_LOAD_XOR_I32:
5282 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5284 case ARM::ATOMIC_LOAD_NAND_I8:
5285 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5286 case ARM::ATOMIC_LOAD_NAND_I16:
5287 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5288 case ARM::ATOMIC_LOAD_NAND_I32:
5289 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5291 case ARM::ATOMIC_LOAD_SUB_I8:
5292 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5293 case ARM::ATOMIC_LOAD_SUB_I16:
5294 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5295 case ARM::ATOMIC_LOAD_SUB_I32:
5296 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5298 case ARM::ATOMIC_LOAD_MIN_I8:
5299 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
5300 case ARM::ATOMIC_LOAD_MIN_I16:
5301 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
5302 case ARM::ATOMIC_LOAD_MIN_I32:
5303 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
5305 case ARM::ATOMIC_LOAD_MAX_I8:
5306 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
5307 case ARM::ATOMIC_LOAD_MAX_I16:
5308 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
5309 case ARM::ATOMIC_LOAD_MAX_I32:
5310 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
5312 case ARM::ATOMIC_LOAD_UMIN_I8:
5313 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
5314 case ARM::ATOMIC_LOAD_UMIN_I16:
5315 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
5316 case ARM::ATOMIC_LOAD_UMIN_I32:
5317 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
5319 case ARM::ATOMIC_LOAD_UMAX_I8:
5320 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
5321 case ARM::ATOMIC_LOAD_UMAX_I16:
5322 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
5323 case ARM::ATOMIC_LOAD_UMAX_I32:
5324 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
5326 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
5327 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
5328 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
5330 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
5331 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
5332 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
5334 case ARM::tMOVCCr_pseudo: {
5335 // To "insert" a SELECT_CC instruction, we actually have to insert the
5336 // diamond control-flow pattern. The incoming instruction knows the
5337 // destination vreg to set, the condition code register to branch on, the
5338 // true/false values to select between, and a branch opcode to use.
5339 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5340 MachineFunction::iterator It = BB;
5346 // cmpTY ccX, r1, r2
5348 // fallthrough --> copy0MBB
5349 MachineBasicBlock *thisMBB = BB;
5350 MachineFunction *F = BB->getParent();
5351 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
5352 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
5353 F->insert(It, copy0MBB);
5354 F->insert(It, sinkMBB);
5356 // Transfer the remainder of BB and its successor edges to sinkMBB.
5357 sinkMBB->splice(sinkMBB->begin(), BB,
5358 llvm::next(MachineBasicBlock::iterator(MI)),
5360 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5362 BB->addSuccessor(copy0MBB);
5363 BB->addSuccessor(sinkMBB);
5365 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
5366 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
5369 // %FalseValue = ...
5370 // # fallthrough to sinkMBB
5373 // Update machine-CFG edges
5374 BB->addSuccessor(sinkMBB);
5377 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5380 BuildMI(*BB, BB->begin(), dl,
5381 TII->get(ARM::PHI), MI->getOperand(0).getReg())
5382 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5383 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5385 MI->eraseFromParent(); // The pseudo instruction is gone now.
5390 case ARM::BCCZi64: {
5391 // If there is an unconditional branch to the other successor, remove it.
5392 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
5394 // Compare both parts that make up the double comparison separately for
5396 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
5398 unsigned LHS1 = MI->getOperand(1).getReg();
5399 unsigned LHS2 = MI->getOperand(2).getReg();
5401 AddDefaultPred(BuildMI(BB, dl,
5402 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5403 .addReg(LHS1).addImm(0));
5404 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5405 .addReg(LHS2).addImm(0)
5406 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5408 unsigned RHS1 = MI->getOperand(3).getReg();
5409 unsigned RHS2 = MI->getOperand(4).getReg();
5410 AddDefaultPred(BuildMI(BB, dl,
5411 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5412 .addReg(LHS1).addReg(RHS1));
5413 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5414 .addReg(LHS2).addReg(RHS2)
5415 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5418 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
5419 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
5420 if (MI->getOperand(0).getImm() == ARMCC::NE)
5421 std::swap(destMBB, exitMBB);
5423 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5424 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
5425 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
5428 MI->eraseFromParent(); // The pseudo instruction is gone now.
5434 //===----------------------------------------------------------------------===//
5435 // ARM Optimization Hooks
5436 //===----------------------------------------------------------------------===//
5439 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
5440 TargetLowering::DAGCombinerInfo &DCI) {
5441 SelectionDAG &DAG = DCI.DAG;
5442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5443 EVT VT = N->getValueType(0);
5444 unsigned Opc = N->getOpcode();
5445 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
5446 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
5447 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
5448 ISD::CondCode CC = ISD::SETCC_INVALID;
5451 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
5453 SDValue CCOp = Slct.getOperand(0);
5454 if (CCOp.getOpcode() == ISD::SETCC)
5455 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
5458 bool DoXform = false;
5460 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
5463 if (LHS.getOpcode() == ISD::Constant &&
5464 cast<ConstantSDNode>(LHS)->isNullValue()) {
5466 } else if (CC != ISD::SETCC_INVALID &&
5467 RHS.getOpcode() == ISD::Constant &&
5468 cast<ConstantSDNode>(RHS)->isNullValue()) {
5469 std::swap(LHS, RHS);
5470 SDValue Op0 = Slct.getOperand(0);
5471 EVT OpVT = isSlctCC ? Op0.getValueType() :
5472 Op0.getOperand(0).getValueType();
5473 bool isInt = OpVT.isInteger();
5474 CC = ISD::getSetCCInverse(CC, isInt);
5476 if (!TLI.isCondCodeLegal(CC, OpVT))
5477 return SDValue(); // Inverse operator isn't legal.
5484 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
5486 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
5487 Slct.getOperand(0), Slct.getOperand(1), CC);
5488 SDValue CCOp = Slct.getOperand(0);
5490 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
5491 CCOp.getOperand(0), CCOp.getOperand(1), CC);
5492 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
5493 CCOp, OtherOp, Result);
5498 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
5499 /// operands N0 and N1. This is a helper for PerformADDCombine that is
5500 /// called with the default operands, and if that fails, with commuted
5502 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
5503 TargetLowering::DAGCombinerInfo &DCI) {
5504 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
5505 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
5506 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
5507 if (Result.getNode()) return Result;
5512 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
5514 static SDValue PerformADDCombine(SDNode *N,
5515 TargetLowering::DAGCombinerInfo &DCI) {
5516 SDValue N0 = N->getOperand(0);
5517 SDValue N1 = N->getOperand(1);
5519 // First try with the default operand order.
5520 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
5521 if (Result.getNode())
5524 // If that didn't work, try again with the operands commuted.
5525 return PerformADDCombineWithOperands(N, N1, N0, DCI);
5528 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
5530 static SDValue PerformSUBCombine(SDNode *N,
5531 TargetLowering::DAGCombinerInfo &DCI) {
5532 SDValue N0 = N->getOperand(0);
5533 SDValue N1 = N->getOperand(1);
5535 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
5536 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
5537 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
5538 if (Result.getNode()) return Result;
5544 /// PerformVMULCombine
5545 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
5546 /// special multiplier accumulator forwarding.
5552 static SDValue PerformVMULCombine(SDNode *N,
5553 TargetLowering::DAGCombinerInfo &DCI,
5554 const ARMSubtarget *Subtarget) {
5555 if (!Subtarget->hasVMLxForwarding())
5558 SelectionDAG &DAG = DCI.DAG;
5559 SDValue N0 = N->getOperand(0);
5560 SDValue N1 = N->getOperand(1);
5561 unsigned Opcode = N0.getOpcode();
5562 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5563 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
5564 Opcode = N0.getOpcode();
5565 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5566 Opcode != ISD::FADD && Opcode != ISD::FSUB)
5571 EVT VT = N->getValueType(0);
5572 DebugLoc DL = N->getDebugLoc();
5573 SDValue N00 = N0->getOperand(0);
5574 SDValue N01 = N0->getOperand(1);
5575 return DAG.getNode(Opcode, DL, VT,
5576 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
5577 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
5580 static SDValue PerformMULCombine(SDNode *N,
5581 TargetLowering::DAGCombinerInfo &DCI,
5582 const ARMSubtarget *Subtarget) {
5583 SelectionDAG &DAG = DCI.DAG;
5585 if (Subtarget->isThumb1Only())
5588 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5591 EVT VT = N->getValueType(0);
5592 if (VT.is64BitVector() || VT.is128BitVector())
5593 return PerformVMULCombine(N, DCI, Subtarget);
5597 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
5601 uint64_t MulAmt = C->getZExtValue();
5602 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
5603 ShiftAmt = ShiftAmt & (32 - 1);
5604 SDValue V = N->getOperand(0);
5605 DebugLoc DL = N->getDebugLoc();
5608 MulAmt >>= ShiftAmt;
5609 if (isPowerOf2_32(MulAmt - 1)) {
5610 // (mul x, 2^N + 1) => (add (shl x, N), x)
5611 Res = DAG.getNode(ISD::ADD, DL, VT,
5612 V, DAG.getNode(ISD::SHL, DL, VT,
5613 V, DAG.getConstant(Log2_32(MulAmt-1),
5615 } else if (isPowerOf2_32(MulAmt + 1)) {
5616 // (mul x, 2^N - 1) => (sub (shl x, N), x)
5617 Res = DAG.getNode(ISD::SUB, DL, VT,
5618 DAG.getNode(ISD::SHL, DL, VT,
5619 V, DAG.getConstant(Log2_32(MulAmt+1),
5626 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
5627 DAG.getConstant(ShiftAmt, MVT::i32));
5629 // Do not add new nodes to DAG combiner worklist.
5630 DCI.CombineTo(N, Res, false);
5634 static SDValue PerformANDCombine(SDNode *N,
5635 TargetLowering::DAGCombinerInfo &DCI) {
5637 // Attempt to use immediate-form VBIC
5638 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5639 DebugLoc dl = N->getDebugLoc();
5640 EVT VT = N->getValueType(0);
5641 SelectionDAG &DAG = DCI.DAG;
5643 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5646 APInt SplatBits, SplatUndef;
5647 unsigned SplatBitSize;
5650 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5651 if (SplatBitSize <= 64) {
5653 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
5654 SplatUndef.getZExtValue(), SplatBitSize,
5655 DAG, VbicVT, VT.is128BitVector(),
5657 if (Val.getNode()) {
5659 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
5660 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
5661 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
5669 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
5670 static SDValue PerformORCombine(SDNode *N,
5671 TargetLowering::DAGCombinerInfo &DCI,
5672 const ARMSubtarget *Subtarget) {
5673 // Attempt to use immediate-form VORR
5674 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5675 DebugLoc dl = N->getDebugLoc();
5676 EVT VT = N->getValueType(0);
5677 SelectionDAG &DAG = DCI.DAG;
5679 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5682 APInt SplatBits, SplatUndef;
5683 unsigned SplatBitSize;
5685 if (BVN && Subtarget->hasNEON() &&
5686 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5687 if (SplatBitSize <= 64) {
5689 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5690 SplatUndef.getZExtValue(), SplatBitSize,
5691 DAG, VorrVT, VT.is128BitVector(),
5693 if (Val.getNode()) {
5695 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
5696 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
5697 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
5702 SDValue N0 = N->getOperand(0);
5703 if (N0.getOpcode() != ISD::AND)
5705 SDValue N1 = N->getOperand(1);
5707 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
5708 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
5709 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
5711 unsigned SplatBitSize;
5714 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
5716 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
5717 HasAnyUndefs) && !HasAnyUndefs) {
5718 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
5720 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
5721 HasAnyUndefs) && !HasAnyUndefs &&
5722 SplatBits0 == ~SplatBits1) {
5723 // Canonicalize the vector type to make instruction selection simpler.
5724 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5725 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
5726 N0->getOperand(1), N0->getOperand(0),
5728 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
5733 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
5736 // BFI is only available on V6T2+
5737 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
5740 DebugLoc DL = N->getDebugLoc();
5741 // 1) or (and A, mask), val => ARMbfi A, val, mask
5742 // iff (val & mask) == val
5744 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5745 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
5746 // && mask == ~mask2
5747 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
5748 // && ~mask == mask2
5749 // (i.e., copy a bitfield value into another bitfield of the same width)
5754 SDValue N00 = N0.getOperand(0);
5756 // The value and the mask need to be constants so we can verify this is
5757 // actually a bitfield set. If the mask is 0xffff, we can do better
5758 // via a movt instruction, so don't use BFI in that case.
5759 SDValue MaskOp = N0.getOperand(1);
5760 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
5763 unsigned Mask = MaskC->getZExtValue();
5767 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
5768 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5770 unsigned Val = N1C->getZExtValue();
5771 if ((Val & ~Mask) != Val)
5774 if (ARM::isBitFieldInvertedMask(Mask)) {
5775 Val >>= CountTrailingZeros_32(~Mask);
5777 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
5778 DAG.getConstant(Val, MVT::i32),
5779 DAG.getConstant(Mask, MVT::i32));
5781 // Do not add new nodes to DAG combiner worklist.
5782 DCI.CombineTo(N, Res, false);
5785 } else if (N1.getOpcode() == ISD::AND) {
5786 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5787 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5790 unsigned Mask2 = N11C->getZExtValue();
5792 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
5794 if (ARM::isBitFieldInvertedMask(Mask) &&
5796 // The pack halfword instruction works better for masks that fit it,
5797 // so use that when it's available.
5798 if (Subtarget->hasT2ExtractPack() &&
5799 (Mask == 0xffff || Mask == 0xffff0000))
5802 unsigned amt = CountTrailingZeros_32(Mask2);
5803 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
5804 DAG.getConstant(amt, MVT::i32));
5805 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
5806 DAG.getConstant(Mask, MVT::i32));
5807 // Do not add new nodes to DAG combiner worklist.
5808 DCI.CombineTo(N, Res, false);
5810 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
5812 // The pack halfword instruction works better for masks that fit it,
5813 // so use that when it's available.
5814 if (Subtarget->hasT2ExtractPack() &&
5815 (Mask2 == 0xffff || Mask2 == 0xffff0000))
5818 unsigned lsb = CountTrailingZeros_32(Mask);
5819 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
5820 DAG.getConstant(lsb, MVT::i32));
5821 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
5822 DAG.getConstant(Mask2, MVT::i32));
5823 // Do not add new nodes to DAG combiner worklist.
5824 DCI.CombineTo(N, Res, false);
5829 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
5830 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
5831 ARM::isBitFieldInvertedMask(~Mask)) {
5832 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
5833 // where lsb(mask) == #shamt and masked bits of B are known zero.
5834 SDValue ShAmt = N00.getOperand(1);
5835 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5836 unsigned LSB = CountTrailingZeros_32(Mask);
5840 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
5841 DAG.getConstant(~Mask, MVT::i32));
5843 // Do not add new nodes to DAG combiner worklist.
5844 DCI.CombineTo(N, Res, false);
5850 /// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff
5852 static SDValue PerformBFICombine(SDNode *N,
5853 TargetLowering::DAGCombinerInfo &DCI) {
5854 SDValue N1 = N->getOperand(1);
5855 if (N1.getOpcode() == ISD::AND) {
5856 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5859 unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
5860 unsigned Mask2 = N11C->getZExtValue();
5861 if ((Mask & Mask2) == Mask2)
5862 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
5863 N->getOperand(0), N1.getOperand(0),
5869 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
5870 /// ARMISD::VMOVRRD.
5871 static SDValue PerformVMOVRRDCombine(SDNode *N,
5872 TargetLowering::DAGCombinerInfo &DCI) {
5873 // vmovrrd(vmovdrr x, y) -> x,y
5874 SDValue InDouble = N->getOperand(0);
5875 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
5876 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
5878 // vmovrrd(load f64) -> (load i32), (load i32)
5879 SDNode *InNode = InDouble.getNode();
5880 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
5881 InNode->getValueType(0) == MVT::f64 &&
5882 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
5883 !cast<LoadSDNode>(InNode)->isVolatile()) {
5884 // TODO: Should this be done for non-FrameIndex operands?
5885 LoadSDNode *LD = cast<LoadSDNode>(InNode);
5887 SelectionDAG &DAG = DCI.DAG;
5888 DebugLoc DL = LD->getDebugLoc();
5889 SDValue BasePtr = LD->getBasePtr();
5890 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
5891 LD->getPointerInfo(), LD->isVolatile(),
5892 LD->isNonTemporal(), LD->getAlignment());
5894 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
5895 DAG.getConstant(4, MVT::i32));
5896 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
5897 LD->getPointerInfo(), LD->isVolatile(),
5898 LD->isNonTemporal(),
5899 std::min(4U, LD->getAlignment() / 2));
5901 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
5902 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
5903 DCI.RemoveFromWorklist(LD);
5911 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
5912 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
5913 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
5914 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
5915 SDValue Op0 = N->getOperand(0);
5916 SDValue Op1 = N->getOperand(1);
5917 if (Op0.getOpcode() == ISD::BITCAST)
5918 Op0 = Op0.getOperand(0);
5919 if (Op1.getOpcode() == ISD::BITCAST)
5920 Op1 = Op1.getOperand(0);
5921 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
5922 Op0.getNode() == Op1.getNode() &&
5923 Op0.getResNo() == 0 && Op1.getResNo() == 1)
5924 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5925 N->getValueType(0), Op0.getOperand(0));
5929 /// PerformSTORECombine - Target-specific dag combine xforms for
5931 static SDValue PerformSTORECombine(SDNode *N,
5932 TargetLowering::DAGCombinerInfo &DCI) {
5933 // Bitcast an i64 store extracted from a vector to f64.
5934 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5935 StoreSDNode *St = cast<StoreSDNode>(N);
5936 SDValue StVal = St->getValue();
5937 if (!ISD::isNormalStore(St) || St->isVolatile())
5940 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
5941 StVal.getNode()->hasOneUse() && !St->isVolatile()) {
5942 SelectionDAG &DAG = DCI.DAG;
5943 DebugLoc DL = St->getDebugLoc();
5944 SDValue BasePtr = St->getBasePtr();
5945 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
5946 StVal.getNode()->getOperand(0), BasePtr,
5947 St->getPointerInfo(), St->isVolatile(),
5948 St->isNonTemporal(), St->getAlignment());
5950 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
5951 DAG.getConstant(4, MVT::i32));
5952 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
5953 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
5954 St->isNonTemporal(),
5955 std::min(4U, St->getAlignment() / 2));
5958 if (StVal.getValueType() != MVT::i64 ||
5959 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5962 SelectionDAG &DAG = DCI.DAG;
5963 DebugLoc dl = StVal.getDebugLoc();
5964 SDValue IntVec = StVal.getOperand(0);
5965 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5966 IntVec.getValueType().getVectorNumElements());
5967 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
5968 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5969 Vec, StVal.getOperand(1));
5970 dl = N->getDebugLoc();
5971 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
5972 // Make the DAGCombiner fold the bitcasts.
5973 DCI.AddToWorklist(Vec.getNode());
5974 DCI.AddToWorklist(ExtElt.getNode());
5975 DCI.AddToWorklist(V.getNode());
5976 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
5977 St->getPointerInfo(), St->isVolatile(),
5978 St->isNonTemporal(), St->getAlignment(),
5982 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
5983 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
5984 /// i64 vector to have f64 elements, since the value can then be loaded
5985 /// directly into a VFP register.
5986 static bool hasNormalLoadOperand(SDNode *N) {
5987 unsigned NumElts = N->getValueType(0).getVectorNumElements();
5988 for (unsigned i = 0; i < NumElts; ++i) {
5989 SDNode *Elt = N->getOperand(i).getNode();
5990 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
5996 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
5997 /// ISD::BUILD_VECTOR.
5998 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
5999 TargetLowering::DAGCombinerInfo &DCI){
6000 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
6001 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
6002 // into a pair of GPRs, which is fine when the value is used as a scalar,
6003 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
6004 SelectionDAG &DAG = DCI.DAG;
6005 if (N->getNumOperands() == 2) {
6006 SDValue RV = PerformVMOVDRRCombine(N, DAG);
6011 // Load i64 elements as f64 values so that type legalization does not split
6012 // them up into i32 values.
6013 EVT VT = N->getValueType(0);
6014 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
6016 DebugLoc dl = N->getDebugLoc();
6017 SmallVector<SDValue, 8> Ops;
6018 unsigned NumElts = VT.getVectorNumElements();
6019 for (unsigned i = 0; i < NumElts; ++i) {
6020 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
6022 // Make the DAGCombiner fold the bitcast.
6023 DCI.AddToWorklist(V.getNode());
6025 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
6026 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
6027 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
6030 /// PerformInsertEltCombine - Target-specific dag combine xforms for
6031 /// ISD::INSERT_VECTOR_ELT.
6032 static SDValue PerformInsertEltCombine(SDNode *N,
6033 TargetLowering::DAGCombinerInfo &DCI) {
6034 // Bitcast an i64 load inserted into a vector to f64.
6035 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6036 EVT VT = N->getValueType(0);
6037 SDNode *Elt = N->getOperand(1).getNode();
6038 if (VT.getVectorElementType() != MVT::i64 ||
6039 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
6042 SelectionDAG &DAG = DCI.DAG;
6043 DebugLoc dl = N->getDebugLoc();
6044 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
6045 VT.getVectorNumElements());
6046 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
6047 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
6048 // Make the DAGCombiner fold the bitcasts.
6049 DCI.AddToWorklist(Vec.getNode());
6050 DCI.AddToWorklist(V.getNode());
6051 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
6052 Vec, V, N->getOperand(2));
6053 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
6056 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
6057 /// ISD::VECTOR_SHUFFLE.
6058 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
6059 // The LLVM shufflevector instruction does not require the shuffle mask
6060 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
6061 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
6062 // operands do not match the mask length, they are extended by concatenating
6063 // them with undef vectors. That is probably the right thing for other
6064 // targets, but for NEON it is better to concatenate two double-register
6065 // size vector operands into a single quad-register size vector. Do that
6066 // transformation here:
6067 // shuffle(concat(v1, undef), concat(v2, undef)) ->
6068 // shuffle(concat(v1, v2), undef)
6069 SDValue Op0 = N->getOperand(0);
6070 SDValue Op1 = N->getOperand(1);
6071 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
6072 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
6073 Op0.getNumOperands() != 2 ||
6074 Op1.getNumOperands() != 2)
6076 SDValue Concat0Op1 = Op0.getOperand(1);
6077 SDValue Concat1Op1 = Op1.getOperand(1);
6078 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
6079 Concat1Op1.getOpcode() != ISD::UNDEF)
6081 // Skip the transformation if any of the types are illegal.
6082 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6083 EVT VT = N->getValueType(0);
6084 if (!TLI.isTypeLegal(VT) ||
6085 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
6086 !TLI.isTypeLegal(Concat1Op1.getValueType()))
6089 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
6090 Op0.getOperand(0), Op1.getOperand(0));
6091 // Translate the shuffle mask.
6092 SmallVector<int, 16> NewMask;
6093 unsigned NumElts = VT.getVectorNumElements();
6094 unsigned HalfElts = NumElts/2;
6095 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
6096 for (unsigned n = 0; n < NumElts; ++n) {
6097 int MaskElt = SVN->getMaskElt(n);
6099 if (MaskElt < (int)HalfElts)
6101 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
6102 NewElt = HalfElts + MaskElt - NumElts;
6103 NewMask.push_back(NewElt);
6105 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
6106 DAG.getUNDEF(VT), NewMask.data());
6109 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
6110 /// NEON load/store intrinsics to merge base address updates.
6111 static SDValue CombineBaseUpdate(SDNode *N,
6112 TargetLowering::DAGCombinerInfo &DCI) {
6113 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
6116 SelectionDAG &DAG = DCI.DAG;
6117 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
6118 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
6119 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
6120 SDValue Addr = N->getOperand(AddrOpIdx);
6122 // Search for a use of the address operand that is an increment.
6123 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
6124 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
6126 if (User->getOpcode() != ISD::ADD ||
6127 UI.getUse().getResNo() != Addr.getResNo())
6130 // Check that the add is independent of the load/store. Otherwise, folding
6131 // it would create a cycle.
6132 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
6135 // Find the new opcode for the updating load/store.
6137 bool isLaneOp = false;
6138 unsigned NewOpc = 0;
6139 unsigned NumVecs = 0;
6141 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
6143 default: assert(0 && "unexpected intrinsic for Neon base update");
6144 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
6146 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
6148 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
6150 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
6152 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
6153 NumVecs = 2; isLaneOp = true; break;
6154 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
6155 NumVecs = 3; isLaneOp = true; break;
6156 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
6157 NumVecs = 4; isLaneOp = true; break;
6158 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
6159 NumVecs = 1; isLoad = false; break;
6160 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
6161 NumVecs = 2; isLoad = false; break;
6162 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
6163 NumVecs = 3; isLoad = false; break;
6164 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
6165 NumVecs = 4; isLoad = false; break;
6166 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
6167 NumVecs = 2; isLoad = false; isLaneOp = true; break;
6168 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
6169 NumVecs = 3; isLoad = false; isLaneOp = true; break;
6170 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
6171 NumVecs = 4; isLoad = false; isLaneOp = true; break;
6175 switch (N->getOpcode()) {
6176 default: assert(0 && "unexpected opcode for Neon base update");
6177 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
6178 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
6179 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
6183 // Find the size of memory referenced by the load/store.
6186 VecTy = N->getValueType(0);
6188 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
6189 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
6191 NumBytes /= VecTy.getVectorNumElements();
6193 // If the increment is a constant, it must match the memory ref size.
6194 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
6195 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
6196 uint64_t IncVal = CInc->getZExtValue();
6197 if (IncVal != NumBytes)
6199 } else if (NumBytes >= 3 * 16) {
6200 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
6201 // separate instructions that make it harder to use a non-constant update.
6205 // Create the new updating load/store node.
6207 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
6209 for (n = 0; n < NumResultVecs; ++n)
6211 Tys[n++] = MVT::i32;
6212 Tys[n] = MVT::Other;
6213 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
6214 SmallVector<SDValue, 8> Ops;
6215 Ops.push_back(N->getOperand(0)); // incoming chain
6216 Ops.push_back(N->getOperand(AddrOpIdx));
6218 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
6219 Ops.push_back(N->getOperand(i));
6221 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
6222 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
6223 Ops.data(), Ops.size(),
6224 MemInt->getMemoryVT(),
6225 MemInt->getMemOperand());
6228 std::vector<SDValue> NewResults;
6229 for (unsigned i = 0; i < NumResultVecs; ++i) {
6230 NewResults.push_back(SDValue(UpdN.getNode(), i));
6232 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
6233 DCI.CombineTo(N, NewResults);
6234 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
6241 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
6242 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
6243 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
6245 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
6246 SelectionDAG &DAG = DCI.DAG;
6247 EVT VT = N->getValueType(0);
6248 // vldN-dup instructions only support 64-bit vectors for N > 1.
6249 if (!VT.is64BitVector())
6252 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
6253 SDNode *VLD = N->getOperand(0).getNode();
6254 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
6256 unsigned NumVecs = 0;
6257 unsigned NewOpc = 0;
6258 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
6259 if (IntNo == Intrinsic::arm_neon_vld2lane) {
6261 NewOpc = ARMISD::VLD2DUP;
6262 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
6264 NewOpc = ARMISD::VLD3DUP;
6265 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
6267 NewOpc = ARMISD::VLD4DUP;
6272 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
6273 // numbers match the load.
6274 unsigned VLDLaneNo =
6275 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
6276 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6278 // Ignore uses of the chain result.
6279 if (UI.getUse().getResNo() == NumVecs)
6282 if (User->getOpcode() != ARMISD::VDUPLANE ||
6283 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
6287 // Create the vldN-dup node.
6290 for (n = 0; n < NumVecs; ++n)
6292 Tys[n] = MVT::Other;
6293 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
6294 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
6295 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
6296 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
6297 Ops, 2, VLDMemInt->getMemoryVT(),
6298 VLDMemInt->getMemOperand());
6301 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6303 unsigned ResNo = UI.getUse().getResNo();
6304 // Ignore uses of the chain result.
6305 if (ResNo == NumVecs)
6308 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
6311 // Now the vldN-lane intrinsic is dead except for its chain result.
6312 // Update uses of the chain.
6313 std::vector<SDValue> VLDDupResults;
6314 for (unsigned n = 0; n < NumVecs; ++n)
6315 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
6316 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
6317 DCI.CombineTo(VLD, VLDDupResults);
6322 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
6323 /// ARMISD::VDUPLANE.
6324 static SDValue PerformVDUPLANECombine(SDNode *N,
6325 TargetLowering::DAGCombinerInfo &DCI) {
6326 SDValue Op = N->getOperand(0);
6328 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
6329 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
6330 if (CombineVLDDUP(N, DCI))
6331 return SDValue(N, 0);
6333 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
6334 // redundant. Ignore bit_converts for now; element sizes are checked below.
6335 while (Op.getOpcode() == ISD::BITCAST)
6336 Op = Op.getOperand(0);
6337 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
6340 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
6341 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
6342 // The canonical VMOV for a zero vector uses a 32-bit element size.
6343 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6345 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
6347 EVT VT = N->getValueType(0);
6348 if (EltSize > VT.getVectorElementType().getSizeInBits())
6351 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
6354 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6355 /// operand of a vector shift operation, where all the elements of the
6356 /// build_vector must have the same constant integer value.
6357 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6358 // Ignore bit_converts.
6359 while (Op.getOpcode() == ISD::BITCAST)
6360 Op = Op.getOperand(0);
6361 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6362 APInt SplatBits, SplatUndef;
6363 unsigned SplatBitSize;
6365 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6366 HasAnyUndefs, ElementBits) ||
6367 SplatBitSize > ElementBits)
6369 Cnt = SplatBits.getSExtValue();
6373 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6374 /// operand of a vector shift left operation. That value must be in the range:
6375 /// 0 <= Value < ElementBits for a left shift; or
6376 /// 0 <= Value <= ElementBits for a long left shift.
6377 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6378 assert(VT.isVector() && "vector shift count is not a vector type");
6379 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6380 if (! getVShiftImm(Op, ElementBits, Cnt))
6382 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
6385 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6386 /// operand of a vector shift right operation. For a shift opcode, the value
6387 /// is positive, but for an intrinsic the value count must be negative. The
6388 /// absolute value must be in the range:
6389 /// 1 <= |Value| <= ElementBits for a right shift; or
6390 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6391 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6393 assert(VT.isVector() && "vector shift count is not a vector type");
6394 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6395 if (! getVShiftImm(Op, ElementBits, Cnt))
6399 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
6402 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
6403 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
6404 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
6407 // Don't do anything for most intrinsics.
6410 // Vector shifts: check for immediate versions and lower them.
6411 // Note: This is done during DAG combining instead of DAG legalizing because
6412 // the build_vectors for 64-bit vector element shift counts are generally
6413 // not legal, and it is hard to see their values after they get legalized to
6414 // loads from a constant pool.
6415 case Intrinsic::arm_neon_vshifts:
6416 case Intrinsic::arm_neon_vshiftu:
6417 case Intrinsic::arm_neon_vshiftls:
6418 case Intrinsic::arm_neon_vshiftlu:
6419 case Intrinsic::arm_neon_vshiftn:
6420 case Intrinsic::arm_neon_vrshifts:
6421 case Intrinsic::arm_neon_vrshiftu:
6422 case Intrinsic::arm_neon_vrshiftn:
6423 case Intrinsic::arm_neon_vqshifts:
6424 case Intrinsic::arm_neon_vqshiftu:
6425 case Intrinsic::arm_neon_vqshiftsu:
6426 case Intrinsic::arm_neon_vqshiftns:
6427 case Intrinsic::arm_neon_vqshiftnu:
6428 case Intrinsic::arm_neon_vqshiftnsu:
6429 case Intrinsic::arm_neon_vqrshiftns:
6430 case Intrinsic::arm_neon_vqrshiftnu:
6431 case Intrinsic::arm_neon_vqrshiftnsu: {
6432 EVT VT = N->getOperand(1).getValueType();
6434 unsigned VShiftOpc = 0;
6437 case Intrinsic::arm_neon_vshifts:
6438 case Intrinsic::arm_neon_vshiftu:
6439 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
6440 VShiftOpc = ARMISD::VSHL;
6443 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
6444 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
6445 ARMISD::VSHRs : ARMISD::VSHRu);
6450 case Intrinsic::arm_neon_vshiftls:
6451 case Intrinsic::arm_neon_vshiftlu:
6452 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
6454 llvm_unreachable("invalid shift count for vshll intrinsic");
6456 case Intrinsic::arm_neon_vrshifts:
6457 case Intrinsic::arm_neon_vrshiftu:
6458 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
6462 case Intrinsic::arm_neon_vqshifts:
6463 case Intrinsic::arm_neon_vqshiftu:
6464 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6468 case Intrinsic::arm_neon_vqshiftsu:
6469 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6471 llvm_unreachable("invalid shift count for vqshlu intrinsic");
6473 case Intrinsic::arm_neon_vshiftn:
6474 case Intrinsic::arm_neon_vrshiftn:
6475 case Intrinsic::arm_neon_vqshiftns:
6476 case Intrinsic::arm_neon_vqshiftnu:
6477 case Intrinsic::arm_neon_vqshiftnsu:
6478 case Intrinsic::arm_neon_vqrshiftns:
6479 case Intrinsic::arm_neon_vqrshiftnu:
6480 case Intrinsic::arm_neon_vqrshiftnsu:
6481 // Narrowing shifts require an immediate right shift.
6482 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
6484 llvm_unreachable("invalid shift count for narrowing vector shift "
6488 llvm_unreachable("unhandled vector shift");
6492 case Intrinsic::arm_neon_vshifts:
6493 case Intrinsic::arm_neon_vshiftu:
6494 // Opcode already set above.
6496 case Intrinsic::arm_neon_vshiftls:
6497 case Intrinsic::arm_neon_vshiftlu:
6498 if (Cnt == VT.getVectorElementType().getSizeInBits())
6499 VShiftOpc = ARMISD::VSHLLi;
6501 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
6502 ARMISD::VSHLLs : ARMISD::VSHLLu);
6504 case Intrinsic::arm_neon_vshiftn:
6505 VShiftOpc = ARMISD::VSHRN; break;
6506 case Intrinsic::arm_neon_vrshifts:
6507 VShiftOpc = ARMISD::VRSHRs; break;
6508 case Intrinsic::arm_neon_vrshiftu:
6509 VShiftOpc = ARMISD::VRSHRu; break;
6510 case Intrinsic::arm_neon_vrshiftn:
6511 VShiftOpc = ARMISD::VRSHRN; break;
6512 case Intrinsic::arm_neon_vqshifts:
6513 VShiftOpc = ARMISD::VQSHLs; break;
6514 case Intrinsic::arm_neon_vqshiftu:
6515 VShiftOpc = ARMISD::VQSHLu; break;
6516 case Intrinsic::arm_neon_vqshiftsu:
6517 VShiftOpc = ARMISD::VQSHLsu; break;
6518 case Intrinsic::arm_neon_vqshiftns:
6519 VShiftOpc = ARMISD::VQSHRNs; break;
6520 case Intrinsic::arm_neon_vqshiftnu:
6521 VShiftOpc = ARMISD::VQSHRNu; break;
6522 case Intrinsic::arm_neon_vqshiftnsu:
6523 VShiftOpc = ARMISD::VQSHRNsu; break;
6524 case Intrinsic::arm_neon_vqrshiftns:
6525 VShiftOpc = ARMISD::VQRSHRNs; break;
6526 case Intrinsic::arm_neon_vqrshiftnu:
6527 VShiftOpc = ARMISD::VQRSHRNu; break;
6528 case Intrinsic::arm_neon_vqrshiftnsu:
6529 VShiftOpc = ARMISD::VQRSHRNsu; break;
6532 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6533 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
6536 case Intrinsic::arm_neon_vshiftins: {
6537 EVT VT = N->getOperand(1).getValueType();
6539 unsigned VShiftOpc = 0;
6541 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
6542 VShiftOpc = ARMISD::VSLI;
6543 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
6544 VShiftOpc = ARMISD::VSRI;
6546 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
6549 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6550 N->getOperand(1), N->getOperand(2),
6551 DAG.getConstant(Cnt, MVT::i32));
6554 case Intrinsic::arm_neon_vqrshifts:
6555 case Intrinsic::arm_neon_vqrshiftu:
6556 // No immediate versions of these to check for.
6563 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
6564 /// lowers them. As with the vector shift intrinsics, this is done during DAG
6565 /// combining instead of DAG legalizing because the build_vectors for 64-bit
6566 /// vector element shift counts are generally not legal, and it is hard to see
6567 /// their values after they get legalized to loads from a constant pool.
6568 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
6569 const ARMSubtarget *ST) {
6570 EVT VT = N->getValueType(0);
6572 // Nothing to be done for scalar shifts.
6573 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6574 if (!VT.isVector() || !TLI.isTypeLegal(VT))
6577 assert(ST->hasNEON() && "unexpected vector shift");
6580 switch (N->getOpcode()) {
6581 default: llvm_unreachable("unexpected shift opcode");
6584 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
6585 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
6586 DAG.getConstant(Cnt, MVT::i32));
6591 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
6592 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
6593 ARMISD::VSHRs : ARMISD::VSHRu);
6594 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
6595 DAG.getConstant(Cnt, MVT::i32));
6601 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
6602 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
6603 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
6604 const ARMSubtarget *ST) {
6605 SDValue N0 = N->getOperand(0);
6607 // Check for sign- and zero-extensions of vector extract operations of 8-
6608 // and 16-bit vector elements. NEON supports these directly. They are
6609 // handled during DAG combining because type legalization will promote them
6610 // to 32-bit types and it is messy to recognize the operations after that.
6611 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6612 SDValue Vec = N0.getOperand(0);
6613 SDValue Lane = N0.getOperand(1);
6614 EVT VT = N->getValueType(0);
6615 EVT EltVT = N0.getValueType();
6616 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6618 if (VT == MVT::i32 &&
6619 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
6620 TLI.isTypeLegal(Vec.getValueType()) &&
6621 isa<ConstantSDNode>(Lane)) {
6624 switch (N->getOpcode()) {
6625 default: llvm_unreachable("unexpected opcode");
6626 case ISD::SIGN_EXTEND:
6627 Opc = ARMISD::VGETLANEs;
6629 case ISD::ZERO_EXTEND:
6630 case ISD::ANY_EXTEND:
6631 Opc = ARMISD::VGETLANEu;
6634 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
6641 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
6642 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
6643 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
6644 const ARMSubtarget *ST) {
6645 // If the target supports NEON, try to use vmax/vmin instructions for f32
6646 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
6647 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
6648 // a NaN; only do the transformation when it matches that behavior.
6650 // For now only do this when using NEON for FP operations; if using VFP, it
6651 // is not obvious that the benefit outweighs the cost of switching to the
6653 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
6654 N->getValueType(0) != MVT::f32)
6657 SDValue CondLHS = N->getOperand(0);
6658 SDValue CondRHS = N->getOperand(1);
6659 SDValue LHS = N->getOperand(2);
6660 SDValue RHS = N->getOperand(3);
6661 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
6663 unsigned Opcode = 0;
6665 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
6666 IsReversed = false; // x CC y ? x : y
6667 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
6668 IsReversed = true ; // x CC y ? y : x
6682 // If LHS is NaN, an ordered comparison will be false and the result will
6683 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
6684 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6685 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
6686 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6688 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
6689 // will return -0, so vmin can only be used for unsafe math or if one of
6690 // the operands is known to be nonzero.
6691 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
6693 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6695 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
6704 // If LHS is NaN, an ordered comparison will be false and the result will
6705 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
6706 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6707 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
6708 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6710 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
6711 // will return +0, so vmax can only be used for unsafe math or if one of
6712 // the operands is known to be nonzero.
6713 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
6715 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6717 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
6723 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
6726 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
6727 DAGCombinerInfo &DCI) const {
6728 switch (N->getOpcode()) {
6730 case ISD::ADD: return PerformADDCombine(N, DCI);
6731 case ISD::SUB: return PerformSUBCombine(N, DCI);
6732 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
6733 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
6734 case ISD::AND: return PerformANDCombine(N, DCI);
6735 case ARMISD::BFI: return PerformBFICombine(N, DCI);
6736 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
6737 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
6738 case ISD::STORE: return PerformSTORECombine(N, DCI);
6739 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
6740 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
6741 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
6742 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
6743 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
6746 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
6747 case ISD::SIGN_EXTEND:
6748 case ISD::ZERO_EXTEND:
6749 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
6750 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
6751 case ARMISD::VLD2DUP:
6752 case ARMISD::VLD3DUP:
6753 case ARMISD::VLD4DUP:
6754 return CombineBaseUpdate(N, DCI);
6755 case ISD::INTRINSIC_VOID:
6756 case ISD::INTRINSIC_W_CHAIN:
6757 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
6758 case Intrinsic::arm_neon_vld1:
6759 case Intrinsic::arm_neon_vld2:
6760 case Intrinsic::arm_neon_vld3:
6761 case Intrinsic::arm_neon_vld4:
6762 case Intrinsic::arm_neon_vld2lane:
6763 case Intrinsic::arm_neon_vld3lane:
6764 case Intrinsic::arm_neon_vld4lane:
6765 case Intrinsic::arm_neon_vst1:
6766 case Intrinsic::arm_neon_vst2:
6767 case Intrinsic::arm_neon_vst3:
6768 case Intrinsic::arm_neon_vst4:
6769 case Intrinsic::arm_neon_vst2lane:
6770 case Intrinsic::arm_neon_vst3lane:
6771 case Intrinsic::arm_neon_vst4lane:
6772 return CombineBaseUpdate(N, DCI);
6780 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
6782 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
6785 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
6786 if (!Subtarget->allowsUnalignedMem())
6789 switch (VT.getSimpleVT().SimpleTy) {
6796 // FIXME: VLD1 etc with standard alignment is legal.
6800 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
6805 switch (VT.getSimpleVT().SimpleTy) {
6806 default: return false;
6821 if ((V & (Scale - 1)) != 0)
6824 return V == (V & ((1LL << 5) - 1));
6827 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
6828 const ARMSubtarget *Subtarget) {
6835 switch (VT.getSimpleVT().SimpleTy) {
6836 default: return false;
6841 // + imm12 or - imm8
6843 return V == (V & ((1LL << 8) - 1));
6844 return V == (V & ((1LL << 12) - 1));
6847 // Same as ARM mode. FIXME: NEON?
6848 if (!Subtarget->hasVFP2())
6853 return V == (V & ((1LL << 8) - 1));
6857 /// isLegalAddressImmediate - Return true if the integer value can be used
6858 /// as the offset of the target addressing mode for load / store of the
6860 static bool isLegalAddressImmediate(int64_t V, EVT VT,
6861 const ARMSubtarget *Subtarget) {
6868 if (Subtarget->isThumb1Only())
6869 return isLegalT1AddressImmediate(V, VT);
6870 else if (Subtarget->isThumb2())
6871 return isLegalT2AddressImmediate(V, VT, Subtarget);
6876 switch (VT.getSimpleVT().SimpleTy) {
6877 default: return false;
6882 return V == (V & ((1LL << 12) - 1));
6885 return V == (V & ((1LL << 8) - 1));
6888 if (!Subtarget->hasVFP2()) // FIXME: NEON?
6893 return V == (V & ((1LL << 8) - 1));
6897 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
6899 int Scale = AM.Scale;
6903 switch (VT.getSimpleVT().SimpleTy) {
6904 default: return false;
6913 return Scale == 2 || Scale == 4 || Scale == 8;
6916 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6920 // Note, we allow "void" uses (basically, uses that aren't loads or
6921 // stores), because arm allows folding a scale into many arithmetic
6922 // operations. This should be made more precise and revisited later.
6924 // Allow r << imm, but the imm has to be a multiple of two.
6925 if (Scale & 1) return false;
6926 return isPowerOf2_32(Scale);
6930 /// isLegalAddressingMode - Return true if the addressing mode represented
6931 /// by AM is legal for this target, for a load/store of the specified type.
6932 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
6933 const Type *Ty) const {
6934 EVT VT = getValueType(Ty, true);
6935 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
6938 // Can never fold addr of global into load/store.
6943 case 0: // no scale reg, must be "r+i" or "r", or "i".
6946 if (Subtarget->isThumb1Only())
6950 // ARM doesn't support any R+R*scale+imm addr modes.
6957 if (Subtarget->isThumb2())
6958 return isLegalT2ScaledAddressingMode(AM, VT);
6960 int Scale = AM.Scale;
6961 switch (VT.getSimpleVT().SimpleTy) {
6962 default: return false;
6966 if (Scale < 0) Scale = -Scale;
6970 return isPowerOf2_32(Scale & ~1);
6974 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6979 // Note, we allow "void" uses (basically, uses that aren't loads or
6980 // stores), because arm allows folding a scale into many arithmetic
6981 // operations. This should be made more precise and revisited later.
6983 // Allow r << imm, but the imm has to be a multiple of two.
6984 if (Scale & 1) return false;
6985 return isPowerOf2_32(Scale);
6992 /// isLegalICmpImmediate - Return true if the specified immediate is legal
6993 /// icmp immediate, that is the target has icmp instructions which can compare
6994 /// a register against the immediate without having to materialize the
6995 /// immediate into a register.
6996 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
6997 if (!Subtarget->isThumb())
6998 return ARM_AM::getSOImmVal(Imm) != -1;
6999 if (Subtarget->isThumb2())
7000 return ARM_AM::getT2SOImmVal(Imm) != -1;
7001 return Imm >= 0 && Imm <= 255;
7004 /// isLegalAddImmediate - Return true if the specified immediate is legal
7005 /// add immediate, that is the target has add instructions which can add
7006 /// a register with the immediate without having to materialize the
7007 /// immediate into a register.
7008 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
7009 return ARM_AM::getSOImmVal(Imm) != -1;
7012 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
7013 bool isSEXTLoad, SDValue &Base,
7014 SDValue &Offset, bool &isInc,
7015 SelectionDAG &DAG) {
7016 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7019 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
7021 Base = Ptr->getOperand(0);
7022 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7023 int RHSC = (int)RHS->getZExtValue();
7024 if (RHSC < 0 && RHSC > -256) {
7025 assert(Ptr->getOpcode() == ISD::ADD);
7027 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7031 isInc = (Ptr->getOpcode() == ISD::ADD);
7032 Offset = Ptr->getOperand(1);
7034 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
7036 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7037 int RHSC = (int)RHS->getZExtValue();
7038 if (RHSC < 0 && RHSC > -0x1000) {
7039 assert(Ptr->getOpcode() == ISD::ADD);
7041 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7042 Base = Ptr->getOperand(0);
7047 if (Ptr->getOpcode() == ISD::ADD) {
7049 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
7050 if (ShOpcVal != ARM_AM::no_shift) {
7051 Base = Ptr->getOperand(1);
7052 Offset = Ptr->getOperand(0);
7054 Base = Ptr->getOperand(0);
7055 Offset = Ptr->getOperand(1);
7060 isInc = (Ptr->getOpcode() == ISD::ADD);
7061 Base = Ptr->getOperand(0);
7062 Offset = Ptr->getOperand(1);
7066 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
7070 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
7071 bool isSEXTLoad, SDValue &Base,
7072 SDValue &Offset, bool &isInc,
7073 SelectionDAG &DAG) {
7074 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7077 Base = Ptr->getOperand(0);
7078 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7079 int RHSC = (int)RHS->getZExtValue();
7080 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
7081 assert(Ptr->getOpcode() == ISD::ADD);
7083 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7085 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
7086 isInc = Ptr->getOpcode() == ISD::ADD;
7087 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
7095 /// getPreIndexedAddressParts - returns true by value, base pointer and
7096 /// offset pointer and addressing mode by reference if the node's address
7097 /// can be legally represented as pre-indexed load / store address.
7099 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7101 ISD::MemIndexedMode &AM,
7102 SelectionDAG &DAG) const {
7103 if (Subtarget->isThumb1Only())
7108 bool isSEXTLoad = false;
7109 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7110 Ptr = LD->getBasePtr();
7111 VT = LD->getMemoryVT();
7112 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
7113 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7114 Ptr = ST->getBasePtr();
7115 VT = ST->getMemoryVT();
7120 bool isLegal = false;
7121 if (Subtarget->isThumb2())
7122 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
7123 Offset, isInc, DAG);
7125 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
7126 Offset, isInc, DAG);
7130 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
7134 /// getPostIndexedAddressParts - returns true by value, base pointer and
7135 /// offset pointer and addressing mode by reference if this node can be
7136 /// combined with a load / store to form a post-indexed load / store.
7137 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
7140 ISD::MemIndexedMode &AM,
7141 SelectionDAG &DAG) const {
7142 if (Subtarget->isThumb1Only())
7147 bool isSEXTLoad = false;
7148 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7149 VT = LD->getMemoryVT();
7150 Ptr = LD->getBasePtr();
7151 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
7152 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7153 VT = ST->getMemoryVT();
7154 Ptr = ST->getBasePtr();
7159 bool isLegal = false;
7160 if (Subtarget->isThumb2())
7161 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
7164 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
7170 // Swap base ptr and offset to catch more post-index load / store when
7171 // it's legal. In Thumb2 mode, offset must be an immediate.
7172 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
7173 !Subtarget->isThumb2())
7174 std::swap(Base, Offset);
7176 // Post-indexed load / store update the base pointer.
7181 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
7185 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7189 const SelectionDAG &DAG,
7190 unsigned Depth) const {
7191 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
7192 switch (Op.getOpcode()) {
7194 case ARMISD::CMOV: {
7195 // Bits are known zero/one if known on the LHS and RHS.
7196 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
7197 if (KnownZero == 0 && KnownOne == 0) return;
7199 APInt KnownZeroRHS, KnownOneRHS;
7200 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
7201 KnownZeroRHS, KnownOneRHS, Depth+1);
7202 KnownZero &= KnownZeroRHS;
7203 KnownOne &= KnownOneRHS;
7209 //===----------------------------------------------------------------------===//
7210 // ARM Inline Assembly Support
7211 //===----------------------------------------------------------------------===//
7213 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
7214 // Looking for "rev" which is V6+.
7215 if (!Subtarget->hasV6Ops())
7218 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
7219 std::string AsmStr = IA->getAsmString();
7220 SmallVector<StringRef, 4> AsmPieces;
7221 SplitString(AsmStr, AsmPieces, ";\n");
7223 switch (AsmPieces.size()) {
7224 default: return false;
7226 AsmStr = AsmPieces[0];
7228 SplitString(AsmStr, AsmPieces, " \t,");
7231 if (AsmPieces.size() == 3 &&
7232 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
7233 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
7234 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
7235 if (Ty && Ty->getBitWidth() == 32)
7236 return IntrinsicLowering::LowerToByteSwap(CI);
7244 /// getConstraintType - Given a constraint letter, return the type of
7245 /// constraint it is for this target.
7246 ARMTargetLowering::ConstraintType
7247 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
7248 if (Constraint.size() == 1) {
7249 switch (Constraint[0]) {
7251 case 'l': return C_RegisterClass;
7252 case 'w': return C_RegisterClass;
7255 return TargetLowering::getConstraintType(Constraint);
7258 /// Examine constraint type and operand type and determine a weight value.
7259 /// This object must already have been set up with the operand type
7260 /// and the current alternative constraint selected.
7261 TargetLowering::ConstraintWeight
7262 ARMTargetLowering::getSingleConstraintMatchWeight(
7263 AsmOperandInfo &info, const char *constraint) const {
7264 ConstraintWeight weight = CW_Invalid;
7265 Value *CallOperandVal = info.CallOperandVal;
7266 // If we don't have a value, we can't do a match,
7267 // but allow it at the lowest weight.
7268 if (CallOperandVal == NULL)
7270 const Type *type = CallOperandVal->getType();
7271 // Look at the constraint type.
7272 switch (*constraint) {
7274 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7277 if (type->isIntegerTy()) {
7278 if (Subtarget->isThumb())
7279 weight = CW_SpecificReg;
7281 weight = CW_Register;
7285 if (type->isFloatingPointTy())
7286 weight = CW_Register;
7292 std::pair<unsigned, const TargetRegisterClass*>
7293 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7295 if (Constraint.size() == 1) {
7296 // GCC ARM Constraint Letters
7297 switch (Constraint[0]) {
7299 if (Subtarget->isThumb())
7300 return std::make_pair(0U, ARM::tGPRRegisterClass);
7302 return std::make_pair(0U, ARM::GPRRegisterClass);
7304 return std::make_pair(0U, ARM::GPRRegisterClass);
7307 return std::make_pair(0U, ARM::SPRRegisterClass);
7308 if (VT.getSizeInBits() == 64)
7309 return std::make_pair(0U, ARM::DPRRegisterClass);
7310 if (VT.getSizeInBits() == 128)
7311 return std::make_pair(0U, ARM::QPRRegisterClass);
7315 if (StringRef("{cc}").equals_lower(Constraint))
7316 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
7318 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7321 std::vector<unsigned> ARMTargetLowering::
7322 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7324 if (Constraint.size() != 1)
7325 return std::vector<unsigned>();
7327 switch (Constraint[0]) { // GCC ARM Constraint Letters
7330 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
7331 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
7334 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
7335 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
7336 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
7337 ARM::R12, ARM::LR, 0);
7340 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
7341 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
7342 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
7343 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
7344 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
7345 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
7346 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
7347 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
7348 if (VT.getSizeInBits() == 64)
7349 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
7350 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
7351 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
7352 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
7353 if (VT.getSizeInBits() == 128)
7354 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
7355 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
7359 return std::vector<unsigned>();
7362 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7363 /// vector. If it is invalid, don't add anything to Ops.
7364 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7366 std::vector<SDValue>&Ops,
7367 SelectionDAG &DAG) const {
7368 SDValue Result(0, 0);
7370 switch (Constraint) {
7372 case 'I': case 'J': case 'K': case 'L':
7373 case 'M': case 'N': case 'O':
7374 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
7378 int64_t CVal64 = C->getSExtValue();
7379 int CVal = (int) CVal64;
7380 // None of these constraints allow values larger than 32 bits. Check
7381 // that the value fits in an int.
7385 switch (Constraint) {
7387 if (Subtarget->isThumb1Only()) {
7388 // This must be a constant between 0 and 255, for ADD
7390 if (CVal >= 0 && CVal <= 255)
7392 } else if (Subtarget->isThumb2()) {
7393 // A constant that can be used as an immediate value in a
7394 // data-processing instruction.
7395 if (ARM_AM::getT2SOImmVal(CVal) != -1)
7398 // A constant that can be used as an immediate value in a
7399 // data-processing instruction.
7400 if (ARM_AM::getSOImmVal(CVal) != -1)
7406 if (Subtarget->isThumb()) { // FIXME thumb2
7407 // This must be a constant between -255 and -1, for negated ADD
7408 // immediates. This can be used in GCC with an "n" modifier that
7409 // prints the negated value, for use with SUB instructions. It is
7410 // not useful otherwise but is implemented for compatibility.
7411 if (CVal >= -255 && CVal <= -1)
7414 // This must be a constant between -4095 and 4095. It is not clear
7415 // what this constraint is intended for. Implemented for
7416 // compatibility with GCC.
7417 if (CVal >= -4095 && CVal <= 4095)
7423 if (Subtarget->isThumb1Only()) {
7424 // A 32-bit value where only one byte has a nonzero value. Exclude
7425 // zero to match GCC. This constraint is used by GCC internally for
7426 // constants that can be loaded with a move/shift combination.
7427 // It is not useful otherwise but is implemented for compatibility.
7428 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
7430 } else if (Subtarget->isThumb2()) {
7431 // A constant whose bitwise inverse can be used as an immediate
7432 // value in a data-processing instruction. This can be used in GCC
7433 // with a "B" modifier that prints the inverted value, for use with
7434 // BIC and MVN instructions. It is not useful otherwise but is
7435 // implemented for compatibility.
7436 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
7439 // A constant whose bitwise inverse can be used as an immediate
7440 // value in a data-processing instruction. This can be used in GCC
7441 // with a "B" modifier that prints the inverted value, for use with
7442 // BIC and MVN instructions. It is not useful otherwise but is
7443 // implemented for compatibility.
7444 if (ARM_AM::getSOImmVal(~CVal) != -1)
7450 if (Subtarget->isThumb1Only()) {
7451 // This must be a constant between -7 and 7,
7452 // for 3-operand ADD/SUB immediate instructions.
7453 if (CVal >= -7 && CVal < 7)
7455 } else if (Subtarget->isThumb2()) {
7456 // A constant whose negation can be used as an immediate value in a
7457 // data-processing instruction. This can be used in GCC with an "n"
7458 // modifier that prints the negated value, for use with SUB
7459 // instructions. It is not useful otherwise but is implemented for
7461 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
7464 // A constant whose negation can be used as an immediate value in a
7465 // data-processing instruction. This can be used in GCC with an "n"
7466 // modifier that prints the negated value, for use with SUB
7467 // instructions. It is not useful otherwise but is implemented for
7469 if (ARM_AM::getSOImmVal(-CVal) != -1)
7475 if (Subtarget->isThumb()) { // FIXME thumb2
7476 // This must be a multiple of 4 between 0 and 1020, for
7477 // ADD sp + immediate.
7478 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
7481 // A power of two or a constant between 0 and 32. This is used in
7482 // GCC for the shift amount on shifted register operands, but it is
7483 // useful in general for any shift amounts.
7484 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
7490 if (Subtarget->isThumb()) { // FIXME thumb2
7491 // This must be a constant between 0 and 31, for shift amounts.
7492 if (CVal >= 0 && CVal <= 31)
7498 if (Subtarget->isThumb()) { // FIXME thumb2
7499 // This must be a multiple of 4 between -508 and 508, for
7500 // ADD/SUB sp = sp + immediate.
7501 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
7506 Result = DAG.getTargetConstant(CVal, Op.getValueType());
7510 if (Result.getNode()) {
7511 Ops.push_back(Result);
7514 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7518 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7519 // The ARM target isn't yet aware of offsets.
7523 int ARM::getVFPf32Imm(const APFloat &FPImm) {
7524 APInt Imm = FPImm.bitcastToAPInt();
7525 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
7526 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
7527 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
7529 // We can handle 4 bits of mantissa.
7530 // mantissa = (16+UInt(e:f:g:h))/16.
7531 if (Mantissa & 0x7ffff)
7534 if ((Mantissa & 0xf) != Mantissa)
7537 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7538 if (Exp < -3 || Exp > 4)
7540 Exp = ((Exp+3) & 0x7) ^ 4;
7542 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7545 int ARM::getVFPf64Imm(const APFloat &FPImm) {
7546 APInt Imm = FPImm.bitcastToAPInt();
7547 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
7548 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
7549 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
7551 // We can handle 4 bits of mantissa.
7552 // mantissa = (16+UInt(e:f:g:h))/16.
7553 if (Mantissa & 0xffffffffffffLL)
7556 if ((Mantissa & 0xf) != Mantissa)
7559 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7560 if (Exp < -3 || Exp > 4)
7562 Exp = ((Exp+3) & 0x7) ^ 4;
7564 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7567 bool ARM::isBitFieldInvertedMask(unsigned v) {
7568 if (v == 0xffffffff)
7570 // there can be 1's on either or both "outsides", all the "inside"
7572 unsigned int lsb = 0, msb = 31;
7573 while (v & (1 << msb)) --msb;
7574 while (v & (1 << lsb)) ++lsb;
7575 for (unsigned int i = lsb; i <= msb; ++i) {
7582 /// isFPImmLegal - Returns true if the target can instruction select the
7583 /// specified FP immediate natively. If false, the legalizer will
7584 /// materialize the FP immediate as a load from a constant pool.
7585 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
7586 if (!Subtarget->hasVFP3())
7589 return ARM::getVFPf32Imm(Imm) != -1;
7591 return ARM::getVFPf64Imm(Imm) != -1;
7595 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
7596 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
7597 /// specified in the intrinsic calls.
7598 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
7600 unsigned Intrinsic) const {
7601 switch (Intrinsic) {
7602 case Intrinsic::arm_neon_vld1:
7603 case Intrinsic::arm_neon_vld2:
7604 case Intrinsic::arm_neon_vld3:
7605 case Intrinsic::arm_neon_vld4:
7606 case Intrinsic::arm_neon_vld2lane:
7607 case Intrinsic::arm_neon_vld3lane:
7608 case Intrinsic::arm_neon_vld4lane: {
7609 Info.opc = ISD::INTRINSIC_W_CHAIN;
7610 // Conservatively set memVT to the entire set of vectors loaded.
7611 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
7612 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7613 Info.ptrVal = I.getArgOperand(0);
7615 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7616 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7617 Info.vol = false; // volatile loads with NEON intrinsics not supported
7618 Info.readMem = true;
7619 Info.writeMem = false;
7622 case Intrinsic::arm_neon_vst1:
7623 case Intrinsic::arm_neon_vst2:
7624 case Intrinsic::arm_neon_vst3:
7625 case Intrinsic::arm_neon_vst4:
7626 case Intrinsic::arm_neon_vst2lane:
7627 case Intrinsic::arm_neon_vst3lane:
7628 case Intrinsic::arm_neon_vst4lane: {
7629 Info.opc = ISD::INTRINSIC_VOID;
7630 // Conservatively set memVT to the entire set of vectors stored.
7631 unsigned NumElts = 0;
7632 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
7633 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
7634 if (!ArgTy->isVectorTy())
7636 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
7638 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7639 Info.ptrVal = I.getArgOperand(0);
7641 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7642 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7643 Info.vol = false; // volatile stores with NEON intrinsics not supported
7644 Info.readMem = false;
7645 Info.writeMem = true;