1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMPerfectShuffle.h"
21 #include "ARMRegisterInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Function.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Instruction.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Type.h"
32 #include "llvm/CodeGen/CallingConvLower.h"
33 #include "llvm/CodeGen/MachineBasicBlock.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/VectorExtras.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/raw_ostream.h"
49 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
53 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
54 CCValAssign::LocInfo &LocInfo,
55 ISD::ArgFlagsTy &ArgFlags,
57 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
58 CCValAssign::LocInfo &LocInfo,
59 ISD::ArgFlagsTy &ArgFlags,
61 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
62 CCValAssign::LocInfo &LocInfo,
63 ISD::ArgFlagsTy &ArgFlags,
66 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
67 EVT PromotedBitwiseVT) {
68 if (VT != PromotedLdStVT) {
69 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
70 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
71 PromotedLdStVT.getSimpleVT());
73 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
74 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
75 PromotedLdStVT.getSimpleVT());
78 EVT ElemTy = VT.getVectorElementType();
79 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
80 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
81 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
82 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
83 if (ElemTy != MVT::i32) {
84 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
85 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
86 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
87 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
89 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
90 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
91 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
92 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
99 // Promote all bit-wise operations.
100 if (VT.isInteger() && VT != PromotedBitwiseVT) {
101 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
102 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
103 PromotedBitwiseVT.getSimpleVT());
104 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
105 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
106 PromotedBitwiseVT.getSimpleVT());
107 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
108 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
109 PromotedBitwiseVT.getSimpleVT());
112 // Neon does not support vector divide/remainder operations.
113 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
116 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
117 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
118 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
121 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
122 addRegisterClass(VT, ARM::DPRRegisterClass);
123 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
126 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
127 addRegisterClass(VT, ARM::QPRRegisterClass);
128 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
131 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
132 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
133 return new TargetLoweringObjectFileMachO();
134 return new ARMElfTargetObjectFile();
137 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
138 : TargetLowering(TM, createTLOF(TM)) {
139 Subtarget = &TM.getSubtarget<ARMSubtarget>();
141 if (Subtarget->isTargetDarwin()) {
142 // Uses VFP for Thumb libfuncs if available.
143 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
144 // Single-precision floating-point arithmetic.
145 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
146 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
147 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
148 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
150 // Double-precision floating-point arithmetic.
151 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
152 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
153 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
154 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
156 // Single-precision comparisons.
157 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
158 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
159 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
160 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
161 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
162 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
163 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
164 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
166 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
167 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
168 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
169 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
170 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
171 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
172 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
173 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
175 // Double-precision comparisons.
176 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
177 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
178 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
179 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
180 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
181 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
182 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
183 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
185 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
194 // Floating-point to integer conversions.
195 // i64 conversions are done via library routines even when generating VFP
196 // instructions, so use the same ones.
197 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
198 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
199 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
200 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
202 // Conversions between floating types.
203 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
204 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
206 // Integer to floating-point conversions.
207 // i64 conversions are done via library routines even when generating VFP
208 // instructions, so use the same ones.
209 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
210 // e.g., __floatunsidf vs. __floatunssidfvfp.
211 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
212 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
213 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
214 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
218 // These libcalls are not available in 32-bit.
219 setLibcallName(RTLIB::SHL_I128, 0);
220 setLibcallName(RTLIB::SRL_I128, 0);
221 setLibcallName(RTLIB::SRA_I128, 0);
223 // Libcalls should use the AAPCS base standard ABI, even if hard float
224 // is in effect, as per the ARM RTABI specification, section 4.1.2.
225 if (Subtarget->isAAPCS_ABI()) {
226 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
227 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
228 CallingConv::ARM_AAPCS);
232 if (Subtarget->isThumb1Only())
233 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
235 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
236 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
237 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
238 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
240 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
243 if (Subtarget->hasNEON()) {
244 addDRTypeForNEON(MVT::v2f32);
245 addDRTypeForNEON(MVT::v8i8);
246 addDRTypeForNEON(MVT::v4i16);
247 addDRTypeForNEON(MVT::v2i32);
248 addDRTypeForNEON(MVT::v1i64);
250 addQRTypeForNEON(MVT::v4f32);
251 addQRTypeForNEON(MVT::v2f64);
252 addQRTypeForNEON(MVT::v16i8);
253 addQRTypeForNEON(MVT::v8i16);
254 addQRTypeForNEON(MVT::v4i32);
255 addQRTypeForNEON(MVT::v2i64);
257 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
258 // neither Neon nor VFP support any arithmetic operations on it.
259 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
260 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
261 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
262 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
263 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
264 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
265 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
266 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
267 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
268 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
269 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
270 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
271 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
272 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
273 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
274 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
275 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
276 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
277 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
278 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
279 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
280 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
281 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
282 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
284 // Neon does not support some operations on v1i64 and v2i64 types.
285 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
286 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
287 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
288 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
290 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
291 setTargetDAGCombine(ISD::SHL);
292 setTargetDAGCombine(ISD::SRL);
293 setTargetDAGCombine(ISD::SRA);
294 setTargetDAGCombine(ISD::SIGN_EXTEND);
295 setTargetDAGCombine(ISD::ZERO_EXTEND);
296 setTargetDAGCombine(ISD::ANY_EXTEND);
299 computeRegisterProperties();
301 // ARM does not have f32 extending load.
302 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
304 // ARM does not have i1 sign extending load.
305 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
307 // ARM supports all 4 flavors of integer indexed load / store.
308 if (!Subtarget->isThumb1Only()) {
309 for (unsigned im = (unsigned)ISD::PRE_INC;
310 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
311 setIndexedLoadAction(im, MVT::i1, Legal);
312 setIndexedLoadAction(im, MVT::i8, Legal);
313 setIndexedLoadAction(im, MVT::i16, Legal);
314 setIndexedLoadAction(im, MVT::i32, Legal);
315 setIndexedStoreAction(im, MVT::i1, Legal);
316 setIndexedStoreAction(im, MVT::i8, Legal);
317 setIndexedStoreAction(im, MVT::i16, Legal);
318 setIndexedStoreAction(im, MVT::i32, Legal);
322 // i64 operation support.
323 if (Subtarget->isThumb1Only()) {
324 setOperationAction(ISD::MUL, MVT::i64, Expand);
325 setOperationAction(ISD::MULHU, MVT::i32, Expand);
326 setOperationAction(ISD::MULHS, MVT::i32, Expand);
327 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
328 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
330 setOperationAction(ISD::MUL, MVT::i64, Expand);
331 setOperationAction(ISD::MULHU, MVT::i32, Expand);
332 if (!Subtarget->hasV6Ops())
333 setOperationAction(ISD::MULHS, MVT::i32, Expand);
335 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
336 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
337 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
338 setOperationAction(ISD::SRL, MVT::i64, Custom);
339 setOperationAction(ISD::SRA, MVT::i64, Custom);
341 // ARM does not have ROTL.
342 setOperationAction(ISD::ROTL, MVT::i32, Expand);
343 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
344 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
345 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
346 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
348 // Only ARMv6 has BSWAP.
349 if (!Subtarget->hasV6Ops())
350 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
352 // These are expanded into libcalls.
353 setOperationAction(ISD::SDIV, MVT::i32, Expand);
354 setOperationAction(ISD::UDIV, MVT::i32, Expand);
355 setOperationAction(ISD::SREM, MVT::i32, Expand);
356 setOperationAction(ISD::UREM, MVT::i32, Expand);
357 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
358 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
360 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
361 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
362 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
363 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
364 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
366 // Use the default implementation.
367 setOperationAction(ISD::VASTART, MVT::Other, Custom);
368 setOperationAction(ISD::VAARG, MVT::Other, Expand);
369 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
370 setOperationAction(ISD::VAEND, MVT::Other, Expand);
371 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
372 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
373 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
374 // FIXME: Shouldn't need this, since no register is used, but the legalizer
375 // doesn't yet know how to not do that for SjLj.
376 setExceptionSelectorRegister(ARM::R0);
377 if (Subtarget->isThumb())
378 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
380 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
381 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
383 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
384 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
387 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
389 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
390 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR iff target supports vfp2.
391 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
393 // We want to custom lower some of our intrinsics.
394 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
396 setOperationAction(ISD::SETCC, MVT::i32, Expand);
397 setOperationAction(ISD::SETCC, MVT::f32, Expand);
398 setOperationAction(ISD::SETCC, MVT::f64, Expand);
399 setOperationAction(ISD::SELECT, MVT::i32, Expand);
400 setOperationAction(ISD::SELECT, MVT::f32, Expand);
401 setOperationAction(ISD::SELECT, MVT::f64, Expand);
402 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
403 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
404 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
406 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
407 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
408 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
409 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
410 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
412 // We don't support sin/cos/fmod/copysign/pow
413 setOperationAction(ISD::FSIN, MVT::f64, Expand);
414 setOperationAction(ISD::FSIN, MVT::f32, Expand);
415 setOperationAction(ISD::FCOS, MVT::f32, Expand);
416 setOperationAction(ISD::FCOS, MVT::f64, Expand);
417 setOperationAction(ISD::FREM, MVT::f64, Expand);
418 setOperationAction(ISD::FREM, MVT::f32, Expand);
419 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
420 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
421 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
423 setOperationAction(ISD::FPOW, MVT::f64, Expand);
424 setOperationAction(ISD::FPOW, MVT::f32, Expand);
426 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
427 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
428 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
429 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
430 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
431 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
434 // We have target-specific dag combine patterns for the following nodes:
435 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
436 setTargetDAGCombine(ISD::ADD);
437 setTargetDAGCombine(ISD::SUB);
439 setStackPointerRegisterToSaveRestore(ARM::SP);
440 setSchedulingPreference(SchedulingForRegPressure);
442 // FIXME: If-converter should use instruction latency to determine
443 // profitability rather than relying on fixed limits.
444 if (Subtarget->getCPUString() == "generic") {
445 // Generic (and overly aggressive) if-conversion limits.
446 setIfCvtBlockSizeLimit(10);
447 setIfCvtDupBlockSizeLimit(2);
448 } else if (Subtarget->hasV6Ops()) {
449 setIfCvtBlockSizeLimit(2);
450 setIfCvtDupBlockSizeLimit(1);
452 setIfCvtBlockSizeLimit(3);
453 setIfCvtDupBlockSizeLimit(2);
456 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
457 // Do not enable CodePlacementOpt for now: it currently runs after the
458 // ARMConstantIslandPass and messes up branch relaxation and placement
459 // of constant islands.
460 // benefitFromCodePlacementOpt = true;
463 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
466 case ARMISD::Wrapper: return "ARMISD::Wrapper";
467 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
468 case ARMISD::CALL: return "ARMISD::CALL";
469 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
470 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
471 case ARMISD::tCALL: return "ARMISD::tCALL";
472 case ARMISD::BRCOND: return "ARMISD::BRCOND";
473 case ARMISD::BR_JT: return "ARMISD::BR_JT";
474 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
475 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
476 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
477 case ARMISD::CMP: return "ARMISD::CMP";
478 case ARMISD::CMPZ: return "ARMISD::CMPZ";
479 case ARMISD::CMPFP: return "ARMISD::CMPFP";
480 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
481 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
482 case ARMISD::CMOV: return "ARMISD::CMOV";
483 case ARMISD::CNEG: return "ARMISD::CNEG";
485 case ARMISD::FTOSI: return "ARMISD::FTOSI";
486 case ARMISD::FTOUI: return "ARMISD::FTOUI";
487 case ARMISD::SITOF: return "ARMISD::SITOF";
488 case ARMISD::UITOF: return "ARMISD::UITOF";
490 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
491 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
492 case ARMISD::RRX: return "ARMISD::RRX";
494 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
495 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
497 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
498 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
500 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
502 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
504 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
505 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
507 case ARMISD::VCEQ: return "ARMISD::VCEQ";
508 case ARMISD::VCGE: return "ARMISD::VCGE";
509 case ARMISD::VCGEU: return "ARMISD::VCGEU";
510 case ARMISD::VCGT: return "ARMISD::VCGT";
511 case ARMISD::VCGTU: return "ARMISD::VCGTU";
512 case ARMISD::VTST: return "ARMISD::VTST";
514 case ARMISD::VSHL: return "ARMISD::VSHL";
515 case ARMISD::VSHRs: return "ARMISD::VSHRs";
516 case ARMISD::VSHRu: return "ARMISD::VSHRu";
517 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
518 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
519 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
520 case ARMISD::VSHRN: return "ARMISD::VSHRN";
521 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
522 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
523 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
524 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
525 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
526 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
527 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
528 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
529 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
530 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
531 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
532 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
533 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
534 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
535 case ARMISD::VDUP: return "ARMISD::VDUP";
536 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
537 case ARMISD::VEXT: return "ARMISD::VEXT";
538 case ARMISD::VREV64: return "ARMISD::VREV64";
539 case ARMISD::VREV32: return "ARMISD::VREV32";
540 case ARMISD::VREV16: return "ARMISD::VREV16";
541 case ARMISD::VZIP: return "ARMISD::VZIP";
542 case ARMISD::VUZP: return "ARMISD::VUZP";
543 case ARMISD::VTRN: return "ARMISD::VTRN";
547 /// getFunctionAlignment - Return the Log2 alignment of this function.
548 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
549 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
552 //===----------------------------------------------------------------------===//
554 //===----------------------------------------------------------------------===//
556 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
557 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
559 default: llvm_unreachable("Unknown condition code!");
560 case ISD::SETNE: return ARMCC::NE;
561 case ISD::SETEQ: return ARMCC::EQ;
562 case ISD::SETGT: return ARMCC::GT;
563 case ISD::SETGE: return ARMCC::GE;
564 case ISD::SETLT: return ARMCC::LT;
565 case ISD::SETLE: return ARMCC::LE;
566 case ISD::SETUGT: return ARMCC::HI;
567 case ISD::SETUGE: return ARMCC::HS;
568 case ISD::SETULT: return ARMCC::LO;
569 case ISD::SETULE: return ARMCC::LS;
573 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
574 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
575 ARMCC::CondCodes &CondCode2) {
576 CondCode2 = ARMCC::AL;
578 default: llvm_unreachable("Unknown FP condition!");
580 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
582 case ISD::SETOGT: CondCode = ARMCC::GT; break;
584 case ISD::SETOGE: CondCode = ARMCC::GE; break;
585 case ISD::SETOLT: CondCode = ARMCC::MI; break;
586 case ISD::SETOLE: CondCode = ARMCC::LS; break;
587 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
588 case ISD::SETO: CondCode = ARMCC::VC; break;
589 case ISD::SETUO: CondCode = ARMCC::VS; break;
590 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
591 case ISD::SETUGT: CondCode = ARMCC::HI; break;
592 case ISD::SETUGE: CondCode = ARMCC::PL; break;
594 case ISD::SETULT: CondCode = ARMCC::LT; break;
596 case ISD::SETULE: CondCode = ARMCC::LE; break;
598 case ISD::SETUNE: CondCode = ARMCC::NE; break;
602 //===----------------------------------------------------------------------===//
603 // Calling Convention Implementation
604 //===----------------------------------------------------------------------===//
606 #include "ARMGenCallingConv.inc"
608 // APCS f64 is in register pairs, possibly split to stack
609 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
610 CCValAssign::LocInfo &LocInfo,
611 CCState &State, bool CanFail) {
612 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
614 // Try to get the first register.
615 if (unsigned Reg = State.AllocateReg(RegList, 4))
616 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
618 // For the 2nd half of a v2f64, do not fail.
622 // Put the whole thing on the stack.
623 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
624 State.AllocateStack(8, 4),
629 // Try to get the second register.
630 if (unsigned Reg = State.AllocateReg(RegList, 4))
631 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
633 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
634 State.AllocateStack(4, 4),
639 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
640 CCValAssign::LocInfo &LocInfo,
641 ISD::ArgFlagsTy &ArgFlags,
643 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
645 if (LocVT == MVT::v2f64 &&
646 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
648 return true; // we handled it
651 // AAPCS f64 is in aligned register pairs
652 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
653 CCValAssign::LocInfo &LocInfo,
654 CCState &State, bool CanFail) {
655 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
656 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
658 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
660 // For the 2nd half of a v2f64, do not just fail.
664 // Put the whole thing on the stack.
665 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
666 State.AllocateStack(8, 8),
672 for (i = 0; i < 2; ++i)
673 if (HiRegList[i] == Reg)
676 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
677 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
682 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
683 CCValAssign::LocInfo &LocInfo,
684 ISD::ArgFlagsTy &ArgFlags,
686 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
688 if (LocVT == MVT::v2f64 &&
689 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
691 return true; // we handled it
694 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
695 CCValAssign::LocInfo &LocInfo, CCState &State) {
696 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
697 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
699 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
701 return false; // we didn't handle it
704 for (i = 0; i < 2; ++i)
705 if (HiRegList[i] == Reg)
708 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
709 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
714 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
715 CCValAssign::LocInfo &LocInfo,
716 ISD::ArgFlagsTy &ArgFlags,
718 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
720 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
722 return true; // we handled it
725 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
726 CCValAssign::LocInfo &LocInfo,
727 ISD::ArgFlagsTy &ArgFlags,
729 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
733 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
734 /// given CallingConvention value.
735 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
737 bool isVarArg) const {
740 llvm_unreachable("Unsupported calling convention");
742 case CallingConv::Fast:
743 // Use target triple & subtarget features to do actual dispatch.
744 if (Subtarget->isAAPCS_ABI()) {
745 if (Subtarget->hasVFP2() &&
746 FloatABIType == FloatABI::Hard && !isVarArg)
747 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
749 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
751 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
752 case CallingConv::ARM_AAPCS_VFP:
753 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
754 case CallingConv::ARM_AAPCS:
755 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
756 case CallingConv::ARM_APCS:
757 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
761 /// LowerCallResult - Lower the result values of a call into the
762 /// appropriate copies out of appropriate physical registers.
764 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
765 CallingConv::ID CallConv, bool isVarArg,
766 const SmallVectorImpl<ISD::InputArg> &Ins,
767 DebugLoc dl, SelectionDAG &DAG,
768 SmallVectorImpl<SDValue> &InVals) {
770 // Assign locations to each value returned by this call.
771 SmallVector<CCValAssign, 16> RVLocs;
772 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
773 RVLocs, *DAG.getContext());
774 CCInfo.AnalyzeCallResult(Ins,
775 CCAssignFnForNode(CallConv, /* Return*/ true,
778 // Copy all of the result registers out of their specified physreg.
779 for (unsigned i = 0; i != RVLocs.size(); ++i) {
780 CCValAssign VA = RVLocs[i];
783 if (VA.needsCustom()) {
784 // Handle f64 or half of a v2f64.
785 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
787 Chain = Lo.getValue(1);
788 InFlag = Lo.getValue(2);
789 VA = RVLocs[++i]; // skip ahead to next loc
790 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
792 Chain = Hi.getValue(1);
793 InFlag = Hi.getValue(2);
794 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
796 if (VA.getLocVT() == MVT::v2f64) {
797 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
798 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
799 DAG.getConstant(0, MVT::i32));
801 VA = RVLocs[++i]; // skip ahead to next loc
802 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
803 Chain = Lo.getValue(1);
804 InFlag = Lo.getValue(2);
805 VA = RVLocs[++i]; // skip ahead to next loc
806 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
807 Chain = Hi.getValue(1);
808 InFlag = Hi.getValue(2);
809 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
810 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
811 DAG.getConstant(1, MVT::i32));
814 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
816 Chain = Val.getValue(1);
817 InFlag = Val.getValue(2);
820 switch (VA.getLocInfo()) {
821 default: llvm_unreachable("Unknown loc info!");
822 case CCValAssign::Full: break;
823 case CCValAssign::BCvt:
824 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
828 InVals.push_back(Val);
834 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
835 /// by "Src" to address "Dst" of size "Size". Alignment information is
836 /// specified by the specific parameter attribute. The copy will be passed as
837 /// a byval function parameter.
838 /// Sometimes what we are copying is the end of a larger object, the part that
839 /// does not fit in registers.
841 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
842 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
844 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
845 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
846 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
849 /// LowerMemOpCallTo - Store the argument to the stack.
851 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
852 SDValue StackPtr, SDValue Arg,
853 DebugLoc dl, SelectionDAG &DAG,
854 const CCValAssign &VA,
855 ISD::ArgFlagsTy Flags) {
856 unsigned LocMemOffset = VA.getLocMemOffset();
857 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
858 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
859 if (Flags.isByVal()) {
860 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
862 return DAG.getStore(Chain, dl, Arg, PtrOff,
863 PseudoSourceValue::getStack(), LocMemOffset);
866 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
867 SDValue Chain, SDValue &Arg,
868 RegsToPassVector &RegsToPass,
869 CCValAssign &VA, CCValAssign &NextVA,
871 SmallVector<SDValue, 8> &MemOpChains,
872 ISD::ArgFlagsTy Flags) {
874 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
875 DAG.getVTList(MVT::i32, MVT::i32), Arg);
876 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
878 if (NextVA.isRegLoc())
879 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
881 assert(NextVA.isMemLoc());
882 if (StackPtr.getNode() == 0)
883 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
885 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
891 /// LowerCall - Lowering a call into a callseq_start <-
892 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
895 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
896 CallingConv::ID CallConv, bool isVarArg,
898 const SmallVectorImpl<ISD::OutputArg> &Outs,
899 const SmallVectorImpl<ISD::InputArg> &Ins,
900 DebugLoc dl, SelectionDAG &DAG,
901 SmallVectorImpl<SDValue> &InVals) {
903 // Analyze operands of the call, assigning locations to each operand.
904 SmallVector<CCValAssign, 16> ArgLocs;
905 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
907 CCInfo.AnalyzeCallOperands(Outs,
908 CCAssignFnForNode(CallConv, /* Return*/ false,
911 // Get a count of how many bytes are to be pushed on the stack.
912 unsigned NumBytes = CCInfo.getNextStackOffset();
914 // Adjust the stack pointer for the new arguments...
915 // These operations are automatically eliminated by the prolog/epilog pass
916 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
918 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
920 RegsToPassVector RegsToPass;
921 SmallVector<SDValue, 8> MemOpChains;
923 // Walk the register/memloc assignments, inserting copies/loads. In the case
924 // of tail call optimization, arguments are handled later.
925 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
928 CCValAssign &VA = ArgLocs[i];
929 SDValue Arg = Outs[realArgIdx].Val;
930 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
932 // Promote the value if needed.
933 switch (VA.getLocInfo()) {
934 default: llvm_unreachable("Unknown loc info!");
935 case CCValAssign::Full: break;
936 case CCValAssign::SExt:
937 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
939 case CCValAssign::ZExt:
940 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
942 case CCValAssign::AExt:
943 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
945 case CCValAssign::BCvt:
946 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
950 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
951 if (VA.needsCustom()) {
952 if (VA.getLocVT() == MVT::v2f64) {
953 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
954 DAG.getConstant(0, MVT::i32));
955 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
956 DAG.getConstant(1, MVT::i32));
958 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
959 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
961 VA = ArgLocs[++i]; // skip ahead to next loc
963 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
964 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
966 assert(VA.isMemLoc());
967 if (StackPtr.getNode() == 0)
968 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
970 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
971 dl, DAG, VA, Flags));
974 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
975 StackPtr, MemOpChains, Flags);
977 } else if (VA.isRegLoc()) {
978 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
980 assert(VA.isMemLoc());
981 if (StackPtr.getNode() == 0)
982 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
984 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
985 dl, DAG, VA, Flags));
989 if (!MemOpChains.empty())
990 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
991 &MemOpChains[0], MemOpChains.size());
993 // Build a sequence of copy-to-reg nodes chained together with token chain
994 // and flag operands which copy the outgoing args into the appropriate regs.
996 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
997 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
998 RegsToPass[i].second, InFlag);
999 InFlag = Chain.getValue(1);
1002 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1003 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1004 // node so that legalize doesn't hack it.
1005 bool isDirect = false;
1006 bool isARMFunc = false;
1007 bool isLocalARMFunc = false;
1008 MachineFunction &MF = DAG.getMachineFunction();
1009 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1010 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1011 GlobalValue *GV = G->getGlobal();
1013 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1014 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1015 getTargetMachine().getRelocationModel() != Reloc::Static;
1016 isARMFunc = !Subtarget->isThumb() || isStub;
1017 // ARM call to a local ARM function is predicable.
1018 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
1019 // tBX takes a register source operand.
1020 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1021 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1022 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1025 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1026 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1027 Callee = DAG.getLoad(getPointerTy(), dl,
1028 DAG.getEntryNode(), CPAddr,
1029 PseudoSourceValue::getConstantPool(), 0);
1030 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1031 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1032 getPointerTy(), Callee, PICLabel);
1034 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
1035 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1037 bool isStub = Subtarget->isTargetDarwin() &&
1038 getTargetMachine().getRelocationModel() != Reloc::Static;
1039 isARMFunc = !Subtarget->isThumb() || isStub;
1040 // tBX takes a register source operand.
1041 const char *Sym = S->getSymbol();
1042 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1043 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1044 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1045 Sym, ARMPCLabelIndex, 4);
1046 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1047 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1048 Callee = DAG.getLoad(getPointerTy(), dl,
1049 DAG.getEntryNode(), CPAddr,
1050 PseudoSourceValue::getConstantPool(), 0);
1051 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1052 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1053 getPointerTy(), Callee, PICLabel);
1055 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1058 // FIXME: handle tail calls differently.
1060 if (Subtarget->isThumb()) {
1061 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1062 CallOpc = ARMISD::CALL_NOLINK;
1064 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1066 CallOpc = (isDirect || Subtarget->hasV5TOps())
1067 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1068 : ARMISD::CALL_NOLINK;
1070 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1071 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1072 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1073 InFlag = Chain.getValue(1);
1076 std::vector<SDValue> Ops;
1077 Ops.push_back(Chain);
1078 Ops.push_back(Callee);
1080 // Add argument registers to the end of the list so that they are known live
1082 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1083 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1084 RegsToPass[i].second.getValueType()));
1086 if (InFlag.getNode())
1087 Ops.push_back(InFlag);
1088 // Returns a chain and a flag for retval copy to use.
1089 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1090 &Ops[0], Ops.size());
1091 InFlag = Chain.getValue(1);
1093 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1094 DAG.getIntPtrConstant(0, true), InFlag);
1096 InFlag = Chain.getValue(1);
1098 // Handle result values, copying them out of physregs into vregs that we
1100 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1105 ARMTargetLowering::LowerReturn(SDValue Chain,
1106 CallingConv::ID CallConv, bool isVarArg,
1107 const SmallVectorImpl<ISD::OutputArg> &Outs,
1108 DebugLoc dl, SelectionDAG &DAG) {
1110 // CCValAssign - represent the assignment of the return value to a location.
1111 SmallVector<CCValAssign, 16> RVLocs;
1113 // CCState - Info about the registers and stack slots.
1114 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1117 // Analyze outgoing return values.
1118 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1121 // If this is the first return lowered for this function, add
1122 // the regs to the liveout set for the function.
1123 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1124 for (unsigned i = 0; i != RVLocs.size(); ++i)
1125 if (RVLocs[i].isRegLoc())
1126 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1131 // Copy the result values into the output registers.
1132 for (unsigned i = 0, realRVLocIdx = 0;
1134 ++i, ++realRVLocIdx) {
1135 CCValAssign &VA = RVLocs[i];
1136 assert(VA.isRegLoc() && "Can only return in registers!");
1138 SDValue Arg = Outs[realRVLocIdx].Val;
1140 switch (VA.getLocInfo()) {
1141 default: llvm_unreachable("Unknown loc info!");
1142 case CCValAssign::Full: break;
1143 case CCValAssign::BCvt:
1144 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1148 if (VA.needsCustom()) {
1149 if (VA.getLocVT() == MVT::v2f64) {
1150 // Extract the first half and return it in two registers.
1151 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1152 DAG.getConstant(0, MVT::i32));
1153 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1154 DAG.getVTList(MVT::i32, MVT::i32), Half);
1156 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1157 Flag = Chain.getValue(1);
1158 VA = RVLocs[++i]; // skip ahead to next loc
1159 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1160 HalfGPRs.getValue(1), Flag);
1161 Flag = Chain.getValue(1);
1162 VA = RVLocs[++i]; // skip ahead to next loc
1164 // Extract the 2nd half and fall through to handle it as an f64 value.
1165 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1166 DAG.getConstant(1, MVT::i32));
1168 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1170 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1171 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1172 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1173 Flag = Chain.getValue(1);
1174 VA = RVLocs[++i]; // skip ahead to next loc
1175 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1178 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1180 // Guarantee that all emitted copies are
1181 // stuck together, avoiding something bad.
1182 Flag = Chain.getValue(1);
1187 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1189 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1194 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1195 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1196 // one of the above mentioned nodes. It has to be wrapped because otherwise
1197 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1198 // be used to form addressing mode. These wrapped nodes will be selected
1200 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1201 EVT PtrVT = Op.getValueType();
1202 // FIXME there is no actual debug info here
1203 DebugLoc dl = Op.getDebugLoc();
1204 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1206 if (CP->isMachineConstantPoolEntry())
1207 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1208 CP->getAlignment());
1210 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1211 CP->getAlignment());
1212 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1215 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
1216 MachineFunction &MF = DAG.getMachineFunction();
1217 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1218 unsigned ARMPCLabelIndex = 0;
1219 DebugLoc DL = Op.getDebugLoc();
1220 EVT PtrVT = getPointerTy();
1221 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1222 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1224 if (RelocM == Reloc::Static) {
1225 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1227 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1228 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1229 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1230 ARMCP::CPBlockAddress,
1232 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1234 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1235 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1236 PseudoSourceValue::getConstantPool(), 0);
1237 if (RelocM == Reloc::Static)
1239 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1240 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1243 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1245 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1246 SelectionDAG &DAG) {
1247 DebugLoc dl = GA->getDebugLoc();
1248 EVT PtrVT = getPointerTy();
1249 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1250 MachineFunction &MF = DAG.getMachineFunction();
1251 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1252 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1253 ARMConstantPoolValue *CPV =
1254 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1255 ARMCP::CPValue, PCAdj, "tlsgd", true);
1256 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1257 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1258 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1259 PseudoSourceValue::getConstantPool(), 0);
1260 SDValue Chain = Argument.getValue(1);
1262 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1263 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1265 // call __tls_get_addr.
1268 Entry.Node = Argument;
1269 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1270 Args.push_back(Entry);
1271 // FIXME: is there useful debug info available here?
1272 std::pair<SDValue, SDValue> CallResult =
1273 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1274 false, false, false, false,
1275 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1276 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1277 return CallResult.first;
1280 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1281 // "local exec" model.
1283 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1284 SelectionDAG &DAG) {
1285 GlobalValue *GV = GA->getGlobal();
1286 DebugLoc dl = GA->getDebugLoc();
1288 SDValue Chain = DAG.getEntryNode();
1289 EVT PtrVT = getPointerTy();
1290 // Get the Thread Pointer
1291 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1293 if (GV->isDeclaration()) {
1294 MachineFunction &MF = DAG.getMachineFunction();
1295 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1296 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1297 // Initial exec model.
1298 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1299 ARMConstantPoolValue *CPV =
1300 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1301 ARMCP::CPValue, PCAdj, "gottpoff", true);
1302 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1303 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1304 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1305 PseudoSourceValue::getConstantPool(), 0);
1306 Chain = Offset.getValue(1);
1308 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1309 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1311 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1312 PseudoSourceValue::getConstantPool(), 0);
1315 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1316 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1317 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1318 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1319 PseudoSourceValue::getConstantPool(), 0);
1322 // The address of the thread local variable is the add of the thread
1323 // pointer with the offset of the variable.
1324 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1328 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1329 // TODO: implement the "local dynamic" model
1330 assert(Subtarget->isTargetELF() &&
1331 "TLS not implemented for non-ELF targets");
1332 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1333 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1334 // otherwise use the "Local Exec" TLS Model
1335 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1336 return LowerToTLSGeneralDynamicModel(GA, DAG);
1338 return LowerToTLSExecModels(GA, DAG);
1341 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1342 SelectionDAG &DAG) {
1343 EVT PtrVT = getPointerTy();
1344 DebugLoc dl = Op.getDebugLoc();
1345 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1346 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1347 if (RelocM == Reloc::PIC_) {
1348 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1349 ARMConstantPoolValue *CPV =
1350 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1351 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1352 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1353 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1355 PseudoSourceValue::getConstantPool(), 0);
1356 SDValue Chain = Result.getValue(1);
1357 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1358 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1360 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1361 PseudoSourceValue::getGOT(), 0);
1364 // If we have T2 ops, we can materialize the address directly via movt/movw
1365 // pair. This is always cheaper.
1366 if (Subtarget->useMovt()) {
1367 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1368 DAG.getTargetGlobalAddress(GV, PtrVT));
1370 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1371 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1372 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1373 PseudoSourceValue::getConstantPool(), 0);
1378 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1379 SelectionDAG &DAG) {
1380 MachineFunction &MF = DAG.getMachineFunction();
1381 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1382 unsigned ARMPCLabelIndex = 0;
1383 EVT PtrVT = getPointerTy();
1384 DebugLoc dl = Op.getDebugLoc();
1385 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1386 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1388 if (RelocM == Reloc::Static)
1389 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1391 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1392 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1393 ARMConstantPoolValue *CPV =
1394 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1395 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1397 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1399 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1400 PseudoSourceValue::getConstantPool(), 0);
1401 SDValue Chain = Result.getValue(1);
1403 if (RelocM == Reloc::PIC_) {
1404 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1405 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1408 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1409 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1410 PseudoSourceValue::getGOT(), 0);
1415 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1417 assert(Subtarget->isTargetELF() &&
1418 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1419 MachineFunction &MF = DAG.getMachineFunction();
1420 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1421 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1422 EVT PtrVT = getPointerTy();
1423 DebugLoc dl = Op.getDebugLoc();
1424 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1425 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1426 "_GLOBAL_OFFSET_TABLE_",
1427 ARMPCLabelIndex, PCAdj);
1428 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1429 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1430 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1431 PseudoSourceValue::getConstantPool(), 0);
1432 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1433 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1437 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1438 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1439 DebugLoc dl = Op.getDebugLoc();
1441 default: return SDValue(); // Don't custom lower most intrinsics.
1442 case Intrinsic::arm_thread_pointer: {
1443 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1444 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1446 case Intrinsic::eh_sjlj_lsda: {
1447 MachineFunction &MF = DAG.getMachineFunction();
1448 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1449 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1450 EVT PtrVT = getPointerTy();
1451 DebugLoc dl = Op.getDebugLoc();
1452 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1454 unsigned PCAdj = (RelocM != Reloc::PIC_)
1455 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1456 ARMConstantPoolValue *CPV =
1457 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1458 ARMCP::CPLSDA, PCAdj);
1459 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1460 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1462 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1463 PseudoSourceValue::getConstantPool(), 0);
1464 SDValue Chain = Result.getValue(1);
1466 if (RelocM == Reloc::PIC_) {
1467 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1468 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1472 case Intrinsic::eh_sjlj_setjmp:
1473 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1477 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1478 const ARMSubtarget *Subtarget) {
1479 DebugLoc dl = Op.getDebugLoc();
1480 SDValue Op5 = Op.getOperand(5);
1482 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1483 if (isDeviceBarrier) {
1484 if (Subtarget->hasV7Ops())
1485 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0));
1487 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0),
1488 DAG.getConstant(0, MVT::i32));
1490 if (Subtarget->hasV7Ops())
1491 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
1493 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
1494 DAG.getConstant(0, MVT::i32));
1499 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1500 unsigned VarArgsFrameIndex) {
1501 // vastart just stores the address of the VarArgsFrameIndex slot into the
1502 // memory location argument.
1503 DebugLoc dl = Op.getDebugLoc();
1504 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1505 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1506 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1507 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1511 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1512 SDNode *Node = Op.getNode();
1513 DebugLoc dl = Node->getDebugLoc();
1514 EVT VT = Node->getValueType(0);
1515 SDValue Chain = Op.getOperand(0);
1516 SDValue Size = Op.getOperand(1);
1517 SDValue Align = Op.getOperand(2);
1519 // Chain the dynamic stack allocation so that it doesn't modify the stack
1520 // pointer when other instructions are using the stack.
1521 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1523 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1524 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1525 if (AlignVal > StackAlign)
1526 // Do this now since selection pass cannot introduce new target
1527 // independent node.
1528 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1530 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1531 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1532 // do even more horrible hack later.
1533 MachineFunction &MF = DAG.getMachineFunction();
1534 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1535 if (AFI->isThumb1OnlyFunction()) {
1537 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1539 uint32_t Val = C->getZExtValue();
1540 if (Val <= 508 && ((Val & 3) == 0))
1544 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1547 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1548 SDValue Ops1[] = { Chain, Size, Align };
1549 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1550 Chain = Res.getValue(1);
1551 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1552 DAG.getIntPtrConstant(0, true), SDValue());
1553 SDValue Ops2[] = { Res, Chain };
1554 return DAG.getMergeValues(Ops2, 2, dl);
1558 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1559 SDValue &Root, SelectionDAG &DAG,
1561 MachineFunction &MF = DAG.getMachineFunction();
1562 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1564 TargetRegisterClass *RC;
1565 if (AFI->isThumb1OnlyFunction())
1566 RC = ARM::tGPRRegisterClass;
1568 RC = ARM::GPRRegisterClass;
1570 // Transform the arguments stored in physical registers into virtual ones.
1571 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1572 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1575 if (NextVA.isMemLoc()) {
1576 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1577 MachineFrameInfo *MFI = MF.getFrameInfo();
1578 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset(),
1581 // Create load node to retrieve arguments from the stack.
1582 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1583 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
1584 PseudoSourceValue::getFixedStack(FI), 0);
1586 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1587 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1590 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
1594 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1595 CallingConv::ID CallConv, bool isVarArg,
1596 const SmallVectorImpl<ISD::InputArg>
1598 DebugLoc dl, SelectionDAG &DAG,
1599 SmallVectorImpl<SDValue> &InVals) {
1601 MachineFunction &MF = DAG.getMachineFunction();
1602 MachineFrameInfo *MFI = MF.getFrameInfo();
1604 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1606 // Assign locations to all of the incoming arguments.
1607 SmallVector<CCValAssign, 16> ArgLocs;
1608 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1610 CCInfo.AnalyzeFormalArguments(Ins,
1611 CCAssignFnForNode(CallConv, /* Return*/ false,
1614 SmallVector<SDValue, 16> ArgValues;
1616 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1617 CCValAssign &VA = ArgLocs[i];
1619 // Arguments stored in registers.
1620 if (VA.isRegLoc()) {
1621 EVT RegVT = VA.getLocVT();
1624 if (VA.needsCustom()) {
1625 // f64 and vector types are split up into multiple registers or
1626 // combinations of registers and stack slots.
1629 if (VA.getLocVT() == MVT::v2f64) {
1630 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1632 VA = ArgLocs[++i]; // skip ahead to next loc
1633 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1635 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1636 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1637 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1638 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1639 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1641 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1644 TargetRegisterClass *RC;
1646 if (RegVT == MVT::f32)
1647 RC = ARM::SPRRegisterClass;
1648 else if (RegVT == MVT::f64)
1649 RC = ARM::DPRRegisterClass;
1650 else if (RegVT == MVT::v2f64)
1651 RC = ARM::QPRRegisterClass;
1652 else if (RegVT == MVT::i32)
1653 RC = (AFI->isThumb1OnlyFunction() ?
1654 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1656 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1658 // Transform the arguments in physical registers into virtual ones.
1659 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1660 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1663 // If this is an 8 or 16-bit value, it is really passed promoted
1664 // to 32 bits. Insert an assert[sz]ext to capture this, then
1665 // truncate to the right size.
1666 switch (VA.getLocInfo()) {
1667 default: llvm_unreachable("Unknown loc info!");
1668 case CCValAssign::Full: break;
1669 case CCValAssign::BCvt:
1670 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1672 case CCValAssign::SExt:
1673 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1674 DAG.getValueType(VA.getValVT()));
1675 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1677 case CCValAssign::ZExt:
1678 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1679 DAG.getValueType(VA.getValVT()));
1680 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1684 InVals.push_back(ArgValue);
1686 } else { // VA.isRegLoc()
1689 assert(VA.isMemLoc());
1690 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1692 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1693 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1696 // Create load nodes to retrieve arguments from the stack.
1697 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1698 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1699 PseudoSourceValue::getFixedStack(FI), 0));
1705 static const unsigned GPRArgRegs[] = {
1706 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1709 unsigned NumGPRs = CCInfo.getFirstUnallocated
1710 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1712 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1713 unsigned VARegSize = (4 - NumGPRs) * 4;
1714 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1715 unsigned ArgOffset = CCInfo.getNextStackOffset();
1716 if (VARegSaveSize) {
1717 // If this function is vararg, store any remaining integer argument regs
1718 // to their spots on the stack so that they may be loaded by deferencing
1719 // the result of va_next.
1720 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1721 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1722 VARegSaveSize - VARegSize,
1724 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1726 SmallVector<SDValue, 4> MemOps;
1727 for (; NumGPRs < 4; ++NumGPRs) {
1728 TargetRegisterClass *RC;
1729 if (AFI->isThumb1OnlyFunction())
1730 RC = ARM::tGPRRegisterClass;
1732 RC = ARM::GPRRegisterClass;
1734 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1735 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1736 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1737 PseudoSourceValue::getFixedStack(VarArgsFrameIndex), 0);
1738 MemOps.push_back(Store);
1739 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1740 DAG.getConstant(4, getPointerTy()));
1742 if (!MemOps.empty())
1743 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1744 &MemOps[0], MemOps.size());
1746 // This will point to the next argument passed via stack.
1747 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset, true, false);
1753 /// isFloatingPointZero - Return true if this is +0.0.
1754 static bool isFloatingPointZero(SDValue Op) {
1755 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1756 return CFP->getValueAPF().isPosZero();
1757 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1758 // Maybe this has already been legalized into the constant pool?
1759 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1760 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1761 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1762 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1763 return CFP->getValueAPF().isPosZero();
1769 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1770 /// the given operands.
1772 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1773 SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) {
1774 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1775 unsigned C = RHSC->getZExtValue();
1776 if (!isLegalICmpImmediate(C)) {
1777 // Constant does not fit, try adjusting it by one?
1782 if (isLegalICmpImmediate(C-1)) {
1783 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1784 RHS = DAG.getConstant(C-1, MVT::i32);
1789 if (C > 0 && isLegalICmpImmediate(C-1)) {
1790 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1791 RHS = DAG.getConstant(C-1, MVT::i32);
1796 if (isLegalICmpImmediate(C+1)) {
1797 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1798 RHS = DAG.getConstant(C+1, MVT::i32);
1803 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
1804 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1805 RHS = DAG.getConstant(C+1, MVT::i32);
1812 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1813 ARMISD::NodeType CompareType;
1816 CompareType = ARMISD::CMP;
1821 CompareType = ARMISD::CMPZ;
1824 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1825 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1828 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1829 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1832 if (!isFloatingPointZero(RHS))
1833 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1835 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1836 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1839 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1840 EVT VT = Op.getValueType();
1841 SDValue LHS = Op.getOperand(0);
1842 SDValue RHS = Op.getOperand(1);
1843 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1844 SDValue TrueVal = Op.getOperand(2);
1845 SDValue FalseVal = Op.getOperand(3);
1846 DebugLoc dl = Op.getDebugLoc();
1848 if (LHS.getValueType() == MVT::i32) {
1850 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1851 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
1852 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1855 ARMCC::CondCodes CondCode, CondCode2;
1856 FPCCToARMCC(CC, CondCode, CondCode2);
1858 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1859 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1860 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1861 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1863 if (CondCode2 != ARMCC::AL) {
1864 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1865 // FIXME: Needs another CMP because flag can have but one use.
1866 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1867 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1868 Result, TrueVal, ARMCC2, CCR, Cmp2);
1873 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1874 SDValue Chain = Op.getOperand(0);
1875 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1876 SDValue LHS = Op.getOperand(2);
1877 SDValue RHS = Op.getOperand(3);
1878 SDValue Dest = Op.getOperand(4);
1879 DebugLoc dl = Op.getDebugLoc();
1881 if (LHS.getValueType() == MVT::i32) {
1883 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1884 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
1885 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1886 Chain, Dest, ARMCC, CCR,Cmp);
1889 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1890 ARMCC::CondCodes CondCode, CondCode2;
1891 FPCCToARMCC(CC, CondCode, CondCode2);
1893 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1894 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1895 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1896 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1897 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1898 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1899 if (CondCode2 != ARMCC::AL) {
1900 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1901 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1902 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1907 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1908 SDValue Chain = Op.getOperand(0);
1909 SDValue Table = Op.getOperand(1);
1910 SDValue Index = Op.getOperand(2);
1911 DebugLoc dl = Op.getDebugLoc();
1913 EVT PTy = getPointerTy();
1914 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1915 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1916 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1917 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1918 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1919 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1920 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1921 if (Subtarget->isThumb2()) {
1922 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1923 // which does another jump to the destination. This also makes it easier
1924 // to translate it to TBB / TBH later.
1925 // FIXME: This might not work if the function is extremely large.
1926 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1927 Addr, Op.getOperand(2), JTI, UId);
1929 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1930 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
1931 PseudoSourceValue::getJumpTable(), 0);
1932 Chain = Addr.getValue(1);
1933 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1934 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1936 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
1937 PseudoSourceValue::getJumpTable(), 0);
1938 Chain = Addr.getValue(1);
1939 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1943 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1944 DebugLoc dl = Op.getDebugLoc();
1946 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1947 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1948 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1951 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1952 EVT VT = Op.getValueType();
1953 DebugLoc dl = Op.getDebugLoc();
1955 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1957 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1958 return DAG.getNode(Opc, dl, VT, Op);
1961 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1962 // Implement fcopysign with a fabs and a conditional fneg.
1963 SDValue Tmp0 = Op.getOperand(0);
1964 SDValue Tmp1 = Op.getOperand(1);
1965 DebugLoc dl = Op.getDebugLoc();
1966 EVT VT = Op.getValueType();
1967 EVT SrcVT = Tmp1.getValueType();
1968 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1969 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1970 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1971 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1972 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1975 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1976 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1977 MFI->setFrameAddressIsTaken(true);
1978 EVT VT = Op.getValueType();
1979 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1980 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1981 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1982 ? ARM::R7 : ARM::R11;
1983 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1985 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1990 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1992 SDValue Dst, SDValue Src,
1993 SDValue Size, unsigned Align,
1995 const Value *DstSV, uint64_t DstSVOff,
1996 const Value *SrcSV, uint64_t SrcSVOff){
1997 // Do repeated 4-byte loads and stores. To be improved.
1998 // This requires 4-byte alignment.
1999 if ((Align & 3) != 0)
2001 // This requires the copy size to be a constant, preferrably
2002 // within a subtarget-specific limit.
2003 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
2006 uint64_t SizeVal = ConstantSize->getZExtValue();
2007 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
2010 unsigned BytesLeft = SizeVal & 3;
2011 unsigned NumMemOps = SizeVal >> 2;
2012 unsigned EmittedNumMemOps = 0;
2014 unsigned VTSize = 4;
2016 const unsigned MAX_LOADS_IN_LDM = 6;
2017 SDValue TFOps[MAX_LOADS_IN_LDM];
2018 SDValue Loads[MAX_LOADS_IN_LDM];
2019 uint64_t SrcOff = 0, DstOff = 0;
2021 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
2022 // same number of stores. The loads and stores will get combined into
2023 // ldm/stm later on.
2024 while (EmittedNumMemOps < NumMemOps) {
2026 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
2027 Loads[i] = DAG.getLoad(VT, dl, Chain,
2028 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2029 DAG.getConstant(SrcOff, MVT::i32)),
2030 SrcSV, SrcSVOff + SrcOff);
2031 TFOps[i] = Loads[i].getValue(1);
2034 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2037 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
2038 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2039 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2040 DAG.getConstant(DstOff, MVT::i32)),
2041 DstSV, DstSVOff + DstOff);
2044 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2046 EmittedNumMemOps += i;
2052 // Issue loads / stores for the trailing (1 - 3) bytes.
2053 unsigned BytesLeftSave = BytesLeft;
2056 if (BytesLeft >= 2) {
2064 Loads[i] = DAG.getLoad(VT, dl, Chain,
2065 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2066 DAG.getConstant(SrcOff, MVT::i32)),
2067 SrcSV, SrcSVOff + SrcOff);
2068 TFOps[i] = Loads[i].getValue(1);
2071 BytesLeft -= VTSize;
2073 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2076 BytesLeft = BytesLeftSave;
2078 if (BytesLeft >= 2) {
2086 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2087 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2088 DAG.getConstant(DstOff, MVT::i32)),
2089 DstSV, DstSVOff + DstOff);
2092 BytesLeft -= VTSize;
2094 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2097 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2098 SDValue Op = N->getOperand(0);
2099 DebugLoc dl = N->getDebugLoc();
2100 if (N->getValueType(0) == MVT::f64) {
2101 // Turn i64->f64 into VMOVDRR.
2102 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2103 DAG.getConstant(0, MVT::i32));
2104 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2105 DAG.getConstant(1, MVT::i32));
2106 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2109 // Turn f64->i64 into VMOVRRD.
2110 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2111 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2113 // Merge the pieces into a single i64 value.
2114 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2117 /// getZeroVector - Returns a vector of specified type with all zero elements.
2119 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2120 assert(VT.isVector() && "Expected a vector type");
2122 // Zero vectors are used to represent vector negation and in those cases
2123 // will be implemented with the NEON VNEG instruction. However, VNEG does
2124 // not support i64 elements, so sometimes the zero vectors will need to be
2125 // explicitly constructed. For those cases, and potentially other uses in
2126 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
2127 // to their dest type. This ensures they get CSE'd.
2129 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2130 SmallVector<SDValue, 8> Ops;
2133 if (VT.getSizeInBits() == 64) {
2134 Ops.assign(8, Cst); TVT = MVT::v8i8;
2136 Ops.assign(16, Cst); TVT = MVT::v16i8;
2138 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2140 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2143 /// getOnesVector - Returns a vector of specified type with all bits set.
2145 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2146 assert(VT.isVector() && "Expected a vector type");
2148 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their
2149 // dest type. This ensures they get CSE'd.
2151 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2152 SmallVector<SDValue, 8> Ops;
2155 if (VT.getSizeInBits() == 64) {
2156 Ops.assign(8, Cst); TVT = MVT::v8i8;
2158 Ops.assign(16, Cst); TVT = MVT::v16i8;
2160 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2162 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2165 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2166 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2167 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) {
2168 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2169 EVT VT = Op.getValueType();
2170 unsigned VTBits = VT.getSizeInBits();
2171 DebugLoc dl = Op.getDebugLoc();
2172 SDValue ShOpLo = Op.getOperand(0);
2173 SDValue ShOpHi = Op.getOperand(1);
2174 SDValue ShAmt = Op.getOperand(2);
2176 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2178 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2180 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2181 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2182 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2183 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2184 DAG.getConstant(VTBits, MVT::i32));
2185 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2186 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2187 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2189 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2190 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2192 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2193 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
2196 SDValue Ops[2] = { Lo, Hi };
2197 return DAG.getMergeValues(Ops, 2, dl);
2200 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2201 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2202 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) {
2203 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2204 EVT VT = Op.getValueType();
2205 unsigned VTBits = VT.getSizeInBits();
2206 DebugLoc dl = Op.getDebugLoc();
2207 SDValue ShOpLo = Op.getOperand(0);
2208 SDValue ShOpHi = Op.getOperand(1);
2209 SDValue ShAmt = Op.getOperand(2);
2212 assert(Op.getOpcode() == ISD::SHL_PARTS);
2213 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2214 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2215 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2216 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2217 DAG.getConstant(VTBits, MVT::i32));
2218 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2219 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2221 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2222 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2223 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2225 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2226 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
2229 SDValue Ops[2] = { Lo, Hi };
2230 return DAG.getMergeValues(Ops, 2, dl);
2233 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2234 const ARMSubtarget *ST) {
2235 EVT VT = N->getValueType(0);
2236 DebugLoc dl = N->getDebugLoc();
2238 // Lower vector shifts on NEON to use VSHL.
2239 if (VT.isVector()) {
2240 assert(ST->hasNEON() && "unexpected vector shift");
2242 // Left shifts translate directly to the vshiftu intrinsic.
2243 if (N->getOpcode() == ISD::SHL)
2244 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2245 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2246 N->getOperand(0), N->getOperand(1));
2248 assert((N->getOpcode() == ISD::SRA ||
2249 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2251 // NEON uses the same intrinsics for both left and right shifts. For
2252 // right shifts, the shift amounts are negative, so negate the vector of
2254 EVT ShiftVT = N->getOperand(1).getValueType();
2255 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2256 getZeroVector(ShiftVT, DAG, dl),
2258 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2259 Intrinsic::arm_neon_vshifts :
2260 Intrinsic::arm_neon_vshiftu);
2261 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2262 DAG.getConstant(vshiftInt, MVT::i32),
2263 N->getOperand(0), NegatedCount);
2266 // We can get here for a node like i32 = ISD::SHL i32, i64
2270 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2271 "Unknown shift to lower!");
2273 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2274 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2275 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2278 // If we are in thumb mode, we don't have RRX.
2279 if (ST->isThumb1Only()) return SDValue();
2281 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2282 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2283 DAG.getConstant(0, MVT::i32));
2284 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2285 DAG.getConstant(1, MVT::i32));
2287 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2288 // captures the result into a carry flag.
2289 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2290 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2292 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2293 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2295 // Merge the pieces into a single i64 value.
2296 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2299 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2300 SDValue TmpOp0, TmpOp1;
2301 bool Invert = false;
2305 SDValue Op0 = Op.getOperand(0);
2306 SDValue Op1 = Op.getOperand(1);
2307 SDValue CC = Op.getOperand(2);
2308 EVT VT = Op.getValueType();
2309 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2310 DebugLoc dl = Op.getDebugLoc();
2312 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2313 switch (SetCCOpcode) {
2314 default: llvm_unreachable("Illegal FP comparison"); break;
2316 case ISD::SETNE: Invert = true; // Fallthrough
2318 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2320 case ISD::SETLT: Swap = true; // Fallthrough
2322 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2324 case ISD::SETLE: Swap = true; // Fallthrough
2326 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2327 case ISD::SETUGE: Swap = true; // Fallthrough
2328 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2329 case ISD::SETUGT: Swap = true; // Fallthrough
2330 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2331 case ISD::SETUEQ: Invert = true; // Fallthrough
2333 // Expand this to (OLT | OGT).
2337 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2338 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2340 case ISD::SETUO: Invert = true; // Fallthrough
2342 // Expand this to (OLT | OGE).
2346 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2347 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2351 // Integer comparisons.
2352 switch (SetCCOpcode) {
2353 default: llvm_unreachable("Illegal integer comparison"); break;
2354 case ISD::SETNE: Invert = true;
2355 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2356 case ISD::SETLT: Swap = true;
2357 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2358 case ISD::SETLE: Swap = true;
2359 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2360 case ISD::SETULT: Swap = true;
2361 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2362 case ISD::SETULE: Swap = true;
2363 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2366 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2367 if (Opc == ARMISD::VCEQ) {
2370 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2372 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2375 // Ignore bitconvert.
2376 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2377 AndOp = AndOp.getOperand(0);
2379 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2381 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2382 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2389 std::swap(Op0, Op1);
2391 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2394 Result = DAG.getNOT(dl, Result, VT);
2399 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2400 /// VMOV instruction, and if so, return the constant being splatted.
2401 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2402 unsigned SplatBitSize, SelectionDAG &DAG) {
2403 switch (SplatBitSize) {
2405 // Any 1-byte value is OK.
2406 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2407 return DAG.getTargetConstant(SplatBits, MVT::i8);
2410 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2411 if ((SplatBits & ~0xff) == 0 ||
2412 (SplatBits & ~0xff00) == 0)
2413 return DAG.getTargetConstant(SplatBits, MVT::i16);
2417 // NEON's 32-bit VMOV supports splat values where:
2418 // * only one byte is nonzero, or
2419 // * the least significant byte is 0xff and the second byte is nonzero, or
2420 // * the least significant 2 bytes are 0xff and the third is nonzero.
2421 if ((SplatBits & ~0xff) == 0 ||
2422 (SplatBits & ~0xff00) == 0 ||
2423 (SplatBits & ~0xff0000) == 0 ||
2424 (SplatBits & ~0xff000000) == 0)
2425 return DAG.getTargetConstant(SplatBits, MVT::i32);
2427 if ((SplatBits & ~0xffff) == 0 &&
2428 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2429 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2431 if ((SplatBits & ~0xffffff) == 0 &&
2432 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2433 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2435 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2436 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2437 // VMOV.I32. A (very) minor optimization would be to replicate the value
2438 // and fall through here to test for a valid 64-bit splat. But, then the
2439 // caller would also need to check and handle the change in size.
2443 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2444 uint64_t BitMask = 0xff;
2446 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2447 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2449 else if ((SplatBits & BitMask) != 0)
2453 return DAG.getTargetConstant(Val, MVT::i64);
2457 llvm_unreachable("unexpected size for isVMOVSplat");
2464 /// getVMOVImm - If this is a build_vector of constants which can be
2465 /// formed by using a VMOV instruction of the specified element size,
2466 /// return the constant being splatted. The ByteSize field indicates the
2467 /// number of bytes of each element [1248].
2468 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2469 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2470 APInt SplatBits, SplatUndef;
2471 unsigned SplatBitSize;
2473 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2474 HasAnyUndefs, ByteSize * 8))
2477 if (SplatBitSize > ByteSize * 8)
2480 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2484 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2485 bool &ReverseVEXT, unsigned &Imm) {
2486 unsigned NumElts = VT.getVectorNumElements();
2487 ReverseVEXT = false;
2490 // If this is a VEXT shuffle, the immediate value is the index of the first
2491 // element. The other shuffle indices must be the successive elements after
2493 unsigned ExpectedElt = Imm;
2494 for (unsigned i = 1; i < NumElts; ++i) {
2495 // Increment the expected index. If it wraps around, it may still be
2496 // a VEXT but the source vectors must be swapped.
2498 if (ExpectedElt == NumElts * 2) {
2503 if (ExpectedElt != static_cast<unsigned>(M[i]))
2507 // Adjust the index value if the source operands will be swapped.
2514 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2515 /// instruction with the specified blocksize. (The order of the elements
2516 /// within each block of the vector is reversed.)
2517 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2518 unsigned BlockSize) {
2519 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2520 "Only possible block sizes for VREV are: 16, 32, 64");
2522 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2526 unsigned NumElts = VT.getVectorNumElements();
2527 unsigned BlockElts = M[0] + 1;
2529 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2532 for (unsigned i = 0; i < NumElts; ++i) {
2533 if ((unsigned) M[i] !=
2534 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2541 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
2542 unsigned &WhichResult) {
2543 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2547 unsigned NumElts = VT.getVectorNumElements();
2548 WhichResult = (M[0] == 0 ? 0 : 1);
2549 for (unsigned i = 0; i < NumElts; i += 2) {
2550 if ((unsigned) M[i] != i + WhichResult ||
2551 (unsigned) M[i+1] != i + NumElts + WhichResult)
2557 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
2558 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2559 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
2560 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2561 unsigned &WhichResult) {
2562 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2566 unsigned NumElts = VT.getVectorNumElements();
2567 WhichResult = (M[0] == 0 ? 0 : 1);
2568 for (unsigned i = 0; i < NumElts; i += 2) {
2569 if ((unsigned) M[i] != i + WhichResult ||
2570 (unsigned) M[i+1] != i + WhichResult)
2576 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
2577 unsigned &WhichResult) {
2578 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2582 unsigned NumElts = VT.getVectorNumElements();
2583 WhichResult = (M[0] == 0 ? 0 : 1);
2584 for (unsigned i = 0; i != NumElts; ++i) {
2585 if ((unsigned) M[i] != 2 * i + WhichResult)
2589 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2590 if (VT.is64BitVector() && EltSz == 32)
2596 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
2597 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2598 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
2599 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2600 unsigned &WhichResult) {
2601 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2605 unsigned Half = VT.getVectorNumElements() / 2;
2606 WhichResult = (M[0] == 0 ? 0 : 1);
2607 for (unsigned j = 0; j != 2; ++j) {
2608 unsigned Idx = WhichResult;
2609 for (unsigned i = 0; i != Half; ++i) {
2610 if ((unsigned) M[i + j * Half] != Idx)
2616 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2617 if (VT.is64BitVector() && EltSz == 32)
2623 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
2624 unsigned &WhichResult) {
2625 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2629 unsigned NumElts = VT.getVectorNumElements();
2630 WhichResult = (M[0] == 0 ? 0 : 1);
2631 unsigned Idx = WhichResult * NumElts / 2;
2632 for (unsigned i = 0; i != NumElts; i += 2) {
2633 if ((unsigned) M[i] != Idx ||
2634 (unsigned) M[i+1] != Idx + NumElts)
2639 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2640 if (VT.is64BitVector() && EltSz == 32)
2646 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
2647 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2648 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
2649 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2650 unsigned &WhichResult) {
2651 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2655 unsigned NumElts = VT.getVectorNumElements();
2656 WhichResult = (M[0] == 0 ? 0 : 1);
2657 unsigned Idx = WhichResult * NumElts / 2;
2658 for (unsigned i = 0; i != NumElts; i += 2) {
2659 if ((unsigned) M[i] != Idx ||
2660 (unsigned) M[i+1] != Idx)
2665 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2666 if (VT.is64BitVector() && EltSz == 32)
2673 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2674 // Canonicalize all-zeros and all-ones vectors.
2675 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
2676 if (ConstVal->isNullValue())
2677 return getZeroVector(VT, DAG, dl);
2678 if (ConstVal->isAllOnesValue())
2679 return getOnesVector(VT, DAG, dl);
2682 if (VT.is64BitVector()) {
2683 switch (Val.getValueType().getSizeInBits()) {
2684 case 8: CanonicalVT = MVT::v8i8; break;
2685 case 16: CanonicalVT = MVT::v4i16; break;
2686 case 32: CanonicalVT = MVT::v2i32; break;
2687 case 64: CanonicalVT = MVT::v1i64; break;
2688 default: llvm_unreachable("unexpected splat element type"); break;
2691 assert(VT.is128BitVector() && "unknown splat vector size");
2692 switch (Val.getValueType().getSizeInBits()) {
2693 case 8: CanonicalVT = MVT::v16i8; break;
2694 case 16: CanonicalVT = MVT::v8i16; break;
2695 case 32: CanonicalVT = MVT::v4i32; break;
2696 case 64: CanonicalVT = MVT::v2i64; break;
2697 default: llvm_unreachable("unexpected splat element type"); break;
2701 // Build a canonical splat for this value.
2702 SmallVector<SDValue, 8> Ops;
2703 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2704 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2706 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2709 // If this is a case we can't handle, return null and let the default
2710 // expansion code take care of it.
2711 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2712 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2713 DebugLoc dl = Op.getDebugLoc();
2714 EVT VT = Op.getValueType();
2716 APInt SplatBits, SplatUndef;
2717 unsigned SplatBitSize;
2719 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2720 if (SplatBitSize <= 64) {
2721 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2722 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2724 return BuildSplat(Val, VT, DAG, dl);
2728 // If there are only 2 elements in a 128-bit vector, insert them into an
2729 // undef vector. This handles the common case for 128-bit vector argument
2730 // passing, where the insertions should be translated to subreg accesses
2731 // with no real instructions.
2732 if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2733 SDValue Val = DAG.getUNDEF(VT);
2734 SDValue Op0 = Op.getOperand(0);
2735 SDValue Op1 = Op.getOperand(1);
2736 if (Op0.getOpcode() != ISD::UNDEF)
2737 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2738 DAG.getIntPtrConstant(0));
2739 if (Op1.getOpcode() != ISD::UNDEF)
2740 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2741 DAG.getIntPtrConstant(1));
2748 /// isShuffleMaskLegal - Targets can use this to indicate that they only
2749 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
2750 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
2751 /// are assumed to be legal.
2753 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
2755 if (VT.getVectorNumElements() == 4 &&
2756 (VT.is128BitVector() || VT.is64BitVector())) {
2757 unsigned PFIndexes[4];
2758 for (unsigned i = 0; i != 4; ++i) {
2762 PFIndexes[i] = M[i];
2765 // Compute the index in the perfect shuffle table.
2766 unsigned PFTableIndex =
2767 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2768 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2769 unsigned Cost = (PFEntry >> 30);
2776 unsigned Imm, WhichResult;
2778 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
2779 isVREVMask(M, VT, 64) ||
2780 isVREVMask(M, VT, 32) ||
2781 isVREVMask(M, VT, 16) ||
2782 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
2783 isVTRNMask(M, VT, WhichResult) ||
2784 isVUZPMask(M, VT, WhichResult) ||
2785 isVZIPMask(M, VT, WhichResult) ||
2786 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
2787 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
2788 isVZIP_v_undef_Mask(M, VT, WhichResult));
2791 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2792 /// the specified operations to build the shuffle.
2793 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
2794 SDValue RHS, SelectionDAG &DAG,
2796 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2797 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2798 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2801 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2810 OP_VUZPL, // VUZP, left result
2811 OP_VUZPR, // VUZP, right result
2812 OP_VZIPL, // VZIP, left result
2813 OP_VZIPR, // VZIP, right result
2814 OP_VTRNL, // VTRN, left result
2815 OP_VTRNR // VTRN, right result
2818 if (OpNum == OP_COPY) {
2819 if (LHSID == (1*9+2)*9+3) return LHS;
2820 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2824 SDValue OpLHS, OpRHS;
2825 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
2826 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
2827 EVT VT = OpLHS.getValueType();
2830 default: llvm_unreachable("Unknown shuffle opcode!");
2832 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
2837 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
2838 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
2842 return DAG.getNode(ARMISD::VEXT, dl, VT,
2844 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
2847 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2848 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
2851 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2852 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
2855 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2856 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
2860 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2861 SDValue V1 = Op.getOperand(0);
2862 SDValue V2 = Op.getOperand(1);
2863 DebugLoc dl = Op.getDebugLoc();
2864 EVT VT = Op.getValueType();
2865 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
2866 SmallVector<int, 8> ShuffleMask;
2868 // Convert shuffles that are directly supported on NEON to target-specific
2869 // DAG nodes, instead of keeping them as shuffles and matching them again
2870 // during code selection. This is more efficient and avoids the possibility
2871 // of inconsistencies between legalization and selection.
2872 // FIXME: floating-point vectors should be canonicalized to integer vectors
2873 // of the same time so that they get CSEd properly.
2874 SVN->getMask(ShuffleMask);
2876 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
2877 int Lane = SVN->getSplatIndex();
2878 // If this is undef splat, generate it via "just" vdup, if possible.
2879 if (Lane == -1) Lane = 0;
2881 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
2882 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
2884 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
2885 DAG.getConstant(Lane, MVT::i32));
2890 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
2893 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
2894 DAG.getConstant(Imm, MVT::i32));
2897 if (isVREVMask(ShuffleMask, VT, 64))
2898 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
2899 if (isVREVMask(ShuffleMask, VT, 32))
2900 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
2901 if (isVREVMask(ShuffleMask, VT, 16))
2902 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
2904 // Check for Neon shuffles that modify both input vectors in place.
2905 // If both results are used, i.e., if there are two shuffles with the same
2906 // source operands and with masks corresponding to both results of one of
2907 // these operations, DAG memoization will ensure that a single node is
2908 // used for both shuffles.
2909 unsigned WhichResult;
2910 if (isVTRNMask(ShuffleMask, VT, WhichResult))
2911 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2912 V1, V2).getValue(WhichResult);
2913 if (isVUZPMask(ShuffleMask, VT, WhichResult))
2914 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2915 V1, V2).getValue(WhichResult);
2916 if (isVZIPMask(ShuffleMask, VT, WhichResult))
2917 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2918 V1, V2).getValue(WhichResult);
2920 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
2921 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2922 V1, V1).getValue(WhichResult);
2923 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
2924 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2925 V1, V1).getValue(WhichResult);
2926 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
2927 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2928 V1, V1).getValue(WhichResult);
2930 // If the shuffle is not directly supported and it has 4 elements, use
2931 // the PerfectShuffle-generated table to synthesize it from other shuffles.
2932 if (VT.getVectorNumElements() == 4 &&
2933 (VT.is128BitVector() || VT.is64BitVector())) {
2934 unsigned PFIndexes[4];
2935 for (unsigned i = 0; i != 4; ++i) {
2936 if (ShuffleMask[i] < 0)
2939 PFIndexes[i] = ShuffleMask[i];
2942 // Compute the index in the perfect shuffle table.
2943 unsigned PFTableIndex =
2944 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2946 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2947 unsigned Cost = (PFEntry >> 30);
2950 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
2956 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2957 EVT VT = Op.getValueType();
2958 DebugLoc dl = Op.getDebugLoc();
2959 SDValue Vec = Op.getOperand(0);
2960 SDValue Lane = Op.getOperand(1);
2961 assert(VT == MVT::i32 &&
2962 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
2963 "unexpected type for custom-lowering vector extract");
2964 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2967 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2968 // The only time a CONCAT_VECTORS operation can have legal types is when
2969 // two 64-bit vectors are concatenated to a 128-bit vector.
2970 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2971 "unexpected CONCAT_VECTORS");
2972 DebugLoc dl = Op.getDebugLoc();
2973 SDValue Val = DAG.getUNDEF(MVT::v2f64);
2974 SDValue Op0 = Op.getOperand(0);
2975 SDValue Op1 = Op.getOperand(1);
2976 if (Op0.getOpcode() != ISD::UNDEF)
2977 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2978 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2979 DAG.getIntPtrConstant(0));
2980 if (Op1.getOpcode() != ISD::UNDEF)
2981 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2982 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2983 DAG.getIntPtrConstant(1));
2984 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
2987 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2988 switch (Op.getOpcode()) {
2989 default: llvm_unreachable("Don't know how to custom lower this!");
2990 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2991 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2992 case ISD::GlobalAddress:
2993 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2994 LowerGlobalAddressELF(Op, DAG);
2995 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2996 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2997 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
2998 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2999 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3000 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
3001 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3002 case ISD::SINT_TO_FP:
3003 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3004 case ISD::FP_TO_SINT:
3005 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3006 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3007 case ISD::RETURNADDR: break;
3008 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3009 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3010 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3011 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3014 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3015 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3016 case ISD::SRL_PARTS:
3017 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3018 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3019 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3020 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3021 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3022 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3027 /// ReplaceNodeResults - Replace the results of node with an illegal result
3028 /// type with new values built out of custom code.
3029 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3030 SmallVectorImpl<SDValue>&Results,
3031 SelectionDAG &DAG) {
3032 switch (N->getOpcode()) {
3034 llvm_unreachable("Don't know how to custom expand this!");
3036 case ISD::BIT_CONVERT:
3037 Results.push_back(ExpandBIT_CONVERT(N, DAG));
3041 SDValue Res = LowerShift(N, DAG, Subtarget);
3043 Results.push_back(Res);
3049 //===----------------------------------------------------------------------===//
3050 // ARM Scheduler Hooks
3051 //===----------------------------------------------------------------------===//
3054 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3055 MachineBasicBlock *BB,
3056 unsigned Size) const {
3057 unsigned dest = MI->getOperand(0).getReg();
3058 unsigned ptr = MI->getOperand(1).getReg();
3059 unsigned oldval = MI->getOperand(2).getReg();
3060 unsigned newval = MI->getOperand(3).getReg();
3061 unsigned scratch = BB->getParent()->getRegInfo()
3062 .createVirtualRegister(ARM::GPRRegisterClass);
3063 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3064 DebugLoc dl = MI->getDebugLoc();
3065 bool isThumb2 = Subtarget->isThumb2();
3067 unsigned ldrOpc, strOpc;
3069 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3071 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3072 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3075 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3076 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3079 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3080 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3084 MachineFunction *MF = BB->getParent();
3085 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3086 MachineFunction::iterator It = BB;
3087 ++It; // insert the new blocks after the current block
3089 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3090 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3091 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3092 MF->insert(It, loop1MBB);
3093 MF->insert(It, loop2MBB);
3094 MF->insert(It, exitMBB);
3095 exitMBB->transferSuccessors(BB);
3099 // fallthrough --> loop1MBB
3100 BB->addSuccessor(loop1MBB);
3103 // ldrex dest, [ptr]
3107 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3108 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3109 .addReg(dest).addReg(oldval));
3110 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3111 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3112 BB->addSuccessor(loop2MBB);
3113 BB->addSuccessor(exitMBB);
3116 // strex scratch, newval, [ptr]
3120 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3122 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3123 .addReg(scratch).addImm(0));
3124 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3125 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3126 BB->addSuccessor(loop1MBB);
3127 BB->addSuccessor(exitMBB);
3136 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3137 unsigned Size, unsigned BinOpcode) const {
3138 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3139 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3141 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3142 MachineFunction *F = BB->getParent();
3143 MachineFunction::iterator It = BB;
3146 unsigned dest = MI->getOperand(0).getReg();
3147 unsigned ptr = MI->getOperand(1).getReg();
3148 unsigned incr = MI->getOperand(2).getReg();
3149 DebugLoc dl = MI->getDebugLoc();
3150 bool isThumb2 = Subtarget->isThumb2();
3151 unsigned ldrOpc, strOpc;
3153 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3155 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3156 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3159 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3160 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3163 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3164 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3168 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
3169 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
3170 F->insert(It, loopMBB);
3171 F->insert(It, exitMBB);
3172 exitMBB->transferSuccessors(BB);
3174 MachineRegisterInfo &RegInfo = F->getRegInfo();
3175 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3176 unsigned scratch2 = (!BinOpcode) ? incr :
3177 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3181 // fallthrough --> loopMBB
3182 BB->addSuccessor(loopMBB);
3186 // <binop> scratch2, dest, incr
3187 // strex scratch, scratch2, ptr
3190 // fallthrough --> exitMBB
3192 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3194 // operand order needs to go the other way for NAND
3195 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3196 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3197 addReg(incr).addReg(dest)).addReg(0);
3199 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3200 addReg(dest).addReg(incr)).addReg(0);
3203 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3205 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3206 .addReg(scratch).addImm(0));
3207 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3208 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3210 BB->addSuccessor(loopMBB);
3211 BB->addSuccessor(exitMBB);
3220 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3221 MachineBasicBlock *BB,
3222 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
3223 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3224 DebugLoc dl = MI->getDebugLoc();
3225 bool isThumb2 = Subtarget->isThumb2();
3226 switch (MI->getOpcode()) {
3229 llvm_unreachable("Unexpected instr type to insert");
3231 case ARM::ATOMIC_LOAD_ADD_I8:
3232 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3233 case ARM::ATOMIC_LOAD_ADD_I16:
3234 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3235 case ARM::ATOMIC_LOAD_ADD_I32:
3236 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3238 case ARM::ATOMIC_LOAD_AND_I8:
3239 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3240 case ARM::ATOMIC_LOAD_AND_I16:
3241 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3242 case ARM::ATOMIC_LOAD_AND_I32:
3243 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3245 case ARM::ATOMIC_LOAD_OR_I8:
3246 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3247 case ARM::ATOMIC_LOAD_OR_I16:
3248 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3249 case ARM::ATOMIC_LOAD_OR_I32:
3250 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3252 case ARM::ATOMIC_LOAD_XOR_I8:
3253 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3254 case ARM::ATOMIC_LOAD_XOR_I16:
3255 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3256 case ARM::ATOMIC_LOAD_XOR_I32:
3257 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3259 case ARM::ATOMIC_LOAD_NAND_I8:
3260 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3261 case ARM::ATOMIC_LOAD_NAND_I16:
3262 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3263 case ARM::ATOMIC_LOAD_NAND_I32:
3264 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3266 case ARM::ATOMIC_LOAD_SUB_I8:
3267 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3268 case ARM::ATOMIC_LOAD_SUB_I16:
3269 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3270 case ARM::ATOMIC_LOAD_SUB_I32:
3271 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3273 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3274 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3275 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3277 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3278 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3279 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3281 case ARM::tMOVCCr_pseudo: {
3282 // To "insert" a SELECT_CC instruction, we actually have to insert the
3283 // diamond control-flow pattern. The incoming instruction knows the
3284 // destination vreg to set, the condition code register to branch on, the
3285 // true/false values to select between, and a branch opcode to use.
3286 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3287 MachineFunction::iterator It = BB;
3293 // cmpTY ccX, r1, r2
3295 // fallthrough --> copy0MBB
3296 MachineBasicBlock *thisMBB = BB;
3297 MachineFunction *F = BB->getParent();
3298 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3299 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3300 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3301 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3302 F->insert(It, copy0MBB);
3303 F->insert(It, sinkMBB);
3304 // Update machine-CFG edges by first adding all successors of the current
3305 // block to the new block which will contain the Phi node for the select.
3306 // Also inform sdisel of the edge changes.
3307 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
3308 E = BB->succ_end(); I != E; ++I) {
3309 EM->insert(std::make_pair(*I, sinkMBB));
3310 sinkMBB->addSuccessor(*I);
3312 // Next, remove all successors of the current block, and add the true
3313 // and fallthrough blocks as its successors.
3314 while (!BB->succ_empty())
3315 BB->removeSuccessor(BB->succ_begin());
3316 BB->addSuccessor(copy0MBB);
3317 BB->addSuccessor(sinkMBB);
3320 // %FalseValue = ...
3321 // # fallthrough to sinkMBB
3324 // Update machine-CFG edges
3325 BB->addSuccessor(sinkMBB);
3328 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3331 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
3332 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3333 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3335 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3342 case ARM::t2SUBrSPi_:
3343 case ARM::t2SUBrSPi12_:
3344 case ARM::t2SUBrSPs_: {
3345 MachineFunction *MF = BB->getParent();
3346 unsigned DstReg = MI->getOperand(0).getReg();
3347 unsigned SrcReg = MI->getOperand(1).getReg();
3348 bool DstIsDead = MI->getOperand(0).isDead();
3349 bool SrcIsKill = MI->getOperand(1).isKill();
3351 if (SrcReg != ARM::SP) {
3352 // Copy the source to SP from virtual register.
3353 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
3354 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3355 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
3356 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
3357 .addReg(SrcReg, getKillRegState(SrcIsKill));
3361 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
3362 switch (MI->getOpcode()) {
3364 llvm_unreachable("Unexpected pseudo instruction!");
3370 OpOpc = ARM::tADDspr;
3373 OpOpc = ARM::tSUBspi;
3375 case ARM::t2SUBrSPi_:
3376 OpOpc = ARM::t2SUBrSPi;
3377 NeedPred = true; NeedCC = true;
3379 case ARM::t2SUBrSPi12_:
3380 OpOpc = ARM::t2SUBrSPi12;
3383 case ARM::t2SUBrSPs_:
3384 OpOpc = ARM::t2SUBrSPs;
3385 NeedPred = true; NeedCC = true; NeedOp3 = true;
3388 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
3389 if (OpOpc == ARM::tAND)
3390 AddDefaultT1CC(MIB);
3391 MIB.addReg(ARM::SP);
3392 MIB.addOperand(MI->getOperand(2));
3394 MIB.addOperand(MI->getOperand(3));
3396 AddDefaultPred(MIB);
3400 // Copy the result from SP to virtual register.
3401 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
3402 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3403 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
3404 BuildMI(BB, dl, TII->get(CopyOpc))
3405 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
3407 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3413 //===----------------------------------------------------------------------===//
3414 // ARM Optimization Hooks
3415 //===----------------------------------------------------------------------===//
3418 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
3419 TargetLowering::DAGCombinerInfo &DCI) {
3420 SelectionDAG &DAG = DCI.DAG;
3421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3422 EVT VT = N->getValueType(0);
3423 unsigned Opc = N->getOpcode();
3424 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
3425 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
3426 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
3427 ISD::CondCode CC = ISD::SETCC_INVALID;
3430 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
3432 SDValue CCOp = Slct.getOperand(0);
3433 if (CCOp.getOpcode() == ISD::SETCC)
3434 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
3437 bool DoXform = false;
3439 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
3442 if (LHS.getOpcode() == ISD::Constant &&
3443 cast<ConstantSDNode>(LHS)->isNullValue()) {
3445 } else if (CC != ISD::SETCC_INVALID &&
3446 RHS.getOpcode() == ISD::Constant &&
3447 cast<ConstantSDNode>(RHS)->isNullValue()) {
3448 std::swap(LHS, RHS);
3449 SDValue Op0 = Slct.getOperand(0);
3450 EVT OpVT = isSlctCC ? Op0.getValueType() :
3451 Op0.getOperand(0).getValueType();
3452 bool isInt = OpVT.isInteger();
3453 CC = ISD::getSetCCInverse(CC, isInt);
3455 if (!TLI.isCondCodeLegal(CC, OpVT))
3456 return SDValue(); // Inverse operator isn't legal.
3463 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
3465 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
3466 Slct.getOperand(0), Slct.getOperand(1), CC);
3467 SDValue CCOp = Slct.getOperand(0);
3469 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
3470 CCOp.getOperand(0), CCOp.getOperand(1), CC);
3471 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3472 CCOp, OtherOp, Result);
3477 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3478 static SDValue PerformADDCombine(SDNode *N,
3479 TargetLowering::DAGCombinerInfo &DCI) {
3480 // added by evan in r37685 with no testcase.
3481 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3483 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
3484 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
3485 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
3486 if (Result.getNode()) return Result;
3488 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3489 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3490 if (Result.getNode()) return Result;
3496 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
3497 static SDValue PerformSUBCombine(SDNode *N,
3498 TargetLowering::DAGCombinerInfo &DCI) {
3499 // added by evan in r37685 with no testcase.
3500 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3502 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
3503 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3504 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3505 if (Result.getNode()) return Result;
3511 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.
3512 static SDValue PerformVMOVRRDCombine(SDNode *N,
3513 TargetLowering::DAGCombinerInfo &DCI) {
3514 // fmrrd(fmdrr x, y) -> x,y
3515 SDValue InDouble = N->getOperand(0);
3516 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
3517 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
3521 /// getVShiftImm - Check if this is a valid build_vector for the immediate
3522 /// operand of a vector shift operation, where all the elements of the
3523 /// build_vector must have the same constant integer value.
3524 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3525 // Ignore bit_converts.
3526 while (Op.getOpcode() == ISD::BIT_CONVERT)
3527 Op = Op.getOperand(0);
3528 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3529 APInt SplatBits, SplatUndef;
3530 unsigned SplatBitSize;
3532 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3533 HasAnyUndefs, ElementBits) ||
3534 SplatBitSize > ElementBits)
3536 Cnt = SplatBits.getSExtValue();
3540 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
3541 /// operand of a vector shift left operation. That value must be in the range:
3542 /// 0 <= Value < ElementBits for a left shift; or
3543 /// 0 <= Value <= ElementBits for a long left shift.
3544 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
3545 assert(VT.isVector() && "vector shift count is not a vector type");
3546 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3547 if (! getVShiftImm(Op, ElementBits, Cnt))
3549 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
3552 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
3553 /// operand of a vector shift right operation. For a shift opcode, the value
3554 /// is positive, but for an intrinsic the value count must be negative. The
3555 /// absolute value must be in the range:
3556 /// 1 <= |Value| <= ElementBits for a right shift; or
3557 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
3558 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
3560 assert(VT.isVector() && "vector shift count is not a vector type");
3561 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3562 if (! getVShiftImm(Op, ElementBits, Cnt))
3566 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
3569 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
3570 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
3571 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3574 // Don't do anything for most intrinsics.
3577 // Vector shifts: check for immediate versions and lower them.
3578 // Note: This is done during DAG combining instead of DAG legalizing because
3579 // the build_vectors for 64-bit vector element shift counts are generally
3580 // not legal, and it is hard to see their values after they get legalized to
3581 // loads from a constant pool.
3582 case Intrinsic::arm_neon_vshifts:
3583 case Intrinsic::arm_neon_vshiftu:
3584 case Intrinsic::arm_neon_vshiftls:
3585 case Intrinsic::arm_neon_vshiftlu:
3586 case Intrinsic::arm_neon_vshiftn:
3587 case Intrinsic::arm_neon_vrshifts:
3588 case Intrinsic::arm_neon_vrshiftu:
3589 case Intrinsic::arm_neon_vrshiftn:
3590 case Intrinsic::arm_neon_vqshifts:
3591 case Intrinsic::arm_neon_vqshiftu:
3592 case Intrinsic::arm_neon_vqshiftsu:
3593 case Intrinsic::arm_neon_vqshiftns:
3594 case Intrinsic::arm_neon_vqshiftnu:
3595 case Intrinsic::arm_neon_vqshiftnsu:
3596 case Intrinsic::arm_neon_vqrshiftns:
3597 case Intrinsic::arm_neon_vqrshiftnu:
3598 case Intrinsic::arm_neon_vqrshiftnsu: {
3599 EVT VT = N->getOperand(1).getValueType();
3601 unsigned VShiftOpc = 0;
3604 case Intrinsic::arm_neon_vshifts:
3605 case Intrinsic::arm_neon_vshiftu:
3606 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
3607 VShiftOpc = ARMISD::VSHL;
3610 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
3611 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
3612 ARMISD::VSHRs : ARMISD::VSHRu);
3617 case Intrinsic::arm_neon_vshiftls:
3618 case Intrinsic::arm_neon_vshiftlu:
3619 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
3621 llvm_unreachable("invalid shift count for vshll intrinsic");
3623 case Intrinsic::arm_neon_vrshifts:
3624 case Intrinsic::arm_neon_vrshiftu:
3625 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
3629 case Intrinsic::arm_neon_vqshifts:
3630 case Intrinsic::arm_neon_vqshiftu:
3631 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3635 case Intrinsic::arm_neon_vqshiftsu:
3636 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3638 llvm_unreachable("invalid shift count for vqshlu intrinsic");
3640 case Intrinsic::arm_neon_vshiftn:
3641 case Intrinsic::arm_neon_vrshiftn:
3642 case Intrinsic::arm_neon_vqshiftns:
3643 case Intrinsic::arm_neon_vqshiftnu:
3644 case Intrinsic::arm_neon_vqshiftnsu:
3645 case Intrinsic::arm_neon_vqrshiftns:
3646 case Intrinsic::arm_neon_vqrshiftnu:
3647 case Intrinsic::arm_neon_vqrshiftnsu:
3648 // Narrowing shifts require an immediate right shift.
3649 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
3651 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
3654 llvm_unreachable("unhandled vector shift");
3658 case Intrinsic::arm_neon_vshifts:
3659 case Intrinsic::arm_neon_vshiftu:
3660 // Opcode already set above.
3662 case Intrinsic::arm_neon_vshiftls:
3663 case Intrinsic::arm_neon_vshiftlu:
3664 if (Cnt == VT.getVectorElementType().getSizeInBits())
3665 VShiftOpc = ARMISD::VSHLLi;
3667 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
3668 ARMISD::VSHLLs : ARMISD::VSHLLu);
3670 case Intrinsic::arm_neon_vshiftn:
3671 VShiftOpc = ARMISD::VSHRN; break;
3672 case Intrinsic::arm_neon_vrshifts:
3673 VShiftOpc = ARMISD::VRSHRs; break;
3674 case Intrinsic::arm_neon_vrshiftu:
3675 VShiftOpc = ARMISD::VRSHRu; break;
3676 case Intrinsic::arm_neon_vrshiftn:
3677 VShiftOpc = ARMISD::VRSHRN; break;
3678 case Intrinsic::arm_neon_vqshifts:
3679 VShiftOpc = ARMISD::VQSHLs; break;
3680 case Intrinsic::arm_neon_vqshiftu:
3681 VShiftOpc = ARMISD::VQSHLu; break;
3682 case Intrinsic::arm_neon_vqshiftsu:
3683 VShiftOpc = ARMISD::VQSHLsu; break;
3684 case Intrinsic::arm_neon_vqshiftns:
3685 VShiftOpc = ARMISD::VQSHRNs; break;
3686 case Intrinsic::arm_neon_vqshiftnu:
3687 VShiftOpc = ARMISD::VQSHRNu; break;
3688 case Intrinsic::arm_neon_vqshiftnsu:
3689 VShiftOpc = ARMISD::VQSHRNsu; break;
3690 case Intrinsic::arm_neon_vqrshiftns:
3691 VShiftOpc = ARMISD::VQRSHRNs; break;
3692 case Intrinsic::arm_neon_vqrshiftnu:
3693 VShiftOpc = ARMISD::VQRSHRNu; break;
3694 case Intrinsic::arm_neon_vqrshiftnsu:
3695 VShiftOpc = ARMISD::VQRSHRNsu; break;
3698 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3699 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
3702 case Intrinsic::arm_neon_vshiftins: {
3703 EVT VT = N->getOperand(1).getValueType();
3705 unsigned VShiftOpc = 0;
3707 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
3708 VShiftOpc = ARMISD::VSLI;
3709 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
3710 VShiftOpc = ARMISD::VSRI;
3712 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
3715 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3716 N->getOperand(1), N->getOperand(2),
3717 DAG.getConstant(Cnt, MVT::i32));
3720 case Intrinsic::arm_neon_vqrshifts:
3721 case Intrinsic::arm_neon_vqrshiftu:
3722 // No immediate versions of these to check for.
3729 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
3730 /// lowers them. As with the vector shift intrinsics, this is done during DAG
3731 /// combining instead of DAG legalizing because the build_vectors for 64-bit
3732 /// vector element shift counts are generally not legal, and it is hard to see
3733 /// their values after they get legalized to loads from a constant pool.
3734 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3735 const ARMSubtarget *ST) {
3736 EVT VT = N->getValueType(0);
3738 // Nothing to be done for scalar shifts.
3739 if (! VT.isVector())
3742 assert(ST->hasNEON() && "unexpected vector shift");
3745 switch (N->getOpcode()) {
3746 default: llvm_unreachable("unexpected shift opcode");
3749 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3750 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
3751 DAG.getConstant(Cnt, MVT::i32));
3756 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3757 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3758 ARMISD::VSHRs : ARMISD::VSHRu);
3759 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
3760 DAG.getConstant(Cnt, MVT::i32));
3766 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3767 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3768 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3769 const ARMSubtarget *ST) {
3770 SDValue N0 = N->getOperand(0);
3772 // Check for sign- and zero-extensions of vector extract operations of 8-
3773 // and 16-bit vector elements. NEON supports these directly. They are
3774 // handled during DAG combining because type legalization will promote them
3775 // to 32-bit types and it is messy to recognize the operations after that.
3776 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3777 SDValue Vec = N0.getOperand(0);
3778 SDValue Lane = N0.getOperand(1);
3779 EVT VT = N->getValueType(0);
3780 EVT EltVT = N0.getValueType();
3781 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3783 if (VT == MVT::i32 &&
3784 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
3785 TLI.isTypeLegal(Vec.getValueType())) {
3788 switch (N->getOpcode()) {
3789 default: llvm_unreachable("unexpected opcode");
3790 case ISD::SIGN_EXTEND:
3791 Opc = ARMISD::VGETLANEs;
3793 case ISD::ZERO_EXTEND:
3794 case ISD::ANY_EXTEND:
3795 Opc = ARMISD::VGETLANEu;
3798 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3805 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
3806 DAGCombinerInfo &DCI) const {
3807 switch (N->getOpcode()) {
3809 case ISD::ADD: return PerformADDCombine(N, DCI);
3810 case ISD::SUB: return PerformSUBCombine(N, DCI);
3811 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
3812 case ISD::INTRINSIC_WO_CHAIN:
3813 return PerformIntrinsicCombine(N, DCI.DAG);
3817 return PerformShiftCombine(N, DCI.DAG, Subtarget);
3818 case ISD::SIGN_EXTEND:
3819 case ISD::ZERO_EXTEND:
3820 case ISD::ANY_EXTEND:
3821 return PerformExtendCombine(N, DCI.DAG, Subtarget);
3826 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
3827 if (!Subtarget->hasV6Ops())
3828 // Pre-v6 does not support unaligned mem access.
3830 else if (!Subtarget->hasV6Ops()) {
3831 // v6 may or may not support unaligned mem access.
3832 if (!Subtarget->isTargetDarwin())
3836 switch (VT.getSimpleVT().SimpleTy) {
3843 // FIXME: VLD1 etc with standard alignment is legal.
3847 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
3852 switch (VT.getSimpleVT().SimpleTy) {
3853 default: return false;
3868 if ((V & (Scale - 1)) != 0)
3871 return V == (V & ((1LL << 5) - 1));
3874 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
3875 const ARMSubtarget *Subtarget) {
3882 switch (VT.getSimpleVT().SimpleTy) {
3883 default: return false;
3888 // + imm12 or - imm8
3890 return V == (V & ((1LL << 8) - 1));
3891 return V == (V & ((1LL << 12) - 1));
3894 // Same as ARM mode. FIXME: NEON?
3895 if (!Subtarget->hasVFP2())
3900 return V == (V & ((1LL << 8) - 1));
3904 /// isLegalAddressImmediate - Return true if the integer value can be used
3905 /// as the offset of the target addressing mode for load / store of the
3907 static bool isLegalAddressImmediate(int64_t V, EVT VT,
3908 const ARMSubtarget *Subtarget) {
3915 if (Subtarget->isThumb1Only())
3916 return isLegalT1AddressImmediate(V, VT);
3917 else if (Subtarget->isThumb2())
3918 return isLegalT2AddressImmediate(V, VT, Subtarget);
3923 switch (VT.getSimpleVT().SimpleTy) {
3924 default: return false;
3929 return V == (V & ((1LL << 12) - 1));
3932 return V == (V & ((1LL << 8) - 1));
3935 if (!Subtarget->hasVFP2()) // FIXME: NEON?
3940 return V == (V & ((1LL << 8) - 1));
3944 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
3946 int Scale = AM.Scale;
3950 switch (VT.getSimpleVT().SimpleTy) {
3951 default: return false;
3960 return Scale == 2 || Scale == 4 || Scale == 8;
3963 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3967 // Note, we allow "void" uses (basically, uses that aren't loads or
3968 // stores), because arm allows folding a scale into many arithmetic
3969 // operations. This should be made more precise and revisited later.
3971 // Allow r << imm, but the imm has to be a multiple of two.
3972 if (Scale & 1) return false;
3973 return isPowerOf2_32(Scale);
3977 /// isLegalAddressingMode - Return true if the addressing mode represented
3978 /// by AM is legal for this target, for a load/store of the specified type.
3979 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3980 const Type *Ty) const {
3981 EVT VT = getValueType(Ty, true);
3982 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
3985 // Can never fold addr of global into load/store.
3990 case 0: // no scale reg, must be "r+i" or "r", or "i".
3993 if (Subtarget->isThumb1Only())
3997 // ARM doesn't support any R+R*scale+imm addr modes.
4004 if (Subtarget->isThumb2())
4005 return isLegalT2ScaledAddressingMode(AM, VT);
4007 int Scale = AM.Scale;
4008 switch (VT.getSimpleVT().SimpleTy) {
4009 default: return false;
4013 if (Scale < 0) Scale = -Scale;
4017 return isPowerOf2_32(Scale & ~1);
4021 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4026 // Note, we allow "void" uses (basically, uses that aren't loads or
4027 // stores), because arm allows folding a scale into many arithmetic
4028 // operations. This should be made more precise and revisited later.
4030 // Allow r << imm, but the imm has to be a multiple of two.
4031 if (Scale & 1) return false;
4032 return isPowerOf2_32(Scale);
4039 /// isLegalICmpImmediate - Return true if the specified immediate is legal
4040 /// icmp immediate, that is the target has icmp instructions which can compare
4041 /// a register against the immediate without having to materialize the
4042 /// immediate into a register.
4043 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4044 if (!Subtarget->isThumb())
4045 return ARM_AM::getSOImmVal(Imm) != -1;
4046 if (Subtarget->isThumb2())
4047 return ARM_AM::getT2SOImmVal(Imm) != -1;
4048 return Imm >= 0 && Imm <= 255;
4051 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
4052 bool isSEXTLoad, SDValue &Base,
4053 SDValue &Offset, bool &isInc,
4054 SelectionDAG &DAG) {
4055 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4058 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
4060 Base = Ptr->getOperand(0);
4061 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4062 int RHSC = (int)RHS->getZExtValue();
4063 if (RHSC < 0 && RHSC > -256) {
4064 assert(Ptr->getOpcode() == ISD::ADD);
4066 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4070 isInc = (Ptr->getOpcode() == ISD::ADD);
4071 Offset = Ptr->getOperand(1);
4073 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
4075 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4076 int RHSC = (int)RHS->getZExtValue();
4077 if (RHSC < 0 && RHSC > -0x1000) {
4078 assert(Ptr->getOpcode() == ISD::ADD);
4080 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4081 Base = Ptr->getOperand(0);
4086 if (Ptr->getOpcode() == ISD::ADD) {
4088 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4089 if (ShOpcVal != ARM_AM::no_shift) {
4090 Base = Ptr->getOperand(1);
4091 Offset = Ptr->getOperand(0);
4093 Base = Ptr->getOperand(0);
4094 Offset = Ptr->getOperand(1);
4099 isInc = (Ptr->getOpcode() == ISD::ADD);
4100 Base = Ptr->getOperand(0);
4101 Offset = Ptr->getOperand(1);
4105 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
4109 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
4110 bool isSEXTLoad, SDValue &Base,
4111 SDValue &Offset, bool &isInc,
4112 SelectionDAG &DAG) {
4113 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4116 Base = Ptr->getOperand(0);
4117 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4118 int RHSC = (int)RHS->getZExtValue();
4119 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
4120 assert(Ptr->getOpcode() == ISD::ADD);
4122 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4124 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
4125 isInc = Ptr->getOpcode() == ISD::ADD;
4126 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
4134 /// getPreIndexedAddressParts - returns true by value, base pointer and
4135 /// offset pointer and addressing mode by reference if the node's address
4136 /// can be legally represented as pre-indexed load / store address.
4138 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
4140 ISD::MemIndexedMode &AM,
4141 SelectionDAG &DAG) const {
4142 if (Subtarget->isThumb1Only())
4147 bool isSEXTLoad = false;
4148 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4149 Ptr = LD->getBasePtr();
4150 VT = LD->getMemoryVT();
4151 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4152 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4153 Ptr = ST->getBasePtr();
4154 VT = ST->getMemoryVT();
4159 bool isLegal = false;
4160 if (Subtarget->isThumb2())
4161 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4162 Offset, isInc, DAG);
4164 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4165 Offset, isInc, DAG);
4169 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
4173 /// getPostIndexedAddressParts - returns true by value, base pointer and
4174 /// offset pointer and addressing mode by reference if this node can be
4175 /// combined with a load / store to form a post-indexed load / store.
4176 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
4179 ISD::MemIndexedMode &AM,
4180 SelectionDAG &DAG) const {
4181 if (Subtarget->isThumb1Only())
4186 bool isSEXTLoad = false;
4187 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4188 VT = LD->getMemoryVT();
4189 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4190 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4191 VT = ST->getMemoryVT();
4196 bool isLegal = false;
4197 if (Subtarget->isThumb2())
4198 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4201 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4206 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
4210 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4214 const SelectionDAG &DAG,
4215 unsigned Depth) const {
4216 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4217 switch (Op.getOpcode()) {
4219 case ARMISD::CMOV: {
4220 // Bits are known zero/one if known on the LHS and RHS.
4221 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
4222 if (KnownZero == 0 && KnownOne == 0) return;
4224 APInt KnownZeroRHS, KnownOneRHS;
4225 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
4226 KnownZeroRHS, KnownOneRHS, Depth+1);
4227 KnownZero &= KnownZeroRHS;
4228 KnownOne &= KnownOneRHS;
4234 //===----------------------------------------------------------------------===//
4235 // ARM Inline Assembly Support
4236 //===----------------------------------------------------------------------===//
4238 /// getConstraintType - Given a constraint letter, return the type of
4239 /// constraint it is for this target.
4240 ARMTargetLowering::ConstraintType
4241 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
4242 if (Constraint.size() == 1) {
4243 switch (Constraint[0]) {
4245 case 'l': return C_RegisterClass;
4246 case 'w': return C_RegisterClass;
4249 return TargetLowering::getConstraintType(Constraint);
4252 std::pair<unsigned, const TargetRegisterClass*>
4253 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4255 if (Constraint.size() == 1) {
4256 // GCC RS6000 Constraint Letters
4257 switch (Constraint[0]) {
4259 if (Subtarget->isThumb1Only())
4260 return std::make_pair(0U, ARM::tGPRRegisterClass);
4262 return std::make_pair(0U, ARM::GPRRegisterClass);
4264 return std::make_pair(0U, ARM::GPRRegisterClass);
4267 return std::make_pair(0U, ARM::SPRRegisterClass);
4269 return std::make_pair(0U, ARM::DPRRegisterClass);
4270 if (VT.getSizeInBits() == 128)
4271 return std::make_pair(0U, ARM::QPRRegisterClass);
4275 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4278 std::vector<unsigned> ARMTargetLowering::
4279 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4281 if (Constraint.size() != 1)
4282 return std::vector<unsigned>();
4284 switch (Constraint[0]) { // GCC ARM Constraint Letters
4287 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4288 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4291 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4292 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4293 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
4294 ARM::R12, ARM::LR, 0);
4297 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
4298 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
4299 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
4300 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
4301 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
4302 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
4303 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
4304 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
4306 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
4307 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
4308 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
4309 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
4310 if (VT.getSizeInBits() == 128)
4311 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
4312 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
4316 return std::vector<unsigned>();
4319 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4320 /// vector. If it is invalid, don't add anything to Ops.
4321 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4324 std::vector<SDValue>&Ops,
4325 SelectionDAG &DAG) const {
4326 SDValue Result(0, 0);
4328 switch (Constraint) {
4330 case 'I': case 'J': case 'K': case 'L':
4331 case 'M': case 'N': case 'O':
4332 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4336 int64_t CVal64 = C->getSExtValue();
4337 int CVal = (int) CVal64;
4338 // None of these constraints allow values larger than 32 bits. Check
4339 // that the value fits in an int.
4343 switch (Constraint) {
4345 if (Subtarget->isThumb1Only()) {
4346 // This must be a constant between 0 and 255, for ADD
4348 if (CVal >= 0 && CVal <= 255)
4350 } else if (Subtarget->isThumb2()) {
4351 // A constant that can be used as an immediate value in a
4352 // data-processing instruction.
4353 if (ARM_AM::getT2SOImmVal(CVal) != -1)
4356 // A constant that can be used as an immediate value in a
4357 // data-processing instruction.
4358 if (ARM_AM::getSOImmVal(CVal) != -1)
4364 if (Subtarget->isThumb()) { // FIXME thumb2
4365 // This must be a constant between -255 and -1, for negated ADD
4366 // immediates. This can be used in GCC with an "n" modifier that
4367 // prints the negated value, for use with SUB instructions. It is
4368 // not useful otherwise but is implemented for compatibility.
4369 if (CVal >= -255 && CVal <= -1)
4372 // This must be a constant between -4095 and 4095. It is not clear
4373 // what this constraint is intended for. Implemented for
4374 // compatibility with GCC.
4375 if (CVal >= -4095 && CVal <= 4095)
4381 if (Subtarget->isThumb1Only()) {
4382 // A 32-bit value where only one byte has a nonzero value. Exclude
4383 // zero to match GCC. This constraint is used by GCC internally for
4384 // constants that can be loaded with a move/shift combination.
4385 // It is not useful otherwise but is implemented for compatibility.
4386 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
4388 } else if (Subtarget->isThumb2()) {
4389 // A constant whose bitwise inverse can be used as an immediate
4390 // value in a data-processing instruction. This can be used in GCC
4391 // with a "B" modifier that prints the inverted value, for use with
4392 // BIC and MVN instructions. It is not useful otherwise but is
4393 // implemented for compatibility.
4394 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
4397 // A constant whose bitwise inverse can be used as an immediate
4398 // value in a data-processing instruction. This can be used in GCC
4399 // with a "B" modifier that prints the inverted value, for use with
4400 // BIC and MVN instructions. It is not useful otherwise but is
4401 // implemented for compatibility.
4402 if (ARM_AM::getSOImmVal(~CVal) != -1)
4408 if (Subtarget->isThumb1Only()) {
4409 // This must be a constant between -7 and 7,
4410 // for 3-operand ADD/SUB immediate instructions.
4411 if (CVal >= -7 && CVal < 7)
4413 } else if (Subtarget->isThumb2()) {
4414 // A constant whose negation can be used as an immediate value in a
4415 // data-processing instruction. This can be used in GCC with an "n"
4416 // modifier that prints the negated value, for use with SUB
4417 // instructions. It is not useful otherwise but is implemented for
4419 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
4422 // A constant whose negation can be used as an immediate value in a
4423 // data-processing instruction. This can be used in GCC with an "n"
4424 // modifier that prints the negated value, for use with SUB
4425 // instructions. It is not useful otherwise but is implemented for
4427 if (ARM_AM::getSOImmVal(-CVal) != -1)
4433 if (Subtarget->isThumb()) { // FIXME thumb2
4434 // This must be a multiple of 4 between 0 and 1020, for
4435 // ADD sp + immediate.
4436 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
4439 // A power of two or a constant between 0 and 32. This is used in
4440 // GCC for the shift amount on shifted register operands, but it is
4441 // useful in general for any shift amounts.
4442 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
4448 if (Subtarget->isThumb()) { // FIXME thumb2
4449 // This must be a constant between 0 and 31, for shift amounts.
4450 if (CVal >= 0 && CVal <= 31)
4456 if (Subtarget->isThumb()) { // FIXME thumb2
4457 // This must be a multiple of 4 between -508 and 508, for
4458 // ADD/SUB sp = sp + immediate.
4459 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
4464 Result = DAG.getTargetConstant(CVal, Op.getValueType());
4468 if (Result.getNode()) {
4469 Ops.push_back(Result);
4472 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
4477 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4478 // The ARM target isn't yet aware of offsets.
4482 int ARM::getVFPf32Imm(const APFloat &FPImm) {
4483 APInt Imm = FPImm.bitcastToAPInt();
4484 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
4485 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
4486 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
4488 // We can handle 4 bits of mantissa.
4489 // mantissa = (16+UInt(e:f:g:h))/16.
4490 if (Mantissa & 0x7ffff)
4493 if ((Mantissa & 0xf) != Mantissa)
4496 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4497 if (Exp < -3 || Exp > 4)
4499 Exp = ((Exp+3) & 0x7) ^ 4;
4501 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4504 int ARM::getVFPf64Imm(const APFloat &FPImm) {
4505 APInt Imm = FPImm.bitcastToAPInt();
4506 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
4507 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
4508 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
4510 // We can handle 4 bits of mantissa.
4511 // mantissa = (16+UInt(e:f:g:h))/16.
4512 if (Mantissa & 0xffffffffffffLL)
4515 if ((Mantissa & 0xf) != Mantissa)
4518 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4519 if (Exp < -3 || Exp > 4)
4521 Exp = ((Exp+3) & 0x7) ^ 4;
4523 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4526 /// isFPImmLegal - Returns true if the target can instruction select the
4527 /// specified FP immediate natively. If false, the legalizer will
4528 /// materialize the FP immediate as a load from a constant pool.
4529 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4530 if (!Subtarget->hasVFP3())
4533 return ARM::getVFPf32Imm(Imm) != -1;
4535 return ARM::getVFPf64Imm(Imm) != -1;