1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instruction.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/VectorExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/MathExtras.h"
44 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
49 CCValAssign::LocInfo &LocInfo,
50 ISD::ArgFlagsTy &ArgFlags,
52 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
53 CCValAssign::LocInfo &LocInfo,
54 ISD::ArgFlagsTy &ArgFlags,
56 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
57 CCValAssign::LocInfo &LocInfo,
58 ISD::ArgFlagsTy &ArgFlags,
61 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
62 MVT PromotedBitwiseVT) {
63 if (VT != PromotedLdStVT) {
64 setOperationAction(ISD::LOAD, VT, Promote);
65 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
67 setOperationAction(ISD::STORE, VT, Promote);
68 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
71 MVT ElemTy = VT.getVectorElementType();
72 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
73 setOperationAction(ISD::VSETCC, VT, Custom);
74 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
75 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
76 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
77 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
78 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
79 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
81 setOperationAction(ISD::SHL, VT, Custom);
82 setOperationAction(ISD::SRA, VT, Custom);
83 setOperationAction(ISD::SRL, VT, Custom);
86 // Promote all bit-wise operations.
87 if (VT.isInteger() && VT != PromotedBitwiseVT) {
88 setOperationAction(ISD::AND, VT, Promote);
89 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
90 setOperationAction(ISD::OR, VT, Promote);
91 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
92 setOperationAction(ISD::XOR, VT, Promote);
93 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
97 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
98 addRegisterClass(VT, ARM::DPRRegisterClass);
99 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
102 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
103 addRegisterClass(VT, ARM::QPRRegisterClass);
104 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
107 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
108 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
109 return new TargetLoweringObjectFileMachO();
110 return new ARMElfTargetObjectFile();
113 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
114 : TargetLowering(TM, createTLOF(TM)), ARMPCLabelIndex(0) {
115 Subtarget = &TM.getSubtarget<ARMSubtarget>();
117 if (Subtarget->isTargetDarwin()) {
118 // Uses VFP for Thumb libfuncs if available.
119 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
120 // Single-precision floating-point arithmetic.
121 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
122 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
123 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
124 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
126 // Double-precision floating-point arithmetic.
127 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
128 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
129 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
130 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
132 // Single-precision comparisons.
133 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
134 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
135 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
136 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
137 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
138 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
139 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
140 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
142 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
143 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
144 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
145 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
146 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
147 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
148 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
149 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
151 // Double-precision comparisons.
152 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
153 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
154 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
155 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
156 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
157 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
158 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
159 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
161 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
162 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
163 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
164 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
165 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
166 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
167 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
168 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
170 // Floating-point to integer conversions.
171 // i64 conversions are done via library routines even when generating VFP
172 // instructions, so use the same ones.
173 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
174 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
175 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
176 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
178 // Conversions between floating types.
179 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
180 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
182 // Integer to floating-point conversions.
183 // i64 conversions are done via library routines even when generating VFP
184 // instructions, so use the same ones.
185 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
186 // e.g., __floatunsidf vs. __floatunssidfvfp.
187 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
188 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
189 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
190 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
194 // These libcalls are not available in 32-bit.
195 setLibcallName(RTLIB::SHL_I128, 0);
196 setLibcallName(RTLIB::SRL_I128, 0);
197 setLibcallName(RTLIB::SRA_I128, 0);
199 if (Subtarget->isThumb1Only())
200 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
202 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
203 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
204 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
205 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
207 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
210 if (Subtarget->hasNEON()) {
211 addDRTypeForNEON(MVT::v2f32);
212 addDRTypeForNEON(MVT::v8i8);
213 addDRTypeForNEON(MVT::v4i16);
214 addDRTypeForNEON(MVT::v2i32);
215 addDRTypeForNEON(MVT::v1i64);
217 addQRTypeForNEON(MVT::v4f32);
218 addQRTypeForNEON(MVT::v2f64);
219 addQRTypeForNEON(MVT::v16i8);
220 addQRTypeForNEON(MVT::v8i16);
221 addQRTypeForNEON(MVT::v4i32);
222 addQRTypeForNEON(MVT::v2i64);
224 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
225 setTargetDAGCombine(ISD::SHL);
226 setTargetDAGCombine(ISD::SRL);
227 setTargetDAGCombine(ISD::SRA);
228 setTargetDAGCombine(ISD::SIGN_EXTEND);
229 setTargetDAGCombine(ISD::ZERO_EXTEND);
230 setTargetDAGCombine(ISD::ANY_EXTEND);
233 computeRegisterProperties();
235 // ARM does not have f32 extending load.
236 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
238 // ARM does not have i1 sign extending load.
239 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
241 // ARM supports all 4 flavors of integer indexed load / store.
242 if (!Subtarget->isThumb1Only()) {
243 for (unsigned im = (unsigned)ISD::PRE_INC;
244 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
245 setIndexedLoadAction(im, MVT::i1, Legal);
246 setIndexedLoadAction(im, MVT::i8, Legal);
247 setIndexedLoadAction(im, MVT::i16, Legal);
248 setIndexedLoadAction(im, MVT::i32, Legal);
249 setIndexedStoreAction(im, MVT::i1, Legal);
250 setIndexedStoreAction(im, MVT::i8, Legal);
251 setIndexedStoreAction(im, MVT::i16, Legal);
252 setIndexedStoreAction(im, MVT::i32, Legal);
256 // i64 operation support.
257 if (Subtarget->isThumb1Only()) {
258 setOperationAction(ISD::MUL, MVT::i64, Expand);
259 setOperationAction(ISD::MULHU, MVT::i32, Expand);
260 setOperationAction(ISD::MULHS, MVT::i32, Expand);
261 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
262 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
264 setOperationAction(ISD::MUL, MVT::i64, Expand);
265 setOperationAction(ISD::MULHU, MVT::i32, Expand);
266 if (!Subtarget->hasV6Ops())
267 setOperationAction(ISD::MULHS, MVT::i32, Expand);
269 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
270 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
271 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
272 setOperationAction(ISD::SRL, MVT::i64, Custom);
273 setOperationAction(ISD::SRA, MVT::i64, Custom);
275 // ARM does not have ROTL.
276 setOperationAction(ISD::ROTL, MVT::i32, Expand);
277 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
278 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
279 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
280 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
282 // Only ARMv6 has BSWAP.
283 if (!Subtarget->hasV6Ops())
284 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
286 // These are expanded into libcalls.
287 setOperationAction(ISD::SDIV, MVT::i32, Expand);
288 setOperationAction(ISD::UDIV, MVT::i32, Expand);
289 setOperationAction(ISD::SREM, MVT::i32, Expand);
290 setOperationAction(ISD::UREM, MVT::i32, Expand);
291 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
292 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
294 // Support label based line numbers.
295 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
296 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
298 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
299 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
300 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
301 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
303 // Use the default implementation.
304 setOperationAction(ISD::VASTART, MVT::Other, Custom);
305 setOperationAction(ISD::VAARG, MVT::Other, Expand);
306 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
307 setOperationAction(ISD::VAEND, MVT::Other, Expand);
308 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
309 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
310 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
311 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
313 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
315 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
319 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
320 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
321 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
323 // We want to custom lower some of our intrinsics.
324 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
325 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
327 setOperationAction(ISD::SETCC, MVT::i32, Expand);
328 setOperationAction(ISD::SETCC, MVT::f32, Expand);
329 setOperationAction(ISD::SETCC, MVT::f64, Expand);
330 setOperationAction(ISD::SELECT, MVT::i32, Expand);
331 setOperationAction(ISD::SELECT, MVT::f32, Expand);
332 setOperationAction(ISD::SELECT, MVT::f64, Expand);
333 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
334 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
335 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
337 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
338 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
339 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
340 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
341 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
343 // We don't support sin/cos/fmod/copysign/pow
344 setOperationAction(ISD::FSIN, MVT::f64, Expand);
345 setOperationAction(ISD::FSIN, MVT::f32, Expand);
346 setOperationAction(ISD::FCOS, MVT::f32, Expand);
347 setOperationAction(ISD::FCOS, MVT::f64, Expand);
348 setOperationAction(ISD::FREM, MVT::f64, Expand);
349 setOperationAction(ISD::FREM, MVT::f32, Expand);
350 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
351 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
352 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
354 setOperationAction(ISD::FPOW, MVT::f64, Expand);
355 setOperationAction(ISD::FPOW, MVT::f32, Expand);
357 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
358 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
359 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
360 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
365 // We have target-specific dag combine patterns for the following nodes:
366 // ARMISD::FMRRD - No need to call setTargetDAGCombine
367 setTargetDAGCombine(ISD::ADD);
368 setTargetDAGCombine(ISD::SUB);
370 setStackPointerRegisterToSaveRestore(ARM::SP);
371 setSchedulingPreference(SchedulingForRegPressure);
372 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
373 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
375 if (!Subtarget->isThumb()) {
376 // Use branch latency information to determine if-conversion limits.
377 // FIXME: If-converter should use instruction latency of the branch being
378 // eliminated to compute the threshold. For ARMv6, the branch "latency"
379 // varies depending on whether it's dynamically or statically predicted
380 // and on whether the destination is in the prefetch buffer.
381 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
382 const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData();
383 unsigned Latency= InstrItins.getLatency(TII->get(ARM::Bcc).getSchedClass());
385 setIfCvtBlockSizeLimit(Latency-1);
387 setIfCvtDupBlockSizeLimit(Latency-2);
389 setIfCvtBlockSizeLimit(10);
390 setIfCvtDupBlockSizeLimit(2);
394 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
395 // Do not enable CodePlacementOpt for now: it currently runs after the
396 // ARMConstantIslandPass and messes up branch relaxation and placement
397 // of constant islands.
398 // benefitFromCodePlacementOpt = true;
401 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
404 case ARMISD::Wrapper: return "ARMISD::Wrapper";
405 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
406 case ARMISD::CALL: return "ARMISD::CALL";
407 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
408 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
409 case ARMISD::tCALL: return "ARMISD::tCALL";
410 case ARMISD::BRCOND: return "ARMISD::BRCOND";
411 case ARMISD::BR_JT: return "ARMISD::BR_JT";
412 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
413 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
414 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
415 case ARMISD::CMP: return "ARMISD::CMP";
416 case ARMISD::CMPZ: return "ARMISD::CMPZ";
417 case ARMISD::CMPFP: return "ARMISD::CMPFP";
418 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
419 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
420 case ARMISD::CMOV: return "ARMISD::CMOV";
421 case ARMISD::CNEG: return "ARMISD::CNEG";
423 case ARMISD::FTOSI: return "ARMISD::FTOSI";
424 case ARMISD::FTOUI: return "ARMISD::FTOUI";
425 case ARMISD::SITOF: return "ARMISD::SITOF";
426 case ARMISD::UITOF: return "ARMISD::UITOF";
428 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
429 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
430 case ARMISD::RRX: return "ARMISD::RRX";
432 case ARMISD::FMRRD: return "ARMISD::FMRRD";
433 case ARMISD::FMDRR: return "ARMISD::FMDRR";
435 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
437 case ARMISD::VCEQ: return "ARMISD::VCEQ";
438 case ARMISD::VCGE: return "ARMISD::VCGE";
439 case ARMISD::VCGEU: return "ARMISD::VCGEU";
440 case ARMISD::VCGT: return "ARMISD::VCGT";
441 case ARMISD::VCGTU: return "ARMISD::VCGTU";
442 case ARMISD::VTST: return "ARMISD::VTST";
444 case ARMISD::VSHL: return "ARMISD::VSHL";
445 case ARMISD::VSHRs: return "ARMISD::VSHRs";
446 case ARMISD::VSHRu: return "ARMISD::VSHRu";
447 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
448 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
449 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
450 case ARMISD::VSHRN: return "ARMISD::VSHRN";
451 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
452 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
453 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
454 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
455 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
456 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
457 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
458 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
459 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
460 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
461 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
462 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
463 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
464 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
465 case ARMISD::VDUPLANEQ: return "ARMISD::VDUPLANEQ";
466 case ARMISD::VLD2D: return "ARMISD::VLD2D";
467 case ARMISD::VLD3D: return "ARMISD::VLD3D";
468 case ARMISD::VLD4D: return "ARMISD::VLD4D";
472 /// getFunctionAlignment - Return the Log2 alignment of this function.
473 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
474 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
477 //===----------------------------------------------------------------------===//
479 //===----------------------------------------------------------------------===//
481 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
482 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
484 default: llvm_unreachable("Unknown condition code!");
485 case ISD::SETNE: return ARMCC::NE;
486 case ISD::SETEQ: return ARMCC::EQ;
487 case ISD::SETGT: return ARMCC::GT;
488 case ISD::SETGE: return ARMCC::GE;
489 case ISD::SETLT: return ARMCC::LT;
490 case ISD::SETLE: return ARMCC::LE;
491 case ISD::SETUGT: return ARMCC::HI;
492 case ISD::SETUGE: return ARMCC::HS;
493 case ISD::SETULT: return ARMCC::LO;
494 case ISD::SETULE: return ARMCC::LS;
498 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
499 /// returns true if the operands should be inverted to form the proper
501 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
502 ARMCC::CondCodes &CondCode2) {
504 CondCode2 = ARMCC::AL;
506 default: llvm_unreachable("Unknown FP condition!");
508 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
510 case ISD::SETOGT: CondCode = ARMCC::GT; break;
512 case ISD::SETOGE: CondCode = ARMCC::GE; break;
513 case ISD::SETOLT: CondCode = ARMCC::MI; break;
514 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
515 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
516 case ISD::SETO: CondCode = ARMCC::VC; break;
517 case ISD::SETUO: CondCode = ARMCC::VS; break;
518 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
519 case ISD::SETUGT: CondCode = ARMCC::HI; break;
520 case ISD::SETUGE: CondCode = ARMCC::PL; break;
522 case ISD::SETULT: CondCode = ARMCC::LT; break;
524 case ISD::SETULE: CondCode = ARMCC::LE; break;
526 case ISD::SETUNE: CondCode = ARMCC::NE; break;
531 //===----------------------------------------------------------------------===//
532 // Calling Convention Implementation
533 //===----------------------------------------------------------------------===//
535 #include "ARMGenCallingConv.inc"
537 // APCS f64 is in register pairs, possibly split to stack
538 static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
539 CCValAssign::LocInfo &LocInfo,
540 CCState &State, bool CanFail) {
541 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
543 // Try to get the first register.
544 if (unsigned Reg = State.AllocateReg(RegList, 4))
545 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
547 // For the 2nd half of a v2f64, do not fail.
551 // Put the whole thing on the stack.
552 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
553 State.AllocateStack(8, 4),
558 // Try to get the second register.
559 if (unsigned Reg = State.AllocateReg(RegList, 4))
560 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
562 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
563 State.AllocateStack(4, 4),
568 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
569 CCValAssign::LocInfo &LocInfo,
570 ISD::ArgFlagsTy &ArgFlags,
572 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
574 if (LocVT == MVT::v2f64 &&
575 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
577 return true; // we handled it
580 // AAPCS f64 is in aligned register pairs
581 static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
582 CCValAssign::LocInfo &LocInfo,
583 CCState &State, bool CanFail) {
584 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
585 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
587 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
589 // For the 2nd half of a v2f64, do not just fail.
593 // Put the whole thing on the stack.
594 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
595 State.AllocateStack(8, 8),
601 for (i = 0; i < 2; ++i)
602 if (HiRegList[i] == Reg)
605 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
606 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
611 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
612 CCValAssign::LocInfo &LocInfo,
613 ISD::ArgFlagsTy &ArgFlags,
615 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
617 if (LocVT == MVT::v2f64 &&
618 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
620 return true; // we handled it
623 static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
624 CCValAssign::LocInfo &LocInfo, CCState &State) {
625 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
626 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
628 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
630 return false; // we didn't handle it
633 for (i = 0; i < 2; ++i)
634 if (HiRegList[i] == Reg)
637 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
638 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
643 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
644 CCValAssign::LocInfo &LocInfo,
645 ISD::ArgFlagsTy &ArgFlags,
647 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
649 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
651 return true; // we handled it
654 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
655 CCValAssign::LocInfo &LocInfo,
656 ISD::ArgFlagsTy &ArgFlags,
658 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
662 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
663 /// given CallingConvention value.
664 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
666 bool isVarArg) const {
669 llvm_unreachable("Unsupported calling convention");
671 case CallingConv::Fast:
672 // Use target triple & subtarget features to do actual dispatch.
673 if (Subtarget->isAAPCS_ABI()) {
674 if (Subtarget->hasVFP2() &&
675 FloatABIType == FloatABI::Hard && !isVarArg)
676 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
678 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
680 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
681 case CallingConv::ARM_AAPCS_VFP:
682 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
683 case CallingConv::ARM_AAPCS:
684 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
685 case CallingConv::ARM_APCS:
686 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
690 /// LowerCallResult - Lower the result values of a call into the
691 /// appropriate copies out of appropriate physical registers.
693 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
694 unsigned CallConv, bool isVarArg,
695 const SmallVectorImpl<ISD::InputArg> &Ins,
696 DebugLoc dl, SelectionDAG &DAG,
697 SmallVectorImpl<SDValue> &InVals) {
699 // Assign locations to each value returned by this call.
700 SmallVector<CCValAssign, 16> RVLocs;
701 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
702 RVLocs, *DAG.getContext());
703 CCInfo.AnalyzeCallResult(Ins,
704 CCAssignFnForNode(CallConv, /* Return*/ true,
707 // Copy all of the result registers out of their specified physreg.
708 for (unsigned i = 0; i != RVLocs.size(); ++i) {
709 CCValAssign VA = RVLocs[i];
712 if (VA.needsCustom()) {
713 // Handle f64 or half of a v2f64.
714 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
716 Chain = Lo.getValue(1);
717 InFlag = Lo.getValue(2);
718 VA = RVLocs[++i]; // skip ahead to next loc
719 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
721 Chain = Hi.getValue(1);
722 InFlag = Hi.getValue(2);
723 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
725 if (VA.getLocVT() == MVT::v2f64) {
726 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
727 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
728 DAG.getConstant(0, MVT::i32));
730 VA = RVLocs[++i]; // skip ahead to next loc
731 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
732 Chain = Lo.getValue(1);
733 InFlag = Lo.getValue(2);
734 VA = RVLocs[++i]; // skip ahead to next loc
735 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
736 Chain = Hi.getValue(1);
737 InFlag = Hi.getValue(2);
738 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
739 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
740 DAG.getConstant(1, MVT::i32));
743 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
745 Chain = Val.getValue(1);
746 InFlag = Val.getValue(2);
749 switch (VA.getLocInfo()) {
750 default: llvm_unreachable("Unknown loc info!");
751 case CCValAssign::Full: break;
752 case CCValAssign::BCvt:
753 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
757 InVals.push_back(Val);
763 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
764 /// by "Src" to address "Dst" of size "Size". Alignment information is
765 /// specified by the specific parameter attribute. The copy will be passed as
766 /// a byval function parameter.
767 /// Sometimes what we are copying is the end of a larger object, the part that
768 /// does not fit in registers.
770 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
771 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
773 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
774 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
775 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
778 /// LowerMemOpCallTo - Store the argument to the stack.
780 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
781 SDValue StackPtr, SDValue Arg,
782 DebugLoc dl, SelectionDAG &DAG,
783 const CCValAssign &VA,
784 ISD::ArgFlagsTy Flags) {
785 unsigned LocMemOffset = VA.getLocMemOffset();
786 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
787 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
788 if (Flags.isByVal()) {
789 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
791 return DAG.getStore(Chain, dl, Arg, PtrOff,
792 PseudoSourceValue::getStack(), LocMemOffset);
795 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
796 SDValue Chain, SDValue &Arg,
797 RegsToPassVector &RegsToPass,
798 CCValAssign &VA, CCValAssign &NextVA,
800 SmallVector<SDValue, 8> &MemOpChains,
801 ISD::ArgFlagsTy Flags) {
803 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
804 DAG.getVTList(MVT::i32, MVT::i32), Arg);
805 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
807 if (NextVA.isRegLoc())
808 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
810 assert(NextVA.isMemLoc());
811 if (StackPtr.getNode() == 0)
812 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
814 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
820 /// LowerCall - Lowering a call into a callseq_start <-
821 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
824 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
825 unsigned CallConv, bool isVarArg,
827 const SmallVectorImpl<ISD::OutputArg> &Outs,
828 const SmallVectorImpl<ISD::InputArg> &Ins,
829 DebugLoc dl, SelectionDAG &DAG,
830 SmallVectorImpl<SDValue> &InVals) {
832 // Analyze operands of the call, assigning locations to each operand.
833 SmallVector<CCValAssign, 16> ArgLocs;
834 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
836 CCInfo.AnalyzeCallOperands(Outs,
837 CCAssignFnForNode(CallConv, /* Return*/ false,
840 // Get a count of how many bytes are to be pushed on the stack.
841 unsigned NumBytes = CCInfo.getNextStackOffset();
843 // Adjust the stack pointer for the new arguments...
844 // These operations are automatically eliminated by the prolog/epilog pass
845 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
847 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
849 RegsToPassVector RegsToPass;
850 SmallVector<SDValue, 8> MemOpChains;
852 // Walk the register/memloc assignments, inserting copies/loads. In the case
853 // of tail call optimization, arguments are handled later.
854 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
857 CCValAssign &VA = ArgLocs[i];
858 SDValue Arg = Outs[realArgIdx].Val;
859 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
861 // Promote the value if needed.
862 switch (VA.getLocInfo()) {
863 default: llvm_unreachable("Unknown loc info!");
864 case CCValAssign::Full: break;
865 case CCValAssign::SExt:
866 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
868 case CCValAssign::ZExt:
869 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
871 case CCValAssign::AExt:
872 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
874 case CCValAssign::BCvt:
875 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
879 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
880 if (VA.needsCustom()) {
881 if (VA.getLocVT() == MVT::v2f64) {
882 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
883 DAG.getConstant(0, MVT::i32));
884 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
885 DAG.getConstant(1, MVT::i32));
887 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
888 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
890 VA = ArgLocs[++i]; // skip ahead to next loc
892 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
893 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
895 assert(VA.isMemLoc());
896 if (StackPtr.getNode() == 0)
897 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
899 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
900 dl, DAG, VA, Flags));
903 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
904 StackPtr, MemOpChains, Flags);
906 } else if (VA.isRegLoc()) {
907 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
909 assert(VA.isMemLoc());
910 if (StackPtr.getNode() == 0)
911 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
913 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
914 dl, DAG, VA, Flags));
918 if (!MemOpChains.empty())
919 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
920 &MemOpChains[0], MemOpChains.size());
922 // Build a sequence of copy-to-reg nodes chained together with token chain
923 // and flag operands which copy the outgoing args into the appropriate regs.
925 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
926 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
927 RegsToPass[i].second, InFlag);
928 InFlag = Chain.getValue(1);
931 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
932 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
933 // node so that legalize doesn't hack it.
934 bool isDirect = false;
935 bool isARMFunc = false;
936 bool isLocalARMFunc = false;
937 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
938 GlobalValue *GV = G->getGlobal();
940 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
941 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
942 getTargetMachine().getRelocationModel() != Reloc::Static;
943 isARMFunc = !Subtarget->isThumb() || isStub;
944 // ARM call to a local ARM function is predicable.
945 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
946 // tBX takes a register source operand.
947 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
948 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
950 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
951 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
952 Callee = DAG.getLoad(getPointerTy(), dl,
953 DAG.getEntryNode(), CPAddr, NULL, 0);
954 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
955 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
956 getPointerTy(), Callee, PICLabel);
958 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
959 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
961 bool isStub = Subtarget->isTargetDarwin() &&
962 getTargetMachine().getRelocationModel() != Reloc::Static;
963 isARMFunc = !Subtarget->isThumb() || isStub;
964 // tBX takes a register source operand.
965 const char *Sym = S->getSymbol();
966 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
967 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
969 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
970 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
971 Callee = DAG.getLoad(getPointerTy(), dl,
972 DAG.getEntryNode(), CPAddr, NULL, 0);
973 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
974 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
975 getPointerTy(), Callee, PICLabel);
977 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
980 // FIXME: handle tail calls differently.
982 if (Subtarget->isThumb()) {
983 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
984 CallOpc = ARMISD::CALL_NOLINK;
986 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
988 CallOpc = (isDirect || Subtarget->hasV5TOps())
989 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
990 : ARMISD::CALL_NOLINK;
992 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
993 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
994 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
995 InFlag = Chain.getValue(1);
998 std::vector<SDValue> Ops;
999 Ops.push_back(Chain);
1000 Ops.push_back(Callee);
1002 // Add argument registers to the end of the list so that they are known live
1004 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1005 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1006 RegsToPass[i].second.getValueType()));
1008 if (InFlag.getNode())
1009 Ops.push_back(InFlag);
1010 // Returns a chain and a flag for retval copy to use.
1011 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1012 &Ops[0], Ops.size());
1013 InFlag = Chain.getValue(1);
1015 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1016 DAG.getIntPtrConstant(0, true), InFlag);
1018 InFlag = Chain.getValue(1);
1020 // Handle result values, copying them out of physregs into vregs that we
1022 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1027 ARMTargetLowering::LowerReturn(SDValue Chain,
1028 unsigned CallConv, bool isVarArg,
1029 const SmallVectorImpl<ISD::OutputArg> &Outs,
1030 DebugLoc dl, SelectionDAG &DAG) {
1032 // CCValAssign - represent the assignment of the return value to a location.
1033 SmallVector<CCValAssign, 16> RVLocs;
1035 // CCState - Info about the registers and stack slots.
1036 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1039 // Analyze outgoing return values.
1040 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1043 // If this is the first return lowered for this function, add
1044 // the regs to the liveout set for the function.
1045 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1046 for (unsigned i = 0; i != RVLocs.size(); ++i)
1047 if (RVLocs[i].isRegLoc())
1048 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1053 // Copy the result values into the output registers.
1054 for (unsigned i = 0, realRVLocIdx = 0;
1056 ++i, ++realRVLocIdx) {
1057 CCValAssign &VA = RVLocs[i];
1058 assert(VA.isRegLoc() && "Can only return in registers!");
1060 SDValue Arg = Outs[realRVLocIdx].Val;
1062 switch (VA.getLocInfo()) {
1063 default: llvm_unreachable("Unknown loc info!");
1064 case CCValAssign::Full: break;
1065 case CCValAssign::BCvt:
1066 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1070 if (VA.needsCustom()) {
1071 if (VA.getLocVT() == MVT::v2f64) {
1072 // Extract the first half and return it in two registers.
1073 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1074 DAG.getConstant(0, MVT::i32));
1075 SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
1076 DAG.getVTList(MVT::i32, MVT::i32), Half);
1078 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1079 Flag = Chain.getValue(1);
1080 VA = RVLocs[++i]; // skip ahead to next loc
1081 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1082 HalfGPRs.getValue(1), Flag);
1083 Flag = Chain.getValue(1);
1084 VA = RVLocs[++i]; // skip ahead to next loc
1086 // Extract the 2nd half and fall through to handle it as an f64 value.
1087 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1088 DAG.getConstant(1, MVT::i32));
1090 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1092 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
1093 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1094 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1095 Flag = Chain.getValue(1);
1096 VA = RVLocs[++i]; // skip ahead to next loc
1097 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1100 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1102 // Guarantee that all emitted copies are
1103 // stuck together, avoiding something bad.
1104 Flag = Chain.getValue(1);
1109 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1111 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1116 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1117 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1118 // one of the above mentioned nodes. It has to be wrapped because otherwise
1119 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1120 // be used to form addressing mode. These wrapped nodes will be selected
1122 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1123 MVT PtrVT = Op.getValueType();
1124 // FIXME there is no actual debug info here
1125 DebugLoc dl = Op.getDebugLoc();
1126 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1128 if (CP->isMachineConstantPoolEntry())
1129 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1130 CP->getAlignment());
1132 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1133 CP->getAlignment());
1134 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1137 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1139 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1140 SelectionDAG &DAG) {
1141 DebugLoc dl = GA->getDebugLoc();
1142 MVT PtrVT = getPointerTy();
1143 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1144 ARMConstantPoolValue *CPV =
1145 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1146 PCAdj, "tlsgd", true);
1147 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1148 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1149 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
1150 SDValue Chain = Argument.getValue(1);
1152 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1153 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1155 // call __tls_get_addr.
1158 Entry.Node = Argument;
1159 Entry.Ty = (const Type *) Type::Int32Ty;
1160 Args.push_back(Entry);
1161 // FIXME: is there useful debug info available here?
1162 std::pair<SDValue, SDValue> CallResult =
1163 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
1164 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1165 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1166 return CallResult.first;
1169 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1170 // "local exec" model.
1172 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1173 SelectionDAG &DAG) {
1174 GlobalValue *GV = GA->getGlobal();
1175 DebugLoc dl = GA->getDebugLoc();
1177 SDValue Chain = DAG.getEntryNode();
1178 MVT PtrVT = getPointerTy();
1179 // Get the Thread Pointer
1180 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1182 if (GV->isDeclaration()) {
1183 // initial exec model
1184 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1185 ARMConstantPoolValue *CPV =
1186 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1187 PCAdj, "gottpoff", true);
1188 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1189 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1190 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1191 Chain = Offset.getValue(1);
1193 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1194 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1196 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1199 ARMConstantPoolValue *CPV =
1200 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
1201 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1202 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1203 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1206 // The address of the thread local variable is the add of the thread
1207 // pointer with the offset of the variable.
1208 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1212 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1213 // TODO: implement the "local dynamic" model
1214 assert(Subtarget->isTargetELF() &&
1215 "TLS not implemented for non-ELF targets");
1216 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1217 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1218 // otherwise use the "Local Exec" TLS Model
1219 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1220 return LowerToTLSGeneralDynamicModel(GA, DAG);
1222 return LowerToTLSExecModels(GA, DAG);
1225 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1226 SelectionDAG &DAG) {
1227 MVT PtrVT = getPointerTy();
1228 DebugLoc dl = Op.getDebugLoc();
1229 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1230 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1231 if (RelocM == Reloc::PIC_) {
1232 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1233 ARMConstantPoolValue *CPV =
1234 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
1235 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1236 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1237 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1239 SDValue Chain = Result.getValue(1);
1240 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1241 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1243 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1246 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1247 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1248 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1252 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
1253 /// even in non-static mode.
1254 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
1255 // If symbol visibility is hidden, the extra load is not needed if
1256 // the symbol is definitely defined in the current translation unit.
1257 bool isDecl = GV->isDeclaration() || GV->hasAvailableExternallyLinkage();
1258 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
1260 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
1263 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1264 SelectionDAG &DAG) {
1265 MVT PtrVT = getPointerTy();
1266 DebugLoc dl = Op.getDebugLoc();
1267 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1268 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1269 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
1271 if (RelocM == Reloc::Static)
1272 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1274 unsigned PCAdj = (RelocM != Reloc::PIC_)
1275 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1276 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1278 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1280 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1282 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1284 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1285 SDValue Chain = Result.getValue(1);
1287 if (RelocM == Reloc::PIC_) {
1288 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1289 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1292 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1297 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1299 assert(Subtarget->isTargetELF() &&
1300 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1301 MVT PtrVT = getPointerTy();
1302 DebugLoc dl = Op.getDebugLoc();
1303 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1304 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
1306 ARMCP::CPValue, PCAdj);
1307 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1308 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1309 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1310 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1311 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1314 static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
1316 SDNode *Node = Op.getNode();
1317 MVT VT = Node->getValueType(0);
1318 DebugLoc dl = Op.getDebugLoc();
1320 if (!VT.is64BitVector())
1321 return SDValue(); // unimplemented
1323 SDValue Ops[] = { Node->getOperand(0),
1324 Node->getOperand(2) };
1325 return DAG.getNode(Opcode, dl, Node->getVTList(), Ops, 2);
1329 ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
1330 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1332 case Intrinsic::arm_neon_vld2i:
1333 case Intrinsic::arm_neon_vld2f:
1334 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD2D);
1335 case Intrinsic::arm_neon_vld3i:
1336 case Intrinsic::arm_neon_vld3f:
1337 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD3D);
1338 case Intrinsic::arm_neon_vld4i:
1339 case Intrinsic::arm_neon_vld4f:
1340 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD4D);
1341 case Intrinsic::arm_neon_vst2i:
1342 case Intrinsic::arm_neon_vst2f:
1343 case Intrinsic::arm_neon_vst3i:
1344 case Intrinsic::arm_neon_vst3f:
1345 case Intrinsic::arm_neon_vst4i:
1346 case Intrinsic::arm_neon_vst4f:
1347 default: return SDValue(); // Don't custom lower most intrinsics.
1352 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1353 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1354 DebugLoc dl = Op.getDebugLoc();
1356 default: return SDValue(); // Don't custom lower most intrinsics.
1357 case Intrinsic::arm_thread_pointer: {
1358 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1359 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1361 case Intrinsic::eh_sjlj_setjmp:
1362 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1366 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1367 unsigned VarArgsFrameIndex) {
1368 // vastart just stores the address of the VarArgsFrameIndex slot into the
1369 // memory location argument.
1370 DebugLoc dl = Op.getDebugLoc();
1371 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1372 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1373 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1374 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1378 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1379 SDValue &Root, SelectionDAG &DAG,
1381 MachineFunction &MF = DAG.getMachineFunction();
1382 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1384 TargetRegisterClass *RC;
1385 if (AFI->isThumb1OnlyFunction())
1386 RC = ARM::tGPRRegisterClass;
1388 RC = ARM::GPRRegisterClass;
1390 // Transform the arguments stored in physical registers into virtual ones.
1391 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1392 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1395 if (NextVA.isMemLoc()) {
1396 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1397 MachineFrameInfo *MFI = MF.getFrameInfo();
1398 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset());
1400 // Create load node to retrieve arguments from the stack.
1401 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1402 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1404 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1405 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1408 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
1412 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1413 unsigned CallConv, bool isVarArg,
1414 const SmallVectorImpl<ISD::InputArg>
1416 DebugLoc dl, SelectionDAG &DAG,
1417 SmallVectorImpl<SDValue> &InVals) {
1419 MachineFunction &MF = DAG.getMachineFunction();
1420 MachineFrameInfo *MFI = MF.getFrameInfo();
1422 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1424 // Assign locations to all of the incoming arguments.
1425 SmallVector<CCValAssign, 16> ArgLocs;
1426 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1428 CCInfo.AnalyzeFormalArguments(Ins,
1429 CCAssignFnForNode(CallConv, /* Return*/ false,
1432 SmallVector<SDValue, 16> ArgValues;
1434 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1435 CCValAssign &VA = ArgLocs[i];
1437 // Arguments stored in registers.
1438 if (VA.isRegLoc()) {
1439 MVT RegVT = VA.getLocVT();
1442 if (VA.needsCustom()) {
1443 // f64 and vector types are split up into multiple registers or
1444 // combinations of registers and stack slots.
1447 if (VA.getLocVT() == MVT::v2f64) {
1448 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1450 VA = ArgLocs[++i]; // skip ahead to next loc
1451 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1453 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1454 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1455 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1456 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1457 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1459 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1462 TargetRegisterClass *RC;
1463 bool IsHardFloatCC = (CallConv == CallingConv::ARM_AAPCS_VFP);
1465 if (IsHardFloatCC && RegVT == MVT::f32)
1466 RC = ARM::SPRRegisterClass;
1467 else if (IsHardFloatCC && RegVT == MVT::f64)
1468 RC = ARM::DPRRegisterClass;
1469 else if (IsHardFloatCC && RegVT == MVT::v2f64)
1470 RC = ARM::QPRRegisterClass;
1471 else if (AFI->isThumb1OnlyFunction())
1472 RC = ARM::tGPRRegisterClass;
1474 RC = ARM::GPRRegisterClass;
1476 assert((RegVT == MVT::i32 || RegVT == MVT::f32 ||
1478 ((RegVT == MVT::f64) || (RegVT == MVT::v2f64)))) &&
1479 "RegVT not supported by FORMAL_ARGUMENTS Lowering");
1481 // Transform the arguments in physical registers into virtual ones.
1482 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1483 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1486 // If this is an 8 or 16-bit value, it is really passed promoted
1487 // to 32 bits. Insert an assert[sz]ext to capture this, then
1488 // truncate to the right size.
1489 switch (VA.getLocInfo()) {
1490 default: llvm_unreachable("Unknown loc info!");
1491 case CCValAssign::Full: break;
1492 case CCValAssign::BCvt:
1493 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1495 case CCValAssign::SExt:
1496 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1497 DAG.getValueType(VA.getValVT()));
1498 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1500 case CCValAssign::ZExt:
1501 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1502 DAG.getValueType(VA.getValVT()));
1503 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1507 InVals.push_back(ArgValue);
1509 } else { // VA.isRegLoc()
1512 assert(VA.isMemLoc());
1513 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1515 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1516 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1518 // Create load nodes to retrieve arguments from the stack.
1519 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1520 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1526 static const unsigned GPRArgRegs[] = {
1527 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1530 unsigned NumGPRs = CCInfo.getFirstUnallocated
1531 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1533 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1534 unsigned VARegSize = (4 - NumGPRs) * 4;
1535 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1536 unsigned ArgOffset = 0;
1537 if (VARegSaveSize) {
1538 // If this function is vararg, store any remaining integer argument regs
1539 // to their spots on the stack so that they may be loaded by deferencing
1540 // the result of va_next.
1541 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1542 ArgOffset = CCInfo.getNextStackOffset();
1543 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1544 VARegSaveSize - VARegSize);
1545 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1547 SmallVector<SDValue, 4> MemOps;
1548 for (; NumGPRs < 4; ++NumGPRs) {
1549 TargetRegisterClass *RC;
1550 if (AFI->isThumb1OnlyFunction())
1551 RC = ARM::tGPRRegisterClass;
1553 RC = ARM::GPRRegisterClass;
1555 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1556 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1557 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1558 MemOps.push_back(Store);
1559 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1560 DAG.getConstant(4, getPointerTy()));
1562 if (!MemOps.empty())
1563 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1564 &MemOps[0], MemOps.size());
1566 // This will point to the next argument passed via stack.
1567 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1573 /// isFloatingPointZero - Return true if this is +0.0.
1574 static bool isFloatingPointZero(SDValue Op) {
1575 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1576 return CFP->getValueAPF().isPosZero();
1577 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1578 // Maybe this has already been legalized into the constant pool?
1579 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1580 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1581 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1582 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1583 return CFP->getValueAPF().isPosZero();
1589 static bool isLegalCmpImmediate(unsigned C, bool isThumb1Only) {
1590 return ( isThumb1Only && (C & ~255U) == 0) ||
1591 (!isThumb1Only && ARM_AM::getSOImmVal(C) != -1);
1594 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1595 /// the given operands.
1596 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1597 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb1Only,
1599 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1600 unsigned C = RHSC->getZExtValue();
1601 if (!isLegalCmpImmediate(C, isThumb1Only)) {
1602 // Constant does not fit, try adjusting it by one?
1607 if (isLegalCmpImmediate(C-1, isThumb1Only)) {
1608 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1609 RHS = DAG.getConstant(C-1, MVT::i32);
1614 if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
1615 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1616 RHS = DAG.getConstant(C-1, MVT::i32);
1621 if (isLegalCmpImmediate(C+1, isThumb1Only)) {
1622 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1623 RHS = DAG.getConstant(C+1, MVT::i32);
1628 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
1629 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1630 RHS = DAG.getConstant(C+1, MVT::i32);
1637 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1638 ARMISD::NodeType CompareType;
1641 CompareType = ARMISD::CMP;
1646 CompareType = ARMISD::CMPZ;
1649 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1650 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1653 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1654 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1657 if (!isFloatingPointZero(RHS))
1658 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1660 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1661 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1664 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1665 const ARMSubtarget *ST) {
1666 MVT VT = Op.getValueType();
1667 SDValue LHS = Op.getOperand(0);
1668 SDValue RHS = Op.getOperand(1);
1669 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1670 SDValue TrueVal = Op.getOperand(2);
1671 SDValue FalseVal = Op.getOperand(3);
1672 DebugLoc dl = Op.getDebugLoc();
1674 if (LHS.getValueType() == MVT::i32) {
1676 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1677 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1678 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1681 ARMCC::CondCodes CondCode, CondCode2;
1682 if (FPCCToARMCC(CC, CondCode, CondCode2))
1683 std::swap(TrueVal, FalseVal);
1685 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1686 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1687 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1688 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1690 if (CondCode2 != ARMCC::AL) {
1691 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1692 // FIXME: Needs another CMP because flag can have but one use.
1693 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1694 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1695 Result, TrueVal, ARMCC2, CCR, Cmp2);
1700 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1701 const ARMSubtarget *ST) {
1702 SDValue Chain = Op.getOperand(0);
1703 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1704 SDValue LHS = Op.getOperand(2);
1705 SDValue RHS = Op.getOperand(3);
1706 SDValue Dest = Op.getOperand(4);
1707 DebugLoc dl = Op.getDebugLoc();
1709 if (LHS.getValueType() == MVT::i32) {
1711 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1712 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1713 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1714 Chain, Dest, ARMCC, CCR,Cmp);
1717 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1718 ARMCC::CondCodes CondCode, CondCode2;
1719 if (FPCCToARMCC(CC, CondCode, CondCode2))
1720 // Swap the LHS/RHS of the comparison if needed.
1721 std::swap(LHS, RHS);
1723 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1724 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1725 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1726 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1727 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1728 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1729 if (CondCode2 != ARMCC::AL) {
1730 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1731 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1732 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1737 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1738 SDValue Chain = Op.getOperand(0);
1739 SDValue Table = Op.getOperand(1);
1740 SDValue Index = Op.getOperand(2);
1741 DebugLoc dl = Op.getDebugLoc();
1743 MVT PTy = getPointerTy();
1744 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1745 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1746 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1747 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1748 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1749 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1750 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1751 if (Subtarget->isThumb2()) {
1752 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1753 // which does another jump to the destination. This also makes it easier
1754 // to translate it to TBB / TBH later.
1755 // FIXME: This might not work if the function is extremely large.
1756 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1757 Addr, Op.getOperand(2), JTI, UId);
1759 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1760 Addr = DAG.getLoad((MVT)MVT::i32, dl, Chain, Addr, NULL, 0);
1761 Chain = Addr.getValue(1);
1762 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1763 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1765 Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
1766 Chain = Addr.getValue(1);
1767 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1771 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1772 DebugLoc dl = Op.getDebugLoc();
1774 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1775 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1776 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1779 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1780 MVT VT = Op.getValueType();
1781 DebugLoc dl = Op.getDebugLoc();
1783 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1785 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1786 return DAG.getNode(Opc, dl, VT, Op);
1789 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1790 // Implement fcopysign with a fabs and a conditional fneg.
1791 SDValue Tmp0 = Op.getOperand(0);
1792 SDValue Tmp1 = Op.getOperand(1);
1793 DebugLoc dl = Op.getDebugLoc();
1794 MVT VT = Op.getValueType();
1795 MVT SrcVT = Tmp1.getValueType();
1796 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1797 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1798 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1799 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1800 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1803 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1804 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1805 MFI->setFrameAddressIsTaken(true);
1806 MVT VT = Op.getValueType();
1807 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1808 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1809 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1810 ? ARM::R7 : ARM::R11;
1811 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1813 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1818 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1820 SDValue Dst, SDValue Src,
1821 SDValue Size, unsigned Align,
1823 const Value *DstSV, uint64_t DstSVOff,
1824 const Value *SrcSV, uint64_t SrcSVOff){
1825 // Do repeated 4-byte loads and stores. To be improved.
1826 // This requires 4-byte alignment.
1827 if ((Align & 3) != 0)
1829 // This requires the copy size to be a constant, preferrably
1830 // within a subtarget-specific limit.
1831 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1834 uint64_t SizeVal = ConstantSize->getZExtValue();
1835 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1838 unsigned BytesLeft = SizeVal & 3;
1839 unsigned NumMemOps = SizeVal >> 2;
1840 unsigned EmittedNumMemOps = 0;
1842 unsigned VTSize = 4;
1844 const unsigned MAX_LOADS_IN_LDM = 6;
1845 SDValue TFOps[MAX_LOADS_IN_LDM];
1846 SDValue Loads[MAX_LOADS_IN_LDM];
1847 uint64_t SrcOff = 0, DstOff = 0;
1849 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1850 // same number of stores. The loads and stores will get combined into
1851 // ldm/stm later on.
1852 while (EmittedNumMemOps < NumMemOps) {
1854 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1855 Loads[i] = DAG.getLoad(VT, dl, Chain,
1856 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1857 DAG.getConstant(SrcOff, MVT::i32)),
1858 SrcSV, SrcSVOff + SrcOff);
1859 TFOps[i] = Loads[i].getValue(1);
1862 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1865 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1866 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1867 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1868 DAG.getConstant(DstOff, MVT::i32)),
1869 DstSV, DstSVOff + DstOff);
1872 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1874 EmittedNumMemOps += i;
1880 // Issue loads / stores for the trailing (1 - 3) bytes.
1881 unsigned BytesLeftSave = BytesLeft;
1884 if (BytesLeft >= 2) {
1892 Loads[i] = DAG.getLoad(VT, dl, Chain,
1893 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1894 DAG.getConstant(SrcOff, MVT::i32)),
1895 SrcSV, SrcSVOff + SrcOff);
1896 TFOps[i] = Loads[i].getValue(1);
1899 BytesLeft -= VTSize;
1901 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1904 BytesLeft = BytesLeftSave;
1906 if (BytesLeft >= 2) {
1914 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1915 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1916 DAG.getConstant(DstOff, MVT::i32)),
1917 DstSV, DstSVOff + DstOff);
1920 BytesLeft -= VTSize;
1922 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1925 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1926 SDValue Op = N->getOperand(0);
1927 DebugLoc dl = N->getDebugLoc();
1928 if (N->getValueType(0) == MVT::f64) {
1929 // Turn i64->f64 into FMDRR.
1930 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1931 DAG.getConstant(0, MVT::i32));
1932 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1933 DAG.getConstant(1, MVT::i32));
1934 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
1937 // Turn f64->i64 into FMRRD.
1938 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
1939 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
1941 // Merge the pieces into a single i64 value.
1942 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
1945 /// getZeroVector - Returns a vector of specified type with all zero elements.
1947 static SDValue getZeroVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
1948 assert(VT.isVector() && "Expected a vector type");
1950 // Zero vectors are used to represent vector negation and in those cases
1951 // will be implemented with the NEON VNEG instruction. However, VNEG does
1952 // not support i64 elements, so sometimes the zero vectors will need to be
1953 // explicitly constructed. For those cases, and potentially other uses in
1954 // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
1955 // to their dest type. This ensures they get CSE'd.
1957 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
1958 if (VT.getSizeInBits() == 64)
1959 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
1961 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
1963 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
1966 /// getOnesVector - Returns a vector of specified type with all bits set.
1968 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
1969 assert(VT.isVector() && "Expected a vector type");
1971 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
1972 // type. This ensures they get CSE'd.
1974 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
1975 if (VT.getSizeInBits() == 64)
1976 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
1978 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
1980 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
1983 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
1984 const ARMSubtarget *ST) {
1985 MVT VT = N->getValueType(0);
1986 DebugLoc dl = N->getDebugLoc();
1988 // Lower vector shifts on NEON to use VSHL.
1989 if (VT.isVector()) {
1990 assert(ST->hasNEON() && "unexpected vector shift");
1992 // Left shifts translate directly to the vshiftu intrinsic.
1993 if (N->getOpcode() == ISD::SHL)
1994 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
1995 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
1996 N->getOperand(0), N->getOperand(1));
1998 assert((N->getOpcode() == ISD::SRA ||
1999 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2001 // NEON uses the same intrinsics for both left and right shifts. For
2002 // right shifts, the shift amounts are negative, so negate the vector of
2004 MVT ShiftVT = N->getOperand(1).getValueType();
2005 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2006 getZeroVector(ShiftVT, DAG, dl),
2008 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2009 Intrinsic::arm_neon_vshifts :
2010 Intrinsic::arm_neon_vshiftu);
2011 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2012 DAG.getConstant(vshiftInt, MVT::i32),
2013 N->getOperand(0), NegatedCount);
2016 assert(VT == MVT::i64 &&
2017 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2018 "Unknown shift to lower!");
2020 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2021 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2022 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2025 // If we are in thumb mode, we don't have RRX.
2026 if (ST->isThumb1Only()) return SDValue();
2028 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2029 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2030 DAG.getConstant(0, MVT::i32));
2031 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2032 DAG.getConstant(1, MVT::i32));
2034 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2035 // captures the result into a carry flag.
2036 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2037 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2039 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2040 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2042 // Merge the pieces into a single i64 value.
2043 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2046 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2047 SDValue TmpOp0, TmpOp1;
2048 bool Invert = false;
2052 SDValue Op0 = Op.getOperand(0);
2053 SDValue Op1 = Op.getOperand(1);
2054 SDValue CC = Op.getOperand(2);
2055 MVT VT = Op.getValueType();
2056 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2057 DebugLoc dl = Op.getDebugLoc();
2059 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2060 switch (SetCCOpcode) {
2061 default: llvm_unreachable("Illegal FP comparison"); break;
2063 case ISD::SETNE: Invert = true; // Fallthrough
2065 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2067 case ISD::SETLT: Swap = true; // Fallthrough
2069 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2071 case ISD::SETLE: Swap = true; // Fallthrough
2073 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2074 case ISD::SETUGE: Swap = true; // Fallthrough
2075 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2076 case ISD::SETUGT: Swap = true; // Fallthrough
2077 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2078 case ISD::SETUEQ: Invert = true; // Fallthrough
2080 // Expand this to (OLT | OGT).
2084 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2085 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2087 case ISD::SETUO: Invert = true; // Fallthrough
2089 // Expand this to (OLT | OGE).
2093 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2094 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2098 // Integer comparisons.
2099 switch (SetCCOpcode) {
2100 default: llvm_unreachable("Illegal integer comparison"); break;
2101 case ISD::SETNE: Invert = true;
2102 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2103 case ISD::SETLT: Swap = true;
2104 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2105 case ISD::SETLE: Swap = true;
2106 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2107 case ISD::SETULT: Swap = true;
2108 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2109 case ISD::SETULE: Swap = true;
2110 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2113 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2114 if (Opc == ARMISD::VCEQ) {
2117 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2119 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2122 // Ignore bitconvert.
2123 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2124 AndOp = AndOp.getOperand(0);
2126 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2128 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2129 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2136 std::swap(Op0, Op1);
2138 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2141 Result = DAG.getNOT(dl, Result, VT);
2146 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2147 /// VMOV instruction, and if so, return the constant being splatted.
2148 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2149 unsigned SplatBitSize, SelectionDAG &DAG) {
2150 switch (SplatBitSize) {
2152 // Any 1-byte value is OK.
2153 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2154 return DAG.getTargetConstant(SplatBits, MVT::i8);
2157 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2158 if ((SplatBits & ~0xff) == 0 ||
2159 (SplatBits & ~0xff00) == 0)
2160 return DAG.getTargetConstant(SplatBits, MVT::i16);
2164 // NEON's 32-bit VMOV supports splat values where:
2165 // * only one byte is nonzero, or
2166 // * the least significant byte is 0xff and the second byte is nonzero, or
2167 // * the least significant 2 bytes are 0xff and the third is nonzero.
2168 if ((SplatBits & ~0xff) == 0 ||
2169 (SplatBits & ~0xff00) == 0 ||
2170 (SplatBits & ~0xff0000) == 0 ||
2171 (SplatBits & ~0xff000000) == 0)
2172 return DAG.getTargetConstant(SplatBits, MVT::i32);
2174 if ((SplatBits & ~0xffff) == 0 &&
2175 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2176 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2178 if ((SplatBits & ~0xffffff) == 0 &&
2179 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2180 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2182 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2183 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2184 // VMOV.I32. A (very) minor optimization would be to replicate the value
2185 // and fall through here to test for a valid 64-bit splat. But, then the
2186 // caller would also need to check and handle the change in size.
2190 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2191 uint64_t BitMask = 0xff;
2193 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2194 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2196 else if ((SplatBits & BitMask) != 0)
2200 return DAG.getTargetConstant(Val, MVT::i64);
2204 llvm_unreachable("unexpected size for isVMOVSplat");
2211 /// getVMOVImm - If this is a build_vector of constants which can be
2212 /// formed by using a VMOV instruction of the specified element size,
2213 /// return the constant being splatted. The ByteSize field indicates the
2214 /// number of bytes of each element [1248].
2215 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2216 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2217 APInt SplatBits, SplatUndef;
2218 unsigned SplatBitSize;
2220 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2221 HasAnyUndefs, ByteSize * 8))
2224 if (SplatBitSize > ByteSize * 8)
2227 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2231 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2232 /// instruction with the specified blocksize. (The order of the elements
2233 /// within each block of the vector is reversed.)
2234 bool ARM::isVREVMask(ShuffleVectorSDNode *N, unsigned BlockSize) {
2235 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2236 "Only possible block sizes for VREV are: 16, 32, 64");
2238 MVT VT = N->getValueType(0);
2239 unsigned NumElts = VT.getVectorNumElements();
2240 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2241 unsigned BlockElts = N->getMaskElt(0) + 1;
2243 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2246 for (unsigned i = 0; i < NumElts; ++i) {
2247 if ((unsigned) N->getMaskElt(i) !=
2248 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2255 static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) {
2256 // Canonicalize all-zeros and all-ones vectors.
2257 ConstantSDNode *ConstVal = dyn_cast<ConstantSDNode>(Val.getNode());
2258 if (ConstVal->isNullValue())
2259 return getZeroVector(VT, DAG, dl);
2260 if (ConstVal->isAllOnesValue())
2261 return getOnesVector(VT, DAG, dl);
2264 if (VT.is64BitVector()) {
2265 switch (Val.getValueType().getSizeInBits()) {
2266 case 8: CanonicalVT = MVT::v8i8; break;
2267 case 16: CanonicalVT = MVT::v4i16; break;
2268 case 32: CanonicalVT = MVT::v2i32; break;
2269 case 64: CanonicalVT = MVT::v1i64; break;
2270 default: llvm_unreachable("unexpected splat element type"); break;
2273 assert(VT.is128BitVector() && "unknown splat vector size");
2274 switch (Val.getValueType().getSizeInBits()) {
2275 case 8: CanonicalVT = MVT::v16i8; break;
2276 case 16: CanonicalVT = MVT::v8i16; break;
2277 case 32: CanonicalVT = MVT::v4i32; break;
2278 case 64: CanonicalVT = MVT::v2i64; break;
2279 default: llvm_unreachable("unexpected splat element type"); break;
2283 // Build a canonical splat for this value.
2284 SmallVector<SDValue, 8> Ops;
2285 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2286 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2288 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2291 // If this is a case we can't handle, return null and let the default
2292 // expansion code take care of it.
2293 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2294 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2295 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
2296 DebugLoc dl = Op.getDebugLoc();
2297 MVT VT = Op.getValueType();
2299 APInt SplatBits, SplatUndef;
2300 unsigned SplatBitSize;
2302 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2303 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2304 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2306 return BuildSplat(Val, VT, DAG, dl);
2309 // If there are only 2 elements in a 128-bit vector, insert them into an
2310 // undef vector. This handles the common case for 128-bit vector argument
2311 // passing, where the insertions should be translated to subreg accesses
2312 // with no real instructions.
2313 if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2314 SDValue Val = DAG.getUNDEF(VT);
2315 SDValue Op0 = Op.getOperand(0);
2316 SDValue Op1 = Op.getOperand(1);
2317 if (Op0.getOpcode() != ISD::UNDEF)
2318 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2319 DAG.getIntPtrConstant(0));
2320 if (Op1.getOpcode() != ISD::UNDEF)
2321 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2322 DAG.getIntPtrConstant(1));
2329 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2333 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
2337 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2338 MVT VT = Op.getValueType();
2339 DebugLoc dl = Op.getDebugLoc();
2340 assert((VT == MVT::i8 || VT == MVT::i16) &&
2341 "unexpected type for custom-lowering vector extract");
2342 SDValue Vec = Op.getOperand(0);
2343 SDValue Lane = Op.getOperand(1);
2344 Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2345 Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
2346 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
2349 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2350 // The only time a CONCAT_VECTORS operation can have legal types is when
2351 // two 64-bit vectors are concatenated to a 128-bit vector.
2352 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2353 "unexpected CONCAT_VECTORS");
2354 DebugLoc dl = Op.getDebugLoc();
2355 SDValue Val = DAG.getUNDEF(MVT::v2f64);
2356 SDValue Op0 = Op.getOperand(0);
2357 SDValue Op1 = Op.getOperand(1);
2358 if (Op0.getOpcode() != ISD::UNDEF)
2359 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2360 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2361 DAG.getIntPtrConstant(0));
2362 if (Op1.getOpcode() != ISD::UNDEF)
2363 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2364 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2365 DAG.getIntPtrConstant(1));
2366 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
2369 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2370 switch (Op.getOpcode()) {
2371 default: llvm_unreachable("Don't know how to custom lower this!");
2372 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2373 case ISD::GlobalAddress:
2374 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2375 LowerGlobalAddressELF(Op, DAG);
2376 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2377 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
2378 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
2379 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2380 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2381 case ISD::SINT_TO_FP:
2382 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
2383 case ISD::FP_TO_SINT:
2384 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
2385 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
2386 case ISD::RETURNADDR: break;
2387 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2388 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2389 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
2390 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2391 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
2394 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
2395 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
2396 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2397 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2398 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2399 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2400 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2405 /// ReplaceNodeResults - Replace the results of node with an illegal result
2406 /// type with new values built out of custom code.
2407 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2408 SmallVectorImpl<SDValue>&Results,
2409 SelectionDAG &DAG) {
2410 switch (N->getOpcode()) {
2412 llvm_unreachable("Don't know how to custom expand this!");
2414 case ISD::BIT_CONVERT:
2415 Results.push_back(ExpandBIT_CONVERT(N, DAG));
2419 SDValue Res = LowerShift(N, DAG, Subtarget);
2421 Results.push_back(Res);
2427 //===----------------------------------------------------------------------===//
2428 // ARM Scheduler Hooks
2429 //===----------------------------------------------------------------------===//
2432 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2433 MachineBasicBlock *BB) const {
2434 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2435 DebugLoc dl = MI->getDebugLoc();
2436 switch (MI->getOpcode()) {
2437 default: assert(false && "Unexpected instr type to insert");
2438 case ARM::tMOVCCr: {
2439 // To "insert" a SELECT_CC instruction, we actually have to insert the
2440 // diamond control-flow pattern. The incoming instruction knows the
2441 // destination vreg to set, the condition code register to branch on, the
2442 // true/false values to select between, and a branch opcode to use.
2443 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2444 MachineFunction::iterator It = BB;
2450 // cmpTY ccX, r1, r2
2452 // fallthrough --> copy0MBB
2453 MachineBasicBlock *thisMBB = BB;
2454 MachineFunction *F = BB->getParent();
2455 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2456 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2457 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2458 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2459 F->insert(It, copy0MBB);
2460 F->insert(It, sinkMBB);
2461 // Update machine-CFG edges by first adding all successors of the current
2462 // block to the new block which will contain the Phi node for the select.
2463 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2464 e = BB->succ_end(); i != e; ++i)
2465 sinkMBB->addSuccessor(*i);
2466 // Next, remove all successors of the current block, and add the true
2467 // and fallthrough blocks as its successors.
2468 while(!BB->succ_empty())
2469 BB->removeSuccessor(BB->succ_begin());
2470 BB->addSuccessor(copy0MBB);
2471 BB->addSuccessor(sinkMBB);
2474 // %FalseValue = ...
2475 // # fallthrough to sinkMBB
2478 // Update machine-CFG edges
2479 BB->addSuccessor(sinkMBB);
2482 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2485 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2486 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2487 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2489 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2495 //===----------------------------------------------------------------------===//
2496 // ARM Optimization Hooks
2497 //===----------------------------------------------------------------------===//
2500 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
2501 TargetLowering::DAGCombinerInfo &DCI) {
2502 SelectionDAG &DAG = DCI.DAG;
2503 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2504 MVT VT = N->getValueType(0);
2505 unsigned Opc = N->getOpcode();
2506 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
2507 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
2508 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
2509 ISD::CondCode CC = ISD::SETCC_INVALID;
2512 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
2514 SDValue CCOp = Slct.getOperand(0);
2515 if (CCOp.getOpcode() == ISD::SETCC)
2516 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
2519 bool DoXform = false;
2521 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
2524 if (LHS.getOpcode() == ISD::Constant &&
2525 cast<ConstantSDNode>(LHS)->isNullValue()) {
2527 } else if (CC != ISD::SETCC_INVALID &&
2528 RHS.getOpcode() == ISD::Constant &&
2529 cast<ConstantSDNode>(RHS)->isNullValue()) {
2530 std::swap(LHS, RHS);
2531 SDValue Op0 = Slct.getOperand(0);
2532 MVT OpVT = isSlctCC ? Op0.getValueType() :
2533 Op0.getOperand(0).getValueType();
2534 bool isInt = OpVT.isInteger();
2535 CC = ISD::getSetCCInverse(CC, isInt);
2537 if (!TLI.isCondCodeLegal(CC, OpVT))
2538 return SDValue(); // Inverse operator isn't legal.
2545 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
2547 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
2548 Slct.getOperand(0), Slct.getOperand(1), CC);
2549 SDValue CCOp = Slct.getOperand(0);
2551 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
2552 CCOp.getOperand(0), CCOp.getOperand(1), CC);
2553 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
2554 CCOp, OtherOp, Result);
2559 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
2560 static SDValue PerformADDCombine(SDNode *N,
2561 TargetLowering::DAGCombinerInfo &DCI) {
2562 // added by evan in r37685 with no testcase.
2563 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2565 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
2566 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
2567 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
2568 if (Result.getNode()) return Result;
2570 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2571 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2572 if (Result.getNode()) return Result;
2578 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
2579 static SDValue PerformSUBCombine(SDNode *N,
2580 TargetLowering::DAGCombinerInfo &DCI) {
2581 // added by evan in r37685 with no testcase.
2582 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2584 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
2585 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2586 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2587 if (Result.getNode()) return Result;
2594 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
2595 static SDValue PerformFMRRDCombine(SDNode *N,
2596 TargetLowering::DAGCombinerInfo &DCI) {
2597 // fmrrd(fmdrr x, y) -> x,y
2598 SDValue InDouble = N->getOperand(0);
2599 if (InDouble.getOpcode() == ARMISD::FMDRR)
2600 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
2604 /// getVShiftImm - Check if this is a valid build_vector for the immediate
2605 /// operand of a vector shift operation, where all the elements of the
2606 /// build_vector must have the same constant integer value.
2607 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
2608 // Ignore bit_converts.
2609 while (Op.getOpcode() == ISD::BIT_CONVERT)
2610 Op = Op.getOperand(0);
2611 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2612 APInt SplatBits, SplatUndef;
2613 unsigned SplatBitSize;
2615 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2616 HasAnyUndefs, ElementBits) ||
2617 SplatBitSize > ElementBits)
2619 Cnt = SplatBits.getSExtValue();
2623 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
2624 /// operand of a vector shift left operation. That value must be in the range:
2625 /// 0 <= Value < ElementBits for a left shift; or
2626 /// 0 <= Value <= ElementBits for a long left shift.
2627 static bool isVShiftLImm(SDValue Op, MVT VT, bool isLong, int64_t &Cnt) {
2628 assert(VT.isVector() && "vector shift count is not a vector type");
2629 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2630 if (! getVShiftImm(Op, ElementBits, Cnt))
2632 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
2635 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
2636 /// operand of a vector shift right operation. For a shift opcode, the value
2637 /// is positive, but for an intrinsic the value count must be negative. The
2638 /// absolute value must be in the range:
2639 /// 1 <= |Value| <= ElementBits for a right shift; or
2640 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
2641 static bool isVShiftRImm(SDValue Op, MVT VT, bool isNarrow, bool isIntrinsic,
2643 assert(VT.isVector() && "vector shift count is not a vector type");
2644 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2645 if (! getVShiftImm(Op, ElementBits, Cnt))
2649 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
2652 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
2653 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
2654 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2657 // Don't do anything for most intrinsics.
2660 // Vector shifts: check for immediate versions and lower them.
2661 // Note: This is done during DAG combining instead of DAG legalizing because
2662 // the build_vectors for 64-bit vector element shift counts are generally
2663 // not legal, and it is hard to see their values after they get legalized to
2664 // loads from a constant pool.
2665 case Intrinsic::arm_neon_vshifts:
2666 case Intrinsic::arm_neon_vshiftu:
2667 case Intrinsic::arm_neon_vshiftls:
2668 case Intrinsic::arm_neon_vshiftlu:
2669 case Intrinsic::arm_neon_vshiftn:
2670 case Intrinsic::arm_neon_vrshifts:
2671 case Intrinsic::arm_neon_vrshiftu:
2672 case Intrinsic::arm_neon_vrshiftn:
2673 case Intrinsic::arm_neon_vqshifts:
2674 case Intrinsic::arm_neon_vqshiftu:
2675 case Intrinsic::arm_neon_vqshiftsu:
2676 case Intrinsic::arm_neon_vqshiftns:
2677 case Intrinsic::arm_neon_vqshiftnu:
2678 case Intrinsic::arm_neon_vqshiftnsu:
2679 case Intrinsic::arm_neon_vqrshiftns:
2680 case Intrinsic::arm_neon_vqrshiftnu:
2681 case Intrinsic::arm_neon_vqrshiftnsu: {
2682 MVT VT = N->getOperand(1).getValueType();
2684 unsigned VShiftOpc = 0;
2687 case Intrinsic::arm_neon_vshifts:
2688 case Intrinsic::arm_neon_vshiftu:
2689 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
2690 VShiftOpc = ARMISD::VSHL;
2693 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
2694 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
2695 ARMISD::VSHRs : ARMISD::VSHRu);
2700 case Intrinsic::arm_neon_vshiftls:
2701 case Intrinsic::arm_neon_vshiftlu:
2702 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
2704 llvm_unreachable("invalid shift count for vshll intrinsic");
2706 case Intrinsic::arm_neon_vrshifts:
2707 case Intrinsic::arm_neon_vrshiftu:
2708 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
2712 case Intrinsic::arm_neon_vqshifts:
2713 case Intrinsic::arm_neon_vqshiftu:
2714 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2718 case Intrinsic::arm_neon_vqshiftsu:
2719 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2721 llvm_unreachable("invalid shift count for vqshlu intrinsic");
2723 case Intrinsic::arm_neon_vshiftn:
2724 case Intrinsic::arm_neon_vrshiftn:
2725 case Intrinsic::arm_neon_vqshiftns:
2726 case Intrinsic::arm_neon_vqshiftnu:
2727 case Intrinsic::arm_neon_vqshiftnsu:
2728 case Intrinsic::arm_neon_vqrshiftns:
2729 case Intrinsic::arm_neon_vqrshiftnu:
2730 case Intrinsic::arm_neon_vqrshiftnsu:
2731 // Narrowing shifts require an immediate right shift.
2732 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
2734 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
2737 llvm_unreachable("unhandled vector shift");
2741 case Intrinsic::arm_neon_vshifts:
2742 case Intrinsic::arm_neon_vshiftu:
2743 // Opcode already set above.
2745 case Intrinsic::arm_neon_vshiftls:
2746 case Intrinsic::arm_neon_vshiftlu:
2747 if (Cnt == VT.getVectorElementType().getSizeInBits())
2748 VShiftOpc = ARMISD::VSHLLi;
2750 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
2751 ARMISD::VSHLLs : ARMISD::VSHLLu);
2753 case Intrinsic::arm_neon_vshiftn:
2754 VShiftOpc = ARMISD::VSHRN; break;
2755 case Intrinsic::arm_neon_vrshifts:
2756 VShiftOpc = ARMISD::VRSHRs; break;
2757 case Intrinsic::arm_neon_vrshiftu:
2758 VShiftOpc = ARMISD::VRSHRu; break;
2759 case Intrinsic::arm_neon_vrshiftn:
2760 VShiftOpc = ARMISD::VRSHRN; break;
2761 case Intrinsic::arm_neon_vqshifts:
2762 VShiftOpc = ARMISD::VQSHLs; break;
2763 case Intrinsic::arm_neon_vqshiftu:
2764 VShiftOpc = ARMISD::VQSHLu; break;
2765 case Intrinsic::arm_neon_vqshiftsu:
2766 VShiftOpc = ARMISD::VQSHLsu; break;
2767 case Intrinsic::arm_neon_vqshiftns:
2768 VShiftOpc = ARMISD::VQSHRNs; break;
2769 case Intrinsic::arm_neon_vqshiftnu:
2770 VShiftOpc = ARMISD::VQSHRNu; break;
2771 case Intrinsic::arm_neon_vqshiftnsu:
2772 VShiftOpc = ARMISD::VQSHRNsu; break;
2773 case Intrinsic::arm_neon_vqrshiftns:
2774 VShiftOpc = ARMISD::VQRSHRNs; break;
2775 case Intrinsic::arm_neon_vqrshiftnu:
2776 VShiftOpc = ARMISD::VQRSHRNu; break;
2777 case Intrinsic::arm_neon_vqrshiftnsu:
2778 VShiftOpc = ARMISD::VQRSHRNsu; break;
2781 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2782 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
2785 case Intrinsic::arm_neon_vshiftins: {
2786 MVT VT = N->getOperand(1).getValueType();
2788 unsigned VShiftOpc = 0;
2790 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
2791 VShiftOpc = ARMISD::VSLI;
2792 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
2793 VShiftOpc = ARMISD::VSRI;
2795 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
2798 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2799 N->getOperand(1), N->getOperand(2),
2800 DAG.getConstant(Cnt, MVT::i32));
2803 case Intrinsic::arm_neon_vqrshifts:
2804 case Intrinsic::arm_neon_vqrshiftu:
2805 // No immediate versions of these to check for.
2812 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
2813 /// lowers them. As with the vector shift intrinsics, this is done during DAG
2814 /// combining instead of DAG legalizing because the build_vectors for 64-bit
2815 /// vector element shift counts are generally not legal, and it is hard to see
2816 /// their values after they get legalized to loads from a constant pool.
2817 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
2818 const ARMSubtarget *ST) {
2819 MVT VT = N->getValueType(0);
2821 // Nothing to be done for scalar shifts.
2822 if (! VT.isVector())
2825 assert(ST->hasNEON() && "unexpected vector shift");
2828 switch (N->getOpcode()) {
2829 default: llvm_unreachable("unexpected shift opcode");
2832 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
2833 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
2834 DAG.getConstant(Cnt, MVT::i32));
2839 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
2840 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
2841 ARMISD::VSHRs : ARMISD::VSHRu);
2842 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
2843 DAG.getConstant(Cnt, MVT::i32));
2849 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
2850 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
2851 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
2852 const ARMSubtarget *ST) {
2853 SDValue N0 = N->getOperand(0);
2855 // Check for sign- and zero-extensions of vector extract operations of 8-
2856 // and 16-bit vector elements. NEON supports these directly. They are
2857 // handled during DAG combining because type legalization will promote them
2858 // to 32-bit types and it is messy to recognize the operations after that.
2859 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
2860 SDValue Vec = N0.getOperand(0);
2861 SDValue Lane = N0.getOperand(1);
2862 MVT VT = N->getValueType(0);
2863 MVT EltVT = N0.getValueType();
2864 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2866 if (VT == MVT::i32 &&
2867 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
2868 TLI.isTypeLegal(Vec.getValueType())) {
2871 switch (N->getOpcode()) {
2872 default: llvm_unreachable("unexpected opcode");
2873 case ISD::SIGN_EXTEND:
2874 Opc = ARMISD::VGETLANEs;
2876 case ISD::ZERO_EXTEND:
2877 case ISD::ANY_EXTEND:
2878 Opc = ARMISD::VGETLANEu;
2881 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
2888 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
2889 DAGCombinerInfo &DCI) const {
2890 switch (N->getOpcode()) {
2892 case ISD::ADD: return PerformADDCombine(N, DCI);
2893 case ISD::SUB: return PerformSUBCombine(N, DCI);
2894 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
2895 case ISD::INTRINSIC_WO_CHAIN:
2896 return PerformIntrinsicCombine(N, DCI.DAG);
2900 return PerformShiftCombine(N, DCI.DAG, Subtarget);
2901 case ISD::SIGN_EXTEND:
2902 case ISD::ZERO_EXTEND:
2903 case ISD::ANY_EXTEND:
2904 return PerformExtendCombine(N, DCI.DAG, Subtarget);
2909 /// isLegalAddressImmediate - Return true if the integer value can be used
2910 /// as the offset of the target addressing mode for load / store of the
2912 static bool isLegalAddressImmediate(int64_t V, MVT VT,
2913 const ARMSubtarget *Subtarget) {
2920 if (Subtarget->isThumb()) { // FIXME for thumb2
2925 switch (VT.getSimpleVT()) {
2926 default: return false;
2941 if ((V & (Scale - 1)) != 0)
2944 return V == (V & ((1LL << 5) - 1));
2949 switch (VT.getSimpleVT()) {
2950 default: return false;
2955 return V == (V & ((1LL << 12) - 1));
2958 return V == (V & ((1LL << 8) - 1));
2961 if (!Subtarget->hasVFP2())
2966 return V == (V & ((1LL << 8) - 1));
2970 /// isLegalAddressingMode - Return true if the addressing mode represented
2971 /// by AM is legal for this target, for a load/store of the specified type.
2972 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
2973 const Type *Ty) const {
2974 MVT VT = getValueType(Ty, true);
2975 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
2978 // Can never fold addr of global into load/store.
2983 case 0: // no scale reg, must be "r+i" or "r", or "i".
2986 if (Subtarget->isThumb()) // FIXME for thumb2
2990 // ARM doesn't support any R+R*scale+imm addr modes.
2997 int Scale = AM.Scale;
2998 switch (VT.getSimpleVT()) {
2999 default: return false;
3004 // This assumes i64 is legalized to a pair of i32. If not (i.e.
3005 // ldrd / strd are used, then its address mode is same as i16.
3007 if (Scale < 0) Scale = -Scale;
3011 return isPowerOf2_32(Scale & ~1);
3014 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3019 // Note, we allow "void" uses (basically, uses that aren't loads or
3020 // stores), because arm allows folding a scale into many arithmetic
3021 // operations. This should be made more precise and revisited later.
3023 // Allow r << imm, but the imm has to be a multiple of two.
3024 if (AM.Scale & 1) return false;
3025 return isPowerOf2_32(AM.Scale);
3032 static bool getARMIndexedAddressParts(SDNode *Ptr, MVT VT,
3033 bool isSEXTLoad, SDValue &Base,
3034 SDValue &Offset, bool &isInc,
3035 SelectionDAG &DAG) {
3036 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3039 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
3041 Base = Ptr->getOperand(0);
3042 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3043 int RHSC = (int)RHS->getZExtValue();
3044 if (RHSC < 0 && RHSC > -256) {
3045 assert(Ptr->getOpcode() == ISD::ADD);
3047 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3051 isInc = (Ptr->getOpcode() == ISD::ADD);
3052 Offset = Ptr->getOperand(1);
3054 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
3056 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3057 int RHSC = (int)RHS->getZExtValue();
3058 if (RHSC < 0 && RHSC > -0x1000) {
3059 assert(Ptr->getOpcode() == ISD::ADD);
3061 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3062 Base = Ptr->getOperand(0);
3067 if (Ptr->getOpcode() == ISD::ADD) {
3069 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
3070 if (ShOpcVal != ARM_AM::no_shift) {
3071 Base = Ptr->getOperand(1);
3072 Offset = Ptr->getOperand(0);
3074 Base = Ptr->getOperand(0);
3075 Offset = Ptr->getOperand(1);
3080 isInc = (Ptr->getOpcode() == ISD::ADD);
3081 Base = Ptr->getOperand(0);
3082 Offset = Ptr->getOperand(1);
3086 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
3090 static bool getT2IndexedAddressParts(SDNode *Ptr, MVT VT,
3091 bool isSEXTLoad, SDValue &Base,
3092 SDValue &Offset, bool &isInc,
3093 SelectionDAG &DAG) {
3094 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3097 Base = Ptr->getOperand(0);
3098 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3099 int RHSC = (int)RHS->getZExtValue();
3100 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
3101 assert(Ptr->getOpcode() == ISD::ADD);
3103 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3105 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
3106 isInc = Ptr->getOpcode() == ISD::ADD;
3107 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
3115 /// getPreIndexedAddressParts - returns true by value, base pointer and
3116 /// offset pointer and addressing mode by reference if the node's address
3117 /// can be legally represented as pre-indexed load / store address.
3119 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3121 ISD::MemIndexedMode &AM,
3122 SelectionDAG &DAG) const {
3123 if (Subtarget->isThumb1Only())
3128 bool isSEXTLoad = false;
3129 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3130 Ptr = LD->getBasePtr();
3131 VT = LD->getMemoryVT();
3132 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3133 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3134 Ptr = ST->getBasePtr();
3135 VT = ST->getMemoryVT();
3140 bool isLegal = false;
3141 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3142 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3143 Offset, isInc, DAG);
3145 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3146 Offset, isInc, DAG);
3150 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3154 /// getPostIndexedAddressParts - returns true by value, base pointer and
3155 /// offset pointer and addressing mode by reference if this node can be
3156 /// combined with a load / store to form a post-indexed load / store.
3157 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3160 ISD::MemIndexedMode &AM,
3161 SelectionDAG &DAG) const {
3162 if (Subtarget->isThumb1Only())
3167 bool isSEXTLoad = false;
3168 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3169 VT = LD->getMemoryVT();
3170 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3171 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3172 VT = ST->getMemoryVT();
3177 bool isLegal = false;
3178 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3179 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3182 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3187 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3191 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3195 const SelectionDAG &DAG,
3196 unsigned Depth) const {
3197 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3198 switch (Op.getOpcode()) {
3200 case ARMISD::CMOV: {
3201 // Bits are known zero/one if known on the LHS and RHS.
3202 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3203 if (KnownZero == 0 && KnownOne == 0) return;
3205 APInt KnownZeroRHS, KnownOneRHS;
3206 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3207 KnownZeroRHS, KnownOneRHS, Depth+1);
3208 KnownZero &= KnownZeroRHS;
3209 KnownOne &= KnownOneRHS;
3215 //===----------------------------------------------------------------------===//
3216 // ARM Inline Assembly Support
3217 //===----------------------------------------------------------------------===//
3219 /// getConstraintType - Given a constraint letter, return the type of
3220 /// constraint it is for this target.
3221 ARMTargetLowering::ConstraintType
3222 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3223 if (Constraint.size() == 1) {
3224 switch (Constraint[0]) {
3226 case 'l': return C_RegisterClass;
3227 case 'w': return C_RegisterClass;
3230 return TargetLowering::getConstraintType(Constraint);
3233 std::pair<unsigned, const TargetRegisterClass*>
3234 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3236 if (Constraint.size() == 1) {
3237 // GCC RS6000 Constraint Letters
3238 switch (Constraint[0]) {
3240 if (Subtarget->isThumb1Only())
3241 return std::make_pair(0U, ARM::tGPRRegisterClass);
3243 return std::make_pair(0U, ARM::GPRRegisterClass);
3245 return std::make_pair(0U, ARM::GPRRegisterClass);
3248 return std::make_pair(0U, ARM::SPRRegisterClass);
3250 return std::make_pair(0U, ARM::DPRRegisterClass);
3254 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3257 std::vector<unsigned> ARMTargetLowering::
3258 getRegClassForInlineAsmConstraint(const std::string &Constraint,
3260 if (Constraint.size() != 1)
3261 return std::vector<unsigned>();
3263 switch (Constraint[0]) { // GCC ARM Constraint Letters
3266 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3267 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3270 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3271 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3272 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3273 ARM::R12, ARM::LR, 0);
3276 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3277 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3278 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3279 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3280 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3281 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3282 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3283 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3285 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3286 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3287 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3288 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3292 return std::vector<unsigned>();
3295 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3296 /// vector. If it is invalid, don't add anything to Ops.
3297 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3300 std::vector<SDValue>&Ops,
3301 SelectionDAG &DAG) const {
3302 SDValue Result(0, 0);
3304 switch (Constraint) {
3306 case 'I': case 'J': case 'K': case 'L':
3307 case 'M': case 'N': case 'O':
3308 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3312 int64_t CVal64 = C->getSExtValue();
3313 int CVal = (int) CVal64;
3314 // None of these constraints allow values larger than 32 bits. Check
3315 // that the value fits in an int.
3319 switch (Constraint) {
3321 if (Subtarget->isThumb1Only()) {
3322 // This must be a constant between 0 and 255, for ADD
3324 if (CVal >= 0 && CVal <= 255)
3326 } else if (Subtarget->isThumb2()) {
3327 // A constant that can be used as an immediate value in a
3328 // data-processing instruction.
3329 if (ARM_AM::getT2SOImmVal(CVal) != -1)
3332 // A constant that can be used as an immediate value in a
3333 // data-processing instruction.
3334 if (ARM_AM::getSOImmVal(CVal) != -1)
3340 if (Subtarget->isThumb()) { // FIXME thumb2
3341 // This must be a constant between -255 and -1, for negated ADD
3342 // immediates. This can be used in GCC with an "n" modifier that
3343 // prints the negated value, for use with SUB instructions. It is
3344 // not useful otherwise but is implemented for compatibility.
3345 if (CVal >= -255 && CVal <= -1)
3348 // This must be a constant between -4095 and 4095. It is not clear
3349 // what this constraint is intended for. Implemented for
3350 // compatibility with GCC.
3351 if (CVal >= -4095 && CVal <= 4095)
3357 if (Subtarget->isThumb1Only()) {
3358 // A 32-bit value where only one byte has a nonzero value. Exclude
3359 // zero to match GCC. This constraint is used by GCC internally for
3360 // constants that can be loaded with a move/shift combination.
3361 // It is not useful otherwise but is implemented for compatibility.
3362 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
3364 } else if (Subtarget->isThumb2()) {
3365 // A constant whose bitwise inverse can be used as an immediate
3366 // value in a data-processing instruction. This can be used in GCC
3367 // with a "B" modifier that prints the inverted value, for use with
3368 // BIC and MVN instructions. It is not useful otherwise but is
3369 // implemented for compatibility.
3370 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
3373 // A constant whose bitwise inverse can be used as an immediate
3374 // value in a data-processing instruction. This can be used in GCC
3375 // with a "B" modifier that prints the inverted value, for use with
3376 // BIC and MVN instructions. It is not useful otherwise but is
3377 // implemented for compatibility.
3378 if (ARM_AM::getSOImmVal(~CVal) != -1)
3384 if (Subtarget->isThumb1Only()) {
3385 // This must be a constant between -7 and 7,
3386 // for 3-operand ADD/SUB immediate instructions.
3387 if (CVal >= -7 && CVal < 7)
3389 } else if (Subtarget->isThumb2()) {
3390 // A constant whose negation can be used as an immediate value in a
3391 // data-processing instruction. This can be used in GCC with an "n"
3392 // modifier that prints the negated value, for use with SUB
3393 // instructions. It is not useful otherwise but is implemented for
3395 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
3398 // A constant whose negation can be used as an immediate value in a
3399 // data-processing instruction. This can be used in GCC with an "n"
3400 // modifier that prints the negated value, for use with SUB
3401 // instructions. It is not useful otherwise but is implemented for
3403 if (ARM_AM::getSOImmVal(-CVal) != -1)
3409 if (Subtarget->isThumb()) { // FIXME thumb2
3410 // This must be a multiple of 4 between 0 and 1020, for
3411 // ADD sp + immediate.
3412 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
3415 // A power of two or a constant between 0 and 32. This is used in
3416 // GCC for the shift amount on shifted register operands, but it is
3417 // useful in general for any shift amounts.
3418 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
3424 if (Subtarget->isThumb()) { // FIXME thumb2
3425 // This must be a constant between 0 and 31, for shift amounts.
3426 if (CVal >= 0 && CVal <= 31)
3432 if (Subtarget->isThumb()) { // FIXME thumb2
3433 // This must be a multiple of 4 between -508 and 508, for
3434 // ADD/SUB sp = sp + immediate.
3435 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
3440 Result = DAG.getTargetConstant(CVal, Op.getValueType());
3444 if (Result.getNode()) {
3445 Ops.push_back(Result);
3448 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,