1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
75 // The APCS parameter registers.
76 static const unsigned GPRArgRegs[] = {
77 ARM::R0, ARM::R1, ARM::R2, ARM::R3
80 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
81 EVT PromotedBitwiseVT) {
82 if (VT != PromotedLdStVT) {
83 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
84 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
85 PromotedLdStVT.getSimpleVT());
87 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
88 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
89 PromotedLdStVT.getSimpleVT());
92 EVT ElemTy = VT.getVectorElementType();
93 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
94 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
96 if (ElemTy != MVT::i32) {
97 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
98 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
100 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
104 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
105 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
106 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
107 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
108 if (VT.isInteger()) {
109 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
112 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
113 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
114 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
115 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
116 setTruncStoreAction(VT.getSimpleVT(),
117 (MVT::SimpleValueType)InnerVT, Expand);
119 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
121 // Promote all bit-wise operations.
122 if (VT.isInteger() && VT != PromotedBitwiseVT) {
123 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
124 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
125 PromotedBitwiseVT.getSimpleVT());
126 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
127 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
128 PromotedBitwiseVT.getSimpleVT());
129 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
130 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
131 PromotedBitwiseVT.getSimpleVT());
134 // Neon does not support vector divide/remainder operations.
135 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
136 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
137 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
138 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
139 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
140 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
143 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
144 addRegisterClass(VT, ARM::DPRRegisterClass);
145 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
148 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
149 addRegisterClass(VT, ARM::QPRRegisterClass);
150 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
153 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
154 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
155 return new TargetLoweringObjectFileMachO();
157 return new ARMElfTargetObjectFile();
160 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
161 : TargetLowering(TM, createTLOF(TM)) {
162 Subtarget = &TM.getSubtarget<ARMSubtarget>();
163 RegInfo = TM.getRegisterInfo();
164 Itins = TM.getInstrItineraryData();
166 if (Subtarget->isTargetDarwin()) {
167 // Uses VFP for Thumb libfuncs if available.
168 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
169 // Single-precision floating-point arithmetic.
170 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
171 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
172 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
173 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
175 // Double-precision floating-point arithmetic.
176 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
177 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
178 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
179 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
181 // Single-precision comparisons.
182 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
183 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
184 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
185 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
186 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
187 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
188 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
189 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
191 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
193 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
194 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
195 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
200 // Double-precision comparisons.
201 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
202 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
203 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
204 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
205 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
206 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
207 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
208 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
210 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
219 // Floating-point to integer conversions.
220 // i64 conversions are done via library routines even when generating VFP
221 // instructions, so use the same ones.
222 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
223 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
224 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
225 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
227 // Conversions between floating types.
228 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
229 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
231 // Integer to floating-point conversions.
232 // i64 conversions are done via library routines even when generating VFP
233 // instructions, so use the same ones.
234 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
235 // e.g., __floatunsidf vs. __floatunssidfvfp.
236 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
237 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
238 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
239 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
243 // These libcalls are not available in 32-bit.
244 setLibcallName(RTLIB::SHL_I128, 0);
245 setLibcallName(RTLIB::SRL_I128, 0);
246 setLibcallName(RTLIB::SRA_I128, 0);
248 if (Subtarget->isAAPCS_ABI()) {
249 // Double-precision floating-point arithmetic helper functions
250 // RTABI chapter 4.1.2, Table 2
251 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
252 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
253 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
254 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
255 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
256 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
257 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
258 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
260 // Double-precision floating-point comparison helper functions
261 // RTABI chapter 4.1.2, Table 3
262 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
263 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
264 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
265 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
266 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
267 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
268 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
269 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
270 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
271 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
272 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
273 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
274 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
275 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
276 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
277 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
278 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
279 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
280 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
281 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
282 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
283 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
284 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
285 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
287 // Single-precision floating-point arithmetic helper functions
288 // RTABI chapter 4.1.2, Table 4
289 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
290 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
291 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
292 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
293 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
294 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
295 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
298 // Single-precision floating-point comparison helper functions
299 // RTABI chapter 4.1.2, Table 5
300 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
301 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
302 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
303 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
304 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
305 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
306 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
307 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
308 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
309 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
310 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
311 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
312 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
313 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
314 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
315 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
316 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
317 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
318 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
319 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
320 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
321 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
322 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
323 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
325 // Floating-point to integer conversions.
326 // RTABI chapter 4.1.2, Table 6
327 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
328 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
329 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
330 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
331 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
332 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
333 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
334 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
335 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
339 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
340 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
342 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
344 // Conversions between floating types.
345 // RTABI chapter 4.1.2, Table 7
346 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
347 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
348 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
349 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
351 // Integer to floating-point conversions.
352 // RTABI chapter 4.1.2, Table 8
353 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
354 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
355 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
356 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
357 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
358 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
359 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
360 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
361 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
362 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
363 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
364 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
365 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
366 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
367 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
368 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
370 // Long long helper functions
371 // RTABI chapter 4.2, Table 9
372 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
373 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
374 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
375 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
376 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
377 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
378 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
383 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
385 // Integer division functions
386 // RTABI chapter 4.3.1
387 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
388 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
389 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
390 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
391 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
392 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
393 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
394 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
395 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
396 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
398 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
401 if (HasDivModLibcall) {
402 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
403 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
406 if (Subtarget->isThumb1Only())
407 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
409 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
410 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
411 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
412 if (!Subtarget->isFPOnlySP())
413 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
415 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
418 if (Subtarget->hasNEON()) {
419 addDRTypeForNEON(MVT::v2f32);
420 addDRTypeForNEON(MVT::v8i8);
421 addDRTypeForNEON(MVT::v4i16);
422 addDRTypeForNEON(MVT::v2i32);
423 addDRTypeForNEON(MVT::v1i64);
425 addQRTypeForNEON(MVT::v4f32);
426 addQRTypeForNEON(MVT::v2f64);
427 addQRTypeForNEON(MVT::v16i8);
428 addQRTypeForNEON(MVT::v8i16);
429 addQRTypeForNEON(MVT::v4i32);
430 addQRTypeForNEON(MVT::v2i64);
432 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
433 // neither Neon nor VFP support any arithmetic operations on it.
434 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
435 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
436 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
437 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
438 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
439 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
440 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
441 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
442 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
443 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
444 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
445 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
446 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
447 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
448 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
449 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
450 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
451 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
452 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
453 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
454 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
455 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
456 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
457 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
459 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
461 // Neon does not support some operations on v1i64 and v2i64 types.
462 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
463 // Custom handling for some quad-vector types to detect VMULL.
464 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
465 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
466 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
467 // Custom handling for some vector types to avoid expensive expansions
468 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
469 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
470 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
471 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
472 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
473 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
474 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
475 // a destination type that is wider than the source.
476 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
477 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
479 setTargetDAGCombine(ISD::INTRINSIC_VOID);
480 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
481 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
482 setTargetDAGCombine(ISD::SHL);
483 setTargetDAGCombine(ISD::SRL);
484 setTargetDAGCombine(ISD::SRA);
485 setTargetDAGCombine(ISD::SIGN_EXTEND);
486 setTargetDAGCombine(ISD::ZERO_EXTEND);
487 setTargetDAGCombine(ISD::ANY_EXTEND);
488 setTargetDAGCombine(ISD::SELECT_CC);
489 setTargetDAGCombine(ISD::BUILD_VECTOR);
490 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
491 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
492 setTargetDAGCombine(ISD::STORE);
495 computeRegisterProperties();
497 // ARM does not have f32 extending load.
498 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
500 // ARM does not have i1 sign extending load.
501 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
503 // ARM supports all 4 flavors of integer indexed load / store.
504 if (!Subtarget->isThumb1Only()) {
505 for (unsigned im = (unsigned)ISD::PRE_INC;
506 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
507 setIndexedLoadAction(im, MVT::i1, Legal);
508 setIndexedLoadAction(im, MVT::i8, Legal);
509 setIndexedLoadAction(im, MVT::i16, Legal);
510 setIndexedLoadAction(im, MVT::i32, Legal);
511 setIndexedStoreAction(im, MVT::i1, Legal);
512 setIndexedStoreAction(im, MVT::i8, Legal);
513 setIndexedStoreAction(im, MVT::i16, Legal);
514 setIndexedStoreAction(im, MVT::i32, Legal);
518 // i64 operation support.
519 setOperationAction(ISD::MUL, MVT::i64, Expand);
520 setOperationAction(ISD::MULHU, MVT::i32, Expand);
521 if (Subtarget->isThumb1Only()) {
522 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
523 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
525 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops())
526 setOperationAction(ISD::MULHS, MVT::i32, Expand);
528 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
529 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
530 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
531 setOperationAction(ISD::SRL, MVT::i64, Custom);
532 setOperationAction(ISD::SRA, MVT::i64, Custom);
534 // ARM does not have ROTL.
535 setOperationAction(ISD::ROTL, MVT::i32, Expand);
536 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
537 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
538 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
539 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
541 // Only ARMv6 has BSWAP.
542 if (!Subtarget->hasV6Ops())
543 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
545 // These are expanded into libcalls.
546 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
547 // v7M has a hardware divider
548 setOperationAction(ISD::SDIV, MVT::i32, Expand);
549 setOperationAction(ISD::UDIV, MVT::i32, Expand);
551 setOperationAction(ISD::SREM, MVT::i32, Expand);
552 setOperationAction(ISD::UREM, MVT::i32, Expand);
553 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
554 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
556 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
557 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
558 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
559 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
560 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
562 setOperationAction(ISD::TRAP, MVT::Other, Legal);
564 // Use the default implementation.
565 setOperationAction(ISD::VASTART, MVT::Other, Custom);
566 setOperationAction(ISD::VAARG, MVT::Other, Expand);
567 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
568 setOperationAction(ISD::VAEND, MVT::Other, Expand);
569 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
570 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
571 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
572 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
573 setExceptionPointerRegister(ARM::R0);
574 setExceptionSelectorRegister(ARM::R1);
576 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
577 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
578 // the default expansion.
579 if (Subtarget->hasDataBarrier() ||
580 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
581 // membarrier needs custom lowering; the rest are legal and handled
583 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
585 // Set them all for expansion, which will force libcalls.
586 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
587 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
588 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
589 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
590 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
591 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
592 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
593 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
600 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
601 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
602 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
603 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
604 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
605 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
606 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
607 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
608 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
609 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
610 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
611 // Since the libcalls include locking, fold in the fences
612 setShouldFoldAtomicFences(true);
614 // 64-bit versions are always libcalls (for now)
615 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
616 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
617 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
618 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
619 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
620 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
621 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
624 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
626 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
627 if (!Subtarget->hasV6Ops()) {
628 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
629 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
631 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
633 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
634 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
635 // iff target supports vfp2.
636 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
637 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
640 // We want to custom lower some of our intrinsics.
641 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
642 if (Subtarget->isTargetDarwin()) {
643 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
644 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
645 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
648 setOperationAction(ISD::SETCC, MVT::i32, Expand);
649 setOperationAction(ISD::SETCC, MVT::f32, Expand);
650 setOperationAction(ISD::SETCC, MVT::f64, Expand);
651 setOperationAction(ISD::SELECT, MVT::i32, Custom);
652 setOperationAction(ISD::SELECT, MVT::f32, Custom);
653 setOperationAction(ISD::SELECT, MVT::f64, Custom);
654 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
655 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
656 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
658 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
659 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
660 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
661 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
662 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
664 // We don't support sin/cos/fmod/copysign/pow
665 setOperationAction(ISD::FSIN, MVT::f64, Expand);
666 setOperationAction(ISD::FSIN, MVT::f32, Expand);
667 setOperationAction(ISD::FCOS, MVT::f32, Expand);
668 setOperationAction(ISD::FCOS, MVT::f64, Expand);
669 setOperationAction(ISD::FREM, MVT::f64, Expand);
670 setOperationAction(ISD::FREM, MVT::f32, Expand);
671 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
672 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
673 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
675 setOperationAction(ISD::FPOW, MVT::f64, Expand);
676 setOperationAction(ISD::FPOW, MVT::f32, Expand);
678 // Various VFP goodness
679 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
680 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
681 if (Subtarget->hasVFP2()) {
682 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
683 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
684 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
685 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
687 // Special handling for half-precision FP.
688 if (!Subtarget->hasFP16()) {
689 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
690 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
694 // We have target-specific dag combine patterns for the following nodes:
695 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
696 setTargetDAGCombine(ISD::ADD);
697 setTargetDAGCombine(ISD::SUB);
698 setTargetDAGCombine(ISD::MUL);
700 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
701 setTargetDAGCombine(ISD::OR);
702 if (Subtarget->hasNEON())
703 setTargetDAGCombine(ISD::AND);
705 setStackPointerRegisterToSaveRestore(ARM::SP);
707 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
708 setSchedulingPreference(Sched::RegPressure);
710 setSchedulingPreference(Sched::Hybrid);
712 //// temporary - rewrite interface to use type
713 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
715 // On ARM arguments smaller than 4 bytes are extended, so all arguments
716 // are at least 4 bytes aligned.
717 setMinStackArgumentAlignment(4);
719 benefitFromCodePlacementOpt = true;
722 // FIXME: It might make sense to define the representative register class as the
723 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
724 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
725 // SPR's representative would be DPR_VFP2. This should work well if register
726 // pressure tracking were modified such that a register use would increment the
727 // pressure of the register class's representative and all of it's super
728 // classes' representatives transitively. We have not implemented this because
729 // of the difficulty prior to coalescing of modeling operand register classes
730 // due to the common occurrence of cross class copies and subregister insertions
732 std::pair<const TargetRegisterClass*, uint8_t>
733 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
734 const TargetRegisterClass *RRC = 0;
736 switch (VT.getSimpleVT().SimpleTy) {
738 return TargetLowering::findRepresentativeClass(VT);
739 // Use DPR as representative register class for all floating point
740 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
741 // the cost is 1 for both f32 and f64.
742 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
743 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
744 RRC = ARM::DPRRegisterClass;
745 // When NEON is used for SP, only half of the register file is available
746 // because operations that define both SP and DP results will be constrained
747 // to the VFP2 class (D0-D15). We currently model this constraint prior to
748 // coalescing by double-counting the SP regs. See the FIXME above.
749 if (Subtarget->useNEONForSinglePrecisionFP())
752 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
753 case MVT::v4f32: case MVT::v2f64:
754 RRC = ARM::DPRRegisterClass;
758 RRC = ARM::DPRRegisterClass;
762 RRC = ARM::DPRRegisterClass;
766 return std::make_pair(RRC, Cost);
769 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
772 case ARMISD::Wrapper: return "ARMISD::Wrapper";
773 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
774 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
775 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
776 case ARMISD::CALL: return "ARMISD::CALL";
777 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
778 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
779 case ARMISD::tCALL: return "ARMISD::tCALL";
780 case ARMISD::BRCOND: return "ARMISD::BRCOND";
781 case ARMISD::BR_JT: return "ARMISD::BR_JT";
782 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
783 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
784 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
785 case ARMISD::CMP: return "ARMISD::CMP";
786 case ARMISD::CMPZ: return "ARMISD::CMPZ";
787 case ARMISD::CMPFP: return "ARMISD::CMPFP";
788 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
789 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
790 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
791 case ARMISD::CMOV: return "ARMISD::CMOV";
793 case ARMISD::RBIT: return "ARMISD::RBIT";
795 case ARMISD::FTOSI: return "ARMISD::FTOSI";
796 case ARMISD::FTOUI: return "ARMISD::FTOUI";
797 case ARMISD::SITOF: return "ARMISD::SITOF";
798 case ARMISD::UITOF: return "ARMISD::UITOF";
800 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
801 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
802 case ARMISD::RRX: return "ARMISD::RRX";
804 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
805 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
807 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
808 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
809 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
811 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
813 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
815 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
817 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
818 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
820 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
822 case ARMISD::VCEQ: return "ARMISD::VCEQ";
823 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
824 case ARMISD::VCGE: return "ARMISD::VCGE";
825 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
826 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
827 case ARMISD::VCGEU: return "ARMISD::VCGEU";
828 case ARMISD::VCGT: return "ARMISD::VCGT";
829 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
830 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
831 case ARMISD::VCGTU: return "ARMISD::VCGTU";
832 case ARMISD::VTST: return "ARMISD::VTST";
834 case ARMISD::VSHL: return "ARMISD::VSHL";
835 case ARMISD::VSHRs: return "ARMISD::VSHRs";
836 case ARMISD::VSHRu: return "ARMISD::VSHRu";
837 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
838 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
839 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
840 case ARMISD::VSHRN: return "ARMISD::VSHRN";
841 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
842 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
843 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
844 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
845 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
846 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
847 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
848 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
849 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
850 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
851 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
852 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
853 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
854 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
855 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
856 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
857 case ARMISD::VDUP: return "ARMISD::VDUP";
858 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
859 case ARMISD::VEXT: return "ARMISD::VEXT";
860 case ARMISD::VREV64: return "ARMISD::VREV64";
861 case ARMISD::VREV32: return "ARMISD::VREV32";
862 case ARMISD::VREV16: return "ARMISD::VREV16";
863 case ARMISD::VZIP: return "ARMISD::VZIP";
864 case ARMISD::VUZP: return "ARMISD::VUZP";
865 case ARMISD::VTRN: return "ARMISD::VTRN";
866 case ARMISD::VTBL1: return "ARMISD::VTBL1";
867 case ARMISD::VTBL2: return "ARMISD::VTBL2";
868 case ARMISD::VMULLs: return "ARMISD::VMULLs";
869 case ARMISD::VMULLu: return "ARMISD::VMULLu";
870 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
871 case ARMISD::FMAX: return "ARMISD::FMAX";
872 case ARMISD::FMIN: return "ARMISD::FMIN";
873 case ARMISD::BFI: return "ARMISD::BFI";
874 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
875 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
876 case ARMISD::VBSL: return "ARMISD::VBSL";
877 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
878 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
879 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
880 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
881 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
882 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
883 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
884 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
885 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
886 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
887 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
888 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
889 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
890 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
891 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
892 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
893 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
894 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
895 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
896 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
900 /// getRegClassFor - Return the register class that should be used for the
901 /// specified value type.
902 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
903 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
904 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
905 // load / store 4 to 8 consecutive D registers.
906 if (Subtarget->hasNEON()) {
907 if (VT == MVT::v4i64)
908 return ARM::QQPRRegisterClass;
909 else if (VT == MVT::v8i64)
910 return ARM::QQQQPRRegisterClass;
912 return TargetLowering::getRegClassFor(VT);
915 // Create a fast isel object.
917 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
918 return ARM::createFastISel(funcInfo);
921 /// getFunctionAlignment - Return the Log2 alignment of this function.
922 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
923 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
926 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
927 /// be used for loads / stores from the global.
928 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
929 return (Subtarget->isThumb1Only() ? 127 : 4095);
932 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
933 unsigned NumVals = N->getNumValues();
935 return Sched::RegPressure;
937 for (unsigned i = 0; i != NumVals; ++i) {
938 EVT VT = N->getValueType(i);
939 if (VT == MVT::Glue || VT == MVT::Other)
941 if (VT.isFloatingPoint() || VT.isVector())
942 return Sched::Latency;
945 if (!N->isMachineOpcode())
946 return Sched::RegPressure;
948 // Load are scheduled for latency even if there instruction itinerary
950 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
951 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
953 if (TID.getNumDefs() == 0)
954 return Sched::RegPressure;
955 if (!Itins->isEmpty() &&
956 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
957 return Sched::Latency;
959 return Sched::RegPressure;
962 //===----------------------------------------------------------------------===//
964 //===----------------------------------------------------------------------===//
966 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
967 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
969 default: llvm_unreachable("Unknown condition code!");
970 case ISD::SETNE: return ARMCC::NE;
971 case ISD::SETEQ: return ARMCC::EQ;
972 case ISD::SETGT: return ARMCC::GT;
973 case ISD::SETGE: return ARMCC::GE;
974 case ISD::SETLT: return ARMCC::LT;
975 case ISD::SETLE: return ARMCC::LE;
976 case ISD::SETUGT: return ARMCC::HI;
977 case ISD::SETUGE: return ARMCC::HS;
978 case ISD::SETULT: return ARMCC::LO;
979 case ISD::SETULE: return ARMCC::LS;
983 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
984 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
985 ARMCC::CondCodes &CondCode2) {
986 CondCode2 = ARMCC::AL;
988 default: llvm_unreachable("Unknown FP condition!");
990 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
992 case ISD::SETOGT: CondCode = ARMCC::GT; break;
994 case ISD::SETOGE: CondCode = ARMCC::GE; break;
995 case ISD::SETOLT: CondCode = ARMCC::MI; break;
996 case ISD::SETOLE: CondCode = ARMCC::LS; break;
997 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
998 case ISD::SETO: CondCode = ARMCC::VC; break;
999 case ISD::SETUO: CondCode = ARMCC::VS; break;
1000 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1001 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1002 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1004 case ISD::SETULT: CondCode = ARMCC::LT; break;
1006 case ISD::SETULE: CondCode = ARMCC::LE; break;
1008 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1012 //===----------------------------------------------------------------------===//
1013 // Calling Convention Implementation
1014 //===----------------------------------------------------------------------===//
1016 #include "ARMGenCallingConv.inc"
1018 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1019 /// given CallingConvention value.
1020 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1022 bool isVarArg) const {
1025 llvm_unreachable("Unsupported calling convention");
1026 case CallingConv::Fast:
1027 if (Subtarget->hasVFP2() && !isVarArg) {
1028 if (!Subtarget->isAAPCS_ABI())
1029 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1030 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1031 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1034 case CallingConv::C: {
1035 // Use target triple & subtarget features to do actual dispatch.
1036 if (!Subtarget->isAAPCS_ABI())
1037 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1038 else if (Subtarget->hasVFP2() &&
1039 FloatABIType == FloatABI::Hard && !isVarArg)
1040 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1041 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1043 case CallingConv::ARM_AAPCS_VFP:
1044 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1045 case CallingConv::ARM_AAPCS:
1046 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1047 case CallingConv::ARM_APCS:
1048 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1052 /// LowerCallResult - Lower the result values of a call into the
1053 /// appropriate copies out of appropriate physical registers.
1055 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1056 CallingConv::ID CallConv, bool isVarArg,
1057 const SmallVectorImpl<ISD::InputArg> &Ins,
1058 DebugLoc dl, SelectionDAG &DAG,
1059 SmallVectorImpl<SDValue> &InVals) const {
1061 // Assign locations to each value returned by this call.
1062 SmallVector<CCValAssign, 16> RVLocs;
1063 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1064 RVLocs, *DAG.getContext());
1065 CCInfo.AnalyzeCallResult(Ins,
1066 CCAssignFnForNode(CallConv, /* Return*/ true,
1069 // Copy all of the result registers out of their specified physreg.
1070 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1071 CCValAssign VA = RVLocs[i];
1074 if (VA.needsCustom()) {
1075 // Handle f64 or half of a v2f64.
1076 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1078 Chain = Lo.getValue(1);
1079 InFlag = Lo.getValue(2);
1080 VA = RVLocs[++i]; // skip ahead to next loc
1081 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1083 Chain = Hi.getValue(1);
1084 InFlag = Hi.getValue(2);
1085 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1087 if (VA.getLocVT() == MVT::v2f64) {
1088 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1089 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1090 DAG.getConstant(0, MVT::i32));
1092 VA = RVLocs[++i]; // skip ahead to next loc
1093 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1094 Chain = Lo.getValue(1);
1095 InFlag = Lo.getValue(2);
1096 VA = RVLocs[++i]; // skip ahead to next loc
1097 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1098 Chain = Hi.getValue(1);
1099 InFlag = Hi.getValue(2);
1100 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1101 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1102 DAG.getConstant(1, MVT::i32));
1105 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1107 Chain = Val.getValue(1);
1108 InFlag = Val.getValue(2);
1111 switch (VA.getLocInfo()) {
1112 default: llvm_unreachable("Unknown loc info!");
1113 case CCValAssign::Full: break;
1114 case CCValAssign::BCvt:
1115 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1119 InVals.push_back(Val);
1125 /// LowerMemOpCallTo - Store the argument to the stack.
1127 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1128 SDValue StackPtr, SDValue Arg,
1129 DebugLoc dl, SelectionDAG &DAG,
1130 const CCValAssign &VA,
1131 ISD::ArgFlagsTy Flags) const {
1132 unsigned LocMemOffset = VA.getLocMemOffset();
1133 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1134 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1135 return DAG.getStore(Chain, dl, Arg, PtrOff,
1136 MachinePointerInfo::getStack(LocMemOffset),
1140 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1141 SDValue Chain, SDValue &Arg,
1142 RegsToPassVector &RegsToPass,
1143 CCValAssign &VA, CCValAssign &NextVA,
1145 SmallVector<SDValue, 8> &MemOpChains,
1146 ISD::ArgFlagsTy Flags) const {
1148 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1149 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1150 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1152 if (NextVA.isRegLoc())
1153 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1155 assert(NextVA.isMemLoc());
1156 if (StackPtr.getNode() == 0)
1157 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1159 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1165 /// LowerCall - Lowering a call into a callseq_start <-
1166 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1169 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1170 CallingConv::ID CallConv, bool isVarArg,
1172 const SmallVectorImpl<ISD::OutputArg> &Outs,
1173 const SmallVectorImpl<SDValue> &OutVals,
1174 const SmallVectorImpl<ISD::InputArg> &Ins,
1175 DebugLoc dl, SelectionDAG &DAG,
1176 SmallVectorImpl<SDValue> &InVals) const {
1177 MachineFunction &MF = DAG.getMachineFunction();
1178 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1179 bool IsSibCall = false;
1180 // Temporarily disable tail calls so things don't break.
1181 if (!EnableARMTailCalls)
1184 // Check if it's really possible to do a tail call.
1185 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1186 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1187 Outs, OutVals, Ins, DAG);
1188 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1189 // detected sibcalls.
1196 // Analyze operands of the call, assigning locations to each operand.
1197 SmallVector<CCValAssign, 16> ArgLocs;
1198 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1200 CCInfo.setCallOrPrologue(Call);
1201 CCInfo.AnalyzeCallOperands(Outs,
1202 CCAssignFnForNode(CallConv, /* Return*/ false,
1205 // Get a count of how many bytes are to be pushed on the stack.
1206 unsigned NumBytes = CCInfo.getNextStackOffset();
1208 // For tail calls, memory operands are available in our caller's stack.
1212 // Adjust the stack pointer for the new arguments...
1213 // These operations are automatically eliminated by the prolog/epilog pass
1215 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1217 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1219 RegsToPassVector RegsToPass;
1220 SmallVector<SDValue, 8> MemOpChains;
1222 // Walk the register/memloc assignments, inserting copies/loads. In the case
1223 // of tail call optimization, arguments are handled later.
1224 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1226 ++i, ++realArgIdx) {
1227 CCValAssign &VA = ArgLocs[i];
1228 SDValue Arg = OutVals[realArgIdx];
1229 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1230 bool isByVal = Flags.isByVal();
1232 // Promote the value if needed.
1233 switch (VA.getLocInfo()) {
1234 default: llvm_unreachable("Unknown loc info!");
1235 case CCValAssign::Full: break;
1236 case CCValAssign::SExt:
1237 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1239 case CCValAssign::ZExt:
1240 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1242 case CCValAssign::AExt:
1243 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1245 case CCValAssign::BCvt:
1246 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1250 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1251 if (VA.needsCustom()) {
1252 if (VA.getLocVT() == MVT::v2f64) {
1253 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1254 DAG.getConstant(0, MVT::i32));
1255 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1256 DAG.getConstant(1, MVT::i32));
1258 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1259 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1261 VA = ArgLocs[++i]; // skip ahead to next loc
1262 if (VA.isRegLoc()) {
1263 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1264 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1266 assert(VA.isMemLoc());
1268 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1269 dl, DAG, VA, Flags));
1272 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1273 StackPtr, MemOpChains, Flags);
1275 } else if (VA.isRegLoc()) {
1276 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1277 } else if (isByVal) {
1278 assert(VA.isMemLoc());
1279 unsigned offset = 0;
1281 // True if this byval aggregate will be split between registers
1283 if (CCInfo.isFirstByValRegValid()) {
1284 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1286 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1287 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1288 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1289 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1290 MachinePointerInfo(),
1292 MemOpChains.push_back(Load.getValue(1));
1293 RegsToPass.push_back(std::make_pair(j, Load));
1295 offset = ARM::R4 - CCInfo.getFirstByValReg();
1296 CCInfo.clearFirstByValReg();
1299 unsigned LocMemOffset = VA.getLocMemOffset();
1300 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1301 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1303 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1304 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1305 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1307 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
1308 Flags.getByValAlign(),
1309 /*isVolatile=*/false,
1310 /*AlwaysInline=*/false,
1311 MachinePointerInfo(0),
1312 MachinePointerInfo(0)));
1314 } else if (!IsSibCall) {
1315 assert(VA.isMemLoc());
1317 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1318 dl, DAG, VA, Flags));
1322 if (!MemOpChains.empty())
1323 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1324 &MemOpChains[0], MemOpChains.size());
1326 // Build a sequence of copy-to-reg nodes chained together with token chain
1327 // and flag operands which copy the outgoing args into the appropriate regs.
1329 // Tail call byval lowering might overwrite argument registers so in case of
1330 // tail call optimization the copies to registers are lowered later.
1332 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1333 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1334 RegsToPass[i].second, InFlag);
1335 InFlag = Chain.getValue(1);
1338 // For tail calls lower the arguments to the 'real' stack slot.
1340 // Force all the incoming stack arguments to be loaded from the stack
1341 // before any new outgoing arguments are stored to the stack, because the
1342 // outgoing stack slots may alias the incoming argument stack slots, and
1343 // the alias isn't otherwise explicit. This is slightly more conservative
1344 // than necessary, because it means that each store effectively depends
1345 // on every argument instead of just those arguments it would clobber.
1347 // Do not flag preceding copytoreg stuff together with the following stuff.
1349 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1350 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1351 RegsToPass[i].second, InFlag);
1352 InFlag = Chain.getValue(1);
1357 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1358 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1359 // node so that legalize doesn't hack it.
1360 bool isDirect = false;
1361 bool isARMFunc = false;
1362 bool isLocalARMFunc = false;
1363 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1365 if (EnableARMLongCalls) {
1366 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1367 && "long-calls with non-static relocation model!");
1368 // Handle a global address or an external symbol. If it's not one of
1369 // those, the target's already in a register, so we don't need to do
1371 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1372 const GlobalValue *GV = G->getGlobal();
1373 // Create a constant pool entry for the callee address
1374 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1375 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1378 // Get the address of the callee into a register
1379 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1380 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1381 Callee = DAG.getLoad(getPointerTy(), dl,
1382 DAG.getEntryNode(), CPAddr,
1383 MachinePointerInfo::getConstantPool(),
1385 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1386 const char *Sym = S->getSymbol();
1388 // Create a constant pool entry for the callee address
1389 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1390 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1391 Sym, ARMPCLabelIndex, 0);
1392 // Get the address of the callee into a register
1393 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1394 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1395 Callee = DAG.getLoad(getPointerTy(), dl,
1396 DAG.getEntryNode(), CPAddr,
1397 MachinePointerInfo::getConstantPool(),
1400 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1401 const GlobalValue *GV = G->getGlobal();
1403 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1404 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1405 getTargetMachine().getRelocationModel() != Reloc::Static;
1406 isARMFunc = !Subtarget->isThumb() || isStub;
1407 // ARM call to a local ARM function is predicable.
1408 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1409 // tBX takes a register source operand.
1410 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1411 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1412 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1415 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1416 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1417 Callee = DAG.getLoad(getPointerTy(), dl,
1418 DAG.getEntryNode(), CPAddr,
1419 MachinePointerInfo::getConstantPool(),
1421 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1422 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1423 getPointerTy(), Callee, PICLabel);
1425 // On ELF targets for PIC code, direct calls should go through the PLT
1426 unsigned OpFlags = 0;
1427 if (Subtarget->isTargetELF() &&
1428 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1429 OpFlags = ARMII::MO_PLT;
1430 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1432 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1434 bool isStub = Subtarget->isTargetDarwin() &&
1435 getTargetMachine().getRelocationModel() != Reloc::Static;
1436 isARMFunc = !Subtarget->isThumb() || isStub;
1437 // tBX takes a register source operand.
1438 const char *Sym = S->getSymbol();
1439 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1440 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1441 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1442 Sym, ARMPCLabelIndex, 4);
1443 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1444 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1445 Callee = DAG.getLoad(getPointerTy(), dl,
1446 DAG.getEntryNode(), CPAddr,
1447 MachinePointerInfo::getConstantPool(),
1449 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1450 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1451 getPointerTy(), Callee, PICLabel);
1453 unsigned OpFlags = 0;
1454 // On ELF targets for PIC code, direct calls should go through the PLT
1455 if (Subtarget->isTargetELF() &&
1456 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1457 OpFlags = ARMII::MO_PLT;
1458 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1462 // FIXME: handle tail calls differently.
1464 if (Subtarget->isThumb()) {
1465 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1466 CallOpc = ARMISD::CALL_NOLINK;
1468 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1470 CallOpc = (isDirect || Subtarget->hasV5TOps())
1471 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1472 : ARMISD::CALL_NOLINK;
1475 std::vector<SDValue> Ops;
1476 Ops.push_back(Chain);
1477 Ops.push_back(Callee);
1479 // Add argument registers to the end of the list so that they are known live
1481 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1482 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1483 RegsToPass[i].second.getValueType()));
1485 if (InFlag.getNode())
1486 Ops.push_back(InFlag);
1488 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1490 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1492 // Returns a chain and a flag for retval copy to use.
1493 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1494 InFlag = Chain.getValue(1);
1496 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1497 DAG.getIntPtrConstant(0, true), InFlag);
1499 InFlag = Chain.getValue(1);
1501 // Handle result values, copying them out of physregs into vregs that we
1503 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1507 /// HandleByVal - Every parameter *after* a byval parameter is passed
1508 /// on the stack. Remember the next parameter register to allocate,
1509 /// and then confiscate the rest of the parameter registers to insure
1512 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1513 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1514 assert((State->getCallOrPrologue() == Prologue ||
1515 State->getCallOrPrologue() == Call) &&
1516 "unhandled ParmContext");
1517 if ((!State->isFirstByValRegValid()) &&
1518 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1519 State->setFirstByValReg(reg);
1520 // At a call site, a byval parameter that is split between
1521 // registers and memory needs its size truncated here. In a
1522 // function prologue, such byval parameters are reassembled in
1523 // memory, and are not truncated.
1524 if (State->getCallOrPrologue() == Call) {
1525 unsigned excess = 4 * (ARM::R4 - reg);
1526 assert(size >= excess && "expected larger existing stack allocation");
1530 // Confiscate any remaining parameter registers to preclude their
1531 // assignment to subsequent parameters.
1532 while (State->AllocateReg(GPRArgRegs, 4))
1536 /// MatchingStackOffset - Return true if the given stack call argument is
1537 /// already available in the same position (relatively) of the caller's
1538 /// incoming argument stack.
1540 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1541 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1542 const ARMInstrInfo *TII) {
1543 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1545 if (Arg.getOpcode() == ISD::CopyFromReg) {
1546 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1547 if (!TargetRegisterInfo::isVirtualRegister(VR))
1549 MachineInstr *Def = MRI->getVRegDef(VR);
1552 if (!Flags.isByVal()) {
1553 if (!TII->isLoadFromStackSlot(Def, FI))
1558 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1559 if (Flags.isByVal())
1560 // ByVal argument is passed in as a pointer but it's now being
1561 // dereferenced. e.g.
1562 // define @foo(%struct.X* %A) {
1563 // tail call @bar(%struct.X* byval %A)
1566 SDValue Ptr = Ld->getBasePtr();
1567 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1570 FI = FINode->getIndex();
1574 assert(FI != INT_MAX);
1575 if (!MFI->isFixedObjectIndex(FI))
1577 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1580 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1581 /// for tail call optimization. Targets which want to do tail call
1582 /// optimization should implement this function.
1584 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1585 CallingConv::ID CalleeCC,
1587 bool isCalleeStructRet,
1588 bool isCallerStructRet,
1589 const SmallVectorImpl<ISD::OutputArg> &Outs,
1590 const SmallVectorImpl<SDValue> &OutVals,
1591 const SmallVectorImpl<ISD::InputArg> &Ins,
1592 SelectionDAG& DAG) const {
1593 const Function *CallerF = DAG.getMachineFunction().getFunction();
1594 CallingConv::ID CallerCC = CallerF->getCallingConv();
1595 bool CCMatch = CallerCC == CalleeCC;
1597 // Look for obvious safe cases to perform tail call optimization that do not
1598 // require ABI changes. This is what gcc calls sibcall.
1600 // Do not sibcall optimize vararg calls unless the call site is not passing
1602 if (isVarArg && !Outs.empty())
1605 // Also avoid sibcall optimization if either caller or callee uses struct
1606 // return semantics.
1607 if (isCalleeStructRet || isCallerStructRet)
1610 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1611 // emitEpilogue is not ready for them.
1612 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1613 // LR. This means if we need to reload LR, it takes an extra instructions,
1614 // which outweighs the value of the tail call; but here we don't know yet
1615 // whether LR is going to be used. Probably the right approach is to
1616 // generate the tail call here and turn it back into CALL/RET in
1617 // emitEpilogue if LR is used.
1619 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1620 // but we need to make sure there are enough registers; the only valid
1621 // registers are the 4 used for parameters. We don't currently do this
1623 if (Subtarget->isThumb1Only())
1626 // If the calling conventions do not match, then we'd better make sure the
1627 // results are returned in the same way as what the caller expects.
1629 SmallVector<CCValAssign, 16> RVLocs1;
1630 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1631 RVLocs1, *DAG.getContext());
1632 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1634 SmallVector<CCValAssign, 16> RVLocs2;
1635 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1636 RVLocs2, *DAG.getContext());
1637 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1639 if (RVLocs1.size() != RVLocs2.size())
1641 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1642 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1644 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1646 if (RVLocs1[i].isRegLoc()) {
1647 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1650 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1656 // If the callee takes no arguments then go on to check the results of the
1658 if (!Outs.empty()) {
1659 // Check if stack adjustment is needed. For now, do not do this if any
1660 // argument is passed on the stack.
1661 SmallVector<CCValAssign, 16> ArgLocs;
1662 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1663 ArgLocs, *DAG.getContext());
1664 CCInfo.AnalyzeCallOperands(Outs,
1665 CCAssignFnForNode(CalleeCC, false, isVarArg));
1666 if (CCInfo.getNextStackOffset()) {
1667 MachineFunction &MF = DAG.getMachineFunction();
1669 // Check if the arguments are already laid out in the right way as
1670 // the caller's fixed stack objects.
1671 MachineFrameInfo *MFI = MF.getFrameInfo();
1672 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1673 const ARMInstrInfo *TII =
1674 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1675 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1677 ++i, ++realArgIdx) {
1678 CCValAssign &VA = ArgLocs[i];
1679 EVT RegVT = VA.getLocVT();
1680 SDValue Arg = OutVals[realArgIdx];
1681 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1682 if (VA.getLocInfo() == CCValAssign::Indirect)
1684 if (VA.needsCustom()) {
1685 // f64 and vector types are split into multiple registers or
1686 // register/stack-slot combinations. The types will not match
1687 // the registers; give up on memory f64 refs until we figure
1688 // out what to do about this.
1691 if (!ArgLocs[++i].isRegLoc())
1693 if (RegVT == MVT::v2f64) {
1694 if (!ArgLocs[++i].isRegLoc())
1696 if (!ArgLocs[++i].isRegLoc())
1699 } else if (!VA.isRegLoc()) {
1700 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1712 ARMTargetLowering::LowerReturn(SDValue Chain,
1713 CallingConv::ID CallConv, bool isVarArg,
1714 const SmallVectorImpl<ISD::OutputArg> &Outs,
1715 const SmallVectorImpl<SDValue> &OutVals,
1716 DebugLoc dl, SelectionDAG &DAG) const {
1718 // CCValAssign - represent the assignment of the return value to a location.
1719 SmallVector<CCValAssign, 16> RVLocs;
1721 // CCState - Info about the registers and stack slots.
1722 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1725 // Analyze outgoing return values.
1726 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1729 // If this is the first return lowered for this function, add
1730 // the regs to the liveout set for the function.
1731 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1732 for (unsigned i = 0; i != RVLocs.size(); ++i)
1733 if (RVLocs[i].isRegLoc())
1734 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1739 // Copy the result values into the output registers.
1740 for (unsigned i = 0, realRVLocIdx = 0;
1742 ++i, ++realRVLocIdx) {
1743 CCValAssign &VA = RVLocs[i];
1744 assert(VA.isRegLoc() && "Can only return in registers!");
1746 SDValue Arg = OutVals[realRVLocIdx];
1748 switch (VA.getLocInfo()) {
1749 default: llvm_unreachable("Unknown loc info!");
1750 case CCValAssign::Full: break;
1751 case CCValAssign::BCvt:
1752 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1756 if (VA.needsCustom()) {
1757 if (VA.getLocVT() == MVT::v2f64) {
1758 // Extract the first half and return it in two registers.
1759 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1760 DAG.getConstant(0, MVT::i32));
1761 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1762 DAG.getVTList(MVT::i32, MVT::i32), Half);
1764 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1765 Flag = Chain.getValue(1);
1766 VA = RVLocs[++i]; // skip ahead to next loc
1767 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1768 HalfGPRs.getValue(1), Flag);
1769 Flag = Chain.getValue(1);
1770 VA = RVLocs[++i]; // skip ahead to next loc
1772 // Extract the 2nd half and fall through to handle it as an f64 value.
1773 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1774 DAG.getConstant(1, MVT::i32));
1776 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1778 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1779 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1780 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1781 Flag = Chain.getValue(1);
1782 VA = RVLocs[++i]; // skip ahead to next loc
1783 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1786 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1788 // Guarantee that all emitted copies are
1789 // stuck together, avoiding something bad.
1790 Flag = Chain.getValue(1);
1795 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1797 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1802 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1803 if (N->getNumValues() != 1)
1805 if (!N->hasNUsesOfValue(1, 0))
1808 unsigned NumCopies = 0;
1810 SDNode *Use = *N->use_begin();
1811 if (Use->getOpcode() == ISD::CopyToReg) {
1812 Copies[NumCopies++] = Use;
1813 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1814 // f64 returned in a pair of GPRs.
1815 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1817 if (UI->getOpcode() != ISD::CopyToReg)
1819 Copies[UI.getUse().getResNo()] = *UI;
1822 } else if (Use->getOpcode() == ISD::BITCAST) {
1823 // f32 returned in a single GPR.
1824 if (!Use->hasNUsesOfValue(1, 0))
1826 Use = *Use->use_begin();
1827 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1829 Copies[NumCopies++] = Use;
1834 if (NumCopies != 1 && NumCopies != 2)
1837 bool HasRet = false;
1838 for (unsigned i = 0; i < NumCopies; ++i) {
1839 SDNode *Copy = Copies[i];
1840 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1842 if (UI->getOpcode() == ISD::CopyToReg) {
1844 if (Use == Copies[0] || Use == Copies[1])
1848 if (UI->getOpcode() != ARMISD::RET_FLAG)
1857 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1858 if (!EnableARMTailCalls)
1861 if (!CI->isTailCall())
1864 return !Subtarget->isThumb1Only();
1867 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1868 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1869 // one of the above mentioned nodes. It has to be wrapped because otherwise
1870 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1871 // be used to form addressing mode. These wrapped nodes will be selected
1873 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1874 EVT PtrVT = Op.getValueType();
1875 // FIXME there is no actual debug info here
1876 DebugLoc dl = Op.getDebugLoc();
1877 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1879 if (CP->isMachineConstantPoolEntry())
1880 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1881 CP->getAlignment());
1883 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1884 CP->getAlignment());
1885 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1888 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1889 return MachineJumpTableInfo::EK_Inline;
1892 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1893 SelectionDAG &DAG) const {
1894 MachineFunction &MF = DAG.getMachineFunction();
1895 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1896 unsigned ARMPCLabelIndex = 0;
1897 DebugLoc DL = Op.getDebugLoc();
1898 EVT PtrVT = getPointerTy();
1899 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1900 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1902 if (RelocM == Reloc::Static) {
1903 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1905 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1906 ARMPCLabelIndex = AFI->createPICLabelUId();
1907 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1908 ARMCP::CPBlockAddress,
1910 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1912 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1913 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1914 MachinePointerInfo::getConstantPool(),
1916 if (RelocM == Reloc::Static)
1918 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1919 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1922 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1924 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1925 SelectionDAG &DAG) const {
1926 DebugLoc dl = GA->getDebugLoc();
1927 EVT PtrVT = getPointerTy();
1928 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1929 MachineFunction &MF = DAG.getMachineFunction();
1930 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1931 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1932 ARMConstantPoolValue *CPV =
1933 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1934 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1935 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1936 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1937 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1938 MachinePointerInfo::getConstantPool(),
1940 SDValue Chain = Argument.getValue(1);
1942 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1943 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1945 // call __tls_get_addr.
1948 Entry.Node = Argument;
1949 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1950 Args.push_back(Entry);
1951 // FIXME: is there useful debug info available here?
1952 std::pair<SDValue, SDValue> CallResult =
1953 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1954 false, false, false, false,
1955 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1956 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1957 return CallResult.first;
1960 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1961 // "local exec" model.
1963 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1964 SelectionDAG &DAG) const {
1965 const GlobalValue *GV = GA->getGlobal();
1966 DebugLoc dl = GA->getDebugLoc();
1968 SDValue Chain = DAG.getEntryNode();
1969 EVT PtrVT = getPointerTy();
1970 // Get the Thread Pointer
1971 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1973 if (GV->isDeclaration()) {
1974 MachineFunction &MF = DAG.getMachineFunction();
1975 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1976 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1977 // Initial exec model.
1978 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1979 ARMConstantPoolValue *CPV =
1980 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1981 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1982 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1983 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1984 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1985 MachinePointerInfo::getConstantPool(),
1987 Chain = Offset.getValue(1);
1989 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1990 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1992 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1993 MachinePointerInfo::getConstantPool(),
1997 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
1998 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1999 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2000 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2001 MachinePointerInfo::getConstantPool(),
2005 // The address of the thread local variable is the add of the thread
2006 // pointer with the offset of the variable.
2007 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2011 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2012 // TODO: implement the "local dynamic" model
2013 assert(Subtarget->isTargetELF() &&
2014 "TLS not implemented for non-ELF targets");
2015 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2016 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
2017 // otherwise use the "Local Exec" TLS Model
2018 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
2019 return LowerToTLSGeneralDynamicModel(GA, DAG);
2021 return LowerToTLSExecModels(GA, DAG);
2024 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2025 SelectionDAG &DAG) const {
2026 EVT PtrVT = getPointerTy();
2027 DebugLoc dl = Op.getDebugLoc();
2028 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2029 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2030 if (RelocM == Reloc::PIC_) {
2031 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2032 ARMConstantPoolValue *CPV =
2033 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2034 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2035 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2036 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2038 MachinePointerInfo::getConstantPool(),
2040 SDValue Chain = Result.getValue(1);
2041 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2042 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2044 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2045 MachinePointerInfo::getGOT(), false, false, 0);
2049 // If we have T2 ops, we can materialize the address directly via movt/movw
2050 // pair. This is always cheaper.
2051 if (Subtarget->useMovt()) {
2053 // FIXME: Once remat is capable of dealing with instructions with register
2054 // operands, expand this into two nodes.
2055 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2056 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2058 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2059 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2060 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2061 MachinePointerInfo::getConstantPool(),
2066 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2067 SelectionDAG &DAG) const {
2068 EVT PtrVT = getPointerTy();
2069 DebugLoc dl = Op.getDebugLoc();
2070 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2071 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2072 MachineFunction &MF = DAG.getMachineFunction();
2073 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2075 if (Subtarget->useMovt()) {
2077 // FIXME: Once remat is capable of dealing with instructions with register
2078 // operands, expand this into two nodes.
2079 if (RelocM == Reloc::Static)
2080 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2081 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2083 unsigned Wrapper = (RelocM == Reloc::PIC_)
2084 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2085 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2086 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2087 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2088 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2089 MachinePointerInfo::getGOT(), false, false, 0);
2093 unsigned ARMPCLabelIndex = 0;
2095 if (RelocM == Reloc::Static) {
2096 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2098 ARMPCLabelIndex = AFI->createPICLabelUId();
2099 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2100 ARMConstantPoolValue *CPV =
2101 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
2102 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2104 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2106 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2107 MachinePointerInfo::getConstantPool(),
2109 SDValue Chain = Result.getValue(1);
2111 if (RelocM == Reloc::PIC_) {
2112 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2113 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2116 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2117 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2123 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2124 SelectionDAG &DAG) const {
2125 assert(Subtarget->isTargetELF() &&
2126 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2127 MachineFunction &MF = DAG.getMachineFunction();
2128 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2129 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2130 EVT PtrVT = getPointerTy();
2131 DebugLoc dl = Op.getDebugLoc();
2132 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2133 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2134 "_GLOBAL_OFFSET_TABLE_",
2135 ARMPCLabelIndex, PCAdj);
2136 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2137 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2138 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2139 MachinePointerInfo::getConstantPool(),
2141 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2142 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2146 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2148 DebugLoc dl = Op.getDebugLoc();
2149 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2154 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2155 DebugLoc dl = Op.getDebugLoc();
2156 SDValue Val = DAG.getConstant(0, MVT::i32);
2157 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2158 Op.getOperand(1), Val);
2162 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2163 DebugLoc dl = Op.getDebugLoc();
2164 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2165 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2169 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2170 const ARMSubtarget *Subtarget) const {
2171 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2172 DebugLoc dl = Op.getDebugLoc();
2174 default: return SDValue(); // Don't custom lower most intrinsics.
2175 case Intrinsic::arm_thread_pointer: {
2176 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2177 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2179 case Intrinsic::eh_sjlj_lsda: {
2180 MachineFunction &MF = DAG.getMachineFunction();
2181 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2182 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2183 EVT PtrVT = getPointerTy();
2184 DebugLoc dl = Op.getDebugLoc();
2185 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2187 unsigned PCAdj = (RelocM != Reloc::PIC_)
2188 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2189 ARMConstantPoolValue *CPV =
2190 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2191 ARMCP::CPLSDA, PCAdj);
2192 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2193 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2195 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2196 MachinePointerInfo::getConstantPool(),
2199 if (RelocM == Reloc::PIC_) {
2200 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2201 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2205 case Intrinsic::arm_neon_vmulls:
2206 case Intrinsic::arm_neon_vmullu: {
2207 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2208 ? ARMISD::VMULLs : ARMISD::VMULLu;
2209 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2210 Op.getOperand(1), Op.getOperand(2));
2215 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2216 const ARMSubtarget *Subtarget) {
2217 DebugLoc dl = Op.getDebugLoc();
2218 if (!Subtarget->hasDataBarrier()) {
2219 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2220 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2222 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2223 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2224 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2225 DAG.getConstant(0, MVT::i32));
2228 SDValue Op5 = Op.getOperand(5);
2229 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2230 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2231 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2232 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2234 ARM_MB::MemBOpt DMBOpt;
2235 if (isDeviceBarrier)
2236 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2238 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2239 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2240 DAG.getConstant(DMBOpt, MVT::i32));
2243 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2244 const ARMSubtarget *Subtarget) {
2245 // ARM pre v5TE and Thumb1 does not have preload instructions.
2246 if (!(Subtarget->isThumb2() ||
2247 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2248 // Just preserve the chain.
2249 return Op.getOperand(0);
2251 DebugLoc dl = Op.getDebugLoc();
2252 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2254 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2255 // ARMv7 with MP extension has PLDW.
2256 return Op.getOperand(0);
2258 if (Subtarget->isThumb())
2260 isRead = ~isRead & 1;
2261 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2263 // Currently there is no intrinsic that matches pli.
2264 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2265 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2266 DAG.getConstant(isData, MVT::i32));
2269 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2270 MachineFunction &MF = DAG.getMachineFunction();
2271 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2273 // vastart just stores the address of the VarArgsFrameIndex slot into the
2274 // memory location argument.
2275 DebugLoc dl = Op.getDebugLoc();
2276 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2277 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2278 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2279 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2280 MachinePointerInfo(SV), false, false, 0);
2284 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2285 SDValue &Root, SelectionDAG &DAG,
2286 DebugLoc dl) const {
2287 MachineFunction &MF = DAG.getMachineFunction();
2288 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2290 TargetRegisterClass *RC;
2291 if (AFI->isThumb1OnlyFunction())
2292 RC = ARM::tGPRRegisterClass;
2294 RC = ARM::GPRRegisterClass;
2296 // Transform the arguments stored in physical registers into virtual ones.
2297 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2298 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2301 if (NextVA.isMemLoc()) {
2302 MachineFrameInfo *MFI = MF.getFrameInfo();
2303 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2305 // Create load node to retrieve arguments from the stack.
2306 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2307 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2308 MachinePointerInfo::getFixedStack(FI),
2311 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2312 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2315 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2319 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2320 unsigned &VARegSize, unsigned &VARegSaveSize)
2323 if (CCInfo.isFirstByValRegValid())
2324 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2326 unsigned int firstUnalloced;
2327 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2328 sizeof(GPRArgRegs) /
2329 sizeof(GPRArgRegs[0]));
2330 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2333 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2334 VARegSize = NumGPRs * 4;
2335 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2338 // The remaining GPRs hold either the beginning of variable-argument
2339 // data, or the beginning of an aggregate passed by value (usuall
2340 // byval). Either way, we allocate stack slots adjacent to the data
2341 // provided by our caller, and store the unallocated registers there.
2342 // If this is a variadic function, the va_list pointer will begin with
2343 // these values; otherwise, this reassembles a (byval) structure that
2344 // was split between registers and memory.
2346 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2347 DebugLoc dl, SDValue &Chain,
2348 unsigned ArgOffset) const {
2349 MachineFunction &MF = DAG.getMachineFunction();
2350 MachineFrameInfo *MFI = MF.getFrameInfo();
2351 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2352 unsigned firstRegToSaveIndex;
2353 if (CCInfo.isFirstByValRegValid())
2354 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2356 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2357 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2360 unsigned VARegSize, VARegSaveSize;
2361 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2362 if (VARegSaveSize) {
2363 // If this function is vararg, store any remaining integer argument regs
2364 // to their spots on the stack so that they may be loaded by deferencing
2365 // the result of va_next.
2366 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2367 AFI->setVarArgsFrameIndex(
2368 MFI->CreateFixedObject(VARegSaveSize,
2369 ArgOffset + VARegSaveSize - VARegSize,
2371 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2374 SmallVector<SDValue, 4> MemOps;
2375 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
2376 TargetRegisterClass *RC;
2377 if (AFI->isThumb1OnlyFunction())
2378 RC = ARM::tGPRRegisterClass;
2380 RC = ARM::GPRRegisterClass;
2382 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2383 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2385 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2386 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2388 MemOps.push_back(Store);
2389 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2390 DAG.getConstant(4, getPointerTy()));
2392 if (!MemOps.empty())
2393 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2394 &MemOps[0], MemOps.size());
2396 // This will point to the next argument passed via stack.
2397 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2401 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2402 CallingConv::ID CallConv, bool isVarArg,
2403 const SmallVectorImpl<ISD::InputArg>
2405 DebugLoc dl, SelectionDAG &DAG,
2406 SmallVectorImpl<SDValue> &InVals)
2408 MachineFunction &MF = DAG.getMachineFunction();
2409 MachineFrameInfo *MFI = MF.getFrameInfo();
2411 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2413 // Assign locations to all of the incoming arguments.
2414 SmallVector<CCValAssign, 16> ArgLocs;
2415 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2417 CCInfo.setCallOrPrologue(Prologue);
2418 CCInfo.AnalyzeFormalArguments(Ins,
2419 CCAssignFnForNode(CallConv, /* Return*/ false,
2422 SmallVector<SDValue, 16> ArgValues;
2423 int lastInsIndex = -1;
2426 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2427 CCValAssign &VA = ArgLocs[i];
2429 // Arguments stored in registers.
2430 if (VA.isRegLoc()) {
2431 EVT RegVT = VA.getLocVT();
2433 if (VA.needsCustom()) {
2434 // f64 and vector types are split up into multiple registers or
2435 // combinations of registers and stack slots.
2436 if (VA.getLocVT() == MVT::v2f64) {
2437 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2439 VA = ArgLocs[++i]; // skip ahead to next loc
2441 if (VA.isMemLoc()) {
2442 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2443 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2444 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2445 MachinePointerInfo::getFixedStack(FI),
2448 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2451 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2452 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2453 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2454 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2455 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2457 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2460 TargetRegisterClass *RC;
2462 if (RegVT == MVT::f32)
2463 RC = ARM::SPRRegisterClass;
2464 else if (RegVT == MVT::f64)
2465 RC = ARM::DPRRegisterClass;
2466 else if (RegVT == MVT::v2f64)
2467 RC = ARM::QPRRegisterClass;
2468 else if (RegVT == MVT::i32)
2469 RC = (AFI->isThumb1OnlyFunction() ?
2470 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2472 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2474 // Transform the arguments in physical registers into virtual ones.
2475 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2476 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2479 // If this is an 8 or 16-bit value, it is really passed promoted
2480 // to 32 bits. Insert an assert[sz]ext to capture this, then
2481 // truncate to the right size.
2482 switch (VA.getLocInfo()) {
2483 default: llvm_unreachable("Unknown loc info!");
2484 case CCValAssign::Full: break;
2485 case CCValAssign::BCvt:
2486 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2488 case CCValAssign::SExt:
2489 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2490 DAG.getValueType(VA.getValVT()));
2491 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2493 case CCValAssign::ZExt:
2494 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2495 DAG.getValueType(VA.getValVT()));
2496 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2500 InVals.push_back(ArgValue);
2502 } else { // VA.isRegLoc()
2505 assert(VA.isMemLoc());
2506 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2508 int index = ArgLocs[i].getValNo();
2510 // Some Ins[] entries become multiple ArgLoc[] entries.
2511 // Process them only once.
2512 if (index != lastInsIndex)
2514 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2515 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2516 // changed with more analysis.
2517 // In case of tail call optimization mark all arguments mutable. Since they
2518 // could be overwritten by lowering of arguments in case of a tail call.
2519 if (Flags.isByVal()) {
2520 unsigned VARegSize, VARegSaveSize;
2521 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2522 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0);
2523 unsigned Bytes = Flags.getByValSize() - VARegSize;
2524 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2525 int FI = MFI->CreateFixedObject(Bytes,
2526 VA.getLocMemOffset(), false);
2527 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2529 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2530 VA.getLocMemOffset(), true);
2532 // Create load nodes to retrieve arguments from the stack.
2533 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2534 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2535 MachinePointerInfo::getFixedStack(FI),
2538 lastInsIndex = index;
2545 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset());
2550 /// isFloatingPointZero - Return true if this is +0.0.
2551 static bool isFloatingPointZero(SDValue Op) {
2552 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2553 return CFP->getValueAPF().isPosZero();
2554 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2555 // Maybe this has already been legalized into the constant pool?
2556 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2557 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2558 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2559 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2560 return CFP->getValueAPF().isPosZero();
2566 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2567 /// the given operands.
2569 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2570 SDValue &ARMcc, SelectionDAG &DAG,
2571 DebugLoc dl) const {
2572 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2573 unsigned C = RHSC->getZExtValue();
2574 if (!isLegalICmpImmediate(C)) {
2575 // Constant does not fit, try adjusting it by one?
2580 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2581 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2582 RHS = DAG.getConstant(C-1, MVT::i32);
2587 if (C != 0 && isLegalICmpImmediate(C-1)) {
2588 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2589 RHS = DAG.getConstant(C-1, MVT::i32);
2594 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2595 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2596 RHS = DAG.getConstant(C+1, MVT::i32);
2601 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2602 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2603 RHS = DAG.getConstant(C+1, MVT::i32);
2610 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2611 ARMISD::NodeType CompareType;
2614 CompareType = ARMISD::CMP;
2619 CompareType = ARMISD::CMPZ;
2622 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2623 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2626 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2628 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2629 DebugLoc dl) const {
2631 if (!isFloatingPointZero(RHS))
2632 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2634 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2635 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2638 /// duplicateCmp - Glue values can have only one use, so this function
2639 /// duplicates a comparison node.
2641 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2642 unsigned Opc = Cmp.getOpcode();
2643 DebugLoc DL = Cmp.getDebugLoc();
2644 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2645 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2647 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2648 Cmp = Cmp.getOperand(0);
2649 Opc = Cmp.getOpcode();
2650 if (Opc == ARMISD::CMPFP)
2651 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2653 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2654 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2656 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2659 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2660 SDValue Cond = Op.getOperand(0);
2661 SDValue SelectTrue = Op.getOperand(1);
2662 SDValue SelectFalse = Op.getOperand(2);
2663 DebugLoc dl = Op.getDebugLoc();
2667 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2668 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2670 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2671 const ConstantSDNode *CMOVTrue =
2672 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2673 const ConstantSDNode *CMOVFalse =
2674 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2676 if (CMOVTrue && CMOVFalse) {
2677 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2678 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2682 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2684 False = SelectFalse;
2685 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2690 if (True.getNode() && False.getNode()) {
2691 EVT VT = Cond.getValueType();
2692 SDValue ARMcc = Cond.getOperand(2);
2693 SDValue CCR = Cond.getOperand(3);
2694 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2695 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2700 return DAG.getSelectCC(dl, Cond,
2701 DAG.getConstant(0, Cond.getValueType()),
2702 SelectTrue, SelectFalse, ISD::SETNE);
2705 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2706 EVT VT = Op.getValueType();
2707 SDValue LHS = Op.getOperand(0);
2708 SDValue RHS = Op.getOperand(1);
2709 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2710 SDValue TrueVal = Op.getOperand(2);
2711 SDValue FalseVal = Op.getOperand(3);
2712 DebugLoc dl = Op.getDebugLoc();
2714 if (LHS.getValueType() == MVT::i32) {
2716 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2717 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2718 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2721 ARMCC::CondCodes CondCode, CondCode2;
2722 FPCCToARMCC(CC, CondCode, CondCode2);
2724 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2725 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2726 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2727 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2729 if (CondCode2 != ARMCC::AL) {
2730 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2731 // FIXME: Needs another CMP because flag can have but one use.
2732 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2733 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2734 Result, TrueVal, ARMcc2, CCR, Cmp2);
2739 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2740 /// to morph to an integer compare sequence.
2741 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2742 const ARMSubtarget *Subtarget) {
2743 SDNode *N = Op.getNode();
2744 if (!N->hasOneUse())
2745 // Otherwise it requires moving the value from fp to integer registers.
2747 if (!N->getNumValues())
2749 EVT VT = Op.getValueType();
2750 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2751 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2752 // vmrs are very slow, e.g. cortex-a8.
2755 if (isFloatingPointZero(Op)) {
2759 return ISD::isNormalLoad(N);
2762 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2763 if (isFloatingPointZero(Op))
2764 return DAG.getConstant(0, MVT::i32);
2766 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2767 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2768 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2769 Ld->isVolatile(), Ld->isNonTemporal(),
2770 Ld->getAlignment());
2772 llvm_unreachable("Unknown VFP cmp argument!");
2775 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2776 SDValue &RetVal1, SDValue &RetVal2) {
2777 if (isFloatingPointZero(Op)) {
2778 RetVal1 = DAG.getConstant(0, MVT::i32);
2779 RetVal2 = DAG.getConstant(0, MVT::i32);
2783 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2784 SDValue Ptr = Ld->getBasePtr();
2785 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2786 Ld->getChain(), Ptr,
2787 Ld->getPointerInfo(),
2788 Ld->isVolatile(), Ld->isNonTemporal(),
2789 Ld->getAlignment());
2791 EVT PtrType = Ptr.getValueType();
2792 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2793 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2794 PtrType, Ptr, DAG.getConstant(4, PtrType));
2795 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2796 Ld->getChain(), NewPtr,
2797 Ld->getPointerInfo().getWithOffset(4),
2798 Ld->isVolatile(), Ld->isNonTemporal(),
2803 llvm_unreachable("Unknown VFP cmp argument!");
2806 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2807 /// f32 and even f64 comparisons to integer ones.
2809 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2810 SDValue Chain = Op.getOperand(0);
2811 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2812 SDValue LHS = Op.getOperand(2);
2813 SDValue RHS = Op.getOperand(3);
2814 SDValue Dest = Op.getOperand(4);
2815 DebugLoc dl = Op.getDebugLoc();
2817 bool SeenZero = false;
2818 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2819 canChangeToInt(RHS, SeenZero, Subtarget) &&
2820 // If one of the operand is zero, it's safe to ignore the NaN case since
2821 // we only care about equality comparisons.
2822 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2823 // If unsafe fp math optimization is enabled and there are no other uses of
2824 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2825 // to an integer comparison.
2826 if (CC == ISD::SETOEQ)
2828 else if (CC == ISD::SETUNE)
2832 if (LHS.getValueType() == MVT::f32) {
2833 LHS = bitcastf32Toi32(LHS, DAG);
2834 RHS = bitcastf32Toi32(RHS, DAG);
2835 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2836 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2837 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2838 Chain, Dest, ARMcc, CCR, Cmp);
2843 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2844 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2845 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2846 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2847 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2848 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2849 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2855 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2856 SDValue Chain = Op.getOperand(0);
2857 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2858 SDValue LHS = Op.getOperand(2);
2859 SDValue RHS = Op.getOperand(3);
2860 SDValue Dest = Op.getOperand(4);
2861 DebugLoc dl = Op.getDebugLoc();
2863 if (LHS.getValueType() == MVT::i32) {
2865 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2866 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2867 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2868 Chain, Dest, ARMcc, CCR, Cmp);
2871 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2874 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2875 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2876 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2877 if (Result.getNode())
2881 ARMCC::CondCodes CondCode, CondCode2;
2882 FPCCToARMCC(CC, CondCode, CondCode2);
2884 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2885 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2886 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2887 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2888 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2889 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2890 if (CondCode2 != ARMCC::AL) {
2891 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2892 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2893 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2898 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2899 SDValue Chain = Op.getOperand(0);
2900 SDValue Table = Op.getOperand(1);
2901 SDValue Index = Op.getOperand(2);
2902 DebugLoc dl = Op.getDebugLoc();
2904 EVT PTy = getPointerTy();
2905 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2906 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2907 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2908 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2909 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2910 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2911 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2912 if (Subtarget->isThumb2()) {
2913 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2914 // which does another jump to the destination. This also makes it easier
2915 // to translate it to TBB / TBH later.
2916 // FIXME: This might not work if the function is extremely large.
2917 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2918 Addr, Op.getOperand(2), JTI, UId);
2920 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2921 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2922 MachinePointerInfo::getJumpTable(),
2924 Chain = Addr.getValue(1);
2925 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2926 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2928 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2929 MachinePointerInfo::getJumpTable(), false, false, 0);
2930 Chain = Addr.getValue(1);
2931 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2935 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2936 DebugLoc dl = Op.getDebugLoc();
2939 switch (Op.getOpcode()) {
2941 assert(0 && "Invalid opcode!");
2942 case ISD::FP_TO_SINT:
2943 Opc = ARMISD::FTOSI;
2945 case ISD::FP_TO_UINT:
2946 Opc = ARMISD::FTOUI;
2949 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2950 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2953 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2954 EVT VT = Op.getValueType();
2955 DebugLoc dl = Op.getDebugLoc();
2957 EVT OperandVT = Op.getOperand(0).getValueType();
2958 assert(OperandVT == MVT::v4i16 && "Invalid type for custom lowering!");
2959 if (VT != MVT::v4f32)
2960 return DAG.UnrollVectorOp(Op.getNode());
2964 switch (Op.getOpcode()) {
2966 assert(0 && "Invalid opcode!");
2967 case ISD::SINT_TO_FP:
2968 CastOpc = ISD::SIGN_EXTEND;
2969 Opc = ISD::SINT_TO_FP;
2971 case ISD::UINT_TO_FP:
2972 CastOpc = ISD::ZERO_EXTEND;
2973 Opc = ISD::UINT_TO_FP;
2977 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
2978 return DAG.getNode(Opc, dl, VT, Op);
2981 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2982 EVT VT = Op.getValueType();
2984 return LowerVectorINT_TO_FP(Op, DAG);
2986 DebugLoc dl = Op.getDebugLoc();
2989 switch (Op.getOpcode()) {
2991 assert(0 && "Invalid opcode!");
2992 case ISD::SINT_TO_FP:
2993 Opc = ARMISD::SITOF;
2995 case ISD::UINT_TO_FP:
2996 Opc = ARMISD::UITOF;
3000 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3001 return DAG.getNode(Opc, dl, VT, Op);
3004 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3005 // Implement fcopysign with a fabs and a conditional fneg.
3006 SDValue Tmp0 = Op.getOperand(0);
3007 SDValue Tmp1 = Op.getOperand(1);
3008 DebugLoc dl = Op.getDebugLoc();
3009 EVT VT = Op.getValueType();
3010 EVT SrcVT = Tmp1.getValueType();
3011 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3012 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3013 bool UseNEON = !InGPR && Subtarget->hasNEON();
3016 // Use VBSL to copy the sign bit.
3017 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3018 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3019 DAG.getTargetConstant(EncodedVal, MVT::i32));
3020 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3022 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3023 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3024 DAG.getConstant(32, MVT::i32));
3025 else /*if (VT == MVT::f32)*/
3026 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3027 if (SrcVT == MVT::f32) {
3028 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3030 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3031 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3032 DAG.getConstant(32, MVT::i32));
3033 } else if (VT == MVT::f32)
3034 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3035 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3036 DAG.getConstant(32, MVT::i32));
3037 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3038 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3040 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3042 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3043 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3044 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3046 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3047 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3048 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3049 if (VT == MVT::f32) {
3050 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3051 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3052 DAG.getConstant(0, MVT::i32));
3054 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3060 // Bitcast operand 1 to i32.
3061 if (SrcVT == MVT::f64)
3062 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3063 &Tmp1, 1).getValue(1);
3064 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3066 // Or in the signbit with integer operations.
3067 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3068 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3069 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3070 if (VT == MVT::f32) {
3071 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3072 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3073 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3074 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3077 // f64: Or the high part with signbit and then combine two parts.
3078 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3080 SDValue Lo = Tmp0.getValue(0);
3081 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3082 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3083 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3086 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3087 MachineFunction &MF = DAG.getMachineFunction();
3088 MachineFrameInfo *MFI = MF.getFrameInfo();
3089 MFI->setReturnAddressIsTaken(true);
3091 EVT VT = Op.getValueType();
3092 DebugLoc dl = Op.getDebugLoc();
3093 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3095 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3096 SDValue Offset = DAG.getConstant(4, MVT::i32);
3097 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3098 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3099 MachinePointerInfo(), false, false, 0);
3102 // Return LR, which contains the return address. Mark it an implicit live-in.
3103 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3104 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3107 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3108 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3109 MFI->setFrameAddressIsTaken(true);
3111 EVT VT = Op.getValueType();
3112 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3113 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3114 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3115 ? ARM::R7 : ARM::R11;
3116 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3118 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3119 MachinePointerInfo(),
3124 /// ExpandBITCAST - If the target supports VFP, this function is called to
3125 /// expand a bit convert where either the source or destination type is i64 to
3126 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3127 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3128 /// vectors), since the legalizer won't know what to do with that.
3129 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3130 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3131 DebugLoc dl = N->getDebugLoc();
3132 SDValue Op = N->getOperand(0);
3134 // This function is only supposed to be called for i64 types, either as the
3135 // source or destination of the bit convert.
3136 EVT SrcVT = Op.getValueType();
3137 EVT DstVT = N->getValueType(0);
3138 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3139 "ExpandBITCAST called for non-i64 type");
3141 // Turn i64->f64 into VMOVDRR.
3142 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3143 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3144 DAG.getConstant(0, MVT::i32));
3145 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3146 DAG.getConstant(1, MVT::i32));
3147 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3148 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3151 // Turn f64->i64 into VMOVRRD.
3152 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3153 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3154 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3155 // Merge the pieces into a single i64 value.
3156 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3162 /// getZeroVector - Returns a vector of specified type with all zero elements.
3163 /// Zero vectors are used to represent vector negation and in those cases
3164 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3165 /// not support i64 elements, so sometimes the zero vectors will need to be
3166 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3168 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3169 assert(VT.isVector() && "Expected a vector type");
3170 // The canonical modified immediate encoding of a zero vector is....0!
3171 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3172 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3173 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3174 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3177 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3178 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3179 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3180 SelectionDAG &DAG) const {
3181 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3182 EVT VT = Op.getValueType();
3183 unsigned VTBits = VT.getSizeInBits();
3184 DebugLoc dl = Op.getDebugLoc();
3185 SDValue ShOpLo = Op.getOperand(0);
3186 SDValue ShOpHi = Op.getOperand(1);
3187 SDValue ShAmt = Op.getOperand(2);
3189 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3191 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3193 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3194 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3195 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3196 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3197 DAG.getConstant(VTBits, MVT::i32));
3198 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3199 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3200 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3202 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3203 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3205 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3206 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3209 SDValue Ops[2] = { Lo, Hi };
3210 return DAG.getMergeValues(Ops, 2, dl);
3213 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3214 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3215 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3216 SelectionDAG &DAG) const {
3217 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3218 EVT VT = Op.getValueType();
3219 unsigned VTBits = VT.getSizeInBits();
3220 DebugLoc dl = Op.getDebugLoc();
3221 SDValue ShOpLo = Op.getOperand(0);
3222 SDValue ShOpHi = Op.getOperand(1);
3223 SDValue ShAmt = Op.getOperand(2);
3226 assert(Op.getOpcode() == ISD::SHL_PARTS);
3227 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3228 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3229 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3230 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3231 DAG.getConstant(VTBits, MVT::i32));
3232 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3233 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3235 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3236 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3237 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3239 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3240 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3243 SDValue Ops[2] = { Lo, Hi };
3244 return DAG.getMergeValues(Ops, 2, dl);
3247 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3248 SelectionDAG &DAG) const {
3249 // The rounding mode is in bits 23:22 of the FPSCR.
3250 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3251 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3252 // so that the shift + and get folded into a bitfield extract.
3253 DebugLoc dl = Op.getDebugLoc();
3254 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3255 DAG.getConstant(Intrinsic::arm_get_fpscr,
3257 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3258 DAG.getConstant(1U << 22, MVT::i32));
3259 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3260 DAG.getConstant(22, MVT::i32));
3261 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3262 DAG.getConstant(3, MVT::i32));
3265 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3266 const ARMSubtarget *ST) {
3267 EVT VT = N->getValueType(0);
3268 DebugLoc dl = N->getDebugLoc();
3270 if (!ST->hasV6T2Ops())
3273 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3274 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3277 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3278 const ARMSubtarget *ST) {
3279 EVT VT = N->getValueType(0);
3280 DebugLoc dl = N->getDebugLoc();
3285 // Lower vector shifts on NEON to use VSHL.
3286 assert(ST->hasNEON() && "unexpected vector shift");
3288 // Left shifts translate directly to the vshiftu intrinsic.
3289 if (N->getOpcode() == ISD::SHL)
3290 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3291 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3292 N->getOperand(0), N->getOperand(1));
3294 assert((N->getOpcode() == ISD::SRA ||
3295 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3297 // NEON uses the same intrinsics for both left and right shifts. For
3298 // right shifts, the shift amounts are negative, so negate the vector of
3300 EVT ShiftVT = N->getOperand(1).getValueType();
3301 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3302 getZeroVector(ShiftVT, DAG, dl),
3304 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3305 Intrinsic::arm_neon_vshifts :
3306 Intrinsic::arm_neon_vshiftu);
3307 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3308 DAG.getConstant(vshiftInt, MVT::i32),
3309 N->getOperand(0), NegatedCount);
3312 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3313 const ARMSubtarget *ST) {
3314 EVT VT = N->getValueType(0);
3315 DebugLoc dl = N->getDebugLoc();
3317 // We can get here for a node like i32 = ISD::SHL i32, i64
3321 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3322 "Unknown shift to lower!");
3324 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3325 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3326 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3329 // If we are in thumb mode, we don't have RRX.
3330 if (ST->isThumb1Only()) return SDValue();
3332 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3333 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3334 DAG.getConstant(0, MVT::i32));
3335 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3336 DAG.getConstant(1, MVT::i32));
3338 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3339 // captures the result into a carry flag.
3340 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3341 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3343 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3344 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3346 // Merge the pieces into a single i64 value.
3347 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3350 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3351 SDValue TmpOp0, TmpOp1;
3352 bool Invert = false;
3356 SDValue Op0 = Op.getOperand(0);
3357 SDValue Op1 = Op.getOperand(1);
3358 SDValue CC = Op.getOperand(2);
3359 EVT VT = Op.getValueType();
3360 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3361 DebugLoc dl = Op.getDebugLoc();
3363 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3364 switch (SetCCOpcode) {
3365 default: llvm_unreachable("Illegal FP comparison"); break;
3367 case ISD::SETNE: Invert = true; // Fallthrough
3369 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3371 case ISD::SETLT: Swap = true; // Fallthrough
3373 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3375 case ISD::SETLE: Swap = true; // Fallthrough
3377 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3378 case ISD::SETUGE: Swap = true; // Fallthrough
3379 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3380 case ISD::SETUGT: Swap = true; // Fallthrough
3381 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3382 case ISD::SETUEQ: Invert = true; // Fallthrough
3384 // Expand this to (OLT | OGT).
3388 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3389 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3391 case ISD::SETUO: Invert = true; // Fallthrough
3393 // Expand this to (OLT | OGE).
3397 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3398 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3402 // Integer comparisons.
3403 switch (SetCCOpcode) {
3404 default: llvm_unreachable("Illegal integer comparison"); break;
3405 case ISD::SETNE: Invert = true;
3406 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3407 case ISD::SETLT: Swap = true;
3408 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3409 case ISD::SETLE: Swap = true;
3410 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3411 case ISD::SETULT: Swap = true;
3412 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3413 case ISD::SETULE: Swap = true;
3414 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3417 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3418 if (Opc == ARMISD::VCEQ) {
3421 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3423 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3426 // Ignore bitconvert.
3427 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3428 AndOp = AndOp.getOperand(0);
3430 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3432 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3433 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3440 std::swap(Op0, Op1);
3442 // If one of the operands is a constant vector zero, attempt to fold the
3443 // comparison to a specialized compare-against-zero form.
3445 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3447 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3448 if (Opc == ARMISD::VCGE)
3449 Opc = ARMISD::VCLEZ;
3450 else if (Opc == ARMISD::VCGT)
3451 Opc = ARMISD::VCLTZ;
3456 if (SingleOp.getNode()) {
3459 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3461 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3463 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3465 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3467 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3469 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3472 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3476 Result = DAG.getNOT(dl, Result, VT);
3481 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3482 /// valid vector constant for a NEON instruction with a "modified immediate"
3483 /// operand (e.g., VMOV). If so, return the encoded value.
3484 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3485 unsigned SplatBitSize, SelectionDAG &DAG,
3486 EVT &VT, bool is128Bits, NEONModImmType type) {
3487 unsigned OpCmode, Imm;
3489 // SplatBitSize is set to the smallest size that splats the vector, so a
3490 // zero vector will always have SplatBitSize == 8. However, NEON modified
3491 // immediate instructions others than VMOV do not support the 8-bit encoding
3492 // of a zero vector, and the default encoding of zero is supposed to be the
3497 switch (SplatBitSize) {
3499 if (type != VMOVModImm)
3501 // Any 1-byte value is OK. Op=0, Cmode=1110.
3502 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3505 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3509 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3510 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3511 if ((SplatBits & ~0xff) == 0) {
3512 // Value = 0x00nn: Op=x, Cmode=100x.
3517 if ((SplatBits & ~0xff00) == 0) {
3518 // Value = 0xnn00: Op=x, Cmode=101x.
3520 Imm = SplatBits >> 8;
3526 // NEON's 32-bit VMOV supports splat values where:
3527 // * only one byte is nonzero, or
3528 // * the least significant byte is 0xff and the second byte is nonzero, or
3529 // * the least significant 2 bytes are 0xff and the third is nonzero.
3530 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3531 if ((SplatBits & ~0xff) == 0) {
3532 // Value = 0x000000nn: Op=x, Cmode=000x.
3537 if ((SplatBits & ~0xff00) == 0) {
3538 // Value = 0x0000nn00: Op=x, Cmode=001x.
3540 Imm = SplatBits >> 8;
3543 if ((SplatBits & ~0xff0000) == 0) {
3544 // Value = 0x00nn0000: Op=x, Cmode=010x.
3546 Imm = SplatBits >> 16;
3549 if ((SplatBits & ~0xff000000) == 0) {
3550 // Value = 0xnn000000: Op=x, Cmode=011x.
3552 Imm = SplatBits >> 24;
3556 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3557 if (type == OtherModImm) return SDValue();
3559 if ((SplatBits & ~0xffff) == 0 &&
3560 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3561 // Value = 0x0000nnff: Op=x, Cmode=1100.
3563 Imm = SplatBits >> 8;
3568 if ((SplatBits & ~0xffffff) == 0 &&
3569 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3570 // Value = 0x00nnffff: Op=x, Cmode=1101.
3572 Imm = SplatBits >> 16;
3573 SplatBits |= 0xffff;
3577 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3578 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3579 // VMOV.I32. A (very) minor optimization would be to replicate the value
3580 // and fall through here to test for a valid 64-bit splat. But, then the
3581 // caller would also need to check and handle the change in size.
3585 if (type != VMOVModImm)
3587 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3588 uint64_t BitMask = 0xff;
3590 unsigned ImmMask = 1;
3592 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3593 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3596 } else if ((SplatBits & BitMask) != 0) {
3602 // Op=1, Cmode=1110.
3605 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3610 llvm_unreachable("unexpected size for isNEONModifiedImm");
3614 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3615 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3618 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3619 bool &ReverseVEXT, unsigned &Imm) {
3620 unsigned NumElts = VT.getVectorNumElements();
3621 ReverseVEXT = false;
3623 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3629 // If this is a VEXT shuffle, the immediate value is the index of the first
3630 // element. The other shuffle indices must be the successive elements after
3632 unsigned ExpectedElt = Imm;
3633 for (unsigned i = 1; i < NumElts; ++i) {
3634 // Increment the expected index. If it wraps around, it may still be
3635 // a VEXT but the source vectors must be swapped.
3637 if (ExpectedElt == NumElts * 2) {
3642 if (M[i] < 0) continue; // ignore UNDEF indices
3643 if (ExpectedElt != static_cast<unsigned>(M[i]))
3647 // Adjust the index value if the source operands will be swapped.
3654 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3655 /// instruction with the specified blocksize. (The order of the elements
3656 /// within each block of the vector is reversed.)
3657 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3658 unsigned BlockSize) {
3659 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3660 "Only possible block sizes for VREV are: 16, 32, 64");
3662 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3666 unsigned NumElts = VT.getVectorNumElements();
3667 unsigned BlockElts = M[0] + 1;
3668 // If the first shuffle index is UNDEF, be optimistic.
3670 BlockElts = BlockSize / EltSz;
3672 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3675 for (unsigned i = 0; i < NumElts; ++i) {
3676 if (M[i] < 0) continue; // ignore UNDEF indices
3677 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3684 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3685 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3686 // range, then 0 is placed into the resulting vector. So pretty much any mask
3687 // of 8 elements can work here.
3688 return VT == MVT::v8i8 && M.size() == 8;
3691 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3692 unsigned &WhichResult) {
3693 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3697 unsigned NumElts = VT.getVectorNumElements();
3698 WhichResult = (M[0] == 0 ? 0 : 1);
3699 for (unsigned i = 0; i < NumElts; i += 2) {
3700 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3701 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3707 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3708 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3709 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3710 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3711 unsigned &WhichResult) {
3712 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3716 unsigned NumElts = VT.getVectorNumElements();
3717 WhichResult = (M[0] == 0 ? 0 : 1);
3718 for (unsigned i = 0; i < NumElts; i += 2) {
3719 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3720 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3726 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3727 unsigned &WhichResult) {
3728 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3732 unsigned NumElts = VT.getVectorNumElements();
3733 WhichResult = (M[0] == 0 ? 0 : 1);
3734 for (unsigned i = 0; i != NumElts; ++i) {
3735 if (M[i] < 0) continue; // ignore UNDEF indices
3736 if ((unsigned) M[i] != 2 * i + WhichResult)
3740 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3741 if (VT.is64BitVector() && EltSz == 32)
3747 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3748 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3749 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3750 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3751 unsigned &WhichResult) {
3752 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3756 unsigned Half = VT.getVectorNumElements() / 2;
3757 WhichResult = (M[0] == 0 ? 0 : 1);
3758 for (unsigned j = 0; j != 2; ++j) {
3759 unsigned Idx = WhichResult;
3760 for (unsigned i = 0; i != Half; ++i) {
3761 int MIdx = M[i + j * Half];
3762 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3768 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3769 if (VT.is64BitVector() && EltSz == 32)
3775 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3776 unsigned &WhichResult) {
3777 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3781 unsigned NumElts = VT.getVectorNumElements();
3782 WhichResult = (M[0] == 0 ? 0 : 1);
3783 unsigned Idx = WhichResult * NumElts / 2;
3784 for (unsigned i = 0; i != NumElts; i += 2) {
3785 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3786 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3791 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3792 if (VT.is64BitVector() && EltSz == 32)
3798 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3799 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3800 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3801 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3802 unsigned &WhichResult) {
3803 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3807 unsigned NumElts = VT.getVectorNumElements();
3808 WhichResult = (M[0] == 0 ? 0 : 1);
3809 unsigned Idx = WhichResult * NumElts / 2;
3810 for (unsigned i = 0; i != NumElts; i += 2) {
3811 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3812 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3817 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3818 if (VT.is64BitVector() && EltSz == 32)
3824 // If N is an integer constant that can be moved into a register in one
3825 // instruction, return an SDValue of such a constant (will become a MOV
3826 // instruction). Otherwise return null.
3827 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3828 const ARMSubtarget *ST, DebugLoc dl) {
3830 if (!isa<ConstantSDNode>(N))
3832 Val = cast<ConstantSDNode>(N)->getZExtValue();
3834 if (ST->isThumb1Only()) {
3835 if (Val <= 255 || ~Val <= 255)
3836 return DAG.getConstant(Val, MVT::i32);
3838 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3839 return DAG.getConstant(Val, MVT::i32);
3844 // If this is a case we can't handle, return null and let the default
3845 // expansion code take care of it.
3846 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3847 const ARMSubtarget *ST) const {
3848 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3849 DebugLoc dl = Op.getDebugLoc();
3850 EVT VT = Op.getValueType();
3852 APInt SplatBits, SplatUndef;
3853 unsigned SplatBitSize;
3855 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3856 if (SplatBitSize <= 64) {
3857 // Check if an immediate VMOV works.
3859 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3860 SplatUndef.getZExtValue(), SplatBitSize,
3861 DAG, VmovVT, VT.is128BitVector(),
3863 if (Val.getNode()) {
3864 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3865 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3868 // Try an immediate VMVN.
3869 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3870 ((1LL << SplatBitSize) - 1));
3871 Val = isNEONModifiedImm(NegatedImm,
3872 SplatUndef.getZExtValue(), SplatBitSize,
3873 DAG, VmovVT, VT.is128BitVector(),
3875 if (Val.getNode()) {
3876 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3877 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3882 // Scan through the operands to see if only one value is used.
3883 unsigned NumElts = VT.getVectorNumElements();
3884 bool isOnlyLowElement = true;
3885 bool usesOnlyOneValue = true;
3886 bool isConstant = true;
3888 for (unsigned i = 0; i < NumElts; ++i) {
3889 SDValue V = Op.getOperand(i);
3890 if (V.getOpcode() == ISD::UNDEF)
3893 isOnlyLowElement = false;
3894 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3897 if (!Value.getNode())
3899 else if (V != Value)
3900 usesOnlyOneValue = false;
3903 if (!Value.getNode())
3904 return DAG.getUNDEF(VT);
3906 if (isOnlyLowElement)
3907 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3909 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3911 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3912 // i32 and try again.
3913 if (usesOnlyOneValue && EltSize <= 32) {
3915 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3916 if (VT.getVectorElementType().isFloatingPoint()) {
3917 SmallVector<SDValue, 8> Ops;
3918 for (unsigned i = 0; i < NumElts; ++i)
3919 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3921 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3922 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3923 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3925 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3927 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3929 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3932 // If all elements are constants and the case above didn't get hit, fall back
3933 // to the default expansion, which will generate a load from the constant
3938 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
3940 SDValue shuffle = ReconstructShuffle(Op, DAG);
3941 if (shuffle != SDValue())
3945 // Vectors with 32- or 64-bit elements can be built by directly assigning
3946 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3947 // will be legalized.
3948 if (EltSize >= 32) {
3949 // Do the expansion with floating-point types, since that is what the VFP
3950 // registers are defined to use, and since i64 is not legal.
3951 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3952 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3953 SmallVector<SDValue, 8> Ops;
3954 for (unsigned i = 0; i < NumElts; ++i)
3955 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3956 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3957 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3963 // Gather data to see if the operation can be modelled as a
3964 // shuffle in combination with VEXTs.
3965 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
3966 SelectionDAG &DAG) const {
3967 DebugLoc dl = Op.getDebugLoc();
3968 EVT VT = Op.getValueType();
3969 unsigned NumElts = VT.getVectorNumElements();
3971 SmallVector<SDValue, 2> SourceVecs;
3972 SmallVector<unsigned, 2> MinElts;
3973 SmallVector<unsigned, 2> MaxElts;
3975 for (unsigned i = 0; i < NumElts; ++i) {
3976 SDValue V = Op.getOperand(i);
3977 if (V.getOpcode() == ISD::UNDEF)
3979 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
3980 // A shuffle can only come from building a vector from various
3981 // elements of other vectors.
3985 // Record this extraction against the appropriate vector if possible...
3986 SDValue SourceVec = V.getOperand(0);
3987 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
3988 bool FoundSource = false;
3989 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
3990 if (SourceVecs[j] == SourceVec) {
3991 if (MinElts[j] > EltNo)
3993 if (MaxElts[j] < EltNo)
4000 // Or record a new source if not...
4002 SourceVecs.push_back(SourceVec);
4003 MinElts.push_back(EltNo);
4004 MaxElts.push_back(EltNo);
4008 // Currently only do something sane when at most two source vectors
4010 if (SourceVecs.size() > 2)
4013 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4014 int VEXTOffsets[2] = {0, 0};
4016 // This loop extracts the usage patterns of the source vectors
4017 // and prepares appropriate SDValues for a shuffle if possible.
4018 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4019 if (SourceVecs[i].getValueType() == VT) {
4020 // No VEXT necessary
4021 ShuffleSrcs[i] = SourceVecs[i];
4024 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4025 // It probably isn't worth padding out a smaller vector just to
4026 // break it down again in a shuffle.
4030 // Since only 64-bit and 128-bit vectors are legal on ARM and
4031 // we've eliminated the other cases...
4032 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4033 "unexpected vector sizes in ReconstructShuffle");
4035 if (MaxElts[i] - MinElts[i] >= NumElts) {
4036 // Span too large for a VEXT to cope
4040 if (MinElts[i] >= NumElts) {
4041 // The extraction can just take the second half
4042 VEXTOffsets[i] = NumElts;
4043 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4045 DAG.getIntPtrConstant(NumElts));
4046 } else if (MaxElts[i] < NumElts) {
4047 // The extraction can just take the first half
4049 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4051 DAG.getIntPtrConstant(0));
4053 // An actual VEXT is needed
4054 VEXTOffsets[i] = MinElts[i];
4055 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4057 DAG.getIntPtrConstant(0));
4058 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4060 DAG.getIntPtrConstant(NumElts));
4061 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4062 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4066 SmallVector<int, 8> Mask;
4068 for (unsigned i = 0; i < NumElts; ++i) {
4069 SDValue Entry = Op.getOperand(i);
4070 if (Entry.getOpcode() == ISD::UNDEF) {
4075 SDValue ExtractVec = Entry.getOperand(0);
4076 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4077 .getOperand(1))->getSExtValue();
4078 if (ExtractVec == SourceVecs[0]) {
4079 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4081 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4085 // Final check before we try to produce nonsense...
4086 if (isShuffleMaskLegal(Mask, VT))
4087 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4093 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4094 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4095 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4096 /// are assumed to be legal.
4098 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4100 if (VT.getVectorNumElements() == 4 &&
4101 (VT.is128BitVector() || VT.is64BitVector())) {
4102 unsigned PFIndexes[4];
4103 for (unsigned i = 0; i != 4; ++i) {
4107 PFIndexes[i] = M[i];
4110 // Compute the index in the perfect shuffle table.
4111 unsigned PFTableIndex =
4112 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4113 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4114 unsigned Cost = (PFEntry >> 30);
4121 unsigned Imm, WhichResult;
4123 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4124 return (EltSize >= 32 ||
4125 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4126 isVREVMask(M, VT, 64) ||
4127 isVREVMask(M, VT, 32) ||
4128 isVREVMask(M, VT, 16) ||
4129 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4130 isVTBLMask(M, VT) ||
4131 isVTRNMask(M, VT, WhichResult) ||
4132 isVUZPMask(M, VT, WhichResult) ||
4133 isVZIPMask(M, VT, WhichResult) ||
4134 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4135 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4136 isVZIP_v_undef_Mask(M, VT, WhichResult));
4139 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4140 /// the specified operations to build the shuffle.
4141 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4142 SDValue RHS, SelectionDAG &DAG,
4144 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4145 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4146 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4149 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4158 OP_VUZPL, // VUZP, left result
4159 OP_VUZPR, // VUZP, right result
4160 OP_VZIPL, // VZIP, left result
4161 OP_VZIPR, // VZIP, right result
4162 OP_VTRNL, // VTRN, left result
4163 OP_VTRNR // VTRN, right result
4166 if (OpNum == OP_COPY) {
4167 if (LHSID == (1*9+2)*9+3) return LHS;
4168 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4172 SDValue OpLHS, OpRHS;
4173 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4174 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4175 EVT VT = OpLHS.getValueType();
4178 default: llvm_unreachable("Unknown shuffle opcode!");
4180 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4185 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4186 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4190 return DAG.getNode(ARMISD::VEXT, dl, VT,
4192 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4195 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4196 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4199 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4200 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4203 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4204 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4208 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4209 SmallVectorImpl<int> &ShuffleMask,
4210 SelectionDAG &DAG) {
4211 // Check to see if we can use the VTBL instruction.
4212 SDValue V1 = Op.getOperand(0);
4213 SDValue V2 = Op.getOperand(1);
4214 DebugLoc DL = Op.getDebugLoc();
4216 SmallVector<SDValue, 8> VTBLMask;
4217 for (SmallVectorImpl<int>::iterator
4218 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4219 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4221 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4222 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4223 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4226 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4227 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4231 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4232 SDValue V1 = Op.getOperand(0);
4233 SDValue V2 = Op.getOperand(1);
4234 DebugLoc dl = Op.getDebugLoc();
4235 EVT VT = Op.getValueType();
4236 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4237 SmallVector<int, 8> ShuffleMask;
4239 // Convert shuffles that are directly supported on NEON to target-specific
4240 // DAG nodes, instead of keeping them as shuffles and matching them again
4241 // during code selection. This is more efficient and avoids the possibility
4242 // of inconsistencies between legalization and selection.
4243 // FIXME: floating-point vectors should be canonicalized to integer vectors
4244 // of the same time so that they get CSEd properly.
4245 SVN->getMask(ShuffleMask);
4247 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4248 if (EltSize <= 32) {
4249 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4250 int Lane = SVN->getSplatIndex();
4251 // If this is undef splat, generate it via "just" vdup, if possible.
4252 if (Lane == -1) Lane = 0;
4254 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4255 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4257 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4258 DAG.getConstant(Lane, MVT::i32));
4263 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4266 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4267 DAG.getConstant(Imm, MVT::i32));
4270 if (isVREVMask(ShuffleMask, VT, 64))
4271 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4272 if (isVREVMask(ShuffleMask, VT, 32))
4273 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4274 if (isVREVMask(ShuffleMask, VT, 16))
4275 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4277 // Check for Neon shuffles that modify both input vectors in place.
4278 // If both results are used, i.e., if there are two shuffles with the same
4279 // source operands and with masks corresponding to both results of one of
4280 // these operations, DAG memoization will ensure that a single node is
4281 // used for both shuffles.
4282 unsigned WhichResult;
4283 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4284 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4285 V1, V2).getValue(WhichResult);
4286 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4287 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4288 V1, V2).getValue(WhichResult);
4289 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4290 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4291 V1, V2).getValue(WhichResult);
4293 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4294 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4295 V1, V1).getValue(WhichResult);
4296 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4297 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4298 V1, V1).getValue(WhichResult);
4299 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4300 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4301 V1, V1).getValue(WhichResult);
4304 // If the shuffle is not directly supported and it has 4 elements, use
4305 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4306 unsigned NumElts = VT.getVectorNumElements();
4308 unsigned PFIndexes[4];
4309 for (unsigned i = 0; i != 4; ++i) {
4310 if (ShuffleMask[i] < 0)
4313 PFIndexes[i] = ShuffleMask[i];
4316 // Compute the index in the perfect shuffle table.
4317 unsigned PFTableIndex =
4318 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4319 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4320 unsigned Cost = (PFEntry >> 30);
4323 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4326 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4327 if (EltSize >= 32) {
4328 // Do the expansion with floating-point types, since that is what the VFP
4329 // registers are defined to use, and since i64 is not legal.
4330 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4331 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4332 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4333 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4334 SmallVector<SDValue, 8> Ops;
4335 for (unsigned i = 0; i < NumElts; ++i) {
4336 if (ShuffleMask[i] < 0)
4337 Ops.push_back(DAG.getUNDEF(EltVT));
4339 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4340 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4341 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4344 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4345 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4348 if (VT == MVT::v8i8) {
4349 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4350 if (NewOp.getNode())
4357 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4358 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4359 SDValue Lane = Op.getOperand(1);
4360 if (!isa<ConstantSDNode>(Lane))
4363 SDValue Vec = Op.getOperand(0);
4364 if (Op.getValueType() == MVT::i32 &&
4365 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4366 DebugLoc dl = Op.getDebugLoc();
4367 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4373 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4374 // The only time a CONCAT_VECTORS operation can have legal types is when
4375 // two 64-bit vectors are concatenated to a 128-bit vector.
4376 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4377 "unexpected CONCAT_VECTORS");
4378 DebugLoc dl = Op.getDebugLoc();
4379 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4380 SDValue Op0 = Op.getOperand(0);
4381 SDValue Op1 = Op.getOperand(1);
4382 if (Op0.getOpcode() != ISD::UNDEF)
4383 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4384 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4385 DAG.getIntPtrConstant(0));
4386 if (Op1.getOpcode() != ISD::UNDEF)
4387 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4388 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4389 DAG.getIntPtrConstant(1));
4390 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4393 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4394 /// element has been zero/sign-extended, depending on the isSigned parameter,
4395 /// from an integer type half its size.
4396 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4398 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4399 EVT VT = N->getValueType(0);
4400 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4401 SDNode *BVN = N->getOperand(0).getNode();
4402 if (BVN->getValueType(0) != MVT::v4i32 ||
4403 BVN->getOpcode() != ISD::BUILD_VECTOR)
4405 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4406 unsigned HiElt = 1 - LoElt;
4407 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4408 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4409 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4410 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4411 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4414 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4415 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4418 if (Hi0->isNullValue() && Hi1->isNullValue())
4424 if (N->getOpcode() != ISD::BUILD_VECTOR)
4427 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4428 SDNode *Elt = N->getOperand(i).getNode();
4429 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4430 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4431 unsigned HalfSize = EltSize / 2;
4433 int64_t SExtVal = C->getSExtValue();
4434 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4437 if ((C->getZExtValue() >> HalfSize) != 0)
4448 /// isSignExtended - Check if a node is a vector value that is sign-extended
4449 /// or a constant BUILD_VECTOR with sign-extended elements.
4450 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4451 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4453 if (isExtendedBUILD_VECTOR(N, DAG, true))
4458 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4459 /// or a constant BUILD_VECTOR with zero-extended elements.
4460 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4461 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4463 if (isExtendedBUILD_VECTOR(N, DAG, false))
4468 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4469 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4470 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4471 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4472 return N->getOperand(0);
4473 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4474 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4475 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4476 LD->isNonTemporal(), LD->getAlignment());
4477 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4478 // have been legalized as a BITCAST from v4i32.
4479 if (N->getOpcode() == ISD::BITCAST) {
4480 SDNode *BVN = N->getOperand(0).getNode();
4481 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4482 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4483 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4484 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4485 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4487 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4488 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4489 EVT VT = N->getValueType(0);
4490 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4491 unsigned NumElts = VT.getVectorNumElements();
4492 MVT TruncVT = MVT::getIntegerVT(EltSize);
4493 SmallVector<SDValue, 8> Ops;
4494 for (unsigned i = 0; i != NumElts; ++i) {
4495 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4496 const APInt &CInt = C->getAPIntValue();
4497 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4499 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4500 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4503 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4504 unsigned Opcode = N->getOpcode();
4505 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4506 SDNode *N0 = N->getOperand(0).getNode();
4507 SDNode *N1 = N->getOperand(1).getNode();
4508 return N0->hasOneUse() && N1->hasOneUse() &&
4509 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4514 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4515 unsigned Opcode = N->getOpcode();
4516 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4517 SDNode *N0 = N->getOperand(0).getNode();
4518 SDNode *N1 = N->getOperand(1).getNode();
4519 return N0->hasOneUse() && N1->hasOneUse() &&
4520 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4525 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4526 // Multiplications are only custom-lowered for 128-bit vectors so that
4527 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4528 EVT VT = Op.getValueType();
4529 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4530 SDNode *N0 = Op.getOperand(0).getNode();
4531 SDNode *N1 = Op.getOperand(1).getNode();
4532 unsigned NewOpc = 0;
4534 bool isN0SExt = isSignExtended(N0, DAG);
4535 bool isN1SExt = isSignExtended(N1, DAG);
4536 if (isN0SExt && isN1SExt)
4537 NewOpc = ARMISD::VMULLs;
4539 bool isN0ZExt = isZeroExtended(N0, DAG);
4540 bool isN1ZExt = isZeroExtended(N1, DAG);
4541 if (isN0ZExt && isN1ZExt)
4542 NewOpc = ARMISD::VMULLu;
4543 else if (isN1SExt || isN1ZExt) {
4544 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4545 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4546 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4547 NewOpc = ARMISD::VMULLs;
4549 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4550 NewOpc = ARMISD::VMULLu;
4552 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4554 NewOpc = ARMISD::VMULLu;
4560 if (VT == MVT::v2i64)
4561 // Fall through to expand this. It is not legal.
4564 // Other vector multiplications are legal.
4569 // Legalize to a VMULL instruction.
4570 DebugLoc DL = Op.getDebugLoc();
4572 SDValue Op1 = SkipExtension(N1, DAG);
4574 Op0 = SkipExtension(N0, DAG);
4575 assert(Op0.getValueType().is64BitVector() &&
4576 Op1.getValueType().is64BitVector() &&
4577 "unexpected types for extended operands to VMULL");
4578 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4581 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4582 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4589 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4590 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4591 EVT Op1VT = Op1.getValueType();
4592 return DAG.getNode(N0->getOpcode(), DL, VT,
4593 DAG.getNode(NewOpc, DL, VT,
4594 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4595 DAG.getNode(NewOpc, DL, VT,
4596 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4600 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4602 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4603 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4604 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4605 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4606 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4607 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4608 // Get reciprocal estimate.
4609 // float4 recip = vrecpeq_f32(yf);
4610 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4611 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4612 // Because char has a smaller range than uchar, we can actually get away
4613 // without any newton steps. This requires that we use a weird bias
4614 // of 0xb000, however (again, this has been exhaustively tested).
4615 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4616 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4617 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4618 Y = DAG.getConstant(0xb000, MVT::i32);
4619 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4620 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4621 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4622 // Convert back to short.
4623 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4624 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4629 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4631 // Convert to float.
4632 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4633 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4634 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4635 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4636 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4637 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4639 // Use reciprocal estimate and one refinement step.
4640 // float4 recip = vrecpeq_f32(yf);
4641 // recip *= vrecpsq_f32(yf, recip);
4642 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4643 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4644 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4645 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4647 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4648 // Because short has a smaller range than ushort, we can actually get away
4649 // with only a single newton step. This requires that we use a weird bias
4650 // of 89, however (again, this has been exhaustively tested).
4651 // float4 result = as_float4(as_int4(xf*recip) + 89);
4652 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4653 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4654 N1 = DAG.getConstant(89, MVT::i32);
4655 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4656 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4657 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4658 // Convert back to integer and return.
4659 // return vmovn_s32(vcvt_s32_f32(result));
4660 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4661 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4665 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4666 EVT VT = Op.getValueType();
4667 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4668 "unexpected type for custom-lowering ISD::SDIV");
4670 DebugLoc dl = Op.getDebugLoc();
4671 SDValue N0 = Op.getOperand(0);
4672 SDValue N1 = Op.getOperand(1);
4675 if (VT == MVT::v8i8) {
4676 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4677 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4679 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4680 DAG.getIntPtrConstant(4));
4681 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4682 DAG.getIntPtrConstant(4));
4683 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4684 DAG.getIntPtrConstant(0));
4685 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4686 DAG.getIntPtrConstant(0));
4688 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4689 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4691 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4692 N0 = LowerCONCAT_VECTORS(N0, DAG);
4694 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4697 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4700 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4701 EVT VT = Op.getValueType();
4702 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4703 "unexpected type for custom-lowering ISD::UDIV");
4705 DebugLoc dl = Op.getDebugLoc();
4706 SDValue N0 = Op.getOperand(0);
4707 SDValue N1 = Op.getOperand(1);
4710 if (VT == MVT::v8i8) {
4711 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4712 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4714 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4715 DAG.getIntPtrConstant(4));
4716 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4717 DAG.getIntPtrConstant(4));
4718 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4719 DAG.getIntPtrConstant(0));
4720 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4721 DAG.getIntPtrConstant(0));
4723 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4724 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4726 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4727 N0 = LowerCONCAT_VECTORS(N0, DAG);
4729 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4730 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4735 // v4i16 sdiv ... Convert to float.
4736 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4737 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4738 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4739 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4740 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4741 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4743 // Use reciprocal estimate and two refinement steps.
4744 // float4 recip = vrecpeq_f32(yf);
4745 // recip *= vrecpsq_f32(yf, recip);
4746 // recip *= vrecpsq_f32(yf, recip);
4747 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4748 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4749 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4750 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4752 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4753 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4754 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4756 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4757 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4758 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4759 // and that it will never cause us to return an answer too large).
4760 // float4 result = as_float4(as_int4(xf*recip) + 89);
4761 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4762 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4763 N1 = DAG.getConstant(2, MVT::i32);
4764 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4765 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4766 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4767 // Convert back to integer and return.
4768 // return vmovn_u32(vcvt_s32_f32(result));
4769 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4770 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4774 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4775 switch (Op.getOpcode()) {
4776 default: llvm_unreachable("Don't know how to custom lower this!");
4777 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4778 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4779 case ISD::GlobalAddress:
4780 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4781 LowerGlobalAddressELF(Op, DAG);
4782 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4783 case ISD::SELECT: return LowerSELECT(Op, DAG);
4784 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4785 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4786 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4787 case ISD::VASTART: return LowerVASTART(Op, DAG);
4788 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4789 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4790 case ISD::SINT_TO_FP:
4791 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4792 case ISD::FP_TO_SINT:
4793 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4794 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4795 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4796 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4797 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4798 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4799 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4800 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4801 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4803 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4806 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4807 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4808 case ISD::SRL_PARTS:
4809 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4810 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4811 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4812 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4813 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4814 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4815 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4816 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4817 case ISD::MUL: return LowerMUL(Op, DAG);
4818 case ISD::SDIV: return LowerSDIV(Op, DAG);
4819 case ISD::UDIV: return LowerUDIV(Op, DAG);
4824 /// ReplaceNodeResults - Replace the results of node with an illegal result
4825 /// type with new values built out of custom code.
4826 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4827 SmallVectorImpl<SDValue>&Results,
4828 SelectionDAG &DAG) const {
4830 switch (N->getOpcode()) {
4832 llvm_unreachable("Don't know how to custom expand this!");
4835 Res = ExpandBITCAST(N, DAG);
4839 Res = Expand64BitShift(N, DAG, Subtarget);
4843 Results.push_back(Res);
4846 //===----------------------------------------------------------------------===//
4847 // ARM Scheduler Hooks
4848 //===----------------------------------------------------------------------===//
4851 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4852 MachineBasicBlock *BB,
4853 unsigned Size) const {
4854 unsigned dest = MI->getOperand(0).getReg();
4855 unsigned ptr = MI->getOperand(1).getReg();
4856 unsigned oldval = MI->getOperand(2).getReg();
4857 unsigned newval = MI->getOperand(3).getReg();
4858 unsigned scratch = BB->getParent()->getRegInfo()
4859 .createVirtualRegister(ARM::GPRRegisterClass);
4860 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4861 DebugLoc dl = MI->getDebugLoc();
4862 bool isThumb2 = Subtarget->isThumb2();
4864 unsigned ldrOpc, strOpc;
4866 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4868 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4869 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4872 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4873 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4876 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4877 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4881 MachineFunction *MF = BB->getParent();
4882 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4883 MachineFunction::iterator It = BB;
4884 ++It; // insert the new blocks after the current block
4886 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4887 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4888 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4889 MF->insert(It, loop1MBB);
4890 MF->insert(It, loop2MBB);
4891 MF->insert(It, exitMBB);
4893 // Transfer the remainder of BB and its successor edges to exitMBB.
4894 exitMBB->splice(exitMBB->begin(), BB,
4895 llvm::next(MachineBasicBlock::iterator(MI)),
4897 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4901 // fallthrough --> loop1MBB
4902 BB->addSuccessor(loop1MBB);
4905 // ldrex dest, [ptr]
4909 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4910 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4911 .addReg(dest).addReg(oldval));
4912 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4913 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4914 BB->addSuccessor(loop2MBB);
4915 BB->addSuccessor(exitMBB);
4918 // strex scratch, newval, [ptr]
4922 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4924 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4925 .addReg(scratch).addImm(0));
4926 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4927 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4928 BB->addSuccessor(loop1MBB);
4929 BB->addSuccessor(exitMBB);
4935 MI->eraseFromParent(); // The instruction is gone now.
4941 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4942 unsigned Size, unsigned BinOpcode) const {
4943 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4944 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4946 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4947 MachineFunction *MF = BB->getParent();
4948 MachineFunction::iterator It = BB;
4951 unsigned dest = MI->getOperand(0).getReg();
4952 unsigned ptr = MI->getOperand(1).getReg();
4953 unsigned incr = MI->getOperand(2).getReg();
4954 DebugLoc dl = MI->getDebugLoc();
4956 bool isThumb2 = Subtarget->isThumb2();
4957 unsigned ldrOpc, strOpc;
4959 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4961 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4962 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4965 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4966 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4969 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4970 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4974 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4975 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4976 MF->insert(It, loopMBB);
4977 MF->insert(It, exitMBB);
4979 // Transfer the remainder of BB and its successor edges to exitMBB.
4980 exitMBB->splice(exitMBB->begin(), BB,
4981 llvm::next(MachineBasicBlock::iterator(MI)),
4983 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4985 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4986 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4987 unsigned scratch2 = (!BinOpcode) ? incr :
4988 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4992 // fallthrough --> loopMBB
4993 BB->addSuccessor(loopMBB);
4997 // <binop> scratch2, dest, incr
4998 // strex scratch, scratch2, ptr
5001 // fallthrough --> exitMBB
5003 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
5005 // operand order needs to go the other way for NAND
5006 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5007 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5008 addReg(incr).addReg(dest)).addReg(0);
5010 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5011 addReg(dest).addReg(incr)).addReg(0);
5014 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
5016 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5017 .addReg(scratch).addImm(0));
5018 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5019 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5021 BB->addSuccessor(loopMBB);
5022 BB->addSuccessor(exitMBB);
5028 MI->eraseFromParent(); // The instruction is gone now.
5034 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
5035 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
5036 E = MBB->succ_end(); I != E; ++I)
5039 llvm_unreachable("Expecting a BB with two successors!");
5043 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5044 MachineBasicBlock *BB) const {
5045 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5046 DebugLoc dl = MI->getDebugLoc();
5047 bool isThumb2 = Subtarget->isThumb2();
5048 switch (MI->getOpcode()) {
5051 llvm_unreachable("Unexpected instr type to insert");
5053 case ARM::ATOMIC_LOAD_ADD_I8:
5054 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5055 case ARM::ATOMIC_LOAD_ADD_I16:
5056 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5057 case ARM::ATOMIC_LOAD_ADD_I32:
5058 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5060 case ARM::ATOMIC_LOAD_AND_I8:
5061 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5062 case ARM::ATOMIC_LOAD_AND_I16:
5063 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5064 case ARM::ATOMIC_LOAD_AND_I32:
5065 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5067 case ARM::ATOMIC_LOAD_OR_I8:
5068 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5069 case ARM::ATOMIC_LOAD_OR_I16:
5070 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5071 case ARM::ATOMIC_LOAD_OR_I32:
5072 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5074 case ARM::ATOMIC_LOAD_XOR_I8:
5075 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5076 case ARM::ATOMIC_LOAD_XOR_I16:
5077 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5078 case ARM::ATOMIC_LOAD_XOR_I32:
5079 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5081 case ARM::ATOMIC_LOAD_NAND_I8:
5082 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5083 case ARM::ATOMIC_LOAD_NAND_I16:
5084 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5085 case ARM::ATOMIC_LOAD_NAND_I32:
5086 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5088 case ARM::ATOMIC_LOAD_SUB_I8:
5089 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5090 case ARM::ATOMIC_LOAD_SUB_I16:
5091 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5092 case ARM::ATOMIC_LOAD_SUB_I32:
5093 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5095 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
5096 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
5097 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
5099 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
5100 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
5101 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
5114 unsigned OldOpc = MI->getOpcode();
5151 llvm_unreachable("Unknown opcode?");
5154 MachineInstrBuilder MIB =
5155 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(Opc));
5156 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
5157 MIB.addOperand(MI->getOperand(i));
5158 AddDefaultPred(MIB);
5159 MIB.addReg(ARM::CPSR, RegState::Define); // S bit
5160 MI->eraseFromParent();
5165 case ARM::tMOVCCr_pseudo: {
5166 // To "insert" a SELECT_CC instruction, we actually have to insert the
5167 // diamond control-flow pattern. The incoming instruction knows the
5168 // destination vreg to set, the condition code register to branch on, the
5169 // true/false values to select between, and a branch opcode to use.
5170 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5171 MachineFunction::iterator It = BB;
5177 // cmpTY ccX, r1, r2
5179 // fallthrough --> copy0MBB
5180 MachineBasicBlock *thisMBB = BB;
5181 MachineFunction *F = BB->getParent();
5182 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
5183 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
5184 F->insert(It, copy0MBB);
5185 F->insert(It, sinkMBB);
5187 // Transfer the remainder of BB and its successor edges to sinkMBB.
5188 sinkMBB->splice(sinkMBB->begin(), BB,
5189 llvm::next(MachineBasicBlock::iterator(MI)),
5191 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5193 BB->addSuccessor(copy0MBB);
5194 BB->addSuccessor(sinkMBB);
5196 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
5197 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
5200 // %FalseValue = ...
5201 // # fallthrough to sinkMBB
5204 // Update machine-CFG edges
5205 BB->addSuccessor(sinkMBB);
5208 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5211 BuildMI(*BB, BB->begin(), dl,
5212 TII->get(ARM::PHI), MI->getOperand(0).getReg())
5213 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5214 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5216 MI->eraseFromParent(); // The pseudo instruction is gone now.
5221 case ARM::BCCZi64: {
5222 // If there is an unconditional branch to the other successor, remove it.
5223 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
5225 // Compare both parts that make up the double comparison separately for
5227 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
5229 unsigned LHS1 = MI->getOperand(1).getReg();
5230 unsigned LHS2 = MI->getOperand(2).getReg();
5232 AddDefaultPred(BuildMI(BB, dl,
5233 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5234 .addReg(LHS1).addImm(0));
5235 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5236 .addReg(LHS2).addImm(0)
5237 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5239 unsigned RHS1 = MI->getOperand(3).getReg();
5240 unsigned RHS2 = MI->getOperand(4).getReg();
5241 AddDefaultPred(BuildMI(BB, dl,
5242 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5243 .addReg(LHS1).addReg(RHS1));
5244 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5245 .addReg(LHS2).addReg(RHS2)
5246 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5249 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
5250 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
5251 if (MI->getOperand(0).getImm() == ARMCC::NE)
5252 std::swap(destMBB, exitMBB);
5254 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5255 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
5256 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
5259 MI->eraseFromParent(); // The pseudo instruction is gone now.
5265 //===----------------------------------------------------------------------===//
5266 // ARM Optimization Hooks
5267 //===----------------------------------------------------------------------===//
5270 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
5271 TargetLowering::DAGCombinerInfo &DCI) {
5272 SelectionDAG &DAG = DCI.DAG;
5273 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5274 EVT VT = N->getValueType(0);
5275 unsigned Opc = N->getOpcode();
5276 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
5277 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
5278 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
5279 ISD::CondCode CC = ISD::SETCC_INVALID;
5282 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
5284 SDValue CCOp = Slct.getOperand(0);
5285 if (CCOp.getOpcode() == ISD::SETCC)
5286 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
5289 bool DoXform = false;
5291 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
5294 if (LHS.getOpcode() == ISD::Constant &&
5295 cast<ConstantSDNode>(LHS)->isNullValue()) {
5297 } else if (CC != ISD::SETCC_INVALID &&
5298 RHS.getOpcode() == ISD::Constant &&
5299 cast<ConstantSDNode>(RHS)->isNullValue()) {
5300 std::swap(LHS, RHS);
5301 SDValue Op0 = Slct.getOperand(0);
5302 EVT OpVT = isSlctCC ? Op0.getValueType() :
5303 Op0.getOperand(0).getValueType();
5304 bool isInt = OpVT.isInteger();
5305 CC = ISD::getSetCCInverse(CC, isInt);
5307 if (!TLI.isCondCodeLegal(CC, OpVT))
5308 return SDValue(); // Inverse operator isn't legal.
5315 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
5317 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
5318 Slct.getOperand(0), Slct.getOperand(1), CC);
5319 SDValue CCOp = Slct.getOperand(0);
5321 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
5322 CCOp.getOperand(0), CCOp.getOperand(1), CC);
5323 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
5324 CCOp, OtherOp, Result);
5329 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
5330 /// operands N0 and N1. This is a helper for PerformADDCombine that is
5331 /// called with the default operands, and if that fails, with commuted
5333 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
5334 TargetLowering::DAGCombinerInfo &DCI) {
5335 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
5336 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
5337 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
5338 if (Result.getNode()) return Result;
5343 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
5345 static SDValue PerformADDCombine(SDNode *N,
5346 TargetLowering::DAGCombinerInfo &DCI) {
5347 SDValue N0 = N->getOperand(0);
5348 SDValue N1 = N->getOperand(1);
5350 // First try with the default operand order.
5351 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
5352 if (Result.getNode())
5355 // If that didn't work, try again with the operands commuted.
5356 return PerformADDCombineWithOperands(N, N1, N0, DCI);
5359 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
5361 static SDValue PerformSUBCombine(SDNode *N,
5362 TargetLowering::DAGCombinerInfo &DCI) {
5363 SDValue N0 = N->getOperand(0);
5364 SDValue N1 = N->getOperand(1);
5366 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
5367 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
5368 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
5369 if (Result.getNode()) return Result;
5375 /// PerformVMULCombine
5376 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
5377 /// special multiplier accumulator forwarding.
5383 static SDValue PerformVMULCombine(SDNode *N,
5384 TargetLowering::DAGCombinerInfo &DCI,
5385 const ARMSubtarget *Subtarget) {
5386 if (!Subtarget->hasVMLxForwarding())
5389 SelectionDAG &DAG = DCI.DAG;
5390 SDValue N0 = N->getOperand(0);
5391 SDValue N1 = N->getOperand(1);
5392 unsigned Opcode = N0.getOpcode();
5393 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5394 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
5395 Opcode = N0.getOpcode();
5396 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5397 Opcode != ISD::FADD && Opcode != ISD::FSUB)
5402 EVT VT = N->getValueType(0);
5403 DebugLoc DL = N->getDebugLoc();
5404 SDValue N00 = N0->getOperand(0);
5405 SDValue N01 = N0->getOperand(1);
5406 return DAG.getNode(Opcode, DL, VT,
5407 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
5408 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
5411 static SDValue PerformMULCombine(SDNode *N,
5412 TargetLowering::DAGCombinerInfo &DCI,
5413 const ARMSubtarget *Subtarget) {
5414 SelectionDAG &DAG = DCI.DAG;
5416 if (Subtarget->isThumb1Only())
5419 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5422 EVT VT = N->getValueType(0);
5423 if (VT.is64BitVector() || VT.is128BitVector())
5424 return PerformVMULCombine(N, DCI, Subtarget);
5428 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
5432 uint64_t MulAmt = C->getZExtValue();
5433 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
5434 ShiftAmt = ShiftAmt & (32 - 1);
5435 SDValue V = N->getOperand(0);
5436 DebugLoc DL = N->getDebugLoc();
5439 MulAmt >>= ShiftAmt;
5440 if (isPowerOf2_32(MulAmt - 1)) {
5441 // (mul x, 2^N + 1) => (add (shl x, N), x)
5442 Res = DAG.getNode(ISD::ADD, DL, VT,
5443 V, DAG.getNode(ISD::SHL, DL, VT,
5444 V, DAG.getConstant(Log2_32(MulAmt-1),
5446 } else if (isPowerOf2_32(MulAmt + 1)) {
5447 // (mul x, 2^N - 1) => (sub (shl x, N), x)
5448 Res = DAG.getNode(ISD::SUB, DL, VT,
5449 DAG.getNode(ISD::SHL, DL, VT,
5450 V, DAG.getConstant(Log2_32(MulAmt+1),
5457 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
5458 DAG.getConstant(ShiftAmt, MVT::i32));
5460 // Do not add new nodes to DAG combiner worklist.
5461 DCI.CombineTo(N, Res, false);
5465 static SDValue PerformANDCombine(SDNode *N,
5466 TargetLowering::DAGCombinerInfo &DCI) {
5468 // Attempt to use immediate-form VBIC
5469 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5470 DebugLoc dl = N->getDebugLoc();
5471 EVT VT = N->getValueType(0);
5472 SelectionDAG &DAG = DCI.DAG;
5474 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5477 APInt SplatBits, SplatUndef;
5478 unsigned SplatBitSize;
5481 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5482 if (SplatBitSize <= 64) {
5484 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
5485 SplatUndef.getZExtValue(), SplatBitSize,
5486 DAG, VbicVT, VT.is128BitVector(),
5488 if (Val.getNode()) {
5490 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
5491 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
5492 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
5500 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
5501 static SDValue PerformORCombine(SDNode *N,
5502 TargetLowering::DAGCombinerInfo &DCI,
5503 const ARMSubtarget *Subtarget) {
5504 // Attempt to use immediate-form VORR
5505 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5506 DebugLoc dl = N->getDebugLoc();
5507 EVT VT = N->getValueType(0);
5508 SelectionDAG &DAG = DCI.DAG;
5510 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5513 APInt SplatBits, SplatUndef;
5514 unsigned SplatBitSize;
5516 if (BVN && Subtarget->hasNEON() &&
5517 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5518 if (SplatBitSize <= 64) {
5520 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5521 SplatUndef.getZExtValue(), SplatBitSize,
5522 DAG, VorrVT, VT.is128BitVector(),
5524 if (Val.getNode()) {
5526 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
5527 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
5528 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
5533 SDValue N0 = N->getOperand(0);
5534 if (N0.getOpcode() != ISD::AND)
5536 SDValue N1 = N->getOperand(1);
5538 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
5539 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
5540 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
5542 unsigned SplatBitSize;
5545 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
5547 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
5548 HasAnyUndefs) && !HasAnyUndefs) {
5549 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
5551 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
5552 HasAnyUndefs) && !HasAnyUndefs &&
5553 SplatBits0 == ~SplatBits1) {
5554 // Canonicalize the vector type to make instruction selection simpler.
5555 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5556 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
5557 N0->getOperand(1), N0->getOperand(0),
5559 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
5564 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
5567 // BFI is only available on V6T2+
5568 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
5571 DebugLoc DL = N->getDebugLoc();
5572 // 1) or (and A, mask), val => ARMbfi A, val, mask
5573 // iff (val & mask) == val
5575 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5576 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
5577 // && mask == ~mask2
5578 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
5579 // && ~mask == mask2
5580 // (i.e., copy a bitfield value into another bitfield of the same width)
5585 SDValue N00 = N0.getOperand(0);
5587 // The value and the mask need to be constants so we can verify this is
5588 // actually a bitfield set. If the mask is 0xffff, we can do better
5589 // via a movt instruction, so don't use BFI in that case.
5590 SDValue MaskOp = N0.getOperand(1);
5591 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
5594 unsigned Mask = MaskC->getZExtValue();
5598 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
5599 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5601 unsigned Val = N1C->getZExtValue();
5602 if ((Val & ~Mask) != Val)
5605 if (ARM::isBitFieldInvertedMask(Mask)) {
5606 Val >>= CountTrailingZeros_32(~Mask);
5608 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
5609 DAG.getConstant(Val, MVT::i32),
5610 DAG.getConstant(Mask, MVT::i32));
5612 // Do not add new nodes to DAG combiner worklist.
5613 DCI.CombineTo(N, Res, false);
5616 } else if (N1.getOpcode() == ISD::AND) {
5617 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5618 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5621 unsigned Mask2 = N11C->getZExtValue();
5623 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
5625 if (ARM::isBitFieldInvertedMask(Mask) &&
5627 // The pack halfword instruction works better for masks that fit it,
5628 // so use that when it's available.
5629 if (Subtarget->hasT2ExtractPack() &&
5630 (Mask == 0xffff || Mask == 0xffff0000))
5633 unsigned amt = CountTrailingZeros_32(Mask2);
5634 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
5635 DAG.getConstant(amt, MVT::i32));
5636 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
5637 DAG.getConstant(Mask, MVT::i32));
5638 // Do not add new nodes to DAG combiner worklist.
5639 DCI.CombineTo(N, Res, false);
5641 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
5643 // The pack halfword instruction works better for masks that fit it,
5644 // so use that when it's available.
5645 if (Subtarget->hasT2ExtractPack() &&
5646 (Mask2 == 0xffff || Mask2 == 0xffff0000))
5649 unsigned lsb = CountTrailingZeros_32(Mask);
5650 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
5651 DAG.getConstant(lsb, MVT::i32));
5652 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
5653 DAG.getConstant(Mask2, MVT::i32));
5654 // Do not add new nodes to DAG combiner worklist.
5655 DCI.CombineTo(N, Res, false);
5660 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
5661 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
5662 ARM::isBitFieldInvertedMask(~Mask)) {
5663 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
5664 // where lsb(mask) == #shamt and masked bits of B are known zero.
5665 SDValue ShAmt = N00.getOperand(1);
5666 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5667 unsigned LSB = CountTrailingZeros_32(Mask);
5671 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
5672 DAG.getConstant(~Mask, MVT::i32));
5674 // Do not add new nodes to DAG combiner worklist.
5675 DCI.CombineTo(N, Res, false);
5681 /// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff
5683 static SDValue PerformBFICombine(SDNode *N,
5684 TargetLowering::DAGCombinerInfo &DCI) {
5685 SDValue N1 = N->getOperand(1);
5686 if (N1.getOpcode() == ISD::AND) {
5687 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5690 unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
5691 unsigned Mask2 = N11C->getZExtValue();
5692 if ((Mask & Mask2) == Mask2)
5693 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
5694 N->getOperand(0), N1.getOperand(0),
5700 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
5701 /// ARMISD::VMOVRRD.
5702 static SDValue PerformVMOVRRDCombine(SDNode *N,
5703 TargetLowering::DAGCombinerInfo &DCI) {
5704 // vmovrrd(vmovdrr x, y) -> x,y
5705 SDValue InDouble = N->getOperand(0);
5706 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
5707 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
5709 // vmovrrd(load f64) -> (load i32), (load i32)
5710 SDNode *InNode = InDouble.getNode();
5711 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
5712 InNode->getValueType(0) == MVT::f64 &&
5713 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
5714 !cast<LoadSDNode>(InNode)->isVolatile()) {
5715 // TODO: Should this be done for non-FrameIndex operands?
5716 LoadSDNode *LD = cast<LoadSDNode>(InNode);
5718 SelectionDAG &DAG = DCI.DAG;
5719 DebugLoc DL = LD->getDebugLoc();
5720 SDValue BasePtr = LD->getBasePtr();
5721 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
5722 LD->getPointerInfo(), LD->isVolatile(),
5723 LD->isNonTemporal(), LD->getAlignment());
5725 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
5726 DAG.getConstant(4, MVT::i32));
5727 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
5728 LD->getPointerInfo(), LD->isVolatile(),
5729 LD->isNonTemporal(),
5730 std::min(4U, LD->getAlignment() / 2));
5732 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
5733 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
5734 DCI.RemoveFromWorklist(LD);
5742 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
5743 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
5744 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
5745 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
5746 SDValue Op0 = N->getOperand(0);
5747 SDValue Op1 = N->getOperand(1);
5748 if (Op0.getOpcode() == ISD::BITCAST)
5749 Op0 = Op0.getOperand(0);
5750 if (Op1.getOpcode() == ISD::BITCAST)
5751 Op1 = Op1.getOperand(0);
5752 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
5753 Op0.getNode() == Op1.getNode() &&
5754 Op0.getResNo() == 0 && Op1.getResNo() == 1)
5755 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5756 N->getValueType(0), Op0.getOperand(0));
5760 /// PerformSTORECombine - Target-specific dag combine xforms for
5762 static SDValue PerformSTORECombine(SDNode *N,
5763 TargetLowering::DAGCombinerInfo &DCI) {
5764 // Bitcast an i64 store extracted from a vector to f64.
5765 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5766 StoreSDNode *St = cast<StoreSDNode>(N);
5767 SDValue StVal = St->getValue();
5768 if (!ISD::isNormalStore(St) || St->isVolatile())
5771 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
5772 StVal.getNode()->hasOneUse() && !St->isVolatile()) {
5773 SelectionDAG &DAG = DCI.DAG;
5774 DebugLoc DL = St->getDebugLoc();
5775 SDValue BasePtr = St->getBasePtr();
5776 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
5777 StVal.getNode()->getOperand(0), BasePtr,
5778 St->getPointerInfo(), St->isVolatile(),
5779 St->isNonTemporal(), St->getAlignment());
5781 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
5782 DAG.getConstant(4, MVT::i32));
5783 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
5784 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
5785 St->isNonTemporal(),
5786 std::min(4U, St->getAlignment() / 2));
5789 if (StVal.getValueType() != MVT::i64 ||
5790 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5793 SelectionDAG &DAG = DCI.DAG;
5794 DebugLoc dl = StVal.getDebugLoc();
5795 SDValue IntVec = StVal.getOperand(0);
5796 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5797 IntVec.getValueType().getVectorNumElements());
5798 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
5799 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5800 Vec, StVal.getOperand(1));
5801 dl = N->getDebugLoc();
5802 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
5803 // Make the DAGCombiner fold the bitcasts.
5804 DCI.AddToWorklist(Vec.getNode());
5805 DCI.AddToWorklist(ExtElt.getNode());
5806 DCI.AddToWorklist(V.getNode());
5807 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
5808 St->getPointerInfo(), St->isVolatile(),
5809 St->isNonTemporal(), St->getAlignment(),
5813 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
5814 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
5815 /// i64 vector to have f64 elements, since the value can then be loaded
5816 /// directly into a VFP register.
5817 static bool hasNormalLoadOperand(SDNode *N) {
5818 unsigned NumElts = N->getValueType(0).getVectorNumElements();
5819 for (unsigned i = 0; i < NumElts; ++i) {
5820 SDNode *Elt = N->getOperand(i).getNode();
5821 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
5827 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
5828 /// ISD::BUILD_VECTOR.
5829 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
5830 TargetLowering::DAGCombinerInfo &DCI){
5831 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
5832 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
5833 // into a pair of GPRs, which is fine when the value is used as a scalar,
5834 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
5835 SelectionDAG &DAG = DCI.DAG;
5836 if (N->getNumOperands() == 2) {
5837 SDValue RV = PerformVMOVDRRCombine(N, DAG);
5842 // Load i64 elements as f64 values so that type legalization does not split
5843 // them up into i32 values.
5844 EVT VT = N->getValueType(0);
5845 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
5847 DebugLoc dl = N->getDebugLoc();
5848 SmallVector<SDValue, 8> Ops;
5849 unsigned NumElts = VT.getVectorNumElements();
5850 for (unsigned i = 0; i < NumElts; ++i) {
5851 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
5853 // Make the DAGCombiner fold the bitcast.
5854 DCI.AddToWorklist(V.getNode());
5856 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
5857 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
5858 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
5861 /// PerformInsertEltCombine - Target-specific dag combine xforms for
5862 /// ISD::INSERT_VECTOR_ELT.
5863 static SDValue PerformInsertEltCombine(SDNode *N,
5864 TargetLowering::DAGCombinerInfo &DCI) {
5865 // Bitcast an i64 load inserted into a vector to f64.
5866 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5867 EVT VT = N->getValueType(0);
5868 SDNode *Elt = N->getOperand(1).getNode();
5869 if (VT.getVectorElementType() != MVT::i64 ||
5870 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
5873 SelectionDAG &DAG = DCI.DAG;
5874 DebugLoc dl = N->getDebugLoc();
5875 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5876 VT.getVectorNumElements());
5877 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
5878 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
5879 // Make the DAGCombiner fold the bitcasts.
5880 DCI.AddToWorklist(Vec.getNode());
5881 DCI.AddToWorklist(V.getNode());
5882 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
5883 Vec, V, N->getOperand(2));
5884 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
5887 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
5888 /// ISD::VECTOR_SHUFFLE.
5889 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
5890 // The LLVM shufflevector instruction does not require the shuffle mask
5891 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
5892 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
5893 // operands do not match the mask length, they are extended by concatenating
5894 // them with undef vectors. That is probably the right thing for other
5895 // targets, but for NEON it is better to concatenate two double-register
5896 // size vector operands into a single quad-register size vector. Do that
5897 // transformation here:
5898 // shuffle(concat(v1, undef), concat(v2, undef)) ->
5899 // shuffle(concat(v1, v2), undef)
5900 SDValue Op0 = N->getOperand(0);
5901 SDValue Op1 = N->getOperand(1);
5902 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
5903 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
5904 Op0.getNumOperands() != 2 ||
5905 Op1.getNumOperands() != 2)
5907 SDValue Concat0Op1 = Op0.getOperand(1);
5908 SDValue Concat1Op1 = Op1.getOperand(1);
5909 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
5910 Concat1Op1.getOpcode() != ISD::UNDEF)
5912 // Skip the transformation if any of the types are illegal.
5913 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5914 EVT VT = N->getValueType(0);
5915 if (!TLI.isTypeLegal(VT) ||
5916 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
5917 !TLI.isTypeLegal(Concat1Op1.getValueType()))
5920 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
5921 Op0.getOperand(0), Op1.getOperand(0));
5922 // Translate the shuffle mask.
5923 SmallVector<int, 16> NewMask;
5924 unsigned NumElts = VT.getVectorNumElements();
5925 unsigned HalfElts = NumElts/2;
5926 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
5927 for (unsigned n = 0; n < NumElts; ++n) {
5928 int MaskElt = SVN->getMaskElt(n);
5930 if (MaskElt < (int)HalfElts)
5932 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
5933 NewElt = HalfElts + MaskElt - NumElts;
5934 NewMask.push_back(NewElt);
5936 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
5937 DAG.getUNDEF(VT), NewMask.data());
5940 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
5941 /// NEON load/store intrinsics to merge base address updates.
5942 static SDValue CombineBaseUpdate(SDNode *N,
5943 TargetLowering::DAGCombinerInfo &DCI) {
5944 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5947 SelectionDAG &DAG = DCI.DAG;
5948 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
5949 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
5950 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
5951 SDValue Addr = N->getOperand(AddrOpIdx);
5953 // Search for a use of the address operand that is an increment.
5954 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
5955 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
5957 if (User->getOpcode() != ISD::ADD ||
5958 UI.getUse().getResNo() != Addr.getResNo())
5961 // Check that the add is independent of the load/store. Otherwise, folding
5962 // it would create a cycle.
5963 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
5966 // Find the new opcode for the updating load/store.
5968 bool isLaneOp = false;
5969 unsigned NewOpc = 0;
5970 unsigned NumVecs = 0;
5972 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
5974 default: assert(0 && "unexpected intrinsic for Neon base update");
5975 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
5977 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
5979 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
5981 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
5983 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
5984 NumVecs = 2; isLaneOp = true; break;
5985 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
5986 NumVecs = 3; isLaneOp = true; break;
5987 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
5988 NumVecs = 4; isLaneOp = true; break;
5989 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
5990 NumVecs = 1; isLoad = false; break;
5991 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
5992 NumVecs = 2; isLoad = false; break;
5993 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
5994 NumVecs = 3; isLoad = false; break;
5995 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
5996 NumVecs = 4; isLoad = false; break;
5997 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
5998 NumVecs = 2; isLoad = false; isLaneOp = true; break;
5999 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
6000 NumVecs = 3; isLoad = false; isLaneOp = true; break;
6001 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
6002 NumVecs = 4; isLoad = false; isLaneOp = true; break;
6006 switch (N->getOpcode()) {
6007 default: assert(0 && "unexpected opcode for Neon base update");
6008 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
6009 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
6010 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
6014 // Find the size of memory referenced by the load/store.
6017 VecTy = N->getValueType(0);
6019 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
6020 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
6022 NumBytes /= VecTy.getVectorNumElements();
6024 // If the increment is a constant, it must match the memory ref size.
6025 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
6026 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
6027 uint64_t IncVal = CInc->getZExtValue();
6028 if (IncVal != NumBytes)
6030 } else if (NumBytes >= 3 * 16) {
6031 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
6032 // separate instructions that make it harder to use a non-constant update.
6036 // Create the new updating load/store node.
6038 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
6040 for (n = 0; n < NumResultVecs; ++n)
6042 Tys[n++] = MVT::i32;
6043 Tys[n] = MVT::Other;
6044 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
6045 SmallVector<SDValue, 8> Ops;
6046 Ops.push_back(N->getOperand(0)); // incoming chain
6047 Ops.push_back(N->getOperand(AddrOpIdx));
6049 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
6050 Ops.push_back(N->getOperand(i));
6052 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
6053 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
6054 Ops.data(), Ops.size(),
6055 MemInt->getMemoryVT(),
6056 MemInt->getMemOperand());
6059 std::vector<SDValue> NewResults;
6060 for (unsigned i = 0; i < NumResultVecs; ++i) {
6061 NewResults.push_back(SDValue(UpdN.getNode(), i));
6063 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
6064 DCI.CombineTo(N, NewResults);
6065 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
6072 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
6073 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
6074 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
6076 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
6077 SelectionDAG &DAG = DCI.DAG;
6078 EVT VT = N->getValueType(0);
6079 // vldN-dup instructions only support 64-bit vectors for N > 1.
6080 if (!VT.is64BitVector())
6083 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
6084 SDNode *VLD = N->getOperand(0).getNode();
6085 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
6087 unsigned NumVecs = 0;
6088 unsigned NewOpc = 0;
6089 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
6090 if (IntNo == Intrinsic::arm_neon_vld2lane) {
6092 NewOpc = ARMISD::VLD2DUP;
6093 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
6095 NewOpc = ARMISD::VLD3DUP;
6096 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
6098 NewOpc = ARMISD::VLD4DUP;
6103 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
6104 // numbers match the load.
6105 unsigned VLDLaneNo =
6106 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
6107 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6109 // Ignore uses of the chain result.
6110 if (UI.getUse().getResNo() == NumVecs)
6113 if (User->getOpcode() != ARMISD::VDUPLANE ||
6114 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
6118 // Create the vldN-dup node.
6121 for (n = 0; n < NumVecs; ++n)
6123 Tys[n] = MVT::Other;
6124 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
6125 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
6126 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
6127 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
6128 Ops, 2, VLDMemInt->getMemoryVT(),
6129 VLDMemInt->getMemOperand());
6132 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6134 unsigned ResNo = UI.getUse().getResNo();
6135 // Ignore uses of the chain result.
6136 if (ResNo == NumVecs)
6139 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
6142 // Now the vldN-lane intrinsic is dead except for its chain result.
6143 // Update uses of the chain.
6144 std::vector<SDValue> VLDDupResults;
6145 for (unsigned n = 0; n < NumVecs; ++n)
6146 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
6147 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
6148 DCI.CombineTo(VLD, VLDDupResults);
6153 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
6154 /// ARMISD::VDUPLANE.
6155 static SDValue PerformVDUPLANECombine(SDNode *N,
6156 TargetLowering::DAGCombinerInfo &DCI) {
6157 SDValue Op = N->getOperand(0);
6159 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
6160 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
6161 if (CombineVLDDUP(N, DCI))
6162 return SDValue(N, 0);
6164 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
6165 // redundant. Ignore bit_converts for now; element sizes are checked below.
6166 while (Op.getOpcode() == ISD::BITCAST)
6167 Op = Op.getOperand(0);
6168 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
6171 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
6172 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
6173 // The canonical VMOV for a zero vector uses a 32-bit element size.
6174 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6176 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
6178 EVT VT = N->getValueType(0);
6179 if (EltSize > VT.getVectorElementType().getSizeInBits())
6182 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
6185 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6186 /// operand of a vector shift operation, where all the elements of the
6187 /// build_vector must have the same constant integer value.
6188 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6189 // Ignore bit_converts.
6190 while (Op.getOpcode() == ISD::BITCAST)
6191 Op = Op.getOperand(0);
6192 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6193 APInt SplatBits, SplatUndef;
6194 unsigned SplatBitSize;
6196 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6197 HasAnyUndefs, ElementBits) ||
6198 SplatBitSize > ElementBits)
6200 Cnt = SplatBits.getSExtValue();
6204 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6205 /// operand of a vector shift left operation. That value must be in the range:
6206 /// 0 <= Value < ElementBits for a left shift; or
6207 /// 0 <= Value <= ElementBits for a long left shift.
6208 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6209 assert(VT.isVector() && "vector shift count is not a vector type");
6210 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6211 if (! getVShiftImm(Op, ElementBits, Cnt))
6213 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
6216 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6217 /// operand of a vector shift right operation. For a shift opcode, the value
6218 /// is positive, but for an intrinsic the value count must be negative. The
6219 /// absolute value must be in the range:
6220 /// 1 <= |Value| <= ElementBits for a right shift; or
6221 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6222 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6224 assert(VT.isVector() && "vector shift count is not a vector type");
6225 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6226 if (! getVShiftImm(Op, ElementBits, Cnt))
6230 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
6233 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
6234 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
6235 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
6238 // Don't do anything for most intrinsics.
6241 // Vector shifts: check for immediate versions and lower them.
6242 // Note: This is done during DAG combining instead of DAG legalizing because
6243 // the build_vectors for 64-bit vector element shift counts are generally
6244 // not legal, and it is hard to see their values after they get legalized to
6245 // loads from a constant pool.
6246 case Intrinsic::arm_neon_vshifts:
6247 case Intrinsic::arm_neon_vshiftu:
6248 case Intrinsic::arm_neon_vshiftls:
6249 case Intrinsic::arm_neon_vshiftlu:
6250 case Intrinsic::arm_neon_vshiftn:
6251 case Intrinsic::arm_neon_vrshifts:
6252 case Intrinsic::arm_neon_vrshiftu:
6253 case Intrinsic::arm_neon_vrshiftn:
6254 case Intrinsic::arm_neon_vqshifts:
6255 case Intrinsic::arm_neon_vqshiftu:
6256 case Intrinsic::arm_neon_vqshiftsu:
6257 case Intrinsic::arm_neon_vqshiftns:
6258 case Intrinsic::arm_neon_vqshiftnu:
6259 case Intrinsic::arm_neon_vqshiftnsu:
6260 case Intrinsic::arm_neon_vqrshiftns:
6261 case Intrinsic::arm_neon_vqrshiftnu:
6262 case Intrinsic::arm_neon_vqrshiftnsu: {
6263 EVT VT = N->getOperand(1).getValueType();
6265 unsigned VShiftOpc = 0;
6268 case Intrinsic::arm_neon_vshifts:
6269 case Intrinsic::arm_neon_vshiftu:
6270 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
6271 VShiftOpc = ARMISD::VSHL;
6274 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
6275 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
6276 ARMISD::VSHRs : ARMISD::VSHRu);
6281 case Intrinsic::arm_neon_vshiftls:
6282 case Intrinsic::arm_neon_vshiftlu:
6283 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
6285 llvm_unreachable("invalid shift count for vshll intrinsic");
6287 case Intrinsic::arm_neon_vrshifts:
6288 case Intrinsic::arm_neon_vrshiftu:
6289 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
6293 case Intrinsic::arm_neon_vqshifts:
6294 case Intrinsic::arm_neon_vqshiftu:
6295 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6299 case Intrinsic::arm_neon_vqshiftsu:
6300 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6302 llvm_unreachable("invalid shift count for vqshlu intrinsic");
6304 case Intrinsic::arm_neon_vshiftn:
6305 case Intrinsic::arm_neon_vrshiftn:
6306 case Intrinsic::arm_neon_vqshiftns:
6307 case Intrinsic::arm_neon_vqshiftnu:
6308 case Intrinsic::arm_neon_vqshiftnsu:
6309 case Intrinsic::arm_neon_vqrshiftns:
6310 case Intrinsic::arm_neon_vqrshiftnu:
6311 case Intrinsic::arm_neon_vqrshiftnsu:
6312 // Narrowing shifts require an immediate right shift.
6313 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
6315 llvm_unreachable("invalid shift count for narrowing vector shift "
6319 llvm_unreachable("unhandled vector shift");
6323 case Intrinsic::arm_neon_vshifts:
6324 case Intrinsic::arm_neon_vshiftu:
6325 // Opcode already set above.
6327 case Intrinsic::arm_neon_vshiftls:
6328 case Intrinsic::arm_neon_vshiftlu:
6329 if (Cnt == VT.getVectorElementType().getSizeInBits())
6330 VShiftOpc = ARMISD::VSHLLi;
6332 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
6333 ARMISD::VSHLLs : ARMISD::VSHLLu);
6335 case Intrinsic::arm_neon_vshiftn:
6336 VShiftOpc = ARMISD::VSHRN; break;
6337 case Intrinsic::arm_neon_vrshifts:
6338 VShiftOpc = ARMISD::VRSHRs; break;
6339 case Intrinsic::arm_neon_vrshiftu:
6340 VShiftOpc = ARMISD::VRSHRu; break;
6341 case Intrinsic::arm_neon_vrshiftn:
6342 VShiftOpc = ARMISD::VRSHRN; break;
6343 case Intrinsic::arm_neon_vqshifts:
6344 VShiftOpc = ARMISD::VQSHLs; break;
6345 case Intrinsic::arm_neon_vqshiftu:
6346 VShiftOpc = ARMISD::VQSHLu; break;
6347 case Intrinsic::arm_neon_vqshiftsu:
6348 VShiftOpc = ARMISD::VQSHLsu; break;
6349 case Intrinsic::arm_neon_vqshiftns:
6350 VShiftOpc = ARMISD::VQSHRNs; break;
6351 case Intrinsic::arm_neon_vqshiftnu:
6352 VShiftOpc = ARMISD::VQSHRNu; break;
6353 case Intrinsic::arm_neon_vqshiftnsu:
6354 VShiftOpc = ARMISD::VQSHRNsu; break;
6355 case Intrinsic::arm_neon_vqrshiftns:
6356 VShiftOpc = ARMISD::VQRSHRNs; break;
6357 case Intrinsic::arm_neon_vqrshiftnu:
6358 VShiftOpc = ARMISD::VQRSHRNu; break;
6359 case Intrinsic::arm_neon_vqrshiftnsu:
6360 VShiftOpc = ARMISD::VQRSHRNsu; break;
6363 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6364 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
6367 case Intrinsic::arm_neon_vshiftins: {
6368 EVT VT = N->getOperand(1).getValueType();
6370 unsigned VShiftOpc = 0;
6372 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
6373 VShiftOpc = ARMISD::VSLI;
6374 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
6375 VShiftOpc = ARMISD::VSRI;
6377 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
6380 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6381 N->getOperand(1), N->getOperand(2),
6382 DAG.getConstant(Cnt, MVT::i32));
6385 case Intrinsic::arm_neon_vqrshifts:
6386 case Intrinsic::arm_neon_vqrshiftu:
6387 // No immediate versions of these to check for.
6394 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
6395 /// lowers them. As with the vector shift intrinsics, this is done during DAG
6396 /// combining instead of DAG legalizing because the build_vectors for 64-bit
6397 /// vector element shift counts are generally not legal, and it is hard to see
6398 /// their values after they get legalized to loads from a constant pool.
6399 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
6400 const ARMSubtarget *ST) {
6401 EVT VT = N->getValueType(0);
6403 // Nothing to be done for scalar shifts.
6404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6405 if (!VT.isVector() || !TLI.isTypeLegal(VT))
6408 assert(ST->hasNEON() && "unexpected vector shift");
6411 switch (N->getOpcode()) {
6412 default: llvm_unreachable("unexpected shift opcode");
6415 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
6416 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
6417 DAG.getConstant(Cnt, MVT::i32));
6422 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
6423 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
6424 ARMISD::VSHRs : ARMISD::VSHRu);
6425 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
6426 DAG.getConstant(Cnt, MVT::i32));
6432 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
6433 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
6434 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
6435 const ARMSubtarget *ST) {
6436 SDValue N0 = N->getOperand(0);
6438 // Check for sign- and zero-extensions of vector extract operations of 8-
6439 // and 16-bit vector elements. NEON supports these directly. They are
6440 // handled during DAG combining because type legalization will promote them
6441 // to 32-bit types and it is messy to recognize the operations after that.
6442 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6443 SDValue Vec = N0.getOperand(0);
6444 SDValue Lane = N0.getOperand(1);
6445 EVT VT = N->getValueType(0);
6446 EVT EltVT = N0.getValueType();
6447 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6449 if (VT == MVT::i32 &&
6450 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
6451 TLI.isTypeLegal(Vec.getValueType()) &&
6452 isa<ConstantSDNode>(Lane)) {
6455 switch (N->getOpcode()) {
6456 default: llvm_unreachable("unexpected opcode");
6457 case ISD::SIGN_EXTEND:
6458 Opc = ARMISD::VGETLANEs;
6460 case ISD::ZERO_EXTEND:
6461 case ISD::ANY_EXTEND:
6462 Opc = ARMISD::VGETLANEu;
6465 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
6472 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
6473 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
6474 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
6475 const ARMSubtarget *ST) {
6476 // If the target supports NEON, try to use vmax/vmin instructions for f32
6477 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
6478 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
6479 // a NaN; only do the transformation when it matches that behavior.
6481 // For now only do this when using NEON for FP operations; if using VFP, it
6482 // is not obvious that the benefit outweighs the cost of switching to the
6484 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
6485 N->getValueType(0) != MVT::f32)
6488 SDValue CondLHS = N->getOperand(0);
6489 SDValue CondRHS = N->getOperand(1);
6490 SDValue LHS = N->getOperand(2);
6491 SDValue RHS = N->getOperand(3);
6492 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
6494 unsigned Opcode = 0;
6496 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
6497 IsReversed = false; // x CC y ? x : y
6498 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
6499 IsReversed = true ; // x CC y ? y : x
6513 // If LHS is NaN, an ordered comparison will be false and the result will
6514 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
6515 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6516 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
6517 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6519 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
6520 // will return -0, so vmin can only be used for unsafe math or if one of
6521 // the operands is known to be nonzero.
6522 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
6524 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6526 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
6535 // If LHS is NaN, an ordered comparison will be false and the result will
6536 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
6537 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6538 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
6539 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6541 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
6542 // will return +0, so vmax can only be used for unsafe math or if one of
6543 // the operands is known to be nonzero.
6544 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
6546 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6548 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
6554 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
6557 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
6558 DAGCombinerInfo &DCI) const {
6559 switch (N->getOpcode()) {
6561 case ISD::ADD: return PerformADDCombine(N, DCI);
6562 case ISD::SUB: return PerformSUBCombine(N, DCI);
6563 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
6564 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
6565 case ISD::AND: return PerformANDCombine(N, DCI);
6566 case ARMISD::BFI: return PerformBFICombine(N, DCI);
6567 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
6568 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
6569 case ISD::STORE: return PerformSTORECombine(N, DCI);
6570 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
6571 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
6572 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
6573 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
6574 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
6577 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
6578 case ISD::SIGN_EXTEND:
6579 case ISD::ZERO_EXTEND:
6580 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
6581 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
6582 case ARMISD::VLD2DUP:
6583 case ARMISD::VLD3DUP:
6584 case ARMISD::VLD4DUP:
6585 return CombineBaseUpdate(N, DCI);
6586 case ISD::INTRINSIC_VOID:
6587 case ISD::INTRINSIC_W_CHAIN:
6588 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
6589 case Intrinsic::arm_neon_vld1:
6590 case Intrinsic::arm_neon_vld2:
6591 case Intrinsic::arm_neon_vld3:
6592 case Intrinsic::arm_neon_vld4:
6593 case Intrinsic::arm_neon_vld2lane:
6594 case Intrinsic::arm_neon_vld3lane:
6595 case Intrinsic::arm_neon_vld4lane:
6596 case Intrinsic::arm_neon_vst1:
6597 case Intrinsic::arm_neon_vst2:
6598 case Intrinsic::arm_neon_vst3:
6599 case Intrinsic::arm_neon_vst4:
6600 case Intrinsic::arm_neon_vst2lane:
6601 case Intrinsic::arm_neon_vst3lane:
6602 case Intrinsic::arm_neon_vst4lane:
6603 return CombineBaseUpdate(N, DCI);
6611 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
6613 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
6616 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
6617 if (!Subtarget->allowsUnalignedMem())
6620 switch (VT.getSimpleVT().SimpleTy) {
6627 // FIXME: VLD1 etc with standard alignment is legal.
6631 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
6636 switch (VT.getSimpleVT().SimpleTy) {
6637 default: return false;
6652 if ((V & (Scale - 1)) != 0)
6655 return V == (V & ((1LL << 5) - 1));
6658 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
6659 const ARMSubtarget *Subtarget) {
6666 switch (VT.getSimpleVT().SimpleTy) {
6667 default: return false;
6672 // + imm12 or - imm8
6674 return V == (V & ((1LL << 8) - 1));
6675 return V == (V & ((1LL << 12) - 1));
6678 // Same as ARM mode. FIXME: NEON?
6679 if (!Subtarget->hasVFP2())
6684 return V == (V & ((1LL << 8) - 1));
6688 /// isLegalAddressImmediate - Return true if the integer value can be used
6689 /// as the offset of the target addressing mode for load / store of the
6691 static bool isLegalAddressImmediate(int64_t V, EVT VT,
6692 const ARMSubtarget *Subtarget) {
6699 if (Subtarget->isThumb1Only())
6700 return isLegalT1AddressImmediate(V, VT);
6701 else if (Subtarget->isThumb2())
6702 return isLegalT2AddressImmediate(V, VT, Subtarget);
6707 switch (VT.getSimpleVT().SimpleTy) {
6708 default: return false;
6713 return V == (V & ((1LL << 12) - 1));
6716 return V == (V & ((1LL << 8) - 1));
6719 if (!Subtarget->hasVFP2()) // FIXME: NEON?
6724 return V == (V & ((1LL << 8) - 1));
6728 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
6730 int Scale = AM.Scale;
6734 switch (VT.getSimpleVT().SimpleTy) {
6735 default: return false;
6744 return Scale == 2 || Scale == 4 || Scale == 8;
6747 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6751 // Note, we allow "void" uses (basically, uses that aren't loads or
6752 // stores), because arm allows folding a scale into many arithmetic
6753 // operations. This should be made more precise and revisited later.
6755 // Allow r << imm, but the imm has to be a multiple of two.
6756 if (Scale & 1) return false;
6757 return isPowerOf2_32(Scale);
6761 /// isLegalAddressingMode - Return true if the addressing mode represented
6762 /// by AM is legal for this target, for a load/store of the specified type.
6763 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
6764 const Type *Ty) const {
6765 EVT VT = getValueType(Ty, true);
6766 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
6769 // Can never fold addr of global into load/store.
6774 case 0: // no scale reg, must be "r+i" or "r", or "i".
6777 if (Subtarget->isThumb1Only())
6781 // ARM doesn't support any R+R*scale+imm addr modes.
6788 if (Subtarget->isThumb2())
6789 return isLegalT2ScaledAddressingMode(AM, VT);
6791 int Scale = AM.Scale;
6792 switch (VT.getSimpleVT().SimpleTy) {
6793 default: return false;
6797 if (Scale < 0) Scale = -Scale;
6801 return isPowerOf2_32(Scale & ~1);
6805 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6810 // Note, we allow "void" uses (basically, uses that aren't loads or
6811 // stores), because arm allows folding a scale into many arithmetic
6812 // operations. This should be made more precise and revisited later.
6814 // Allow r << imm, but the imm has to be a multiple of two.
6815 if (Scale & 1) return false;
6816 return isPowerOf2_32(Scale);
6823 /// isLegalICmpImmediate - Return true if the specified immediate is legal
6824 /// icmp immediate, that is the target has icmp instructions which can compare
6825 /// a register against the immediate without having to materialize the
6826 /// immediate into a register.
6827 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
6828 if (!Subtarget->isThumb())
6829 return ARM_AM::getSOImmVal(Imm) != -1;
6830 if (Subtarget->isThumb2())
6831 return ARM_AM::getT2SOImmVal(Imm) != -1;
6832 return Imm >= 0 && Imm <= 255;
6835 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
6836 bool isSEXTLoad, SDValue &Base,
6837 SDValue &Offset, bool &isInc,
6838 SelectionDAG &DAG) {
6839 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
6842 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
6844 Base = Ptr->getOperand(0);
6845 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6846 int RHSC = (int)RHS->getZExtValue();
6847 if (RHSC < 0 && RHSC > -256) {
6848 assert(Ptr->getOpcode() == ISD::ADD);
6850 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6854 isInc = (Ptr->getOpcode() == ISD::ADD);
6855 Offset = Ptr->getOperand(1);
6857 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
6859 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6860 int RHSC = (int)RHS->getZExtValue();
6861 if (RHSC < 0 && RHSC > -0x1000) {
6862 assert(Ptr->getOpcode() == ISD::ADD);
6864 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6865 Base = Ptr->getOperand(0);
6870 if (Ptr->getOpcode() == ISD::ADD) {
6872 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
6873 if (ShOpcVal != ARM_AM::no_shift) {
6874 Base = Ptr->getOperand(1);
6875 Offset = Ptr->getOperand(0);
6877 Base = Ptr->getOperand(0);
6878 Offset = Ptr->getOperand(1);
6883 isInc = (Ptr->getOpcode() == ISD::ADD);
6884 Base = Ptr->getOperand(0);
6885 Offset = Ptr->getOperand(1);
6889 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
6893 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
6894 bool isSEXTLoad, SDValue &Base,
6895 SDValue &Offset, bool &isInc,
6896 SelectionDAG &DAG) {
6897 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
6900 Base = Ptr->getOperand(0);
6901 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6902 int RHSC = (int)RHS->getZExtValue();
6903 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
6904 assert(Ptr->getOpcode() == ISD::ADD);
6906 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6908 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
6909 isInc = Ptr->getOpcode() == ISD::ADD;
6910 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
6918 /// getPreIndexedAddressParts - returns true by value, base pointer and
6919 /// offset pointer and addressing mode by reference if the node's address
6920 /// can be legally represented as pre-indexed load / store address.
6922 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
6924 ISD::MemIndexedMode &AM,
6925 SelectionDAG &DAG) const {
6926 if (Subtarget->isThumb1Only())
6931 bool isSEXTLoad = false;
6932 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6933 Ptr = LD->getBasePtr();
6934 VT = LD->getMemoryVT();
6935 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
6936 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6937 Ptr = ST->getBasePtr();
6938 VT = ST->getMemoryVT();
6943 bool isLegal = false;
6944 if (Subtarget->isThumb2())
6945 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6946 Offset, isInc, DAG);
6948 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6949 Offset, isInc, DAG);
6953 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
6957 /// getPostIndexedAddressParts - returns true by value, base pointer and
6958 /// offset pointer and addressing mode by reference if this node can be
6959 /// combined with a load / store to form a post-indexed load / store.
6960 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
6963 ISD::MemIndexedMode &AM,
6964 SelectionDAG &DAG) const {
6965 if (Subtarget->isThumb1Only())
6970 bool isSEXTLoad = false;
6971 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6972 VT = LD->getMemoryVT();
6973 Ptr = LD->getBasePtr();
6974 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
6975 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6976 VT = ST->getMemoryVT();
6977 Ptr = ST->getBasePtr();
6982 bool isLegal = false;
6983 if (Subtarget->isThumb2())
6984 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6987 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6993 // Swap base ptr and offset to catch more post-index load / store when
6994 // it's legal. In Thumb2 mode, offset must be an immediate.
6995 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
6996 !Subtarget->isThumb2())
6997 std::swap(Base, Offset);
6999 // Post-indexed load / store update the base pointer.
7004 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
7008 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7012 const SelectionDAG &DAG,
7013 unsigned Depth) const {
7014 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
7015 switch (Op.getOpcode()) {
7017 case ARMISD::CMOV: {
7018 // Bits are known zero/one if known on the LHS and RHS.
7019 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
7020 if (KnownZero == 0 && KnownOne == 0) return;
7022 APInt KnownZeroRHS, KnownOneRHS;
7023 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
7024 KnownZeroRHS, KnownOneRHS, Depth+1);
7025 KnownZero &= KnownZeroRHS;
7026 KnownOne &= KnownOneRHS;
7032 //===----------------------------------------------------------------------===//
7033 // ARM Inline Assembly Support
7034 //===----------------------------------------------------------------------===//
7036 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
7037 // Looking for "rev" which is V6+.
7038 if (!Subtarget->hasV6Ops())
7041 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
7042 std::string AsmStr = IA->getAsmString();
7043 SmallVector<StringRef, 4> AsmPieces;
7044 SplitString(AsmStr, AsmPieces, ";\n");
7046 switch (AsmPieces.size()) {
7047 default: return false;
7049 AsmStr = AsmPieces[0];
7051 SplitString(AsmStr, AsmPieces, " \t,");
7054 if (AsmPieces.size() == 3 &&
7055 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
7056 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
7057 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
7058 if (Ty && Ty->getBitWidth() == 32)
7059 return IntrinsicLowering::LowerToByteSwap(CI);
7067 /// getConstraintType - Given a constraint letter, return the type of
7068 /// constraint it is for this target.
7069 ARMTargetLowering::ConstraintType
7070 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
7071 if (Constraint.size() == 1) {
7072 switch (Constraint[0]) {
7074 case 'l': return C_RegisterClass;
7075 case 'w': return C_RegisterClass;
7078 return TargetLowering::getConstraintType(Constraint);
7081 /// Examine constraint type and operand type and determine a weight value.
7082 /// This object must already have been set up with the operand type
7083 /// and the current alternative constraint selected.
7084 TargetLowering::ConstraintWeight
7085 ARMTargetLowering::getSingleConstraintMatchWeight(
7086 AsmOperandInfo &info, const char *constraint) const {
7087 ConstraintWeight weight = CW_Invalid;
7088 Value *CallOperandVal = info.CallOperandVal;
7089 // If we don't have a value, we can't do a match,
7090 // but allow it at the lowest weight.
7091 if (CallOperandVal == NULL)
7093 const Type *type = CallOperandVal->getType();
7094 // Look at the constraint type.
7095 switch (*constraint) {
7097 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7100 if (type->isIntegerTy()) {
7101 if (Subtarget->isThumb())
7102 weight = CW_SpecificReg;
7104 weight = CW_Register;
7108 if (type->isFloatingPointTy())
7109 weight = CW_Register;
7115 std::pair<unsigned, const TargetRegisterClass*>
7116 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7118 if (Constraint.size() == 1) {
7119 // GCC ARM Constraint Letters
7120 switch (Constraint[0]) {
7122 if (Subtarget->isThumb())
7123 return std::make_pair(0U, ARM::tGPRRegisterClass);
7125 return std::make_pair(0U, ARM::GPRRegisterClass);
7127 return std::make_pair(0U, ARM::GPRRegisterClass);
7130 return std::make_pair(0U, ARM::SPRRegisterClass);
7131 if (VT.getSizeInBits() == 64)
7132 return std::make_pair(0U, ARM::DPRRegisterClass);
7133 if (VT.getSizeInBits() == 128)
7134 return std::make_pair(0U, ARM::QPRRegisterClass);
7138 if (StringRef("{cc}").equals_lower(Constraint))
7139 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
7141 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7144 std::vector<unsigned> ARMTargetLowering::
7145 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7147 if (Constraint.size() != 1)
7148 return std::vector<unsigned>();
7150 switch (Constraint[0]) { // GCC ARM Constraint Letters
7153 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
7154 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
7157 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
7158 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
7159 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
7160 ARM::R12, ARM::LR, 0);
7163 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
7164 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
7165 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
7166 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
7167 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
7168 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
7169 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
7170 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
7171 if (VT.getSizeInBits() == 64)
7172 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
7173 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
7174 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
7175 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
7176 if (VT.getSizeInBits() == 128)
7177 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
7178 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
7182 return std::vector<unsigned>();
7185 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7186 /// vector. If it is invalid, don't add anything to Ops.
7187 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7189 std::vector<SDValue>&Ops,
7190 SelectionDAG &DAG) const {
7191 SDValue Result(0, 0);
7193 switch (Constraint) {
7195 case 'I': case 'J': case 'K': case 'L':
7196 case 'M': case 'N': case 'O':
7197 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
7201 int64_t CVal64 = C->getSExtValue();
7202 int CVal = (int) CVal64;
7203 // None of these constraints allow values larger than 32 bits. Check
7204 // that the value fits in an int.
7208 switch (Constraint) {
7210 if (Subtarget->isThumb1Only()) {
7211 // This must be a constant between 0 and 255, for ADD
7213 if (CVal >= 0 && CVal <= 255)
7215 } else if (Subtarget->isThumb2()) {
7216 // A constant that can be used as an immediate value in a
7217 // data-processing instruction.
7218 if (ARM_AM::getT2SOImmVal(CVal) != -1)
7221 // A constant that can be used as an immediate value in a
7222 // data-processing instruction.
7223 if (ARM_AM::getSOImmVal(CVal) != -1)
7229 if (Subtarget->isThumb()) { // FIXME thumb2
7230 // This must be a constant between -255 and -1, for negated ADD
7231 // immediates. This can be used in GCC with an "n" modifier that
7232 // prints the negated value, for use with SUB instructions. It is
7233 // not useful otherwise but is implemented for compatibility.
7234 if (CVal >= -255 && CVal <= -1)
7237 // This must be a constant between -4095 and 4095. It is not clear
7238 // what this constraint is intended for. Implemented for
7239 // compatibility with GCC.
7240 if (CVal >= -4095 && CVal <= 4095)
7246 if (Subtarget->isThumb1Only()) {
7247 // A 32-bit value where only one byte has a nonzero value. Exclude
7248 // zero to match GCC. This constraint is used by GCC internally for
7249 // constants that can be loaded with a move/shift combination.
7250 // It is not useful otherwise but is implemented for compatibility.
7251 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
7253 } else if (Subtarget->isThumb2()) {
7254 // A constant whose bitwise inverse can be used as an immediate
7255 // value in a data-processing instruction. This can be used in GCC
7256 // with a "B" modifier that prints the inverted value, for use with
7257 // BIC and MVN instructions. It is not useful otherwise but is
7258 // implemented for compatibility.
7259 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
7262 // A constant whose bitwise inverse can be used as an immediate
7263 // value in a data-processing instruction. This can be used in GCC
7264 // with a "B" modifier that prints the inverted value, for use with
7265 // BIC and MVN instructions. It is not useful otherwise but is
7266 // implemented for compatibility.
7267 if (ARM_AM::getSOImmVal(~CVal) != -1)
7273 if (Subtarget->isThumb1Only()) {
7274 // This must be a constant between -7 and 7,
7275 // for 3-operand ADD/SUB immediate instructions.
7276 if (CVal >= -7 && CVal < 7)
7278 } else if (Subtarget->isThumb2()) {
7279 // A constant whose negation can be used as an immediate value in a
7280 // data-processing instruction. This can be used in GCC with an "n"
7281 // modifier that prints the negated value, for use with SUB
7282 // instructions. It is not useful otherwise but is implemented for
7284 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
7287 // A constant whose negation can be used as an immediate value in a
7288 // data-processing instruction. This can be used in GCC with an "n"
7289 // modifier that prints the negated value, for use with SUB
7290 // instructions. It is not useful otherwise but is implemented for
7292 if (ARM_AM::getSOImmVal(-CVal) != -1)
7298 if (Subtarget->isThumb()) { // FIXME thumb2
7299 // This must be a multiple of 4 between 0 and 1020, for
7300 // ADD sp + immediate.
7301 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
7304 // A power of two or a constant between 0 and 32. This is used in
7305 // GCC for the shift amount on shifted register operands, but it is
7306 // useful in general for any shift amounts.
7307 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
7313 if (Subtarget->isThumb()) { // FIXME thumb2
7314 // This must be a constant between 0 and 31, for shift amounts.
7315 if (CVal >= 0 && CVal <= 31)
7321 if (Subtarget->isThumb()) { // FIXME thumb2
7322 // This must be a multiple of 4 between -508 and 508, for
7323 // ADD/SUB sp = sp + immediate.
7324 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
7329 Result = DAG.getTargetConstant(CVal, Op.getValueType());
7333 if (Result.getNode()) {
7334 Ops.push_back(Result);
7337 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7341 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7342 // The ARM target isn't yet aware of offsets.
7346 int ARM::getVFPf32Imm(const APFloat &FPImm) {
7347 APInt Imm = FPImm.bitcastToAPInt();
7348 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
7349 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
7350 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
7352 // We can handle 4 bits of mantissa.
7353 // mantissa = (16+UInt(e:f:g:h))/16.
7354 if (Mantissa & 0x7ffff)
7357 if ((Mantissa & 0xf) != Mantissa)
7360 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7361 if (Exp < -3 || Exp > 4)
7363 Exp = ((Exp+3) & 0x7) ^ 4;
7365 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7368 int ARM::getVFPf64Imm(const APFloat &FPImm) {
7369 APInt Imm = FPImm.bitcastToAPInt();
7370 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
7371 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
7372 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
7374 // We can handle 4 bits of mantissa.
7375 // mantissa = (16+UInt(e:f:g:h))/16.
7376 if (Mantissa & 0xffffffffffffLL)
7379 if ((Mantissa & 0xf) != Mantissa)
7382 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7383 if (Exp < -3 || Exp > 4)
7385 Exp = ((Exp+3) & 0x7) ^ 4;
7387 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7390 bool ARM::isBitFieldInvertedMask(unsigned v) {
7391 if (v == 0xffffffff)
7393 // there can be 1's on either or both "outsides", all the "inside"
7395 unsigned int lsb = 0, msb = 31;
7396 while (v & (1 << msb)) --msb;
7397 while (v & (1 << lsb)) ++lsb;
7398 for (unsigned int i = lsb; i <= msb; ++i) {
7405 /// isFPImmLegal - Returns true if the target can instruction select the
7406 /// specified FP immediate natively. If false, the legalizer will
7407 /// materialize the FP immediate as a load from a constant pool.
7408 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
7409 if (!Subtarget->hasVFP3())
7412 return ARM::getVFPf32Imm(Imm) != -1;
7414 return ARM::getVFPf64Imm(Imm) != -1;
7418 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
7419 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
7420 /// specified in the intrinsic calls.
7421 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
7423 unsigned Intrinsic) const {
7424 switch (Intrinsic) {
7425 case Intrinsic::arm_neon_vld1:
7426 case Intrinsic::arm_neon_vld2:
7427 case Intrinsic::arm_neon_vld3:
7428 case Intrinsic::arm_neon_vld4:
7429 case Intrinsic::arm_neon_vld2lane:
7430 case Intrinsic::arm_neon_vld3lane:
7431 case Intrinsic::arm_neon_vld4lane: {
7432 Info.opc = ISD::INTRINSIC_W_CHAIN;
7433 // Conservatively set memVT to the entire set of vectors loaded.
7434 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
7435 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7436 Info.ptrVal = I.getArgOperand(0);
7438 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7439 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7440 Info.vol = false; // volatile loads with NEON intrinsics not supported
7441 Info.readMem = true;
7442 Info.writeMem = false;
7445 case Intrinsic::arm_neon_vst1:
7446 case Intrinsic::arm_neon_vst2:
7447 case Intrinsic::arm_neon_vst3:
7448 case Intrinsic::arm_neon_vst4:
7449 case Intrinsic::arm_neon_vst2lane:
7450 case Intrinsic::arm_neon_vst3lane:
7451 case Intrinsic::arm_neon_vst4lane: {
7452 Info.opc = ISD::INTRINSIC_VOID;
7453 // Conservatively set memVT to the entire set of vectors stored.
7454 unsigned NumElts = 0;
7455 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
7456 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
7457 if (!ArgTy->isVectorTy())
7459 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
7461 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7462 Info.ptrVal = I.getArgOperand(0);
7464 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7465 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7466 Info.vol = false; // volatile stores with NEON intrinsics not supported
7467 Info.readMem = false;
7468 Info.writeMem = true;