1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Instruction.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/ADT/VectorExtras.h"
36 #include "llvm/Support/MathExtras.h"
39 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
40 : TargetLowering(TM), ARMPCLabelIndex(0) {
41 Subtarget = &TM.getSubtarget<ARMSubtarget>();
43 if (Subtarget->isTargetDarwin()) {
45 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL);
46 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL);
48 // Uses VFP for Thumb libfuncs if available.
49 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
50 // Single-precision floating-point arithmetic.
51 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
52 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
53 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
54 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
56 // Double-precision floating-point arithmetic.
57 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
58 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
59 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
60 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
62 // Single-precision comparisons.
63 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
64 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
65 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
66 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
67 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
68 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
69 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
70 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
72 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
73 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
74 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
75 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
76 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
77 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
78 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
79 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
81 // Double-precision comparisons.
82 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
83 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
84 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
85 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
86 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
87 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
88 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
89 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
91 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
95 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
96 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
97 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
98 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
100 // Floating-point to integer conversions.
101 // i64 conversions are done via library routines even when generating VFP
102 // instructions, so use the same ones.
103 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
104 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
105 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
106 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
108 // Conversions between floating types.
109 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
110 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
112 // Integer to floating-point conversions.
113 // i64 conversions are done via library routines even when generating VFP
114 // instructions, so use the same ones.
115 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
116 // __floatunsidf vs. __floatunssidfvfp.
117 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
118 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
119 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
120 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
124 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
125 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
126 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
127 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
129 computeRegisterProperties();
131 // ARM does not have f32 extending load.
132 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
134 // ARM supports all 4 flavors of integer indexed load / store.
135 for (unsigned im = (unsigned)ISD::PRE_INC;
136 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
137 setIndexedLoadAction(im, MVT::i1, Legal);
138 setIndexedLoadAction(im, MVT::i8, Legal);
139 setIndexedLoadAction(im, MVT::i16, Legal);
140 setIndexedLoadAction(im, MVT::i32, Legal);
141 setIndexedStoreAction(im, MVT::i1, Legal);
142 setIndexedStoreAction(im, MVT::i8, Legal);
143 setIndexedStoreAction(im, MVT::i16, Legal);
144 setIndexedStoreAction(im, MVT::i32, Legal);
147 // i64 operation support.
148 if (Subtarget->isThumb()) {
149 setOperationAction(ISD::MUL, MVT::i64, Expand);
150 setOperationAction(ISD::MULHU, MVT::i32, Expand);
151 setOperationAction(ISD::MULHS, MVT::i32, Expand);
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::MUL, MVT::i64, Expand);
156 setOperationAction(ISD::MULHU, MVT::i32, Expand);
157 if (!Subtarget->hasV6Ops())
158 setOperationAction(ISD::MULHS, MVT::i32, Expand);
160 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
161 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
162 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
163 setOperationAction(ISD::SRL, MVT::i64, Custom);
164 setOperationAction(ISD::SRA, MVT::i64, Custom);
166 // ARM does not have ROTL.
167 setOperationAction(ISD::ROTL, MVT::i32, Expand);
168 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
169 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
170 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
171 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
173 // Only ARMv6 has BSWAP.
174 if (!Subtarget->hasV6Ops())
175 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
177 // These are expanded into libcalls.
178 setOperationAction(ISD::SDIV, MVT::i32, Expand);
179 setOperationAction(ISD::UDIV, MVT::i32, Expand);
180 setOperationAction(ISD::SREM, MVT::i32, Expand);
181 setOperationAction(ISD::UREM, MVT::i32, Expand);
182 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
183 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
185 // Support label based line numbers.
186 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
187 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
189 setOperationAction(ISD::RET, MVT::Other, Custom);
190 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
191 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
192 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
193 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
195 // Expand mem operations genericly.
196 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
197 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
198 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
200 // Use the default implementation.
201 setOperationAction(ISD::VASTART , MVT::Other, Expand);
202 setOperationAction(ISD::VAARG , MVT::Other, Expand);
203 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
204 setOperationAction(ISD::VAEND , MVT::Other, Expand);
205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
209 if (!Subtarget->hasV6Ops()) {
210 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
215 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
216 // Turn f64->i64 into FMRRD iff target supports vfp2.
217 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
219 // We want to custom lower some of our intrinsics.
220 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
222 setOperationAction(ISD::SETCC , MVT::i32, Expand);
223 setOperationAction(ISD::SETCC , MVT::f32, Expand);
224 setOperationAction(ISD::SETCC , MVT::f64, Expand);
225 setOperationAction(ISD::SELECT , MVT::i32, Expand);
226 setOperationAction(ISD::SELECT , MVT::f32, Expand);
227 setOperationAction(ISD::SELECT , MVT::f64, Expand);
228 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
229 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
230 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
232 setOperationAction(ISD::BRCOND , MVT::Other, Expand);
233 setOperationAction(ISD::BR_CC , MVT::i32, Custom);
234 setOperationAction(ISD::BR_CC , MVT::f32, Custom);
235 setOperationAction(ISD::BR_CC , MVT::f64, Custom);
236 setOperationAction(ISD::BR_JT , MVT::Other, Custom);
238 setOperationAction(ISD::VASTART, MVT::Other, Custom);
239 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
240 setOperationAction(ISD::VAEND, MVT::Other, Expand);
241 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
242 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
244 // FP Constants can't be immediates.
245 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
246 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
248 // We don't support sin/cos/fmod/copysign/pow
249 setOperationAction(ISD::FSIN , MVT::f64, Expand);
250 setOperationAction(ISD::FSIN , MVT::f32, Expand);
251 setOperationAction(ISD::FCOS , MVT::f32, Expand);
252 setOperationAction(ISD::FCOS , MVT::f64, Expand);
253 setOperationAction(ISD::FREM , MVT::f64, Expand);
254 setOperationAction(ISD::FREM , MVT::f32, Expand);
255 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
256 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
257 setOperationAction(ISD::FPOW , MVT::f64, Expand);
258 setOperationAction(ISD::FPOW , MVT::f32, Expand);
260 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
261 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
262 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
263 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
264 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
266 // We have target-specific dag combine patterns for the following nodes:
267 // ARMISD::FMRRD - No need to call setTargetDAGCombine
269 setStackPointerRegisterToSaveRestore(ARM::SP);
270 setSchedulingPreference(SchedulingForRegPressure);
271 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
272 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
274 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
278 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
281 case ARMISD::Wrapper: return "ARMISD::Wrapper";
282 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
283 case ARMISD::CALL: return "ARMISD::CALL";
284 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
285 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
286 case ARMISD::tCALL: return "ARMISD::tCALL";
287 case ARMISD::BRCOND: return "ARMISD::BRCOND";
288 case ARMISD::BR_JT: return "ARMISD::BR_JT";
289 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
290 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
291 case ARMISD::CMP: return "ARMISD::CMP";
292 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
293 case ARMISD::CMPFP: return "ARMISD::CMPFP";
294 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
295 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
296 case ARMISD::CMOV: return "ARMISD::CMOV";
297 case ARMISD::CNEG: return "ARMISD::CNEG";
299 case ARMISD::FTOSI: return "ARMISD::FTOSI";
300 case ARMISD::FTOUI: return "ARMISD::FTOUI";
301 case ARMISD::SITOF: return "ARMISD::SITOF";
302 case ARMISD::UITOF: return "ARMISD::UITOF";
304 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
305 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
306 case ARMISD::RRX: return "ARMISD::RRX";
308 case ARMISD::FMRRD: return "ARMISD::FMRRD";
309 case ARMISD::FMDRR: return "ARMISD::FMDRR";
311 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
315 //===----------------------------------------------------------------------===//
317 //===----------------------------------------------------------------------===//
320 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
321 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
323 default: assert(0 && "Unknown condition code!");
324 case ISD::SETNE: return ARMCC::NE;
325 case ISD::SETEQ: return ARMCC::EQ;
326 case ISD::SETGT: return ARMCC::GT;
327 case ISD::SETGE: return ARMCC::GE;
328 case ISD::SETLT: return ARMCC::LT;
329 case ISD::SETLE: return ARMCC::LE;
330 case ISD::SETUGT: return ARMCC::HI;
331 case ISD::SETUGE: return ARMCC::HS;
332 case ISD::SETULT: return ARMCC::LO;
333 case ISD::SETULE: return ARMCC::LS;
337 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
338 /// returns true if the operands should be inverted to form the proper
340 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
341 ARMCC::CondCodes &CondCode2) {
343 CondCode2 = ARMCC::AL;
345 default: assert(0 && "Unknown FP condition!");
347 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
349 case ISD::SETOGT: CondCode = ARMCC::GT; break;
351 case ISD::SETOGE: CondCode = ARMCC::GE; break;
352 case ISD::SETOLT: CondCode = ARMCC::MI; break;
353 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
354 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
355 case ISD::SETO: CondCode = ARMCC::VC; break;
356 case ISD::SETUO: CondCode = ARMCC::VS; break;
357 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
358 case ISD::SETUGT: CondCode = ARMCC::HI; break;
359 case ISD::SETUGE: CondCode = ARMCC::PL; break;
361 case ISD::SETULT: CondCode = ARMCC::LT; break;
363 case ISD::SETULE: CondCode = ARMCC::LE; break;
365 case ISD::SETUNE: CondCode = ARMCC::NE; break;
371 HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
372 unsigned StackOffset, unsigned &NeededGPRs,
373 unsigned &NeededStackSize, unsigned &GPRPad,
374 unsigned &StackPad, unsigned Flags) {
379 unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs);
380 GPRPad = NumGPRs % ((align + 3)/4);
381 StackPad = StackOffset % align;
382 unsigned firstGPR = NumGPRs + GPRPad;
384 default: assert(0 && "Unhandled argument type!");
396 else if (firstGPR == 3) {
404 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
405 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
407 SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
408 MVT::ValueType RetVT= Op.Val->getValueType(0);
409 SDOperand Chain = Op.getOperand(0);
410 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
411 assert((CallConv == CallingConv::C ||
412 CallConv == CallingConv::Fast) && "unknown calling convention");
413 SDOperand Callee = Op.getOperand(4);
414 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
415 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
416 unsigned NumGPRs = 0; // GPRs used for parameter passing.
418 // Count how many bytes are to be pushed on the stack.
419 unsigned NumBytes = 0;
421 // Add up all the space actually used.
422 for (unsigned i = 0; i < NumOps; ++i) {
427 MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
428 unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
429 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
430 GPRPad, StackPad, Flags);
431 NumBytes += ObjSize + StackPad;
432 NumGPRs += ObjGPRs + GPRPad;
435 // Adjust the stack pointer for the new arguments...
436 // These operations are automatically eliminated by the prolog/epilog pass
437 Chain = DAG.getCALLSEQ_START(Chain,
438 DAG.getConstant(NumBytes, MVT::i32));
440 SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
442 static const unsigned GPRArgRegs[] = {
443 ARM::R0, ARM::R1, ARM::R2, ARM::R3
447 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
448 std::vector<SDOperand> MemOpChains;
449 for (unsigned i = 0; i != NumOps; ++i) {
450 SDOperand Arg = Op.getOperand(5+2*i);
451 unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
452 MVT::ValueType ArgVT = Arg.getValueType();
458 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
459 ObjSize, GPRPad, StackPad, Flags);
461 ArgOffset += StackPad;
464 default: assert(0 && "Unexpected ValueType for argument!");
466 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
469 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
470 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
473 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
474 DAG.getConstant(0, getPointerTy()));
475 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
476 DAG.getConstant(1, getPointerTy()));
477 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
479 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
481 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
482 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
483 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
488 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
489 DAG.getVTList(MVT::i32, MVT::i32),
491 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
493 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
496 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
497 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
498 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
505 assert(ObjSize != 0);
506 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
507 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
508 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
512 ArgOffset += ObjSize;
515 if (!MemOpChains.empty())
516 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
517 &MemOpChains[0], MemOpChains.size());
519 // Build a sequence of copy-to-reg nodes chained together with token chain
520 // and flag operands which copy the outgoing args into the appropriate regs.
522 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
523 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
525 InFlag = Chain.getValue(1);
528 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
529 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
530 // node so that legalize doesn't hack it.
531 bool isDirect = false;
532 bool isARMFunc = false;
533 bool isLocalARMFunc = false;
534 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
535 GlobalValue *GV = G->getGlobal();
537 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
538 GV->hasLinkOnceLinkage());
539 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
540 getTargetMachine().getRelocationModel() != Reloc::Static;
541 isARMFunc = !Subtarget->isThumb() || isStub;
542 // ARM call to a local ARM function is predicable.
543 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
544 // tBX takes a register source operand.
545 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
546 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
548 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
549 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
550 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
551 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
552 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
554 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
555 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
557 bool isStub = Subtarget->isTargetDarwin() &&
558 getTargetMachine().getRelocationModel() != Reloc::Static;
559 isARMFunc = !Subtarget->isThumb() || isStub;
560 // tBX takes a register source operand.
561 const char *Sym = S->getSymbol();
562 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
563 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
565 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
566 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
567 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
568 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
569 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
571 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
574 // FIXME: handle tail calls differently.
576 if (Subtarget->isThumb()) {
577 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
578 CallOpc = ARMISD::CALL_NOLINK;
580 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
582 CallOpc = (isDirect || Subtarget->hasV5TOps())
583 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
584 : ARMISD::CALL_NOLINK;
586 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
587 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
588 Chain = DAG.getCopyToReg(Chain, ARM::LR,
589 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
590 InFlag = Chain.getValue(1);
593 std::vector<MVT::ValueType> NodeTys;
594 NodeTys.push_back(MVT::Other); // Returns a chain
595 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
597 std::vector<SDOperand> Ops;
598 Ops.push_back(Chain);
599 Ops.push_back(Callee);
601 // Add argument registers to the end of the list so that they are known live
603 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
604 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
605 RegsToPass[i].second.getValueType()));
608 Ops.push_back(InFlag);
609 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
610 InFlag = Chain.getValue(1);
612 Chain = DAG.getCALLSEQ_END(Chain,
613 DAG.getConstant(NumBytes, MVT::i32),
614 DAG.getConstant(0, MVT::i32),
616 if (RetVT != MVT::Other)
617 InFlag = Chain.getValue(1);
619 std::vector<SDOperand> ResultVals;
622 // If the call has results, copy the values out of the ret val registers.
624 default: assert(0 && "Unexpected ret value!");
628 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
629 ResultVals.push_back(Chain.getValue(0));
630 if (Op.Val->getValueType(1) == MVT::i32) {
631 // Returns a i64 value.
632 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
633 Chain.getValue(2)).getValue(1);
634 ResultVals.push_back(Chain.getValue(0));
635 NodeTys.push_back(MVT::i32);
637 NodeTys.push_back(MVT::i32);
640 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
641 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
643 NodeTys.push_back(MVT::f32);
646 SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
647 SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
648 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
649 NodeTys.push_back(MVT::f64);
654 NodeTys.push_back(MVT::Other);
656 if (ResultVals.empty())
659 ResultVals.push_back(Chain);
660 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
662 return Res.getValue(Op.ResNo);
665 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
667 SDOperand Chain = Op.getOperand(0);
668 switch(Op.getNumOperands()) {
670 assert(0 && "Do not know how to return this many arguments!");
673 SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
674 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
677 Op = Op.getOperand(1);
678 if (Op.getValueType() == MVT::f32) {
679 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
680 } else if (Op.getValueType() == MVT::f64) {
681 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
683 Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
684 SDOperand Sign = DAG.getConstant(0, MVT::i32);
685 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
686 Op.getValue(1), Sign);
688 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
689 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
690 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
693 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
694 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
695 // If we haven't noted the R0+R1 are live out, do so now.
696 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
697 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
698 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
703 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
704 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
707 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
708 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
709 // one of the above mentioned nodes. It has to be wrapped because otherwise
710 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
711 // be used to form addressing mode. These wrapped nodes will be selected
713 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
714 MVT::ValueType PtrVT = Op.getValueType();
715 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
717 if (CP->isMachineConstantPoolEntry())
718 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
721 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
723 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
726 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
728 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
730 MVT::ValueType PtrVT = getPointerTy();
731 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
732 ARMConstantPoolValue *CPV =
733 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
734 PCAdj, "tlsgd", true);
735 SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
736 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
737 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
738 SDOperand Chain = Argument.getValue(1);
740 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
741 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
743 // call __tls_get_addr.
746 Entry.Node = Argument;
747 Entry.Ty = (const Type *) Type::Int32Ty;
748 Args.push_back(Entry);
749 std::pair<SDOperand, SDOperand> CallResult =
750 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false,
751 CallingConv::C, false,
752 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
753 return CallResult.first;
756 // Lower ISD::GlobalTLSAddress using the "initial exec" or
757 // "local exec" model.
759 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
761 GlobalValue *GV = GA->getGlobal();
763 SDOperand Chain = DAG.getEntryNode();
764 MVT::ValueType PtrVT = getPointerTy();
765 // Get the Thread Pointer
766 SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
768 if (GV->isDeclaration()){
769 // initial exec model
770 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
771 ARMConstantPoolValue *CPV =
772 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
773 PCAdj, "gottpoff", true);
774 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
775 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
776 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
777 Chain = Offset.getValue(1);
779 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
780 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
782 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
785 ARMConstantPoolValue *CPV =
786 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
787 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
788 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
789 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
792 // The address of the thread local variable is the add of the thread
793 // pointer with the offset of the variable.
794 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
798 ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
799 // TODO: implement the "local dynamic" model
800 assert(Subtarget->isTargetELF() &&
801 "TLS not implemented for non-ELF targets");
802 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
803 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
804 // otherwise use the "Local Exec" TLS Model
805 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
806 return LowerToTLSGeneralDynamicModel(GA, DAG);
808 return LowerToTLSExecModels(GA, DAG);
811 SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
813 MVT::ValueType PtrVT = getPointerTy();
814 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
815 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
816 if (RelocM == Reloc::PIC_) {
817 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
818 ARMConstantPoolValue *CPV =
819 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
820 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
821 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
822 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
823 SDOperand Chain = Result.getValue(1);
824 SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
825 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
827 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
830 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
831 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
832 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
836 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
837 /// even in non-static mode.
838 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
839 return RelocM != Reloc::Static &&
840 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
841 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode()));
844 SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
846 MVT::ValueType PtrVT = getPointerTy();
847 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
848 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
849 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
851 if (RelocM == Reloc::Static)
852 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
854 unsigned PCAdj = (RelocM != Reloc::PIC_)
855 ? 0 : (Subtarget->isThumb() ? 4 : 8);
856 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
858 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
860 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
862 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
864 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
865 SDOperand Chain = Result.getValue(1);
867 if (RelocM == Reloc::PIC_) {
868 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
869 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
872 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
877 SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
879 assert(Subtarget->isTargetELF() &&
880 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
881 MVT::ValueType PtrVT = getPointerTy();
882 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
883 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
885 ARMCP::CPValue, PCAdj);
886 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
887 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
888 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
889 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
890 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
893 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
894 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
895 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
897 default: return SDOperand(); // Don't custom lower most intrinsics.
898 case Intrinsic::arm_thread_pointer:
899 return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
903 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
904 unsigned VarArgsFrameIndex) {
905 // vastart just stores the address of the VarArgsFrameIndex slot into the
906 // memory location argument.
907 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
908 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
909 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
910 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
914 static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
915 unsigned *vRegs, unsigned ArgNo,
916 unsigned &NumGPRs, unsigned &ArgOffset) {
917 MachineFunction &MF = DAG.getMachineFunction();
918 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
919 SDOperand Root = Op.getOperand(0);
920 std::vector<SDOperand> ArgValues;
921 MachineRegisterInfo &RegInfo = MF.getRegInfo();
923 static const unsigned GPRArgRegs[] = {
924 ARM::R0, ARM::R1, ARM::R2, ARM::R3
931 unsigned Flags = Op.getConstantOperandVal(ArgNo + 3);
932 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
933 ObjSize, GPRPad, StackPad, Flags);
935 ArgOffset += StackPad;
939 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
940 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
941 vRegs[NumGPRs] = VReg;
942 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
943 if (ObjectVT == MVT::f32)
944 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
945 } else if (ObjGPRs == 2) {
946 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
947 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
948 vRegs[NumGPRs] = VReg;
949 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
951 VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
952 RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
953 vRegs[NumGPRs+1] = VReg;
954 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
956 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
957 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
962 // If the argument is actually used, emit a load from the right stack
964 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
965 MachineFrameInfo *MFI = MF.getFrameInfo();
966 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
967 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
969 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
971 SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
972 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
973 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
976 // Don't emit a dead load.
977 ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT);
980 ArgOffset += ObjSize; // Move on to the next argument.
987 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
988 std::vector<SDOperand> ArgValues;
989 SDOperand Root = Op.getOperand(0);
990 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
991 unsigned NumGPRs = 0; // GPRs used for parameter passing.
994 unsigned NumArgs = Op.Val->getNumValues()-1;
995 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
996 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo,
997 NumGPRs, ArgOffset));
999 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1001 static const unsigned GPRArgRegs[] = {
1002 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1005 MachineFunction &MF = DAG.getMachineFunction();
1006 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1007 MachineFrameInfo *MFI = MF.getFrameInfo();
1008 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1009 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1010 unsigned VARegSize = (4 - NumGPRs) * 4;
1011 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1012 if (VARegSaveSize) {
1013 // If this function is vararg, store any remaining integer argument regs
1014 // to their spots on the stack so that they may be loaded by deferencing
1015 // the result of va_next.
1016 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1017 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1018 VARegSaveSize - VARegSize);
1019 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1021 SmallVector<SDOperand, 4> MemOps;
1022 for (; NumGPRs < 4; ++NumGPRs) {
1023 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
1024 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
1025 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1026 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1027 MemOps.push_back(Store);
1028 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1029 DAG.getConstant(4, getPointerTy()));
1031 if (!MemOps.empty())
1032 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1033 &MemOps[0], MemOps.size());
1035 // This will point to the next argument passed via stack.
1036 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1039 ArgValues.push_back(Root);
1041 // Return the new list of results.
1042 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1043 Op.Val->value_end());
1044 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1047 /// isFloatingPointZero - Return true if this is +0.0.
1048 static bool isFloatingPointZero(SDOperand Op) {
1049 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1050 return CFP->getValueAPF().isPosZero();
1051 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
1052 // Maybe this has already been legalized into the constant pool?
1053 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1054 SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
1055 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1056 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1057 return CFP->getValueAPF().isPosZero();
1063 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1064 return ( isThumb && (C & ~255U) == 0) ||
1065 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1068 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1069 /// the given operands.
1070 static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
1071 SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
1072 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
1073 unsigned C = RHSC->getValue();
1074 if (!isLegalCmpImmediate(C, isThumb)) {
1075 // Constant does not fit, try adjusting it by one?
1080 if (isLegalCmpImmediate(C-1, isThumb)) {
1081 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1082 RHS = DAG.getConstant(C-1, MVT::i32);
1087 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1088 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1089 RHS = DAG.getConstant(C-1, MVT::i32);
1094 if (isLegalCmpImmediate(C+1, isThumb)) {
1095 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1096 RHS = DAG.getConstant(C+1, MVT::i32);
1101 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1102 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1103 RHS = DAG.getConstant(C+1, MVT::i32);
1110 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1111 ARMISD::NodeType CompareType;
1114 CompareType = ARMISD::CMP;
1120 // Uses only N and Z Flags
1121 CompareType = ARMISD::CMPNZ;
1124 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1125 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
1128 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1129 static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
1131 if (!isFloatingPointZero(RHS))
1132 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
1134 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
1135 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
1138 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
1139 const ARMSubtarget *ST) {
1140 MVT::ValueType VT = Op.getValueType();
1141 SDOperand LHS = Op.getOperand(0);
1142 SDOperand RHS = Op.getOperand(1);
1143 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1144 SDOperand TrueVal = Op.getOperand(2);
1145 SDOperand FalseVal = Op.getOperand(3);
1147 if (LHS.getValueType() == MVT::i32) {
1149 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1150 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1151 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
1154 ARMCC::CondCodes CondCode, CondCode2;
1155 if (FPCCToARMCC(CC, CondCode, CondCode2))
1156 std::swap(TrueVal, FalseVal);
1158 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1159 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1160 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1161 SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
1163 if (CondCode2 != ARMCC::AL) {
1164 SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1165 // FIXME: Needs another CMP because flag can have but one use.
1166 SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
1167 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
1172 static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
1173 const ARMSubtarget *ST) {
1174 SDOperand Chain = Op.getOperand(0);
1175 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1176 SDOperand LHS = Op.getOperand(2);
1177 SDOperand RHS = Op.getOperand(3);
1178 SDOperand Dest = Op.getOperand(4);
1180 if (LHS.getValueType() == MVT::i32) {
1182 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1183 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1184 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
1187 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1188 ARMCC::CondCodes CondCode, CondCode2;
1189 if (FPCCToARMCC(CC, CondCode, CondCode2))
1190 // Swap the LHS/RHS of the comparison if needed.
1191 std::swap(LHS, RHS);
1193 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1194 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1195 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1196 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1197 SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1198 SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1199 if (CondCode2 != ARMCC::AL) {
1200 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1201 SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1202 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1207 SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
1208 SDOperand Chain = Op.getOperand(0);
1209 SDOperand Table = Op.getOperand(1);
1210 SDOperand Index = Op.getOperand(2);
1212 MVT::ValueType PTy = getPointerTy();
1213 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1214 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1215 SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1216 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1217 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1218 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1219 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1220 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1221 Addr = DAG.getLoad(isPIC ? (MVT::ValueType)MVT::i32 : PTy,
1222 Chain, Addr, NULL, 0);
1223 Chain = Addr.getValue(1);
1225 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1226 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1229 static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
1231 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1232 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1233 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1236 static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1237 MVT::ValueType VT = Op.getValueType();
1239 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1241 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1242 return DAG.getNode(Opc, VT, Op);
1245 static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
1246 // Implement fcopysign with a fabs and a conditional fneg.
1247 SDOperand Tmp0 = Op.getOperand(0);
1248 SDOperand Tmp1 = Op.getOperand(1);
1249 MVT::ValueType VT = Op.getValueType();
1250 MVT::ValueType SrcVT = Tmp1.getValueType();
1251 SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1252 SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1253 SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1254 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1255 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1258 SDOperand ARMTargetLowering::LowerMEMCPYInline(SDOperand Chain,
1263 SelectionDAG &DAG) {
1264 // Do repeated 4-byte loads and stores. To be improved.
1265 assert((Align & 3) == 0 && "Expected 4-byte aligned addresses!");
1266 unsigned BytesLeft = Size & 3;
1267 unsigned NumMemOps = Size >> 2;
1268 unsigned EmittedNumMemOps = 0;
1269 unsigned SrcOff = 0, DstOff = 0;
1270 MVT::ValueType VT = MVT::i32;
1271 unsigned VTSize = 4;
1273 const unsigned MAX_LOADS_IN_LDM = 6;
1274 SDOperand TFOps[MAX_LOADS_IN_LDM];
1275 SDOperand Loads[MAX_LOADS_IN_LDM];
1277 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1278 // same number of stores. The loads and stores will get combined into
1279 // ldm/stm later on.
1280 while (EmittedNumMemOps < NumMemOps) {
1282 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1283 Loads[i] = DAG.getLoad(VT, Chain,
1284 DAG.getNode(ISD::ADD, MVT::i32, Source,
1285 DAG.getConstant(SrcOff, MVT::i32)),
1287 TFOps[i] = Loads[i].getValue(1);
1290 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1293 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1294 TFOps[i] = DAG.getStore(Chain, Loads[i],
1295 DAG.getNode(ISD::ADD, MVT::i32, Dest,
1296 DAG.getConstant(DstOff, MVT::i32)),
1300 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1302 EmittedNumMemOps += i;
1308 // Issue loads / stores for the trailing (1 - 3) bytes.
1309 unsigned BytesLeftSave = BytesLeft;
1312 if (BytesLeft >= 2) {
1320 Loads[i] = DAG.getLoad(VT, Chain,
1321 DAG.getNode(ISD::ADD, MVT::i32, Source,
1322 DAG.getConstant(SrcOff, MVT::i32)),
1324 TFOps[i] = Loads[i].getValue(1);
1327 BytesLeft -= VTSize;
1329 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1332 BytesLeft = BytesLeftSave;
1334 if (BytesLeft >= 2) {
1342 TFOps[i] = DAG.getStore(Chain, Loads[i],
1343 DAG.getNode(ISD::ADD, MVT::i32, Dest,
1344 DAG.getConstant(DstOff, MVT::i32)),
1348 BytesLeft -= VTSize;
1350 return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1353 static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1354 // Turn f64->i64 into FMRRD.
1355 assert(N->getValueType(0) == MVT::i64 &&
1356 N->getOperand(0).getValueType() == MVT::f64);
1358 SDOperand Op = N->getOperand(0);
1359 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1362 // Merge the pieces into a single i64 value.
1363 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).Val;
1366 static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1367 assert(N->getValueType(0) == MVT::i64 &&
1368 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1369 "Unknown shift to lower!");
1371 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1372 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1373 cast<ConstantSDNode>(N->getOperand(1))->getValue() != 1)
1376 // If we are in thumb mode, we don't have RRX.
1377 if (ST->isThumb()) return 0;
1379 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1380 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1381 DAG.getConstant(0, MVT::i32));
1382 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1383 DAG.getConstant(1, MVT::i32));
1385 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1386 // captures the result into a carry flag.
1387 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1388 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1390 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1391 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1393 // Merge the pieces into a single i64 value.
1394 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val;
1398 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1399 switch (Op.getOpcode()) {
1400 default: assert(0 && "Don't know how to custom lower this!"); abort();
1401 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1402 case ISD::GlobalAddress:
1403 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1404 LowerGlobalAddressELF(Op, DAG);
1405 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1406 case ISD::CALL: return LowerCALL(Op, DAG);
1407 case ISD::RET: return LowerRET(Op, DAG);
1408 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1409 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1410 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1411 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1412 case ISD::SINT_TO_FP:
1413 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1414 case ISD::FP_TO_SINT:
1415 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1416 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1417 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1418 case ISD::RETURNADDR: break;
1419 case ISD::FRAMEADDR: break;
1420 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1421 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
1422 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1425 // FIXME: Remove these when LegalizeDAGTypes lands.
1426 case ISD::BIT_CONVERT: return SDOperand(ExpandBIT_CONVERT(Op.Val, DAG), 0);
1428 case ISD::SRA: return SDOperand(ExpandSRx(Op.Val, DAG,Subtarget),0);
1434 /// ExpandOperationResult - Provide custom lowering hooks for expanding
1436 SDNode *ARMTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
1437 switch (N->getOpcode()) {
1438 default: assert(0 && "Don't know how to custom expand this!"); abort();
1439 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(N, DAG);
1441 case ISD::SRA: return ExpandSRx(N, DAG, Subtarget);
1446 //===----------------------------------------------------------------------===//
1447 // ARM Scheduler Hooks
1448 //===----------------------------------------------------------------------===//
1451 ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1452 MachineBasicBlock *BB) {
1453 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1454 switch (MI->getOpcode()) {
1455 default: assert(false && "Unexpected instr type to insert");
1456 case ARM::tMOVCCr: {
1457 // To "insert" a SELECT_CC instruction, we actually have to insert the
1458 // diamond control-flow pattern. The incoming instruction knows the
1459 // destination vreg to set, the condition code register to branch on, the
1460 // true/false values to select between, and a branch opcode to use.
1461 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1462 ilist<MachineBasicBlock>::iterator It = BB;
1468 // cmpTY ccX, r1, r2
1470 // fallthrough --> copy0MBB
1471 MachineBasicBlock *thisMBB = BB;
1472 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1473 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1474 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1475 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1476 MachineFunction *F = BB->getParent();
1477 F->getBasicBlockList().insert(It, copy0MBB);
1478 F->getBasicBlockList().insert(It, sinkMBB);
1479 // Update machine-CFG edges by first adding all successors of the current
1480 // block to the new block which will contain the Phi node for the select.
1481 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1482 e = BB->succ_end(); i != e; ++i)
1483 sinkMBB->addSuccessor(*i);
1484 // Next, remove all successors of the current block, and add the true
1485 // and fallthrough blocks as its successors.
1486 while(!BB->succ_empty())
1487 BB->removeSuccessor(BB->succ_begin());
1488 BB->addSuccessor(copy0MBB);
1489 BB->addSuccessor(sinkMBB);
1492 // %FalseValue = ...
1493 // # fallthrough to sinkMBB
1496 // Update machine-CFG edges
1497 BB->addSuccessor(sinkMBB);
1500 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1503 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1504 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1505 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1507 delete MI; // The pseudo instruction is gone now.
1513 //===----------------------------------------------------------------------===//
1514 // ARM Optimization Hooks
1515 //===----------------------------------------------------------------------===//
1517 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
1518 static SDOperand PerformFMRRDCombine(SDNode *N,
1519 TargetLowering::DAGCombinerInfo &DCI) {
1520 // fmrrd(fmdrr x, y) -> x,y
1521 SDOperand InDouble = N->getOperand(0);
1522 if (InDouble.getOpcode() == ARMISD::FMDRR)
1523 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
1527 SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N,
1528 DAGCombinerInfo &DCI) const {
1529 switch (N->getOpcode()) {
1531 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
1538 /// isLegalAddressImmediate - Return true if the integer value can be used
1539 /// as the offset of the target addressing mode for load / store of the
1541 static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
1542 const ARMSubtarget *Subtarget) {
1546 if (Subtarget->isThumb()) {
1552 default: return false;
1567 if ((V & (Scale - 1)) != 0)
1570 return V == V & ((1LL << 5) - 1);
1576 default: return false;
1581 return V == V & ((1LL << 12) - 1);
1584 return V == V & ((1LL << 8) - 1);
1587 if (!Subtarget->hasVFP2())
1592 return V == V & ((1LL << 8) - 1);
1596 /// isLegalAddressingMode - Return true if the addressing mode represented
1597 /// by AM is legal for this target, for a load/store of the specified type.
1598 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1599 const Type *Ty) const {
1600 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget))
1603 // Can never fold addr of global into load/store.
1608 case 0: // no scale reg, must be "r+i" or "r", or "i".
1611 if (Subtarget->isThumb())
1615 // ARM doesn't support any R+R*scale+imm addr modes.
1619 int Scale = AM.Scale;
1620 switch (getValueType(Ty)) {
1621 default: return false;
1626 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1627 // ldrd / strd are used, then its address mode is same as i16.
1629 if (Scale < 0) Scale = -Scale;
1633 return isPowerOf2_32(Scale & ~1);
1636 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1641 // Note, we allow "void" uses (basically, uses that aren't loads or
1642 // stores), because arm allows folding a scale into many arithmetic
1643 // operations. This should be made more precise and revisited later.
1645 // Allow r << imm, but the imm has to be a multiple of two.
1646 if (AM.Scale & 1) return false;
1647 return isPowerOf2_32(AM.Scale);
1655 static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
1656 bool isSEXTLoad, SDOperand &Base,
1657 SDOperand &Offset, bool &isInc,
1658 SelectionDAG &DAG) {
1659 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1662 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1664 Base = Ptr->getOperand(0);
1665 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1666 int RHSC = (int)RHS->getValue();
1667 if (RHSC < 0 && RHSC > -256) {
1669 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1673 isInc = (Ptr->getOpcode() == ISD::ADD);
1674 Offset = Ptr->getOperand(1);
1676 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1678 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1679 int RHSC = (int)RHS->getValue();
1680 if (RHSC < 0 && RHSC > -0x1000) {
1682 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1683 Base = Ptr->getOperand(0);
1688 if (Ptr->getOpcode() == ISD::ADD) {
1690 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1691 if (ShOpcVal != ARM_AM::no_shift) {
1692 Base = Ptr->getOperand(1);
1693 Offset = Ptr->getOperand(0);
1695 Base = Ptr->getOperand(0);
1696 Offset = Ptr->getOperand(1);
1701 isInc = (Ptr->getOpcode() == ISD::ADD);
1702 Base = Ptr->getOperand(0);
1703 Offset = Ptr->getOperand(1);
1707 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1711 /// getPreIndexedAddressParts - returns true by value, base pointer and
1712 /// offset pointer and addressing mode by reference if the node's address
1713 /// can be legally represented as pre-indexed load / store address.
1715 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1717 ISD::MemIndexedMode &AM,
1718 SelectionDAG &DAG) {
1719 if (Subtarget->isThumb())
1724 bool isSEXTLoad = false;
1725 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1726 Ptr = LD->getBasePtr();
1727 VT = LD->getLoadedVT();
1728 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1729 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1730 Ptr = ST->getBasePtr();
1731 VT = ST->getStoredVT();
1736 bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
1739 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1745 /// getPostIndexedAddressParts - returns true by value, base pointer and
1746 /// offset pointer and addressing mode by reference if this node can be
1747 /// combined with a load / store to form a post-indexed load / store.
1748 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1751 ISD::MemIndexedMode &AM,
1752 SelectionDAG &DAG) {
1753 if (Subtarget->isThumb())
1758 bool isSEXTLoad = false;
1759 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1760 VT = LD->getLoadedVT();
1761 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1762 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1763 VT = ST->getStoredVT();
1768 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1771 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1777 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1779 uint64_t &KnownZero,
1781 const SelectionDAG &DAG,
1782 unsigned Depth) const {
1785 switch (Op.getOpcode()) {
1787 case ARMISD::CMOV: {
1788 // Bits are known zero/one if known on the LHS and RHS.
1789 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1790 if (KnownZero == 0 && KnownOne == 0) return;
1792 uint64_t KnownZeroRHS, KnownOneRHS;
1793 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
1794 KnownZeroRHS, KnownOneRHS, Depth+1);
1795 KnownZero &= KnownZeroRHS;
1796 KnownOne &= KnownOneRHS;
1802 //===----------------------------------------------------------------------===//
1803 // ARM Inline Assembly Support
1804 //===----------------------------------------------------------------------===//
1806 /// getConstraintType - Given a constraint letter, return the type of
1807 /// constraint it is for this target.
1808 ARMTargetLowering::ConstraintType
1809 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
1810 if (Constraint.size() == 1) {
1811 switch (Constraint[0]) {
1813 case 'l': return C_RegisterClass;
1814 case 'w': return C_RegisterClass;
1817 return TargetLowering::getConstraintType(Constraint);
1820 std::pair<unsigned, const TargetRegisterClass*>
1821 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1822 MVT::ValueType VT) const {
1823 if (Constraint.size() == 1) {
1824 // GCC RS6000 Constraint Letters
1825 switch (Constraint[0]) {
1827 // FIXME: in thumb mode, 'l' is only low-regs.
1830 return std::make_pair(0U, ARM::GPRRegisterClass);
1833 return std::make_pair(0U, ARM::SPRRegisterClass);
1835 return std::make_pair(0U, ARM::DPRRegisterClass);
1839 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1842 std::vector<unsigned> ARMTargetLowering::
1843 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1844 MVT::ValueType VT) const {
1845 if (Constraint.size() != 1)
1846 return std::vector<unsigned>();
1848 switch (Constraint[0]) { // GCC ARM Constraint Letters
1852 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1853 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1854 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1855 ARM::R12, ARM::LR, 0);
1858 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1859 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1860 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1861 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
1862 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
1863 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
1864 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
1865 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
1867 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1868 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1869 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
1870 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
1874 return std::vector<unsigned>();