1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMCallingConv.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMPerfectShuffle.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/IR/IRBuilder.h"
41 #include "llvm/IR/Instruction.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/Type.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 #define DEBUG_TYPE "arm-isel"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
58 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions"),
66 ARMInterworking("arm-interworking", cl::Hidden,
67 cl::desc("Enable / disable ARM interworking (for debugging only)"),
71 class ARMCCState : public CCState {
73 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
74 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
76 : CCState(CC, isVarArg, MF, locs, C) {
77 assert(((PC == Call) || (PC == Prologue)) &&
78 "ARMCCState users must specify whether their context is call"
79 "or prologue generation.");
85 // The APCS parameter registers.
86 static const MCPhysReg GPRArgRegs[] = {
87 ARM::R0, ARM::R1, ARM::R2, ARM::R3
90 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
91 MVT PromotedBitwiseVT) {
92 if (VT != PromotedLdStVT) {
93 setOperationAction(ISD::LOAD, VT, Promote);
94 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
96 setOperationAction(ISD::STORE, VT, Promote);
97 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
100 MVT ElemTy = VT.getVectorElementType();
101 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
102 setOperationAction(ISD::SETCC, VT, Custom);
103 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
104 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
105 if (ElemTy == MVT::i32) {
106 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
107 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
108 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
109 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
111 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
112 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
113 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
114 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
116 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
117 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
118 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
119 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
120 setOperationAction(ISD::SELECT, VT, Expand);
121 setOperationAction(ISD::SELECT_CC, VT, Expand);
122 setOperationAction(ISD::VSELECT, VT, Expand);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
124 if (VT.isInteger()) {
125 setOperationAction(ISD::SHL, VT, Custom);
126 setOperationAction(ISD::SRA, VT, Custom);
127 setOperationAction(ISD::SRL, VT, Custom);
130 // Promote all bit-wise operations.
131 if (VT.isInteger() && VT != PromotedBitwiseVT) {
132 setOperationAction(ISD::AND, VT, Promote);
133 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
134 setOperationAction(ISD::OR, VT, Promote);
135 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
136 setOperationAction(ISD::XOR, VT, Promote);
137 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
140 // Neon does not support vector divide/remainder operations.
141 setOperationAction(ISD::SDIV, VT, Expand);
142 setOperationAction(ISD::UDIV, VT, Expand);
143 setOperationAction(ISD::FDIV, VT, Expand);
144 setOperationAction(ISD::SREM, VT, Expand);
145 setOperationAction(ISD::UREM, VT, Expand);
146 setOperationAction(ISD::FREM, VT, Expand);
149 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
150 addRegisterClass(VT, &ARM::DPRRegClass);
151 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
154 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
155 addRegisterClass(VT, &ARM::DPairRegClass);
156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
159 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM)
160 : TargetLowering(TM, TM.getObjFileLowering()) {
161 Subtarget = &TM.getSubtarget<ARMSubtarget>();
162 RegInfo = TM.getSubtargetImpl()->getRegisterInfo();
163 Itins = TM.getSubtargetImpl()->getInstrItineraryData();
165 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
167 if (Subtarget->isTargetMachO()) {
168 // Uses VFP for Thumb libfuncs if available.
169 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
170 Subtarget->hasARMOps() && !TM.Options.UseSoftFloat) {
171 // Single-precision floating-point arithmetic.
172 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
173 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
174 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
175 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
177 // Double-precision floating-point arithmetic.
178 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
179 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
180 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
181 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
183 // Single-precision comparisons.
184 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
185 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
186 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
187 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
188 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
189 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
190 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
191 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
193 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
194 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
195 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
202 // Double-precision comparisons.
203 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
204 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
205 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
206 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
207 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
208 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
209 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
210 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
212 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
221 // Floating-point to integer conversions.
222 // i64 conversions are done via library routines even when generating VFP
223 // instructions, so use the same ones.
224 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
225 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
226 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
227 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
229 // Conversions between floating types.
230 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
231 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
233 // Integer to floating-point conversions.
234 // i64 conversions are done via library routines even when generating VFP
235 // instructions, so use the same ones.
236 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
237 // e.g., __floatunsidf vs. __floatunssidfvfp.
238 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
239 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
240 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
241 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
245 // These libcalls are not available in 32-bit.
246 setLibcallName(RTLIB::SHL_I128, nullptr);
247 setLibcallName(RTLIB::SRL_I128, nullptr);
248 setLibcallName(RTLIB::SRA_I128, nullptr);
250 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
251 !Subtarget->isTargetWindows()) {
252 static const struct {
253 const RTLIB::Libcall Op;
254 const char * const Name;
255 const CallingConv::ID CC;
256 const ISD::CondCode Cond;
258 // Double-precision floating-point arithmetic helper functions
259 // RTABI chapter 4.1.2, Table 2
260 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
261 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
262 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
263 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
265 // Double-precision floating-point comparison helper functions
266 // RTABI chapter 4.1.2, Table 3
267 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
268 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
269 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
270 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
271 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
272 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
273 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
274 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
276 // Single-precision floating-point arithmetic helper functions
277 // RTABI chapter 4.1.2, Table 4
278 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
279 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
280 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
281 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
283 // Single-precision floating-point comparison helper functions
284 // RTABI chapter 4.1.2, Table 5
285 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
286 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
287 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
288 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
289 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
290 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
291 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
292 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
294 // Floating-point to integer conversions.
295 // RTABI chapter 4.1.2, Table 6
296 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
297 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
298 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
299 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
300 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
301 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
302 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
303 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
305 // Conversions between floating types.
306 // RTABI chapter 4.1.2, Table 7
307 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
308 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
309 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
311 // Integer to floating-point conversions.
312 // RTABI chapter 4.1.2, Table 8
313 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
314 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
315 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
316 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
317 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
318 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
319 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
320 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
322 // Long long helper functions
323 // RTABI chapter 4.2, Table 9
324 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
325 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
326 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
327 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
329 // Integer division functions
330 // RTABI chapter 4.3.1
331 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
333 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
334 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
335 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
336 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
337 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
338 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341 // RTABI chapter 4.3.4
342 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
343 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
344 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
347 for (const auto &LC : LibraryCalls) {
348 setLibcallName(LC.Op, LC.Name);
349 setLibcallCallingConv(LC.Op, LC.CC);
350 if (LC.Cond != ISD::SETCC_INVALID)
351 setCmpLibcallCC(LC.Op, LC.Cond);
355 if (Subtarget->isTargetWindows()) {
356 static const struct {
357 const RTLIB::Libcall Op;
358 const char * const Name;
359 const CallingConv::ID CC;
361 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
362 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
363 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
364 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
365 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
366 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
367 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
368 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
371 for (const auto &LC : LibraryCalls) {
372 setLibcallName(LC.Op, LC.Name);
373 setLibcallCallingConv(LC.Op, LC.CC);
377 // Use divmod compiler-rt calls for iOS 5.0 and later.
378 if (Subtarget->getTargetTriple().isiOS() &&
379 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
380 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
381 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
384 // The half <-> float conversion functions are always soft-float, but are
385 // needed for some targets which use a hard-float calling convention by
387 if (Subtarget->isAAPCS_ABI()) {
388 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
393 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
394 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
397 if (Subtarget->isThumb1Only())
398 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
400 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
401 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
402 !Subtarget->isThumb1Only()) {
403 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
404 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
407 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
408 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
409 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
410 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
411 setTruncStoreAction((MVT::SimpleValueType)VT,
412 (MVT::SimpleValueType)InnerVT, Expand);
413 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
414 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
415 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
417 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
418 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
419 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
420 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
422 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
425 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
426 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
428 if (Subtarget->hasNEON()) {
429 addDRTypeForNEON(MVT::v2f32);
430 addDRTypeForNEON(MVT::v8i8);
431 addDRTypeForNEON(MVT::v4i16);
432 addDRTypeForNEON(MVT::v2i32);
433 addDRTypeForNEON(MVT::v1i64);
435 addQRTypeForNEON(MVT::v4f32);
436 addQRTypeForNEON(MVT::v2f64);
437 addQRTypeForNEON(MVT::v16i8);
438 addQRTypeForNEON(MVT::v8i16);
439 addQRTypeForNEON(MVT::v4i32);
440 addQRTypeForNEON(MVT::v2i64);
442 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
443 // neither Neon nor VFP support any arithmetic operations on it.
444 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
445 // supported for v4f32.
446 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
447 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
448 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
449 // FIXME: Code duplication: FDIV and FREM are expanded always, see
450 // ARMTargetLowering::addTypeForNEON method for details.
451 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
452 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
453 // FIXME: Create unittest.
454 // In another words, find a way when "copysign" appears in DAG with vector
456 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
457 // FIXME: Code duplication: SETCC has custom operation action, see
458 // ARMTargetLowering::addTypeForNEON method for details.
459 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
460 // FIXME: Create unittest for FNEG and for FABS.
461 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
462 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
463 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
464 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
465 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
466 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
467 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
468 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
469 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
470 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
471 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
472 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
473 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
474 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
475 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
476 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
477 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
478 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
479 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
481 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
482 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
483 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
484 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
485 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
486 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
487 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
488 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
489 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
490 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
491 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
492 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
493 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
494 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
495 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
497 // Mark v2f32 intrinsics.
498 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
499 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
500 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
501 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
502 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
503 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
504 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
505 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
506 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
507 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
508 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
509 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
510 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
511 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
512 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
514 // Neon does not support some operations on v1i64 and v2i64 types.
515 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
516 // Custom handling for some quad-vector types to detect VMULL.
517 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
518 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
519 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
520 // Custom handling for some vector types to avoid expensive expansions
521 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
522 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
523 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
524 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
525 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
526 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
527 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
528 // a destination type that is wider than the source, and nor does
529 // it have a FP_TO_[SU]INT instruction with a narrower destination than
531 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
532 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
533 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
534 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
536 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
537 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
539 // NEON does not have single instruction CTPOP for vectors with element
540 // types wider than 8-bits. However, custom lowering can leverage the
541 // v8i8/v16i8 vcnt instruction.
542 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
543 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
544 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
545 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
547 // NEON only has FMA instructions as of VFP4.
548 if (!Subtarget->hasVFP4()) {
549 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
550 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
553 setTargetDAGCombine(ISD::INTRINSIC_VOID);
554 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
555 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
556 setTargetDAGCombine(ISD::SHL);
557 setTargetDAGCombine(ISD::SRL);
558 setTargetDAGCombine(ISD::SRA);
559 setTargetDAGCombine(ISD::SIGN_EXTEND);
560 setTargetDAGCombine(ISD::ZERO_EXTEND);
561 setTargetDAGCombine(ISD::ANY_EXTEND);
562 setTargetDAGCombine(ISD::SELECT_CC);
563 setTargetDAGCombine(ISD::BUILD_VECTOR);
564 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
565 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
566 setTargetDAGCombine(ISD::STORE);
567 setTargetDAGCombine(ISD::FP_TO_SINT);
568 setTargetDAGCombine(ISD::FP_TO_UINT);
569 setTargetDAGCombine(ISD::FDIV);
571 // It is legal to extload from v4i8 to v4i16 or v4i32.
572 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
573 MVT::v4i16, MVT::v2i16,
575 for (unsigned i = 0; i < 6; ++i) {
576 setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal);
577 setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal);
578 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal);
582 // ARM and Thumb2 support UMLAL/SMLAL.
583 if (!Subtarget->isThumb1Only())
584 setTargetDAGCombine(ISD::ADDC);
586 if (Subtarget->isFPOnlySP()) {
587 // When targetting a floating-point unit with only single-precision
588 // operations, f64 is legal for the few double-precision instructions which
589 // are present However, no double-precision operations other than moves,
590 // loads and stores are provided by the hardware.
591 setOperationAction(ISD::FADD, MVT::f64, Expand);
592 setOperationAction(ISD::FSUB, MVT::f64, Expand);
593 setOperationAction(ISD::FMUL, MVT::f64, Expand);
594 setOperationAction(ISD::FMA, MVT::f64, Expand);
595 setOperationAction(ISD::FDIV, MVT::f64, Expand);
596 setOperationAction(ISD::FREM, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
599 setOperationAction(ISD::FNEG, MVT::f64, Expand);
600 setOperationAction(ISD::FABS, MVT::f64, Expand);
601 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
602 setOperationAction(ISD::FSIN, MVT::f64, Expand);
603 setOperationAction(ISD::FCOS, MVT::f64, Expand);
604 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
605 setOperationAction(ISD::FPOW, MVT::f64, Expand);
606 setOperationAction(ISD::FLOG, MVT::f64, Expand);
607 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
608 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
609 setOperationAction(ISD::FEXP, MVT::f64, Expand);
610 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
611 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
612 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
613 setOperationAction(ISD::FRINT, MVT::f64, Expand);
614 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
615 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
616 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
617 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
620 computeRegisterProperties();
622 // ARM does not have floating-point extending loads.
623 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
624 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
626 // ... or truncating stores
627 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
628 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
629 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
631 // ARM does not have i1 sign extending load.
632 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
634 // ARM supports all 4 flavors of integer indexed load / store.
635 if (!Subtarget->isThumb1Only()) {
636 for (unsigned im = (unsigned)ISD::PRE_INC;
637 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
638 setIndexedLoadAction(im, MVT::i1, Legal);
639 setIndexedLoadAction(im, MVT::i8, Legal);
640 setIndexedLoadAction(im, MVT::i16, Legal);
641 setIndexedLoadAction(im, MVT::i32, Legal);
642 setIndexedStoreAction(im, MVT::i1, Legal);
643 setIndexedStoreAction(im, MVT::i8, Legal);
644 setIndexedStoreAction(im, MVT::i16, Legal);
645 setIndexedStoreAction(im, MVT::i32, Legal);
649 setOperationAction(ISD::SADDO, MVT::i32, Custom);
650 setOperationAction(ISD::UADDO, MVT::i32, Custom);
651 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
652 setOperationAction(ISD::USUBO, MVT::i32, Custom);
654 // i64 operation support.
655 setOperationAction(ISD::MUL, MVT::i64, Expand);
656 setOperationAction(ISD::MULHU, MVT::i32, Expand);
657 if (Subtarget->isThumb1Only()) {
658 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
659 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
661 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
662 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
663 setOperationAction(ISD::MULHS, MVT::i32, Expand);
665 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
666 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
667 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
668 setOperationAction(ISD::SRL, MVT::i64, Custom);
669 setOperationAction(ISD::SRA, MVT::i64, Custom);
671 if (!Subtarget->isThumb1Only()) {
672 // FIXME: We should do this for Thumb1 as well.
673 setOperationAction(ISD::ADDC, MVT::i32, Custom);
674 setOperationAction(ISD::ADDE, MVT::i32, Custom);
675 setOperationAction(ISD::SUBC, MVT::i32, Custom);
676 setOperationAction(ISD::SUBE, MVT::i32, Custom);
679 // ARM does not have ROTL.
680 setOperationAction(ISD::ROTL, MVT::i32, Expand);
681 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
682 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
683 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
684 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
686 // These just redirect to CTTZ and CTLZ on ARM.
687 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
688 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
690 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
692 // Only ARMv6 has BSWAP.
693 if (!Subtarget->hasV6Ops())
694 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
696 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
697 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
698 // These are expanded into libcalls if the cpu doesn't have HW divider.
699 setOperationAction(ISD::SDIV, MVT::i32, Expand);
700 setOperationAction(ISD::UDIV, MVT::i32, Expand);
703 // FIXME: Also set divmod for SREM on EABI
704 setOperationAction(ISD::SREM, MVT::i32, Expand);
705 setOperationAction(ISD::UREM, MVT::i32, Expand);
706 // Register based DivRem for AEABI (RTABI 4.2)
707 if (Subtarget->isTargetAEABI()) {
708 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
709 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
710 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
711 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
712 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
713 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
714 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
715 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
717 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
718 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
719 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
720 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
721 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
722 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
723 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
724 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
726 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
727 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
729 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
730 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
733 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
734 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
735 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
736 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
737 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
739 setOperationAction(ISD::TRAP, MVT::Other, Legal);
741 // Use the default implementation.
742 setOperationAction(ISD::VASTART, MVT::Other, Custom);
743 setOperationAction(ISD::VAARG, MVT::Other, Expand);
744 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
745 setOperationAction(ISD::VAEND, MVT::Other, Expand);
746 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
747 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
749 if (!Subtarget->isTargetMachO()) {
750 // Non-MachO platforms may return values in these registers via the
751 // personality function.
752 setExceptionPointerRegister(ARM::R0);
753 setExceptionSelectorRegister(ARM::R1);
756 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
757 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
759 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
761 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
762 // the default expansion. If we are targeting a single threaded system,
763 // then set them all for expand so we can lower them later into their
765 if (TM.Options.ThreadModel == ThreadModel::Single)
766 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
767 else if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
768 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
769 // to ldrex/strex loops already.
770 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
772 // On v8, we have particularly efficient implementations of atomic fences
773 // if they can be combined with nearby atomic loads and stores.
774 if (!Subtarget->hasV8Ops()) {
775 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
776 setInsertFencesForAtomic(true);
779 // If there's anything we can use as a barrier, go through custom lowering
781 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
782 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
784 // Set them all for expansion, which will force libcalls.
785 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
786 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
787 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
788 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
789 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
790 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
791 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
792 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
793 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
794 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
795 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
796 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
797 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
798 // Unordered/Monotonic case.
799 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
800 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
803 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
805 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
806 if (!Subtarget->hasV6Ops()) {
807 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
808 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
810 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
812 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
813 !Subtarget->isThumb1Only()) {
814 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
815 // iff target supports vfp2.
816 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
817 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
820 // We want to custom lower some of our intrinsics.
821 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
822 if (Subtarget->isTargetDarwin()) {
823 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
824 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
825 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
828 setOperationAction(ISD::SETCC, MVT::i32, Expand);
829 setOperationAction(ISD::SETCC, MVT::f32, Expand);
830 setOperationAction(ISD::SETCC, MVT::f64, Expand);
831 setOperationAction(ISD::SELECT, MVT::i32, Custom);
832 setOperationAction(ISD::SELECT, MVT::f32, Custom);
833 setOperationAction(ISD::SELECT, MVT::f64, Custom);
834 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
835 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
836 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
838 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
839 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
840 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
841 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
842 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
844 // We don't support sin/cos/fmod/copysign/pow
845 setOperationAction(ISD::FSIN, MVT::f64, Expand);
846 setOperationAction(ISD::FSIN, MVT::f32, Expand);
847 setOperationAction(ISD::FCOS, MVT::f32, Expand);
848 setOperationAction(ISD::FCOS, MVT::f64, Expand);
849 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
850 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
851 setOperationAction(ISD::FREM, MVT::f64, Expand);
852 setOperationAction(ISD::FREM, MVT::f32, Expand);
853 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
854 !Subtarget->isThumb1Only()) {
855 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
856 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
858 setOperationAction(ISD::FPOW, MVT::f64, Expand);
859 setOperationAction(ISD::FPOW, MVT::f32, Expand);
861 if (!Subtarget->hasVFP4()) {
862 setOperationAction(ISD::FMA, MVT::f64, Expand);
863 setOperationAction(ISD::FMA, MVT::f32, Expand);
866 // Various VFP goodness
867 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
868 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
869 if (Subtarget->hasVFP2()) {
870 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
871 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
872 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
873 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
876 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
877 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
878 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
879 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
882 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
883 if (!Subtarget->hasFP16()) {
884 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
885 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
889 // Combine sin / cos into one node or libcall if possible.
890 if (Subtarget->hasSinCos()) {
891 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
892 setLibcallName(RTLIB::SINCOS_F64, "sincos");
893 if (Subtarget->getTargetTriple().isiOS()) {
894 // For iOS, we don't want to the normal expansion of a libcall to
895 // sincos. We want to issue a libcall to __sincos_stret.
896 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
897 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
901 // FP-ARMv8 implements a lot of rounding-like FP operations.
902 if (Subtarget->hasFPARMv8()) {
903 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
904 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
905 setOperationAction(ISD::FROUND, MVT::f32, Legal);
906 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
907 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
908 setOperationAction(ISD::FRINT, MVT::f32, Legal);
909 if (!Subtarget->isFPOnlySP()) {
910 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
911 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
912 setOperationAction(ISD::FROUND, MVT::f64, Legal);
913 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
914 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
915 setOperationAction(ISD::FRINT, MVT::f64, Legal);
918 // We have target-specific dag combine patterns for the following nodes:
919 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
920 setTargetDAGCombine(ISD::ADD);
921 setTargetDAGCombine(ISD::SUB);
922 setTargetDAGCombine(ISD::MUL);
923 setTargetDAGCombine(ISD::AND);
924 setTargetDAGCombine(ISD::OR);
925 setTargetDAGCombine(ISD::XOR);
927 if (Subtarget->hasV6Ops())
928 setTargetDAGCombine(ISD::SRL);
930 setStackPointerRegisterToSaveRestore(ARM::SP);
932 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
933 !Subtarget->hasVFP2())
934 setSchedulingPreference(Sched::RegPressure);
936 setSchedulingPreference(Sched::Hybrid);
938 //// temporary - rewrite interface to use type
939 MaxStoresPerMemset = 8;
940 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
941 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
942 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
943 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
944 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
946 // On ARM arguments smaller than 4 bytes are extended, so all arguments
947 // are at least 4 bytes aligned.
948 setMinStackArgumentAlignment(4);
950 // Prefer likely predicted branches to selects on out-of-order cores.
951 PredictableSelectIsExpensive = Subtarget->isLikeA9();
953 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
956 // FIXME: It might make sense to define the representative register class as the
957 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
958 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
959 // SPR's representative would be DPR_VFP2. This should work well if register
960 // pressure tracking were modified such that a register use would increment the
961 // pressure of the register class's representative and all of it's super
962 // classes' representatives transitively. We have not implemented this because
963 // of the difficulty prior to coalescing of modeling operand register classes
964 // due to the common occurrence of cross class copies and subregister insertions
966 std::pair<const TargetRegisterClass*, uint8_t>
967 ARMTargetLowering::findRepresentativeClass(MVT VT) const{
968 const TargetRegisterClass *RRC = nullptr;
970 switch (VT.SimpleTy) {
972 return TargetLowering::findRepresentativeClass(VT);
973 // Use DPR as representative register class for all floating point
974 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
975 // the cost is 1 for both f32 and f64.
976 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
977 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
978 RRC = &ARM::DPRRegClass;
979 // When NEON is used for SP, only half of the register file is available
980 // because operations that define both SP and DP results will be constrained
981 // to the VFP2 class (D0-D15). We currently model this constraint prior to
982 // coalescing by double-counting the SP regs. See the FIXME above.
983 if (Subtarget->useNEONForSinglePrecisionFP())
986 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
987 case MVT::v4f32: case MVT::v2f64:
988 RRC = &ARM::DPRRegClass;
992 RRC = &ARM::DPRRegClass;
996 RRC = &ARM::DPRRegClass;
1000 return std::make_pair(RRC, Cost);
1003 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1005 default: return nullptr;
1006 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1007 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1008 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1009 case ARMISD::CALL: return "ARMISD::CALL";
1010 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1011 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1012 case ARMISD::tCALL: return "ARMISD::tCALL";
1013 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1014 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1015 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1016 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1017 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1018 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1019 case ARMISD::CMP: return "ARMISD::CMP";
1020 case ARMISD::CMN: return "ARMISD::CMN";
1021 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1022 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1023 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1024 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1025 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1027 case ARMISD::CMOV: return "ARMISD::CMOV";
1029 case ARMISD::RBIT: return "ARMISD::RBIT";
1031 case ARMISD::FTOSI: return "ARMISD::FTOSI";
1032 case ARMISD::FTOUI: return "ARMISD::FTOUI";
1033 case ARMISD::SITOF: return "ARMISD::SITOF";
1034 case ARMISD::UITOF: return "ARMISD::UITOF";
1036 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1037 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1038 case ARMISD::RRX: return "ARMISD::RRX";
1040 case ARMISD::ADDC: return "ARMISD::ADDC";
1041 case ARMISD::ADDE: return "ARMISD::ADDE";
1042 case ARMISD::SUBC: return "ARMISD::SUBC";
1043 case ARMISD::SUBE: return "ARMISD::SUBE";
1045 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1046 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1048 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1049 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
1051 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1053 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1055 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1057 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1059 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1061 case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1063 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1064 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1065 case ARMISD::VCGE: return "ARMISD::VCGE";
1066 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1067 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1068 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1069 case ARMISD::VCGT: return "ARMISD::VCGT";
1070 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1071 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1072 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1073 case ARMISD::VTST: return "ARMISD::VTST";
1075 case ARMISD::VSHL: return "ARMISD::VSHL";
1076 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1077 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1078 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1079 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1080 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1081 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1082 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1083 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1084 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1085 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1086 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1087 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1088 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1089 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1090 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1091 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1092 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1093 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1094 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1095 case ARMISD::VDUP: return "ARMISD::VDUP";
1096 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1097 case ARMISD::VEXT: return "ARMISD::VEXT";
1098 case ARMISD::VREV64: return "ARMISD::VREV64";
1099 case ARMISD::VREV32: return "ARMISD::VREV32";
1100 case ARMISD::VREV16: return "ARMISD::VREV16";
1101 case ARMISD::VZIP: return "ARMISD::VZIP";
1102 case ARMISD::VUZP: return "ARMISD::VUZP";
1103 case ARMISD::VTRN: return "ARMISD::VTRN";
1104 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1105 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1106 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1107 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1108 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1109 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1110 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1111 case ARMISD::FMAX: return "ARMISD::FMAX";
1112 case ARMISD::FMIN: return "ARMISD::FMIN";
1113 case ARMISD::VMAXNM: return "ARMISD::VMAX";
1114 case ARMISD::VMINNM: return "ARMISD::VMIN";
1115 case ARMISD::BFI: return "ARMISD::BFI";
1116 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1117 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1118 case ARMISD::VBSL: return "ARMISD::VBSL";
1119 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1120 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1121 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1122 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1123 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1124 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1125 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1126 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1127 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1128 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1129 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1130 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1131 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1132 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1133 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1134 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1135 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1136 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1137 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1138 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1142 EVT ARMTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1143 if (!VT.isVector()) return getPointerTy();
1144 return VT.changeVectorElementTypeToInteger();
1147 /// getRegClassFor - Return the register class that should be used for the
1148 /// specified value type.
1149 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1150 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1151 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1152 // load / store 4 to 8 consecutive D registers.
1153 if (Subtarget->hasNEON()) {
1154 if (VT == MVT::v4i64)
1155 return &ARM::QQPRRegClass;
1156 if (VT == MVT::v8i64)
1157 return &ARM::QQQQPRRegClass;
1159 return TargetLowering::getRegClassFor(VT);
1162 // Create a fast isel object.
1164 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1165 const TargetLibraryInfo *libInfo) const {
1166 return ARM::createFastISel(funcInfo, libInfo);
1169 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
1170 /// be used for loads / stores from the global.
1171 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1172 return (Subtarget->isThumb1Only() ? 127 : 4095);
1175 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1176 unsigned NumVals = N->getNumValues();
1178 return Sched::RegPressure;
1180 for (unsigned i = 0; i != NumVals; ++i) {
1181 EVT VT = N->getValueType(i);
1182 if (VT == MVT::Glue || VT == MVT::Other)
1184 if (VT.isFloatingPoint() || VT.isVector())
1188 if (!N->isMachineOpcode())
1189 return Sched::RegPressure;
1191 // Load are scheduled for latency even if there instruction itinerary
1192 // is not available.
1193 const TargetInstrInfo *TII =
1194 getTargetMachine().getSubtargetImpl()->getInstrInfo();
1195 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1197 if (MCID.getNumDefs() == 0)
1198 return Sched::RegPressure;
1199 if (!Itins->isEmpty() &&
1200 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1203 return Sched::RegPressure;
1206 //===----------------------------------------------------------------------===//
1208 //===----------------------------------------------------------------------===//
1210 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1211 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1213 default: llvm_unreachable("Unknown condition code!");
1214 case ISD::SETNE: return ARMCC::NE;
1215 case ISD::SETEQ: return ARMCC::EQ;
1216 case ISD::SETGT: return ARMCC::GT;
1217 case ISD::SETGE: return ARMCC::GE;
1218 case ISD::SETLT: return ARMCC::LT;
1219 case ISD::SETLE: return ARMCC::LE;
1220 case ISD::SETUGT: return ARMCC::HI;
1221 case ISD::SETUGE: return ARMCC::HS;
1222 case ISD::SETULT: return ARMCC::LO;
1223 case ISD::SETULE: return ARMCC::LS;
1227 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1228 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1229 ARMCC::CondCodes &CondCode2) {
1230 CondCode2 = ARMCC::AL;
1232 default: llvm_unreachable("Unknown FP condition!");
1234 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1236 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1238 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1239 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1240 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1241 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1242 case ISD::SETO: CondCode = ARMCC::VC; break;
1243 case ISD::SETUO: CondCode = ARMCC::VS; break;
1244 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1245 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1246 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1248 case ISD::SETULT: CondCode = ARMCC::LT; break;
1250 case ISD::SETULE: CondCode = ARMCC::LE; break;
1252 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1256 //===----------------------------------------------------------------------===//
1257 // Calling Convention Implementation
1258 //===----------------------------------------------------------------------===//
1260 #include "ARMGenCallingConv.inc"
1262 /// getEffectiveCallingConv - Get the effective calling convention, taking into
1263 /// account presence of floating point hardware and calling convention
1264 /// limitations, such as support for variadic functions.
1266 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1267 bool isVarArg) const {
1270 llvm_unreachable("Unsupported calling convention");
1271 case CallingConv::ARM_AAPCS:
1272 case CallingConv::ARM_APCS:
1273 case CallingConv::GHC:
1275 case CallingConv::ARM_AAPCS_VFP:
1276 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1277 case CallingConv::C:
1278 if (!Subtarget->isAAPCS_ABI())
1279 return CallingConv::ARM_APCS;
1280 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1281 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1283 return CallingConv::ARM_AAPCS_VFP;
1285 return CallingConv::ARM_AAPCS;
1286 case CallingConv::Fast:
1287 if (!Subtarget->isAAPCS_ABI()) {
1288 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1289 return CallingConv::Fast;
1290 return CallingConv::ARM_APCS;
1291 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1292 return CallingConv::ARM_AAPCS_VFP;
1294 return CallingConv::ARM_AAPCS;
1298 /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1299 /// CallingConvention.
1300 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1302 bool isVarArg) const {
1303 switch (getEffectiveCallingConv(CC, isVarArg)) {
1305 llvm_unreachable("Unsupported calling convention");
1306 case CallingConv::ARM_APCS:
1307 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1308 case CallingConv::ARM_AAPCS:
1309 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1310 case CallingConv::ARM_AAPCS_VFP:
1311 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1312 case CallingConv::Fast:
1313 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1314 case CallingConv::GHC:
1315 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1319 /// LowerCallResult - Lower the result values of a call into the
1320 /// appropriate copies out of appropriate physical registers.
1322 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1323 CallingConv::ID CallConv, bool isVarArg,
1324 const SmallVectorImpl<ISD::InputArg> &Ins,
1325 SDLoc dl, SelectionDAG &DAG,
1326 SmallVectorImpl<SDValue> &InVals,
1327 bool isThisReturn, SDValue ThisVal) const {
1329 // Assign locations to each value returned by this call.
1330 SmallVector<CCValAssign, 16> RVLocs;
1331 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1332 *DAG.getContext(), Call);
1333 CCInfo.AnalyzeCallResult(Ins,
1334 CCAssignFnForNode(CallConv, /* Return*/ true,
1337 // Copy all of the result registers out of their specified physreg.
1338 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1339 CCValAssign VA = RVLocs[i];
1341 // Pass 'this' value directly from the argument to return value, to avoid
1342 // reg unit interference
1343 if (i == 0 && isThisReturn) {
1344 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1345 "unexpected return calling convention register assignment");
1346 InVals.push_back(ThisVal);
1351 if (VA.needsCustom()) {
1352 // Handle f64 or half of a v2f64.
1353 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1355 Chain = Lo.getValue(1);
1356 InFlag = Lo.getValue(2);
1357 VA = RVLocs[++i]; // skip ahead to next loc
1358 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1360 Chain = Hi.getValue(1);
1361 InFlag = Hi.getValue(2);
1362 if (!Subtarget->isLittle())
1364 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1366 if (VA.getLocVT() == MVT::v2f64) {
1367 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1368 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1369 DAG.getConstant(0, MVT::i32));
1371 VA = RVLocs[++i]; // skip ahead to next loc
1372 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1373 Chain = Lo.getValue(1);
1374 InFlag = Lo.getValue(2);
1375 VA = RVLocs[++i]; // skip ahead to next loc
1376 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1377 Chain = Hi.getValue(1);
1378 InFlag = Hi.getValue(2);
1379 if (!Subtarget->isLittle())
1381 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1382 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1383 DAG.getConstant(1, MVT::i32));
1386 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1388 Chain = Val.getValue(1);
1389 InFlag = Val.getValue(2);
1392 switch (VA.getLocInfo()) {
1393 default: llvm_unreachable("Unknown loc info!");
1394 case CCValAssign::Full: break;
1395 case CCValAssign::BCvt:
1396 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1400 InVals.push_back(Val);
1406 /// LowerMemOpCallTo - Store the argument to the stack.
1408 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1409 SDValue StackPtr, SDValue Arg,
1410 SDLoc dl, SelectionDAG &DAG,
1411 const CCValAssign &VA,
1412 ISD::ArgFlagsTy Flags) const {
1413 unsigned LocMemOffset = VA.getLocMemOffset();
1414 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1415 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1416 return DAG.getStore(Chain, dl, Arg, PtrOff,
1417 MachinePointerInfo::getStack(LocMemOffset),
1421 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1422 SDValue Chain, SDValue &Arg,
1423 RegsToPassVector &RegsToPass,
1424 CCValAssign &VA, CCValAssign &NextVA,
1426 SmallVectorImpl<SDValue> &MemOpChains,
1427 ISD::ArgFlagsTy Flags) const {
1429 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1430 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1431 unsigned id = Subtarget->isLittle() ? 0 : 1;
1432 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1434 if (NextVA.isRegLoc())
1435 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1437 assert(NextVA.isMemLoc());
1438 if (!StackPtr.getNode())
1439 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1441 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1447 /// LowerCall - Lowering a call into a callseq_start <-
1448 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1451 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1452 SmallVectorImpl<SDValue> &InVals) const {
1453 SelectionDAG &DAG = CLI.DAG;
1455 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1456 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1457 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1458 SDValue Chain = CLI.Chain;
1459 SDValue Callee = CLI.Callee;
1460 bool &isTailCall = CLI.IsTailCall;
1461 CallingConv::ID CallConv = CLI.CallConv;
1462 bool doesNotRet = CLI.DoesNotReturn;
1463 bool isVarArg = CLI.IsVarArg;
1465 MachineFunction &MF = DAG.getMachineFunction();
1466 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1467 bool isThisReturn = false;
1468 bool isSibCall = false;
1470 // Disable tail calls if they're not supported.
1471 if (!Subtarget->supportsTailCall() || MF.getTarget().Options.DisableTailCalls)
1475 // Check if it's really possible to do a tail call.
1476 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1477 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1478 Outs, OutVals, Ins, DAG);
1479 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
1480 report_fatal_error("failed to perform tail call elimination on a call "
1481 "site marked musttail");
1482 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1483 // detected sibcalls.
1490 // Analyze operands of the call, assigning locations to each operand.
1491 SmallVector<CCValAssign, 16> ArgLocs;
1492 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1493 *DAG.getContext(), Call);
1494 CCInfo.AnalyzeCallOperands(Outs,
1495 CCAssignFnForNode(CallConv, /* Return*/ false,
1498 // Get a count of how many bytes are to be pushed on the stack.
1499 unsigned NumBytes = CCInfo.getNextStackOffset();
1501 // For tail calls, memory operands are available in our caller's stack.
1505 // Adjust the stack pointer for the new arguments...
1506 // These operations are automatically eliminated by the prolog/epilog pass
1508 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1511 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1513 RegsToPassVector RegsToPass;
1514 SmallVector<SDValue, 8> MemOpChains;
1516 // Walk the register/memloc assignments, inserting copies/loads. In the case
1517 // of tail call optimization, arguments are handled later.
1518 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1520 ++i, ++realArgIdx) {
1521 CCValAssign &VA = ArgLocs[i];
1522 SDValue Arg = OutVals[realArgIdx];
1523 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1524 bool isByVal = Flags.isByVal();
1526 // Promote the value if needed.
1527 switch (VA.getLocInfo()) {
1528 default: llvm_unreachable("Unknown loc info!");
1529 case CCValAssign::Full: break;
1530 case CCValAssign::SExt:
1531 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1533 case CCValAssign::ZExt:
1534 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1536 case CCValAssign::AExt:
1537 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1539 case CCValAssign::BCvt:
1540 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1544 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1545 if (VA.needsCustom()) {
1546 if (VA.getLocVT() == MVT::v2f64) {
1547 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1548 DAG.getConstant(0, MVT::i32));
1549 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1550 DAG.getConstant(1, MVT::i32));
1552 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1553 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1555 VA = ArgLocs[++i]; // skip ahead to next loc
1556 if (VA.isRegLoc()) {
1557 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1558 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1560 assert(VA.isMemLoc());
1562 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1563 dl, DAG, VA, Flags));
1566 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1567 StackPtr, MemOpChains, Flags);
1569 } else if (VA.isRegLoc()) {
1570 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1571 assert(VA.getLocVT() == MVT::i32 &&
1572 "unexpected calling convention register assignment");
1573 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1574 "unexpected use of 'returned'");
1575 isThisReturn = true;
1577 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1578 } else if (isByVal) {
1579 assert(VA.isMemLoc());
1580 unsigned offset = 0;
1582 // True if this byval aggregate will be split between registers
1584 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1585 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1587 if (CurByValIdx < ByValArgsCount) {
1589 unsigned RegBegin, RegEnd;
1590 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1592 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1594 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1595 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1596 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1597 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1598 MachinePointerInfo(),
1599 false, false, false,
1600 DAG.InferPtrAlignment(AddArg));
1601 MemOpChains.push_back(Load.getValue(1));
1602 RegsToPass.push_back(std::make_pair(j, Load));
1605 // If parameter size outsides register area, "offset" value
1606 // helps us to calculate stack slot for remained part properly.
1607 offset = RegEnd - RegBegin;
1609 CCInfo.nextInRegsParam();
1612 if (Flags.getByValSize() > 4*offset) {
1613 unsigned LocMemOffset = VA.getLocMemOffset();
1614 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1615 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1617 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1618 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1619 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1621 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1623 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1624 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1625 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1628 } else if (!isSibCall) {
1629 assert(VA.isMemLoc());
1631 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1632 dl, DAG, VA, Flags));
1636 if (!MemOpChains.empty())
1637 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1639 // Build a sequence of copy-to-reg nodes chained together with token chain
1640 // and flag operands which copy the outgoing args into the appropriate regs.
1642 // Tail call byval lowering might overwrite argument registers so in case of
1643 // tail call optimization the copies to registers are lowered later.
1645 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1646 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1647 RegsToPass[i].second, InFlag);
1648 InFlag = Chain.getValue(1);
1651 // For tail calls lower the arguments to the 'real' stack slot.
1653 // Force all the incoming stack arguments to be loaded from the stack
1654 // before any new outgoing arguments are stored to the stack, because the
1655 // outgoing stack slots may alias the incoming argument stack slots, and
1656 // the alias isn't otherwise explicit. This is slightly more conservative
1657 // than necessary, because it means that each store effectively depends
1658 // on every argument instead of just those arguments it would clobber.
1660 // Do not flag preceding copytoreg stuff together with the following stuff.
1662 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1663 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1664 RegsToPass[i].second, InFlag);
1665 InFlag = Chain.getValue(1);
1670 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1671 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1672 // node so that legalize doesn't hack it.
1673 bool isDirect = false;
1674 bool isARMFunc = false;
1675 bool isLocalARMFunc = false;
1676 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1678 if (EnableARMLongCalls) {
1679 assert((Subtarget->isTargetWindows() ||
1680 getTargetMachine().getRelocationModel() == Reloc::Static) &&
1681 "long-calls with non-static relocation model!");
1682 // Handle a global address or an external symbol. If it's not one of
1683 // those, the target's already in a register, so we don't need to do
1685 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1686 const GlobalValue *GV = G->getGlobal();
1687 // Create a constant pool entry for the callee address
1688 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1689 ARMConstantPoolValue *CPV =
1690 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1692 // Get the address of the callee into a register
1693 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1694 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1695 Callee = DAG.getLoad(getPointerTy(), dl,
1696 DAG.getEntryNode(), CPAddr,
1697 MachinePointerInfo::getConstantPool(),
1698 false, false, false, 0);
1699 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1700 const char *Sym = S->getSymbol();
1702 // Create a constant pool entry for the callee address
1703 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1704 ARMConstantPoolValue *CPV =
1705 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1706 ARMPCLabelIndex, 0);
1707 // Get the address of the callee into a register
1708 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1709 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1710 Callee = DAG.getLoad(getPointerTy(), dl,
1711 DAG.getEntryNode(), CPAddr,
1712 MachinePointerInfo::getConstantPool(),
1713 false, false, false, 0);
1715 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1716 const GlobalValue *GV = G->getGlobal();
1718 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1719 bool isStub = (isExt && Subtarget->isTargetMachO()) &&
1720 getTargetMachine().getRelocationModel() != Reloc::Static;
1721 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1722 // ARM call to a local ARM function is predicable.
1723 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1724 // tBX takes a register source operand.
1725 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1726 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1727 Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
1728 DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
1729 0, ARMII::MO_NONLAZY));
1730 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
1731 MachinePointerInfo::getGOT(), false, false, true, 0);
1732 } else if (Subtarget->isTargetCOFF()) {
1733 assert(Subtarget->isTargetWindows() &&
1734 "Windows is the only supported COFF target");
1735 unsigned TargetFlags = GV->hasDLLImportStorageClass()
1736 ? ARMII::MO_DLLIMPORT
1737 : ARMII::MO_NO_FLAG;
1738 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), /*Offset=*/0,
1740 if (GV->hasDLLImportStorageClass())
1741 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1742 DAG.getNode(ARMISD::Wrapper, dl, getPointerTy(),
1743 Callee), MachinePointerInfo::getGOT(),
1744 false, false, false, 0);
1746 // On ELF targets for PIC code, direct calls should go through the PLT
1747 unsigned OpFlags = 0;
1748 if (Subtarget->isTargetELF() &&
1749 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1750 OpFlags = ARMII::MO_PLT;
1751 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1753 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1755 bool isStub = Subtarget->isTargetMachO() &&
1756 getTargetMachine().getRelocationModel() != Reloc::Static;
1757 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1758 // tBX takes a register source operand.
1759 const char *Sym = S->getSymbol();
1760 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1761 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1762 ARMConstantPoolValue *CPV =
1763 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1764 ARMPCLabelIndex, 4);
1765 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1766 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1767 Callee = DAG.getLoad(getPointerTy(), dl,
1768 DAG.getEntryNode(), CPAddr,
1769 MachinePointerInfo::getConstantPool(),
1770 false, false, false, 0);
1771 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1772 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1773 getPointerTy(), Callee, PICLabel);
1775 unsigned OpFlags = 0;
1776 // On ELF targets for PIC code, direct calls should go through the PLT
1777 if (Subtarget->isTargetELF() &&
1778 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1779 OpFlags = ARMII::MO_PLT;
1780 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1784 // FIXME: handle tail calls differently.
1786 bool HasMinSizeAttr = MF.getFunction()->getAttributes().hasAttribute(
1787 AttributeSet::FunctionIndex, Attribute::MinSize);
1788 if (Subtarget->isThumb()) {
1789 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1790 CallOpc = ARMISD::CALL_NOLINK;
1792 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1794 if (!isDirect && !Subtarget->hasV5TOps())
1795 CallOpc = ARMISD::CALL_NOLINK;
1796 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1797 // Emit regular call when code size is the priority
1799 // "mov lr, pc; b _foo" to avoid confusing the RSP
1800 CallOpc = ARMISD::CALL_NOLINK;
1802 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1805 std::vector<SDValue> Ops;
1806 Ops.push_back(Chain);
1807 Ops.push_back(Callee);
1809 // Add argument registers to the end of the list so that they are known live
1811 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1812 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1813 RegsToPass[i].second.getValueType()));
1815 // Add a register mask operand representing the call-preserved registers.
1817 const uint32_t *Mask;
1818 const TargetRegisterInfo *TRI =
1819 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
1820 const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo*>(TRI);
1822 // For 'this' returns, use the R0-preserving mask if applicable
1823 Mask = ARI->getThisReturnPreservedMask(CallConv);
1825 // Set isThisReturn to false if the calling convention is not one that
1826 // allows 'returned' to be modeled in this way, so LowerCallResult does
1827 // not try to pass 'this' straight through
1828 isThisReturn = false;
1829 Mask = ARI->getCallPreservedMask(CallConv);
1832 Mask = ARI->getCallPreservedMask(CallConv);
1834 assert(Mask && "Missing call preserved mask for calling convention");
1835 Ops.push_back(DAG.getRegisterMask(Mask));
1838 if (InFlag.getNode())
1839 Ops.push_back(InFlag);
1841 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1843 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
1845 // Returns a chain and a flag for retval copy to use.
1846 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
1847 InFlag = Chain.getValue(1);
1849 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1850 DAG.getIntPtrConstant(0, true), InFlag, dl);
1852 InFlag = Chain.getValue(1);
1854 // Handle result values, copying them out of physregs into vregs that we
1856 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1857 InVals, isThisReturn,
1858 isThisReturn ? OutVals[0] : SDValue());
1861 /// HandleByVal - Every parameter *after* a byval parameter is passed
1862 /// on the stack. Remember the next parameter register to allocate,
1863 /// and then confiscate the rest of the parameter registers to insure
1866 ARMTargetLowering::HandleByVal(
1867 CCState *State, unsigned &size, unsigned Align) const {
1868 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1869 assert((State->getCallOrPrologue() == Prologue ||
1870 State->getCallOrPrologue() == Call) &&
1871 "unhandled ParmContext");
1873 if ((ARM::R0 <= reg) && (reg <= ARM::R3)) {
1874 if (Subtarget->isAAPCS_ABI() && Align > 4) {
1875 unsigned AlignInRegs = Align / 4;
1876 unsigned Waste = (ARM::R4 - reg) % AlignInRegs;
1877 for (unsigned i = 0; i < Waste; ++i)
1878 reg = State->AllocateReg(GPRArgRegs, 4);
1881 unsigned excess = 4 * (ARM::R4 - reg);
1883 // Special case when NSAA != SP and parameter size greater than size of
1884 // all remained GPR regs. In that case we can't split parameter, we must
1885 // send it to stack. We also must set NCRN to R4, so waste all
1886 // remained registers.
1887 const unsigned NSAAOffset = State->getNextStackOffset();
1888 if (Subtarget->isAAPCS_ABI() && NSAAOffset != 0 && size > excess) {
1889 while (State->AllocateReg(GPRArgRegs, 4))
1894 // First register for byval parameter is the first register that wasn't
1895 // allocated before this method call, so it would be "reg".
1896 // If parameter is small enough to be saved in range [reg, r4), then
1897 // the end (first after last) register would be reg + param-size-in-regs,
1898 // else parameter would be splitted between registers and stack,
1899 // end register would be r4 in this case.
1900 unsigned ByValRegBegin = reg;
1901 unsigned ByValRegEnd = (size < excess) ? reg + size/4 : (unsigned)ARM::R4;
1902 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1903 // Note, first register is allocated in the beginning of function already,
1904 // allocate remained amount of registers we need.
1905 for (unsigned i = reg+1; i != ByValRegEnd; ++i)
1906 State->AllocateReg(GPRArgRegs, 4);
1907 // A byval parameter that is split between registers and memory needs its
1908 // size truncated here.
1909 // In the case where the entire structure fits in registers, we set the
1910 // size in memory to zero.
1919 /// MatchingStackOffset - Return true if the given stack call argument is
1920 /// already available in the same position (relatively) of the caller's
1921 /// incoming argument stack.
1923 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1924 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1925 const TargetInstrInfo *TII) {
1926 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1928 if (Arg.getOpcode() == ISD::CopyFromReg) {
1929 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1930 if (!TargetRegisterInfo::isVirtualRegister(VR))
1932 MachineInstr *Def = MRI->getVRegDef(VR);
1935 if (!Flags.isByVal()) {
1936 if (!TII->isLoadFromStackSlot(Def, FI))
1941 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1942 if (Flags.isByVal())
1943 // ByVal argument is passed in as a pointer but it's now being
1944 // dereferenced. e.g.
1945 // define @foo(%struct.X* %A) {
1946 // tail call @bar(%struct.X* byval %A)
1949 SDValue Ptr = Ld->getBasePtr();
1950 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1953 FI = FINode->getIndex();
1957 assert(FI != INT_MAX);
1958 if (!MFI->isFixedObjectIndex(FI))
1960 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1963 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1964 /// for tail call optimization. Targets which want to do tail call
1965 /// optimization should implement this function.
1967 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1968 CallingConv::ID CalleeCC,
1970 bool isCalleeStructRet,
1971 bool isCallerStructRet,
1972 const SmallVectorImpl<ISD::OutputArg> &Outs,
1973 const SmallVectorImpl<SDValue> &OutVals,
1974 const SmallVectorImpl<ISD::InputArg> &Ins,
1975 SelectionDAG& DAG) const {
1976 const Function *CallerF = DAG.getMachineFunction().getFunction();
1977 CallingConv::ID CallerCC = CallerF->getCallingConv();
1978 bool CCMatch = CallerCC == CalleeCC;
1980 // Look for obvious safe cases to perform tail call optimization that do not
1981 // require ABI changes. This is what gcc calls sibcall.
1983 // Do not sibcall optimize vararg calls unless the call site is not passing
1985 if (isVarArg && !Outs.empty())
1988 // Exception-handling functions need a special set of instructions to indicate
1989 // a return to the hardware. Tail-calling another function would probably
1991 if (CallerF->hasFnAttribute("interrupt"))
1994 // Also avoid sibcall optimization if either caller or callee uses struct
1995 // return semantics.
1996 if (isCalleeStructRet || isCallerStructRet)
1999 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
2000 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
2001 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
2002 // support in the assembler and linker to be used. This would need to be
2003 // fixed to fully support tail calls in Thumb1.
2005 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
2006 // LR. This means if we need to reload LR, it takes an extra instructions,
2007 // which outweighs the value of the tail call; but here we don't know yet
2008 // whether LR is going to be used. Probably the right approach is to
2009 // generate the tail call here and turn it back into CALL/RET in
2010 // emitEpilogue if LR is used.
2012 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
2013 // but we need to make sure there are enough registers; the only valid
2014 // registers are the 4 used for parameters. We don't currently do this
2016 if (Subtarget->isThumb1Only())
2019 // Externally-defined functions with weak linkage should not be
2020 // tail-called on ARM when the OS does not support dynamic
2021 // pre-emption of symbols, as the AAELF spec requires normal calls
2022 // to undefined weak functions to be replaced with a NOP or jump to the
2023 // next instruction. The behaviour of branch instructions in this
2024 // situation (as used for tail calls) is implementation-defined, so we
2025 // cannot rely on the linker replacing the tail call with a return.
2026 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2027 const GlobalValue *GV = G->getGlobal();
2028 if (GV->hasExternalWeakLinkage())
2032 // If the calling conventions do not match, then we'd better make sure the
2033 // results are returned in the same way as what the caller expects.
2035 SmallVector<CCValAssign, 16> RVLocs1;
2036 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2037 *DAG.getContext(), Call);
2038 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
2040 SmallVector<CCValAssign, 16> RVLocs2;
2041 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2042 *DAG.getContext(), Call);
2043 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2045 if (RVLocs1.size() != RVLocs2.size())
2047 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2048 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2050 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2052 if (RVLocs1[i].isRegLoc()) {
2053 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2056 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2062 // If Caller's vararg or byval argument has been split between registers and
2063 // stack, do not perform tail call, since part of the argument is in caller's
2065 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
2066 getInfo<ARMFunctionInfo>();
2067 if (AFI_Caller->getArgRegsSaveSize())
2070 // If the callee takes no arguments then go on to check the results of the
2072 if (!Outs.empty()) {
2073 // Check if stack adjustment is needed. For now, do not do this if any
2074 // argument is passed on the stack.
2075 SmallVector<CCValAssign, 16> ArgLocs;
2076 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2077 *DAG.getContext(), Call);
2078 CCInfo.AnalyzeCallOperands(Outs,
2079 CCAssignFnForNode(CalleeCC, false, isVarArg));
2080 if (CCInfo.getNextStackOffset()) {
2081 MachineFunction &MF = DAG.getMachineFunction();
2083 // Check if the arguments are already laid out in the right way as
2084 // the caller's fixed stack objects.
2085 MachineFrameInfo *MFI = MF.getFrameInfo();
2086 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2087 const TargetInstrInfo *TII =
2088 getTargetMachine().getSubtargetImpl()->getInstrInfo();
2089 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2091 ++i, ++realArgIdx) {
2092 CCValAssign &VA = ArgLocs[i];
2093 EVT RegVT = VA.getLocVT();
2094 SDValue Arg = OutVals[realArgIdx];
2095 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2096 if (VA.getLocInfo() == CCValAssign::Indirect)
2098 if (VA.needsCustom()) {
2099 // f64 and vector types are split into multiple registers or
2100 // register/stack-slot combinations. The types will not match
2101 // the registers; give up on memory f64 refs until we figure
2102 // out what to do about this.
2105 if (!ArgLocs[++i].isRegLoc())
2107 if (RegVT == MVT::v2f64) {
2108 if (!ArgLocs[++i].isRegLoc())
2110 if (!ArgLocs[++i].isRegLoc())
2113 } else if (!VA.isRegLoc()) {
2114 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2126 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2127 MachineFunction &MF, bool isVarArg,
2128 const SmallVectorImpl<ISD::OutputArg> &Outs,
2129 LLVMContext &Context) const {
2130 SmallVector<CCValAssign, 16> RVLocs;
2131 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2132 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2136 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2137 SDLoc DL, SelectionDAG &DAG) {
2138 const MachineFunction &MF = DAG.getMachineFunction();
2139 const Function *F = MF.getFunction();
2141 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2143 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2144 // version of the "preferred return address". These offsets affect the return
2145 // instruction if this is a return from PL1 without hypervisor extensions.
2146 // IRQ/FIQ: +4 "subs pc, lr, #4"
2147 // SWI: 0 "subs pc, lr, #0"
2148 // ABORT: +4 "subs pc, lr, #4"
2149 // UNDEF: +4/+2 "subs pc, lr, #0"
2150 // UNDEF varies depending on where the exception came from ARM or Thumb
2151 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2154 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2157 else if (IntKind == "SWI" || IntKind == "UNDEF")
2160 report_fatal_error("Unsupported interrupt attribute. If present, value "
2161 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2163 RetOps.insert(RetOps.begin() + 1, DAG.getConstant(LROffset, MVT::i32, false));
2165 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2169 ARMTargetLowering::LowerReturn(SDValue Chain,
2170 CallingConv::ID CallConv, bool isVarArg,
2171 const SmallVectorImpl<ISD::OutputArg> &Outs,
2172 const SmallVectorImpl<SDValue> &OutVals,
2173 SDLoc dl, SelectionDAG &DAG) const {
2175 // CCValAssign - represent the assignment of the return value to a location.
2176 SmallVector<CCValAssign, 16> RVLocs;
2178 // CCState - Info about the registers and stack slots.
2179 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2180 *DAG.getContext(), Call);
2182 // Analyze outgoing return values.
2183 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2187 SmallVector<SDValue, 4> RetOps;
2188 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2189 bool isLittleEndian = Subtarget->isLittle();
2191 MachineFunction &MF = DAG.getMachineFunction();
2192 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2193 AFI->setReturnRegsCount(RVLocs.size());
2195 // Copy the result values into the output registers.
2196 for (unsigned i = 0, realRVLocIdx = 0;
2198 ++i, ++realRVLocIdx) {
2199 CCValAssign &VA = RVLocs[i];
2200 assert(VA.isRegLoc() && "Can only return in registers!");
2202 SDValue Arg = OutVals[realRVLocIdx];
2204 switch (VA.getLocInfo()) {
2205 default: llvm_unreachable("Unknown loc info!");
2206 case CCValAssign::Full: break;
2207 case CCValAssign::BCvt:
2208 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2212 if (VA.needsCustom()) {
2213 if (VA.getLocVT() == MVT::v2f64) {
2214 // Extract the first half and return it in two registers.
2215 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2216 DAG.getConstant(0, MVT::i32));
2217 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2218 DAG.getVTList(MVT::i32, MVT::i32), Half);
2220 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2221 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2223 Flag = Chain.getValue(1);
2224 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2225 VA = RVLocs[++i]; // skip ahead to next loc
2226 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2227 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2229 Flag = Chain.getValue(1);
2230 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2231 VA = RVLocs[++i]; // skip ahead to next loc
2233 // Extract the 2nd half and fall through to handle it as an f64 value.
2234 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2235 DAG.getConstant(1, MVT::i32));
2237 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2239 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2240 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2241 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2242 fmrrd.getValue(isLittleEndian ? 0 : 1),
2244 Flag = Chain.getValue(1);
2245 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2246 VA = RVLocs[++i]; // skip ahead to next loc
2247 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2248 fmrrd.getValue(isLittleEndian ? 1 : 0),
2251 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2253 // Guarantee that all emitted copies are
2254 // stuck together, avoiding something bad.
2255 Flag = Chain.getValue(1);
2256 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2259 // Update chain and glue.
2262 RetOps.push_back(Flag);
2264 // CPUs which aren't M-class use a special sequence to return from
2265 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2266 // though we use "subs pc, lr, #N").
2268 // M-class CPUs actually use a normal return sequence with a special
2269 // (hardware-provided) value in LR, so the normal code path works.
2270 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2271 !Subtarget->isMClass()) {
2272 if (Subtarget->isThumb1Only())
2273 report_fatal_error("interrupt attribute is not supported in Thumb1");
2274 return LowerInterruptReturn(RetOps, dl, DAG);
2277 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2280 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2281 if (N->getNumValues() != 1)
2283 if (!N->hasNUsesOfValue(1, 0))
2286 SDValue TCChain = Chain;
2287 SDNode *Copy = *N->use_begin();
2288 if (Copy->getOpcode() == ISD::CopyToReg) {
2289 // If the copy has a glue operand, we conservatively assume it isn't safe to
2290 // perform a tail call.
2291 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2293 TCChain = Copy->getOperand(0);
2294 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2295 SDNode *VMov = Copy;
2296 // f64 returned in a pair of GPRs.
2297 SmallPtrSet<SDNode*, 2> Copies;
2298 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2300 if (UI->getOpcode() != ISD::CopyToReg)
2304 if (Copies.size() > 2)
2307 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2309 SDValue UseChain = UI->getOperand(0);
2310 if (Copies.count(UseChain.getNode()))
2314 // We are at the top of this chain.
2315 // If the copy has a glue operand, we conservatively assume it
2316 // isn't safe to perform a tail call.
2317 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2323 } else if (Copy->getOpcode() == ISD::BITCAST) {
2324 // f32 returned in a single GPR.
2325 if (!Copy->hasOneUse())
2327 Copy = *Copy->use_begin();
2328 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2330 // If the copy has a glue operand, we conservatively assume it isn't safe to
2331 // perform a tail call.
2332 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2334 TCChain = Copy->getOperand(0);
2339 bool HasRet = false;
2340 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2342 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2343 UI->getOpcode() != ARMISD::INTRET_FLAG)
2355 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2356 if (!Subtarget->supportsTailCall())
2359 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2362 return !Subtarget->isThumb1Only();
2365 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2366 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2367 // one of the above mentioned nodes. It has to be wrapped because otherwise
2368 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2369 // be used to form addressing mode. These wrapped nodes will be selected
2371 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2372 EVT PtrVT = Op.getValueType();
2373 // FIXME there is no actual debug info here
2375 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2377 if (CP->isMachineConstantPoolEntry())
2378 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2379 CP->getAlignment());
2381 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2382 CP->getAlignment());
2383 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2386 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2387 return MachineJumpTableInfo::EK_Inline;
2390 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2391 SelectionDAG &DAG) const {
2392 MachineFunction &MF = DAG.getMachineFunction();
2393 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2394 unsigned ARMPCLabelIndex = 0;
2396 EVT PtrVT = getPointerTy();
2397 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2398 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2400 if (RelocM == Reloc::Static) {
2401 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2403 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2404 ARMPCLabelIndex = AFI->createPICLabelUId();
2405 ARMConstantPoolValue *CPV =
2406 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2407 ARMCP::CPBlockAddress, PCAdj);
2408 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2410 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2411 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2412 MachinePointerInfo::getConstantPool(),
2413 false, false, false, 0);
2414 if (RelocM == Reloc::Static)
2416 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2417 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2420 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2422 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2423 SelectionDAG &DAG) const {
2425 EVT PtrVT = getPointerTy();
2426 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2427 MachineFunction &MF = DAG.getMachineFunction();
2428 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2429 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2430 ARMConstantPoolValue *CPV =
2431 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2432 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2433 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2434 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2435 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2436 MachinePointerInfo::getConstantPool(),
2437 false, false, false, 0);
2438 SDValue Chain = Argument.getValue(1);
2440 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2441 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2443 // call __tls_get_addr.
2446 Entry.Node = Argument;
2447 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2448 Args.push_back(Entry);
2450 // FIXME: is there useful debug info available here?
2451 TargetLowering::CallLoweringInfo CLI(DAG);
2452 CLI.setDebugLoc(dl).setChain(Chain)
2453 .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2454 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args),
2457 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2458 return CallResult.first;
2461 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2462 // "local exec" model.
2464 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2466 TLSModel::Model model) const {
2467 const GlobalValue *GV = GA->getGlobal();
2470 SDValue Chain = DAG.getEntryNode();
2471 EVT PtrVT = getPointerTy();
2472 // Get the Thread Pointer
2473 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2475 if (model == TLSModel::InitialExec) {
2476 MachineFunction &MF = DAG.getMachineFunction();
2477 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2478 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2479 // Initial exec model.
2480 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2481 ARMConstantPoolValue *CPV =
2482 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2483 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2485 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2486 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2487 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2488 MachinePointerInfo::getConstantPool(),
2489 false, false, false, 0);
2490 Chain = Offset.getValue(1);
2492 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2493 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2495 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2496 MachinePointerInfo::getConstantPool(),
2497 false, false, false, 0);
2500 assert(model == TLSModel::LocalExec);
2501 ARMConstantPoolValue *CPV =
2502 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2503 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2504 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2505 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2506 MachinePointerInfo::getConstantPool(),
2507 false, false, false, 0);
2510 // The address of the thread local variable is the add of the thread
2511 // pointer with the offset of the variable.
2512 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2516 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2517 // TODO: implement the "local dynamic" model
2518 assert(Subtarget->isTargetELF() &&
2519 "TLS not implemented for non-ELF targets");
2520 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2522 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2525 case TLSModel::GeneralDynamic:
2526 case TLSModel::LocalDynamic:
2527 return LowerToTLSGeneralDynamicModel(GA, DAG);
2528 case TLSModel::InitialExec:
2529 case TLSModel::LocalExec:
2530 return LowerToTLSExecModels(GA, DAG, model);
2532 llvm_unreachable("bogus TLS model");
2535 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2536 SelectionDAG &DAG) const {
2537 EVT PtrVT = getPointerTy();
2539 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2540 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2541 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2542 ARMConstantPoolValue *CPV =
2543 ARMConstantPoolConstant::Create(GV,
2544 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2545 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2546 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2547 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2549 MachinePointerInfo::getConstantPool(),
2550 false, false, false, 0);
2551 SDValue Chain = Result.getValue(1);
2552 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2553 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2555 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2556 MachinePointerInfo::getGOT(),
2557 false, false, false, 0);
2561 // If we have T2 ops, we can materialize the address directly via movt/movw
2562 // pair. This is always cheaper.
2563 if (Subtarget->useMovt(DAG.getMachineFunction())) {
2565 // FIXME: Once remat is capable of dealing with instructions with register
2566 // operands, expand this into two nodes.
2567 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2568 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2570 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2571 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2572 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2573 MachinePointerInfo::getConstantPool(),
2574 false, false, false, 0);
2578 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2579 SelectionDAG &DAG) const {
2580 EVT PtrVT = getPointerTy();
2582 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2583 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2585 if (Subtarget->useMovt(DAG.getMachineFunction()))
2588 // FIXME: Once remat is capable of dealing with instructions with register
2589 // operands, expand this into multiple nodes
2591 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2593 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2594 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2596 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2597 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2598 MachinePointerInfo::getGOT(), false, false, false, 0);
2602 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
2603 SelectionDAG &DAG) const {
2604 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
2605 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
2606 "Windows on ARM expects to use movw/movt");
2608 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2609 const ARMII::TOF TargetFlags =
2610 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
2611 EVT PtrVT = getPointerTy();
2617 // FIXME: Once remat is capable of dealing with instructions with register
2618 // operands, expand this into two nodes.
2619 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2620 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
2622 if (GV->hasDLLImportStorageClass())
2623 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2624 MachinePointerInfo::getGOT(), false, false, false, 0);
2628 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2629 SelectionDAG &DAG) const {
2630 assert(Subtarget->isTargetELF() &&
2631 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2632 MachineFunction &MF = DAG.getMachineFunction();
2633 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2634 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2635 EVT PtrVT = getPointerTy();
2637 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2638 ARMConstantPoolValue *CPV =
2639 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2640 ARMPCLabelIndex, PCAdj);
2641 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2642 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2643 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2644 MachinePointerInfo::getConstantPool(),
2645 false, false, false, 0);
2646 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2647 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2651 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2653 SDValue Val = DAG.getConstant(0, MVT::i32);
2654 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2655 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2656 Op.getOperand(1), Val);
2660 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2662 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2663 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2667 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2668 const ARMSubtarget *Subtarget) const {
2669 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2672 default: return SDValue(); // Don't custom lower most intrinsics.
2673 case Intrinsic::arm_rbit: {
2674 assert(Op.getOperand(1).getValueType() == MVT::i32 &&
2675 "RBIT intrinsic must have i32 type!");
2676 return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1));
2678 case Intrinsic::arm_thread_pointer: {
2679 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2680 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2682 case Intrinsic::eh_sjlj_lsda: {
2683 MachineFunction &MF = DAG.getMachineFunction();
2684 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2685 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2686 EVT PtrVT = getPointerTy();
2687 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2689 unsigned PCAdj = (RelocM != Reloc::PIC_)
2690 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2691 ARMConstantPoolValue *CPV =
2692 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2693 ARMCP::CPLSDA, PCAdj);
2694 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2695 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2697 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2698 MachinePointerInfo::getConstantPool(),
2699 false, false, false, 0);
2701 if (RelocM == Reloc::PIC_) {
2702 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2703 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2707 case Intrinsic::arm_neon_vmulls:
2708 case Intrinsic::arm_neon_vmullu: {
2709 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2710 ? ARMISD::VMULLs : ARMISD::VMULLu;
2711 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2712 Op.getOperand(1), Op.getOperand(2));
2717 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2718 const ARMSubtarget *Subtarget) {
2719 // FIXME: handle "fence singlethread" more efficiently.
2721 if (!Subtarget->hasDataBarrier()) {
2722 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2723 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2725 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2726 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2727 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2728 DAG.getConstant(0, MVT::i32));
2731 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2732 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2733 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
2734 if (Subtarget->isMClass()) {
2735 // Only a full system barrier exists in the M-class architectures.
2736 Domain = ARM_MB::SY;
2737 } else if (Subtarget->isSwift() && Ord == Release) {
2738 // Swift happens to implement ISHST barriers in a way that's compatible with
2739 // Release semantics but weaker than ISH so we'd be fools not to use
2740 // it. Beware: other processors probably don't!
2741 Domain = ARM_MB::ISHST;
2744 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2745 DAG.getConstant(Intrinsic::arm_dmb, MVT::i32),
2746 DAG.getConstant(Domain, MVT::i32));
2749 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2750 const ARMSubtarget *Subtarget) {
2751 // ARM pre v5TE and Thumb1 does not have preload instructions.
2752 if (!(Subtarget->isThumb2() ||
2753 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2754 // Just preserve the chain.
2755 return Op.getOperand(0);
2758 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2760 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2761 // ARMv7 with MP extension has PLDW.
2762 return Op.getOperand(0);
2764 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2765 if (Subtarget->isThumb()) {
2767 isRead = ~isRead & 1;
2768 isData = ~isData & 1;
2771 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2772 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2773 DAG.getConstant(isData, MVT::i32));
2776 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2777 MachineFunction &MF = DAG.getMachineFunction();
2778 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2780 // vastart just stores the address of the VarArgsFrameIndex slot into the
2781 // memory location argument.
2783 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2784 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2785 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2786 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2787 MachinePointerInfo(SV), false, false, 0);
2791 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2792 SDValue &Root, SelectionDAG &DAG,
2794 MachineFunction &MF = DAG.getMachineFunction();
2795 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2797 const TargetRegisterClass *RC;
2798 if (AFI->isThumb1OnlyFunction())
2799 RC = &ARM::tGPRRegClass;
2801 RC = &ARM::GPRRegClass;
2803 // Transform the arguments stored in physical registers into virtual ones.
2804 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2805 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2808 if (NextVA.isMemLoc()) {
2809 MachineFrameInfo *MFI = MF.getFrameInfo();
2810 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2812 // Create load node to retrieve arguments from the stack.
2813 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2814 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2815 MachinePointerInfo::getFixedStack(FI),
2816 false, false, false, 0);
2818 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2819 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2821 if (!Subtarget->isLittle())
2822 std::swap (ArgValue, ArgValue2);
2823 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2827 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2828 unsigned InRegsParamRecordIdx,
2830 unsigned &ArgRegsSize,
2831 unsigned &ArgRegsSaveSize)
2834 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2835 unsigned RBegin, REnd;
2836 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2837 NumGPRs = REnd - RBegin;
2839 unsigned int firstUnalloced;
2840 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2841 sizeof(GPRArgRegs) /
2842 sizeof(GPRArgRegs[0]));
2843 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2846 unsigned Align = MF.getTarget()
2848 ->getFrameLowering()
2849 ->getStackAlignment();
2850 ArgRegsSize = NumGPRs * 4;
2852 // If parameter is split between stack and GPRs...
2853 if (NumGPRs && Align > 4 &&
2854 (ArgRegsSize < ArgSize ||
2855 InRegsParamRecordIdx >= CCInfo.getInRegsParamsCount())) {
2856 // Add padding for part of param recovered from GPRs. For example,
2857 // if Align == 8, its last byte must be at address K*8 - 1.
2858 // We need to do it, since remained (stack) part of parameter has
2859 // stack alignment, and we need to "attach" "GPRs head" without gaps
2862 // |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
2863 // [ [padding] [GPRs head] ] [ Tail passed via stack ....
2865 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2867 OffsetToAlignment(ArgRegsSize + AFI->getArgRegsSaveSize(), Align);
2868 ArgRegsSaveSize = ArgRegsSize + Padding;
2870 // We don't need to extend regs save size for byval parameters if they
2871 // are passed via GPRs only.
2872 ArgRegsSaveSize = ArgRegsSize;
2875 // The remaining GPRs hold either the beginning of variable-argument
2876 // data, or the beginning of an aggregate passed by value (usually
2877 // byval). Either way, we allocate stack slots adjacent to the data
2878 // provided by our caller, and store the unallocated registers there.
2879 // If this is a variadic function, the va_list pointer will begin with
2880 // these values; otherwise, this reassembles a (byval) structure that
2881 // was split between registers and memory.
2882 // Return: The frame index registers were stored into.
2884 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
2885 SDLoc dl, SDValue &Chain,
2886 const Value *OrigArg,
2887 unsigned InRegsParamRecordIdx,
2888 unsigned OffsetFromOrigArg,
2892 unsigned ByValStoreOffset,
2893 unsigned TotalArgRegsSaveSize) const {
2895 // Currently, two use-cases possible:
2896 // Case #1. Non-var-args function, and we meet first byval parameter.
2897 // Setup first unallocated register as first byval register;
2898 // eat all remained registers
2899 // (these two actions are performed by HandleByVal method).
2900 // Then, here, we initialize stack frame with
2901 // "store-reg" instructions.
2902 // Case #2. Var-args function, that doesn't contain byval parameters.
2903 // The same: eat all remained unallocated registers,
2904 // initialize stack frame.
2906 MachineFunction &MF = DAG.getMachineFunction();
2907 MachineFrameInfo *MFI = MF.getFrameInfo();
2908 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2909 unsigned firstRegToSaveIndex, lastRegToSaveIndex;
2910 unsigned RBegin, REnd;
2911 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2912 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2913 firstRegToSaveIndex = RBegin - ARM::R0;
2914 lastRegToSaveIndex = REnd - ARM::R0;
2916 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2917 (GPRArgRegs, array_lengthof(GPRArgRegs));
2918 lastRegToSaveIndex = 4;
2921 unsigned ArgRegsSize, ArgRegsSaveSize;
2922 computeRegArea(CCInfo, MF, InRegsParamRecordIdx, ArgSize,
2923 ArgRegsSize, ArgRegsSaveSize);
2925 // Store any by-val regs to their spots on the stack so that they may be
2926 // loaded by deferencing the result of formal parameter pointer or va_next.
2927 // Note: once stack area for byval/varargs registers
2928 // was initialized, it can't be initialized again.
2929 if (ArgRegsSaveSize) {
2930 unsigned Padding = ArgRegsSaveSize - ArgRegsSize;
2933 assert(AFI->getStoredByValParamsPadding() == 0 &&
2934 "The only parameter may be padded.");
2935 AFI->setStoredByValParamsPadding(Padding);
2938 int FrameIndex = MFI->CreateFixedObject(ArgRegsSaveSize,
2941 (int64_t)TotalArgRegsSaveSize,
2943 SDValue FIN = DAG.getFrameIndex(FrameIndex, getPointerTy());
2945 MFI->CreateFixedObject(Padding,
2946 ArgOffset + ByValStoreOffset -
2947 (int64_t)ArgRegsSaveSize,
2951 SmallVector<SDValue, 4> MemOps;
2952 for (unsigned i = 0; firstRegToSaveIndex < lastRegToSaveIndex;
2953 ++firstRegToSaveIndex, ++i) {
2954 const TargetRegisterClass *RC;
2955 if (AFI->isThumb1OnlyFunction())
2956 RC = &ARM::tGPRRegClass;
2958 RC = &ARM::GPRRegClass;
2960 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2961 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2963 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2964 MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i),
2966 MemOps.push_back(Store);
2967 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2968 DAG.getConstant(4, getPointerTy()));
2971 AFI->setArgRegsSaveSize(ArgRegsSaveSize + AFI->getArgRegsSaveSize());
2973 if (!MemOps.empty())
2974 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2978 // We cannot allocate a zero-byte object for the first variadic argument,
2979 // so just make up a size.
2982 // This will point to the next argument passed via stack.
2983 return MFI->CreateFixedObject(
2984 ArgSize, ArgOffset, !ForceMutable);
2988 // Setup stack frame, the va_list pointer will start from.
2990 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2991 SDLoc dl, SDValue &Chain,
2993 unsigned TotalArgRegsSaveSize,
2994 bool ForceMutable) const {
2995 MachineFunction &MF = DAG.getMachineFunction();
2996 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2998 // Try to store any remaining integer argument regs
2999 // to their spots on the stack so that they may be loaded by deferencing
3000 // the result of va_next.
3001 // If there is no regs to be stored, just point address after last
3002 // argument passed via stack.
3004 StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3005 CCInfo.getInRegsParamsCount(), 0, ArgOffset, 0, ForceMutable,
3006 0, TotalArgRegsSaveSize);
3008 AFI->setVarArgsFrameIndex(FrameIndex);
3012 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
3013 CallingConv::ID CallConv, bool isVarArg,
3014 const SmallVectorImpl<ISD::InputArg>
3016 SDLoc dl, SelectionDAG &DAG,
3017 SmallVectorImpl<SDValue> &InVals)
3019 MachineFunction &MF = DAG.getMachineFunction();
3020 MachineFrameInfo *MFI = MF.getFrameInfo();
3022 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3024 // Assign locations to all of the incoming arguments.
3025 SmallVector<CCValAssign, 16> ArgLocs;
3026 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3027 *DAG.getContext(), Prologue);
3028 CCInfo.AnalyzeFormalArguments(Ins,
3029 CCAssignFnForNode(CallConv, /* Return*/ false,
3032 SmallVector<SDValue, 16> ArgValues;
3033 int lastInsIndex = -1;
3035 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
3036 unsigned CurArgIdx = 0;
3038 // Initially ArgRegsSaveSize is zero.
3039 // Then we increase this value each time we meet byval parameter.
3040 // We also increase this value in case of varargs function.
3041 AFI->setArgRegsSaveSize(0);
3043 unsigned ByValStoreOffset = 0;
3044 unsigned TotalArgRegsSaveSize = 0;
3045 unsigned ArgRegsSaveSizeMaxAlign = 4;
3047 // Calculate the amount of stack space that we need to allocate to store
3048 // byval and variadic arguments that are passed in registers.
3049 // We need to know this before we allocate the first byval or variadic
3050 // argument, as they will be allocated a stack slot below the CFA (Canonical
3051 // Frame Address, the stack pointer at entry to the function).
3052 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3053 CCValAssign &VA = ArgLocs[i];
3054 if (VA.isMemLoc()) {
3055 int index = VA.getValNo();
3056 if (index != lastInsIndex) {
3057 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3058 if (Flags.isByVal()) {
3059 unsigned ExtraArgRegsSize;
3060 unsigned ExtraArgRegsSaveSize;
3061 computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsProcessed(),
3062 Flags.getByValSize(),
3063 ExtraArgRegsSize, ExtraArgRegsSaveSize);
3065 TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
3066 if (Flags.getByValAlign() > ArgRegsSaveSizeMaxAlign)
3067 ArgRegsSaveSizeMaxAlign = Flags.getByValAlign();
3068 CCInfo.nextInRegsParam();
3070 lastInsIndex = index;
3074 CCInfo.rewindByValRegsInfo();
3076 if (isVarArg && MFI->hasVAStart()) {
3077 unsigned ExtraArgRegsSize;
3078 unsigned ExtraArgRegsSaveSize;
3079 computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsCount(), 0,
3080 ExtraArgRegsSize, ExtraArgRegsSaveSize);
3081 TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
3083 // If the arg regs save area contains N-byte aligned values, the
3084 // bottom of it must be at least N-byte aligned.
3085 TotalArgRegsSaveSize = RoundUpToAlignment(TotalArgRegsSaveSize, ArgRegsSaveSizeMaxAlign);
3086 TotalArgRegsSaveSize = std::min(TotalArgRegsSaveSize, 16U);
3088 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3089 CCValAssign &VA = ArgLocs[i];
3090 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
3091 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
3092 // Arguments stored in registers.
3093 if (VA.isRegLoc()) {
3094 EVT RegVT = VA.getLocVT();
3096 if (VA.needsCustom()) {
3097 // f64 and vector types are split up into multiple registers or
3098 // combinations of registers and stack slots.
3099 if (VA.getLocVT() == MVT::v2f64) {
3100 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3102 VA = ArgLocs[++i]; // skip ahead to next loc
3104 if (VA.isMemLoc()) {
3105 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3106 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3107 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3108 MachinePointerInfo::getFixedStack(FI),
3109 false, false, false, 0);
3111 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3114 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3115 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3116 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
3117 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3118 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
3120 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3123 const TargetRegisterClass *RC;
3125 if (RegVT == MVT::f32)
3126 RC = &ARM::SPRRegClass;
3127 else if (RegVT == MVT::f64)
3128 RC = &ARM::DPRRegClass;
3129 else if (RegVT == MVT::v2f64)
3130 RC = &ARM::QPRRegClass;
3131 else if (RegVT == MVT::i32)
3132 RC = AFI->isThumb1OnlyFunction() ?
3133 (const TargetRegisterClass*)&ARM::tGPRRegClass :
3134 (const TargetRegisterClass*)&ARM::GPRRegClass;
3136 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3138 // Transform the arguments in physical registers into virtual ones.
3139 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3140 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3143 // If this is an 8 or 16-bit value, it is really passed promoted
3144 // to 32 bits. Insert an assert[sz]ext to capture this, then
3145 // truncate to the right size.
3146 switch (VA.getLocInfo()) {
3147 default: llvm_unreachable("Unknown loc info!");
3148 case CCValAssign::Full: break;
3149 case CCValAssign::BCvt:
3150 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3152 case CCValAssign::SExt:
3153 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3154 DAG.getValueType(VA.getValVT()));
3155 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3157 case CCValAssign::ZExt:
3158 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3159 DAG.getValueType(VA.getValVT()));
3160 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3164 InVals.push_back(ArgValue);
3166 } else { // VA.isRegLoc()
3169 assert(VA.isMemLoc());
3170 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3172 int index = ArgLocs[i].getValNo();
3174 // Some Ins[] entries become multiple ArgLoc[] entries.
3175 // Process them only once.
3176 if (index != lastInsIndex)
3178 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3179 // FIXME: For now, all byval parameter objects are marked mutable.
3180 // This can be changed with more analysis.
3181 // In case of tail call optimization mark all arguments mutable.
3182 // Since they could be overwritten by lowering of arguments in case of
3184 if (Flags.isByVal()) {
3185 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3187 ByValStoreOffset = RoundUpToAlignment(ByValStoreOffset, Flags.getByValAlign());
3188 int FrameIndex = StoreByValRegs(
3189 CCInfo, DAG, dl, Chain, CurOrigArg,
3191 Ins[VA.getValNo()].PartOffset,
3192 VA.getLocMemOffset(),
3193 Flags.getByValSize(),
3194 true /*force mutable frames*/,
3196 TotalArgRegsSaveSize);
3197 ByValStoreOffset += Flags.getByValSize();
3198 ByValStoreOffset = std::min(ByValStoreOffset, 16U);
3199 InVals.push_back(DAG.getFrameIndex(FrameIndex, getPointerTy()));
3200 CCInfo.nextInRegsParam();
3202 unsigned FIOffset = VA.getLocMemOffset();
3203 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3206 // Create load nodes to retrieve arguments from the stack.
3207 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3208 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3209 MachinePointerInfo::getFixedStack(FI),
3210 false, false, false, 0));
3212 lastInsIndex = index;
3218 if (isVarArg && MFI->hasVAStart())
3219 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3220 CCInfo.getNextStackOffset(),
3221 TotalArgRegsSaveSize);
3223 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3228 /// isFloatingPointZero - Return true if this is +0.0.
3229 static bool isFloatingPointZero(SDValue Op) {
3230 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3231 return CFP->getValueAPF().isPosZero();
3232 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3233 // Maybe this has already been legalized into the constant pool?
3234 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3235 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3236 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3237 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3238 return CFP->getValueAPF().isPosZero();
3240 } else if (Op->getOpcode() == ISD::BITCAST &&
3241 Op->getValueType(0) == MVT::f64) {
3242 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3243 // created by LowerConstantFP().
3244 SDValue BitcastOp = Op->getOperand(0);
3245 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM) {
3246 SDValue MoveOp = BitcastOp->getOperand(0);
3247 if (MoveOp->getOpcode() == ISD::TargetConstant &&
3248 cast<ConstantSDNode>(MoveOp)->getZExtValue() == 0) {
3256 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3257 /// the given operands.
3259 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3260 SDValue &ARMcc, SelectionDAG &DAG,
3262 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3263 unsigned C = RHSC->getZExtValue();
3264 if (!isLegalICmpImmediate(C)) {
3265 // Constant does not fit, try adjusting it by one?
3270 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3271 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3272 RHS = DAG.getConstant(C-1, MVT::i32);
3277 if (C != 0 && isLegalICmpImmediate(C-1)) {
3278 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3279 RHS = DAG.getConstant(C-1, MVT::i32);
3284 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3285 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3286 RHS = DAG.getConstant(C+1, MVT::i32);
3291 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3292 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3293 RHS = DAG.getConstant(C+1, MVT::i32);
3300 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3301 ARMISD::NodeType CompareType;
3304 CompareType = ARMISD::CMP;
3309 CompareType = ARMISD::CMPZ;
3312 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3313 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3316 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3318 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3320 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
3322 if (!isFloatingPointZero(RHS))
3323 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3325 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3326 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3329 /// duplicateCmp - Glue values can have only one use, so this function
3330 /// duplicates a comparison node.
3332 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3333 unsigned Opc = Cmp.getOpcode();
3335 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3336 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3338 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3339 Cmp = Cmp.getOperand(0);
3340 Opc = Cmp.getOpcode();
3341 if (Opc == ARMISD::CMPFP)
3342 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3344 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3345 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3347 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3350 std::pair<SDValue, SDValue>
3351 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3352 SDValue &ARMcc) const {
3353 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3355 SDValue Value, OverflowCmp;
3356 SDValue LHS = Op.getOperand(0);
3357 SDValue RHS = Op.getOperand(1);
3360 // FIXME: We are currently always generating CMPs because we don't support
3361 // generating CMN through the backend. This is not as good as the natural
3362 // CMP case because it causes a register dependency and cannot be folded
3365 switch (Op.getOpcode()) {
3367 llvm_unreachable("Unknown overflow instruction!");
3369 ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3370 Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3371 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3374 ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3375 Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3376 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3379 ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3380 Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3381 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3384 ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3385 Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3386 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3390 return std::make_pair(Value, OverflowCmp);
3395 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
3396 // Let legalize expand this if it isn't a legal type yet.
3397 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3400 SDValue Value, OverflowCmp;
3402 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3403 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3404 // We use 0 and 1 as false and true values.
3405 SDValue TVal = DAG.getConstant(1, MVT::i32);
3406 SDValue FVal = DAG.getConstant(0, MVT::i32);
3407 EVT VT = Op.getValueType();
3409 SDValue Overflow = DAG.getNode(ARMISD::CMOV, SDLoc(Op), VT, TVal, FVal,
3410 ARMcc, CCR, OverflowCmp);
3412 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3413 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
3417 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3418 SDValue Cond = Op.getOperand(0);
3419 SDValue SelectTrue = Op.getOperand(1);
3420 SDValue SelectFalse = Op.getOperand(2);
3422 unsigned Opc = Cond.getOpcode();
3424 if (Cond.getResNo() == 1 &&
3425 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3426 Opc == ISD::USUBO)) {
3427 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
3430 SDValue Value, OverflowCmp;
3432 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
3433 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3434 EVT VT = Op.getValueType();
3436 return getCMOV(SDLoc(Op), VT, SelectTrue, SelectFalse, ARMcc, CCR,
3442 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3443 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3445 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3446 const ConstantSDNode *CMOVTrue =
3447 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3448 const ConstantSDNode *CMOVFalse =
3449 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3451 if (CMOVTrue && CMOVFalse) {
3452 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3453 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3457 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3459 False = SelectFalse;
3460 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3465 if (True.getNode() && False.getNode()) {
3466 EVT VT = Op.getValueType();
3467 SDValue ARMcc = Cond.getOperand(2);
3468 SDValue CCR = Cond.getOperand(3);
3469 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3470 assert(True.getValueType() == VT);
3471 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
3476 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3477 // undefined bits before doing a full-word comparison with zero.
3478 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3479 DAG.getConstant(1, Cond.getValueType()));
3481 return DAG.getSelectCC(dl, Cond,
3482 DAG.getConstant(0, Cond.getValueType()),
3483 SelectTrue, SelectFalse, ISD::SETNE);
3486 static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) {
3487 if (CC == ISD::SETNE)
3489 return ISD::getSetCCInverse(CC, true);
3492 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3493 bool &swpCmpOps, bool &swpVselOps) {
3494 // Start by selecting the GE condition code for opcodes that return true for
3496 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3498 CondCode = ARMCC::GE;
3500 // and GT for opcodes that return false for 'equality'.
3501 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3503 CondCode = ARMCC::GT;
3505 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3506 // to swap the compare operands.
3507 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3511 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3512 // If we have an unordered opcode, we need to swap the operands to the VSEL
3513 // instruction (effectively negating the condition).
3515 // This also has the effect of swapping which one of 'less' or 'greater'
3516 // returns true, so we also swap the compare operands. It also switches
3517 // whether we return true for 'equality', so we compensate by picking the
3518 // opposite condition code to our original choice.
3519 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3520 CC == ISD::SETUGT) {
3521 swpCmpOps = !swpCmpOps;
3522 swpVselOps = !swpVselOps;
3523 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3526 // 'ordered' is 'anything but unordered', so use the VS condition code and
3527 // swap the VSEL operands.
3528 if (CC == ISD::SETO) {
3529 CondCode = ARMCC::VS;
3533 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3534 // code and swap the VSEL operands.
3535 if (CC == ISD::SETUNE) {
3536 CondCode = ARMCC::EQ;
3541 SDValue ARMTargetLowering::getCMOV(SDLoc dl, EVT VT, SDValue FalseVal,
3542 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
3543 SDValue Cmp, SelectionDAG &DAG) const {
3544 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
3545 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3546 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
3547 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3548 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
3550 SDValue TrueLow = TrueVal.getValue(0);
3551 SDValue TrueHigh = TrueVal.getValue(1);
3552 SDValue FalseLow = FalseVal.getValue(0);
3553 SDValue FalseHigh = FalseVal.getValue(1);
3555 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
3557 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
3558 ARMcc, CCR, duplicateCmp(Cmp, DAG));
3560 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
3562 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3567 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3568 EVT VT = Op.getValueType();
3569 SDValue LHS = Op.getOperand(0);
3570 SDValue RHS = Op.getOperand(1);
3571 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3572 SDValue TrueVal = Op.getOperand(2);
3573 SDValue FalseVal = Op.getOperand(3);
3576 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3577 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3580 // If softenSetCCOperands only returned one value, we should compare it to
3582 if (!RHS.getNode()) {
3583 RHS = DAG.getConstant(0, LHS.getValueType());
3588 if (LHS.getValueType() == MVT::i32) {
3589 // Try to generate VSEL on ARMv8.
3590 // The VSEL instruction can't use all the usual ARM condition
3591 // codes: it only has two bits to select the condition code, so it's
3592 // constrained to use only GE, GT, VS and EQ.
3594 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3595 // swap the operands of the previous compare instruction (effectively
3596 // inverting the compare condition, swapping 'less' and 'greater') and
3597 // sometimes need to swap the operands to the VSEL (which inverts the
3598 // condition in the sense of firing whenever the previous condition didn't)
3599 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3600 TrueVal.getValueType() == MVT::f64)) {
3601 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3602 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3603 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3604 CC = getInverseCCForVSEL(CC);
3605 std::swap(TrueVal, FalseVal);
3610 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3611 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3612 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3615 ARMCC::CondCodes CondCode, CondCode2;
3616 FPCCToARMCC(CC, CondCode, CondCode2);
3618 // Try to generate VSEL on ARMv8.
3619 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3620 TrueVal.getValueType() == MVT::f64)) {
3621 // We can select VMAXNM/VMINNM from a compare followed by a select with the
3622 // same operands, as follows:
3623 // c = fcmp [ogt, olt, ugt, ult] a, b
3625 // We only do this in unsafe-fp-math, because signed zeros and NaNs are
3626 // handled differently than the original code sequence.
3627 if (getTargetMachine().Options.UnsafeFPMath) {
3628 if (LHS == TrueVal && RHS == FalseVal) {
3629 if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3630 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3631 if (CC == ISD::SETOLT || CC == ISD::SETULT)
3632 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3633 } else if (LHS == FalseVal && RHS == TrueVal) {
3634 if (CC == ISD::SETOLT || CC == ISD::SETULT)
3635 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3636 if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3637 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3641 bool swpCmpOps = false;
3642 bool swpVselOps = false;
3643 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3645 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3646 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3648 std::swap(LHS, RHS);
3650 std::swap(TrueVal, FalseVal);
3654 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3655 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3656 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3657 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3658 if (CondCode2 != ARMCC::AL) {
3659 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
3660 // FIXME: Needs another CMP because flag can have but one use.
3661 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3662 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
3667 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3668 /// to morph to an integer compare sequence.
3669 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3670 const ARMSubtarget *Subtarget) {
3671 SDNode *N = Op.getNode();
3672 if (!N->hasOneUse())
3673 // Otherwise it requires moving the value from fp to integer registers.
3675 if (!N->getNumValues())
3677 EVT VT = Op.getValueType();
3678 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3679 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3680 // vmrs are very slow, e.g. cortex-a8.
3683 if (isFloatingPointZero(Op)) {
3687 return ISD::isNormalLoad(N);
3690 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3691 if (isFloatingPointZero(Op))
3692 return DAG.getConstant(0, MVT::i32);
3694 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3695 return DAG.getLoad(MVT::i32, SDLoc(Op),
3696 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3697 Ld->isVolatile(), Ld->isNonTemporal(),
3698 Ld->isInvariant(), Ld->getAlignment());
3700 llvm_unreachable("Unknown VFP cmp argument!");
3703 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3704 SDValue &RetVal1, SDValue &RetVal2) {
3705 if (isFloatingPointZero(Op)) {
3706 RetVal1 = DAG.getConstant(0, MVT::i32);
3707 RetVal2 = DAG.getConstant(0, MVT::i32);
3711 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3712 SDValue Ptr = Ld->getBasePtr();
3713 RetVal1 = DAG.getLoad(MVT::i32, SDLoc(Op),
3714 Ld->getChain(), Ptr,
3715 Ld->getPointerInfo(),
3716 Ld->isVolatile(), Ld->isNonTemporal(),
3717 Ld->isInvariant(), Ld->getAlignment());
3719 EVT PtrType = Ptr.getValueType();
3720 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3721 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(Op),
3722 PtrType, Ptr, DAG.getConstant(4, PtrType));
3723 RetVal2 = DAG.getLoad(MVT::i32, SDLoc(Op),
3724 Ld->getChain(), NewPtr,
3725 Ld->getPointerInfo().getWithOffset(4),
3726 Ld->isVolatile(), Ld->isNonTemporal(),
3727 Ld->isInvariant(), NewAlign);
3731 llvm_unreachable("Unknown VFP cmp argument!");
3734 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3735 /// f32 and even f64 comparisons to integer ones.
3737 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3738 SDValue Chain = Op.getOperand(0);
3739 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3740 SDValue LHS = Op.getOperand(2);
3741 SDValue RHS = Op.getOperand(3);
3742 SDValue Dest = Op.getOperand(4);
3745 bool LHSSeenZero = false;
3746 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3747 bool RHSSeenZero = false;
3748 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3749 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3750 // If unsafe fp math optimization is enabled and there are no other uses of
3751 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3752 // to an integer comparison.
3753 if (CC == ISD::SETOEQ)
3755 else if (CC == ISD::SETUNE)
3758 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3760 if (LHS.getValueType() == MVT::f32) {
3761 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3762 bitcastf32Toi32(LHS, DAG), Mask);
3763 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3764 bitcastf32Toi32(RHS, DAG), Mask);
3765 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3766 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3767 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3768 Chain, Dest, ARMcc, CCR, Cmp);
3773 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3774 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3775 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3776 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3777 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3778 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3779 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3780 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3781 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
3787 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3788 SDValue Chain = Op.getOperand(0);
3789 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3790 SDValue LHS = Op.getOperand(2);
3791 SDValue RHS = Op.getOperand(3);
3792 SDValue Dest = Op.getOperand(4);
3795 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3796 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3799 // If softenSetCCOperands only returned one value, we should compare it to
3801 if (!RHS.getNode()) {
3802 RHS = DAG.getConstant(0, LHS.getValueType());
3807 if (LHS.getValueType() == MVT::i32) {
3809 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3810 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3811 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3812 Chain, Dest, ARMcc, CCR, Cmp);
3815 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3817 if (getTargetMachine().Options.UnsafeFPMath &&
3818 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3819 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3820 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3821 if (Result.getNode())
3825 ARMCC::CondCodes CondCode, CondCode2;
3826 FPCCToARMCC(CC, CondCode, CondCode2);
3828 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3829 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3830 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3831 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3832 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3833 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3834 if (CondCode2 != ARMCC::AL) {
3835 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3836 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3837 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3842 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3843 SDValue Chain = Op.getOperand(0);
3844 SDValue Table = Op.getOperand(1);
3845 SDValue Index = Op.getOperand(2);
3848 EVT PTy = getPointerTy();
3849 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3850 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3851 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3852 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3853 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3854 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3855 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3856 if (Subtarget->isThumb2()) {
3857 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3858 // which does another jump to the destination. This also makes it easier
3859 // to translate it to TBB / TBH later.
3860 // FIXME: This might not work if the function is extremely large.
3861 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3862 Addr, Op.getOperand(2), JTI, UId);
3864 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3865 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3866 MachinePointerInfo::getJumpTable(),
3867 false, false, false, 0);
3868 Chain = Addr.getValue(1);
3869 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3870 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3872 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3873 MachinePointerInfo::getJumpTable(),
3874 false, false, false, 0);
3875 Chain = Addr.getValue(1);
3876 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3880 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3881 EVT VT = Op.getValueType();
3884 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3885 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3887 return DAG.UnrollVectorOp(Op.getNode());
3890 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3891 "Invalid type for custom lowering!");
3892 if (VT != MVT::v4i16)
3893 return DAG.UnrollVectorOp(Op.getNode());
3895 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3896 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3899 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
3900 EVT VT = Op.getValueType();
3902 return LowerVectorFP_TO_INT(Op, DAG);
3904 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
3906 if (Op.getOpcode() == ISD::FP_TO_SINT)
3907 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
3910 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
3912 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3913 /*isSigned*/ false, SDLoc(Op)).first;
3919 switch (Op.getOpcode()) {
3920 default: llvm_unreachable("Invalid opcode!");
3921 case ISD::FP_TO_SINT:
3922 Opc = ARMISD::FTOSI;
3924 case ISD::FP_TO_UINT:
3925 Opc = ARMISD::FTOUI;
3928 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3929 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3932 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3933 EVT VT = Op.getValueType();
3936 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3937 if (VT.getVectorElementType() == MVT::f32)
3939 return DAG.UnrollVectorOp(Op.getNode());
3942 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3943 "Invalid type for custom lowering!");
3944 if (VT != MVT::v4f32)
3945 return DAG.UnrollVectorOp(Op.getNode());
3949 switch (Op.getOpcode()) {
3950 default: llvm_unreachable("Invalid opcode!");
3951 case ISD::SINT_TO_FP:
3952 CastOpc = ISD::SIGN_EXTEND;
3953 Opc = ISD::SINT_TO_FP;
3955 case ISD::UINT_TO_FP:
3956 CastOpc = ISD::ZERO_EXTEND;
3957 Opc = ISD::UINT_TO_FP;
3961 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3962 return DAG.getNode(Opc, dl, VT, Op);
3965 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
3966 EVT VT = Op.getValueType();
3968 return LowerVectorINT_TO_FP(Op, DAG);
3970 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
3972 if (Op.getOpcode() == ISD::SINT_TO_FP)
3973 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
3976 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
3978 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3979 /*isSigned*/ false, SDLoc(Op)).first;
3985 switch (Op.getOpcode()) {
3986 default: llvm_unreachable("Invalid opcode!");
3987 case ISD::SINT_TO_FP:
3988 Opc = ARMISD::SITOF;
3990 case ISD::UINT_TO_FP:
3991 Opc = ARMISD::UITOF;
3995 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3996 return DAG.getNode(Opc, dl, VT, Op);
3999 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4000 // Implement fcopysign with a fabs and a conditional fneg.
4001 SDValue Tmp0 = Op.getOperand(0);
4002 SDValue Tmp1 = Op.getOperand(1);
4004 EVT VT = Op.getValueType();
4005 EVT SrcVT = Tmp1.getValueType();
4006 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4007 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4008 bool UseNEON = !InGPR && Subtarget->hasNEON();
4011 // Use VBSL to copy the sign bit.
4012 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4013 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4014 DAG.getTargetConstant(EncodedVal, MVT::i32));
4015 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4017 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4018 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4019 DAG.getConstant(32, MVT::i32));
4020 else /*if (VT == MVT::f32)*/
4021 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4022 if (SrcVT == MVT::f32) {
4023 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4025 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4026 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4027 DAG.getConstant(32, MVT::i32));
4028 } else if (VT == MVT::f32)
4029 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4030 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4031 DAG.getConstant(32, MVT::i32));
4032 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4033 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4035 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4037 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4038 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4039 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4041 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4042 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4043 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4044 if (VT == MVT::f32) {
4045 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4046 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4047 DAG.getConstant(0, MVT::i32));
4049 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4055 // Bitcast operand 1 to i32.
4056 if (SrcVT == MVT::f64)
4057 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4059 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4061 // Or in the signbit with integer operations.
4062 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
4063 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
4064 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4065 if (VT == MVT::f32) {
4066 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4067 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4068 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4069 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4072 // f64: Or the high part with signbit and then combine two parts.
4073 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4075 SDValue Lo = Tmp0.getValue(0);
4076 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4077 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4078 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4081 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4082 MachineFunction &MF = DAG.getMachineFunction();
4083 MachineFrameInfo *MFI = MF.getFrameInfo();
4084 MFI->setReturnAddressIsTaken(true);
4086 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
4089 EVT VT = Op.getValueType();
4091 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4093 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4094 SDValue Offset = DAG.getConstant(4, MVT::i32);
4095 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
4096 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
4097 MachinePointerInfo(), false, false, false, 0);
4100 // Return LR, which contains the return address. Mark it an implicit live-in.
4101 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4102 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
4105 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
4106 const ARMBaseRegisterInfo &ARI =
4107 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
4108 MachineFunction &MF = DAG.getMachineFunction();
4109 MachineFrameInfo *MFI = MF.getFrameInfo();
4110 MFI->setFrameAddressIsTaken(true);
4112 EVT VT = Op.getValueType();
4113 SDLoc dl(Op); // FIXME probably not meaningful
4114 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4115 unsigned FrameReg = ARI.getFrameRegister(MF);
4116 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
4118 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
4119 MachinePointerInfo(),
4120 false, false, false, 0);
4124 // FIXME? Maybe this could be a TableGen attribute on some registers and
4125 // this table could be generated automatically from RegInfo.
4126 unsigned ARMTargetLowering::getRegisterByName(const char* RegName,
4128 unsigned Reg = StringSwitch<unsigned>(RegName)
4129 .Case("sp", ARM::SP)
4133 report_fatal_error("Invalid register name global variable");
4136 /// ExpandBITCAST - If the target supports VFP, this function is called to
4137 /// expand a bit convert where either the source or destination type is i64 to
4138 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
4139 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
4140 /// vectors), since the legalizer won't know what to do with that.
4141 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
4142 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4144 SDValue Op = N->getOperand(0);
4146 // This function is only supposed to be called for i64 types, either as the
4147 // source or destination of the bit convert.
4148 EVT SrcVT = Op.getValueType();
4149 EVT DstVT = N->getValueType(0);
4150 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
4151 "ExpandBITCAST called for non-i64 type");
4153 // Turn i64->f64 into VMOVDRR.
4154 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
4155 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4156 DAG.getConstant(0, MVT::i32));
4157 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4158 DAG.getConstant(1, MVT::i32));
4159 return DAG.getNode(ISD::BITCAST, dl, DstVT,
4160 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
4163 // Turn f64->i64 into VMOVRRD.
4164 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
4166 if (TLI.isBigEndian() && SrcVT.isVector() &&
4167 SrcVT.getVectorNumElements() > 1)
4168 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4169 DAG.getVTList(MVT::i32, MVT::i32),
4170 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
4172 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4173 DAG.getVTList(MVT::i32, MVT::i32), Op);
4174 // Merge the pieces into a single i64 value.
4175 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
4181 /// getZeroVector - Returns a vector of specified type with all zero elements.
4182 /// Zero vectors are used to represent vector negation and in those cases
4183 /// will be implemented with the NEON VNEG instruction. However, VNEG does
4184 /// not support i64 elements, so sometimes the zero vectors will need to be
4185 /// explicitly constructed. Regardless, use a canonical VMOV to create the
4187 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
4188 assert(VT.isVector() && "Expected a vector type");
4189 // The canonical modified immediate encoding of a zero vector is....0!
4190 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
4191 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
4192 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
4193 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4196 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4197 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4198 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
4199 SelectionDAG &DAG) const {
4200 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4201 EVT VT = Op.getValueType();
4202 unsigned VTBits = VT.getSizeInBits();
4204 SDValue ShOpLo = Op.getOperand(0);
4205 SDValue ShOpHi = Op.getOperand(1);
4206 SDValue ShAmt = Op.getOperand(2);
4208 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4210 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4212 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4213 DAG.getConstant(VTBits, MVT::i32), ShAmt);
4214 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4215 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4216 DAG.getConstant(VTBits, MVT::i32));
4217 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4218 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4219 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4221 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4222 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
4224 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4225 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
4228 SDValue Ops[2] = { Lo, Hi };
4229 return DAG.getMergeValues(Ops, dl);
4232 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4233 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4234 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
4235 SelectionDAG &DAG) const {
4236 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4237 EVT VT = Op.getValueType();
4238 unsigned VTBits = VT.getSizeInBits();
4240 SDValue ShOpLo = Op.getOperand(0);
4241 SDValue ShOpHi = Op.getOperand(1);
4242 SDValue ShAmt = Op.getOperand(2);
4245 assert(Op.getOpcode() == ISD::SHL_PARTS);
4246 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4247 DAG.getConstant(VTBits, MVT::i32), ShAmt);
4248 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4249 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4250 DAG.getConstant(VTBits, MVT::i32));
4251 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4252 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4254 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4255 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4256 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
4258 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4259 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
4262 SDValue Ops[2] = { Lo, Hi };
4263 return DAG.getMergeValues(Ops, dl);
4266 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4267 SelectionDAG &DAG) const {
4268 // The rounding mode is in bits 23:22 of the FPSCR.
4269 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
4270 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4271 // so that the shift + and get folded into a bitfield extract.
4273 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
4274 DAG.getConstant(Intrinsic::arm_get_fpscr,
4276 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
4277 DAG.getConstant(1U << 22, MVT::i32));
4278 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
4279 DAG.getConstant(22, MVT::i32));
4280 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
4281 DAG.getConstant(3, MVT::i32));
4284 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
4285 const ARMSubtarget *ST) {
4286 EVT VT = N->getValueType(0);
4289 if (!ST->hasV6T2Ops())
4292 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
4293 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
4296 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
4297 /// for each 16-bit element from operand, repeated. The basic idea is to
4298 /// leverage vcnt to get the 8-bit counts, gather and add the results.
4300 /// Trace for v4i16:
4301 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4302 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
4303 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
4304 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
4305 /// [b0 b1 b2 b3 b4 b5 b6 b7]
4306 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
4307 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4308 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
4309 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
4310 EVT VT = N->getValueType(0);
4313 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4314 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
4315 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
4316 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4317 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4318 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
4321 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
4322 /// bit-count for each 16-bit element from the operand. We need slightly
4323 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
4324 /// 64/128-bit registers.
4326 /// Trace for v4i16:
4327 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4328 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
4329 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
4330 /// v4i16:Extracted = [k0 k1 k2 k3 ]
4331 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
4332 EVT VT = N->getValueType(0);
4335 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
4336 if (VT.is64BitVector()) {
4337 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
4338 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
4339 DAG.getIntPtrConstant(0));
4341 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
4342 BitCounts, DAG.getIntPtrConstant(0));
4343 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
4347 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
4348 /// bit-count for each 32-bit element from the operand. The idea here is
4349 /// to split the vector into 16-bit elements, leverage the 16-bit count
4350 /// routine, and then combine the results.
4352 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4353 /// input = [v0 v1 ] (vi: 32-bit elements)
4354 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4355 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
4356 /// vrev: N0 = [k1 k0 k3 k2 ]
4358 /// N1 =+[k1 k0 k3 k2 ]
4360 /// N2 =+[k1 k3 k0 k2 ]
4362 /// Extended =+[k1 k3 k0 k2 ]
4364 /// Extracted=+[k1 k3 ]
4366 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4367 EVT VT = N->getValueType(0);
4370 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4372 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4373 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4374 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4375 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4376 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4378 if (VT.is64BitVector()) {
4379 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4380 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4381 DAG.getIntPtrConstant(0));
4383 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4384 DAG.getIntPtrConstant(0));
4385 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4389 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4390 const ARMSubtarget *ST) {
4391 EVT VT = N->getValueType(0);
4393 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4394 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4395 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4396 "Unexpected type for custom ctpop lowering");
4398 if (VT.getVectorElementType() == MVT::i32)
4399 return lowerCTPOP32BitElements(N, DAG);
4401 return lowerCTPOP16BitElements(N, DAG);
4404 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4405 const ARMSubtarget *ST) {
4406 EVT VT = N->getValueType(0);
4412 // Lower vector shifts on NEON to use VSHL.
4413 assert(ST->hasNEON() && "unexpected vector shift");
4415 // Left shifts translate directly to the vshiftu intrinsic.
4416 if (N->getOpcode() == ISD::SHL)
4417 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4418 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
4419 N->getOperand(0), N->getOperand(1));
4421 assert((N->getOpcode() == ISD::SRA ||
4422 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4424 // NEON uses the same intrinsics for both left and right shifts. For
4425 // right shifts, the shift amounts are negative, so negate the vector of
4427 EVT ShiftVT = N->getOperand(1).getValueType();
4428 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4429 getZeroVector(ShiftVT, DAG, dl),
4431 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4432 Intrinsic::arm_neon_vshifts :
4433 Intrinsic::arm_neon_vshiftu);
4434 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4435 DAG.getConstant(vshiftInt, MVT::i32),
4436 N->getOperand(0), NegatedCount);
4439 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4440 const ARMSubtarget *ST) {
4441 EVT VT = N->getValueType(0);
4444 // We can get here for a node like i32 = ISD::SHL i32, i64
4448 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4449 "Unknown shift to lower!");
4451 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4452 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
4453 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
4456 // If we are in thumb mode, we don't have RRX.
4457 if (ST->isThumb1Only()) return SDValue();
4459 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4460 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4461 DAG.getConstant(0, MVT::i32));
4462 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4463 DAG.getConstant(1, MVT::i32));
4465 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4466 // captures the result into a carry flag.
4467 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4468 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
4470 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4471 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4473 // Merge the pieces into a single i64 value.
4474 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4477 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4478 SDValue TmpOp0, TmpOp1;
4479 bool Invert = false;
4483 SDValue Op0 = Op.getOperand(0);
4484 SDValue Op1 = Op.getOperand(1);
4485 SDValue CC = Op.getOperand(2);
4486 EVT VT = Op.getValueType();
4487 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4490 if (Op1.getValueType().isFloatingPoint()) {
4491 switch (SetCCOpcode) {
4492 default: llvm_unreachable("Illegal FP comparison");
4494 case ISD::SETNE: Invert = true; // Fallthrough
4496 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4498 case ISD::SETLT: Swap = true; // Fallthrough
4500 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4502 case ISD::SETLE: Swap = true; // Fallthrough
4504 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4505 case ISD::SETUGE: Swap = true; // Fallthrough
4506 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4507 case ISD::SETUGT: Swap = true; // Fallthrough
4508 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4509 case ISD::SETUEQ: Invert = true; // Fallthrough
4511 // Expand this to (OLT | OGT).
4515 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4516 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
4518 case ISD::SETUO: Invert = true; // Fallthrough
4520 // Expand this to (OLT | OGE).
4524 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4525 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
4529 // Integer comparisons.
4530 switch (SetCCOpcode) {
4531 default: llvm_unreachable("Illegal integer comparison");
4532 case ISD::SETNE: Invert = true;
4533 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4534 case ISD::SETLT: Swap = true;
4535 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4536 case ISD::SETLE: Swap = true;
4537 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4538 case ISD::SETULT: Swap = true;
4539 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4540 case ISD::SETULE: Swap = true;
4541 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4544 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4545 if (Opc == ARMISD::VCEQ) {
4548 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4550 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4553 // Ignore bitconvert.
4554 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4555 AndOp = AndOp.getOperand(0);
4557 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4559 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
4560 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
4567 std::swap(Op0, Op1);
4569 // If one of the operands is a constant vector zero, attempt to fold the
4570 // comparison to a specialized compare-against-zero form.
4572 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4574 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4575 if (Opc == ARMISD::VCGE)
4576 Opc = ARMISD::VCLEZ;
4577 else if (Opc == ARMISD::VCGT)
4578 Opc = ARMISD::VCLTZ;
4583 if (SingleOp.getNode()) {
4586 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
4588 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
4590 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
4592 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
4594 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
4596 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4599 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4603 Result = DAG.getNOT(dl, Result, VT);
4608 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
4609 /// valid vector constant for a NEON instruction with a "modified immediate"
4610 /// operand (e.g., VMOV). If so, return the encoded value.
4611 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4612 unsigned SplatBitSize, SelectionDAG &DAG,
4613 EVT &VT, bool is128Bits, NEONModImmType type) {
4614 unsigned OpCmode, Imm;
4616 // SplatBitSize is set to the smallest size that splats the vector, so a
4617 // zero vector will always have SplatBitSize == 8. However, NEON modified
4618 // immediate instructions others than VMOV do not support the 8-bit encoding
4619 // of a zero vector, and the default encoding of zero is supposed to be the
4624 switch (SplatBitSize) {
4626 if (type != VMOVModImm)
4628 // Any 1-byte value is OK. Op=0, Cmode=1110.
4629 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4632 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4636 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4637 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4638 if ((SplatBits & ~0xff) == 0) {
4639 // Value = 0x00nn: Op=x, Cmode=100x.
4644 if ((SplatBits & ~0xff00) == 0) {
4645 // Value = 0xnn00: Op=x, Cmode=101x.
4647 Imm = SplatBits >> 8;
4653 // NEON's 32-bit VMOV supports splat values where:
4654 // * only one byte is nonzero, or
4655 // * the least significant byte is 0xff and the second byte is nonzero, or
4656 // * the least significant 2 bytes are 0xff and the third is nonzero.
4657 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4658 if ((SplatBits & ~0xff) == 0) {
4659 // Value = 0x000000nn: Op=x, Cmode=000x.
4664 if ((SplatBits & ~0xff00) == 0) {
4665 // Value = 0x0000nn00: Op=x, Cmode=001x.
4667 Imm = SplatBits >> 8;
4670 if ((SplatBits & ~0xff0000) == 0) {
4671 // Value = 0x00nn0000: Op=x, Cmode=010x.
4673 Imm = SplatBits >> 16;
4676 if ((SplatBits & ~0xff000000) == 0) {
4677 // Value = 0xnn000000: Op=x, Cmode=011x.
4679 Imm = SplatBits >> 24;
4683 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4684 if (type == OtherModImm) return SDValue();
4686 if ((SplatBits & ~0xffff) == 0 &&
4687 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4688 // Value = 0x0000nnff: Op=x, Cmode=1100.
4690 Imm = SplatBits >> 8;
4694 if ((SplatBits & ~0xffffff) == 0 &&
4695 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4696 // Value = 0x00nnffff: Op=x, Cmode=1101.
4698 Imm = SplatBits >> 16;
4702 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4703 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4704 // VMOV.I32. A (very) minor optimization would be to replicate the value
4705 // and fall through here to test for a valid 64-bit splat. But, then the
4706 // caller would also need to check and handle the change in size.
4710 if (type != VMOVModImm)
4712 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4713 uint64_t BitMask = 0xff;
4715 unsigned ImmMask = 1;
4717 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4718 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4721 } else if ((SplatBits & BitMask) != 0) {
4728 if (DAG.getTargetLoweringInfo().isBigEndian())
4729 // swap higher and lower 32 bit word
4730 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
4732 // Op=1, Cmode=1110.
4734 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4739 llvm_unreachable("unexpected size for isNEONModifiedImm");
4742 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4743 return DAG.getTargetConstant(EncodedVal, MVT::i32);
4746 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4747 const ARMSubtarget *ST) const {
4751 bool IsDouble = Op.getValueType() == MVT::f64;
4752 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4754 // Use the default (constant pool) lowering for double constants when we have
4756 if (IsDouble && Subtarget->isFPOnlySP())
4759 // Try splatting with a VMOV.f32...
4760 APFloat FPVal = CFP->getValueAPF();
4761 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4764 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4765 // We have code in place to select a valid ConstantFP already, no need to
4770 // It's a float and we are trying to use NEON operations where
4771 // possible. Lower it to a splat followed by an extract.
4773 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4774 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4776 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4777 DAG.getConstant(0, MVT::i32));
4780 // The rest of our options are NEON only, make sure that's allowed before
4782 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4786 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4788 // It wouldn't really be worth bothering for doubles except for one very
4789 // important value, which does happen to match: 0.0. So make sure we don't do
4791 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4794 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4795 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4797 if (NewVal != SDValue()) {
4799 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4802 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4804 // It's a float: cast and extract a vector element.
4805 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4807 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4808 DAG.getConstant(0, MVT::i32));
4811 // Finally, try a VMVN.i32
4812 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4814 if (NewVal != SDValue()) {
4816 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4819 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4821 // It's a float: cast and extract a vector element.
4822 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4824 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4825 DAG.getConstant(0, MVT::i32));
4831 // check if an VEXT instruction can handle the shuffle mask when the
4832 // vector sources of the shuffle are the same.
4833 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4834 unsigned NumElts = VT.getVectorNumElements();
4836 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4842 // If this is a VEXT shuffle, the immediate value is the index of the first
4843 // element. The other shuffle indices must be the successive elements after
4845 unsigned ExpectedElt = Imm;
4846 for (unsigned i = 1; i < NumElts; ++i) {
4847 // Increment the expected index. If it wraps around, just follow it
4848 // back to index zero and keep going.
4850 if (ExpectedElt == NumElts)
4853 if (M[i] < 0) continue; // ignore UNDEF indices
4854 if (ExpectedElt != static_cast<unsigned>(M[i]))
4862 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4863 bool &ReverseVEXT, unsigned &Imm) {
4864 unsigned NumElts = VT.getVectorNumElements();
4865 ReverseVEXT = false;
4867 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4873 // If this is a VEXT shuffle, the immediate value is the index of the first
4874 // element. The other shuffle indices must be the successive elements after
4876 unsigned ExpectedElt = Imm;
4877 for (unsigned i = 1; i < NumElts; ++i) {
4878 // Increment the expected index. If it wraps around, it may still be
4879 // a VEXT but the source vectors must be swapped.
4881 if (ExpectedElt == NumElts * 2) {
4886 if (M[i] < 0) continue; // ignore UNDEF indices
4887 if (ExpectedElt != static_cast<unsigned>(M[i]))
4891 // Adjust the index value if the source operands will be swapped.
4898 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
4899 /// instruction with the specified blocksize. (The order of the elements
4900 /// within each block of the vector is reversed.)
4901 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4902 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4903 "Only possible block sizes for VREV are: 16, 32, 64");
4905 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4909 unsigned NumElts = VT.getVectorNumElements();
4910 unsigned BlockElts = M[0] + 1;
4911 // If the first shuffle index is UNDEF, be optimistic.
4913 BlockElts = BlockSize / EltSz;
4915 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4918 for (unsigned i = 0; i < NumElts; ++i) {
4919 if (M[i] < 0) continue; // ignore UNDEF indices
4920 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
4927 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
4928 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
4929 // range, then 0 is placed into the resulting vector. So pretty much any mask
4930 // of 8 elements can work here.
4931 return VT == MVT::v8i8 && M.size() == 8;
4934 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4935 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4939 unsigned NumElts = VT.getVectorNumElements();
4940 WhichResult = (M[0] == 0 ? 0 : 1);
4941 for (unsigned i = 0; i < NumElts; i += 2) {
4942 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4943 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
4949 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4950 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4951 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4952 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4953 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4957 unsigned NumElts = VT.getVectorNumElements();
4958 WhichResult = (M[0] == 0 ? 0 : 1);
4959 for (unsigned i = 0; i < NumElts; i += 2) {
4960 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4961 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
4967 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4968 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4972 unsigned NumElts = VT.getVectorNumElements();
4973 WhichResult = (M[0] == 0 ? 0 : 1);
4974 for (unsigned i = 0; i != NumElts; ++i) {
4975 if (M[i] < 0) continue; // ignore UNDEF indices
4976 if ((unsigned) M[i] != 2 * i + WhichResult)
4980 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4981 if (VT.is64BitVector() && EltSz == 32)
4987 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4988 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4989 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4990 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4991 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4995 unsigned Half = VT.getVectorNumElements() / 2;
4996 WhichResult = (M[0] == 0 ? 0 : 1);
4997 for (unsigned j = 0; j != 2; ++j) {
4998 unsigned Idx = WhichResult;
4999 for (unsigned i = 0; i != Half; ++i) {
5000 int MIdx = M[i + j * Half];
5001 if (MIdx >= 0 && (unsigned) MIdx != Idx)
5007 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5008 if (VT.is64BitVector() && EltSz == 32)
5014 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5015 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5019 unsigned NumElts = VT.getVectorNumElements();
5020 WhichResult = (M[0] == 0 ? 0 : 1);
5021 unsigned Idx = WhichResult * NumElts / 2;
5022 for (unsigned i = 0; i != NumElts; i += 2) {
5023 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
5024 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
5029 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5030 if (VT.is64BitVector() && EltSz == 32)
5036 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
5037 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5038 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5039 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5040 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5044 unsigned NumElts = VT.getVectorNumElements();
5045 WhichResult = (M[0] == 0 ? 0 : 1);
5046 unsigned Idx = WhichResult * NumElts / 2;
5047 for (unsigned i = 0; i != NumElts; i += 2) {
5048 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
5049 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
5054 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5055 if (VT.is64BitVector() && EltSz == 32)
5061 /// \return true if this is a reverse operation on an vector.
5062 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
5063 unsigned NumElts = VT.getVectorNumElements();
5064 // Make sure the mask has the right size.
5065 if (NumElts != M.size())
5068 // Look for <15, ..., 3, -1, 1, 0>.
5069 for (unsigned i = 0; i != NumElts; ++i)
5070 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
5076 // If N is an integer constant that can be moved into a register in one
5077 // instruction, return an SDValue of such a constant (will become a MOV
5078 // instruction). Otherwise return null.
5079 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
5080 const ARMSubtarget *ST, SDLoc dl) {
5082 if (!isa<ConstantSDNode>(N))
5084 Val = cast<ConstantSDNode>(N)->getZExtValue();
5086 if (ST->isThumb1Only()) {
5087 if (Val <= 255 || ~Val <= 255)
5088 return DAG.getConstant(Val, MVT::i32);
5090 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
5091 return DAG.getConstant(Val, MVT::i32);
5096 // If this is a case we can't handle, return null and let the default
5097 // expansion code take care of it.
5098 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
5099 const ARMSubtarget *ST) const {
5100 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5102 EVT VT = Op.getValueType();
5104 APInt SplatBits, SplatUndef;
5105 unsigned SplatBitSize;
5107 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5108 if (SplatBitSize <= 64) {
5109 // Check if an immediate VMOV works.
5111 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5112 SplatUndef.getZExtValue(), SplatBitSize,
5113 DAG, VmovVT, VT.is128BitVector(),
5115 if (Val.getNode()) {
5116 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
5117 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5120 // Try an immediate VMVN.
5121 uint64_t NegatedImm = (~SplatBits).getZExtValue();
5122 Val = isNEONModifiedImm(NegatedImm,
5123 SplatUndef.getZExtValue(), SplatBitSize,
5124 DAG, VmovVT, VT.is128BitVector(),
5126 if (Val.getNode()) {
5127 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
5128 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5131 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
5132 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
5133 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
5135 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
5136 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
5142 // Scan through the operands to see if only one value is used.
5144 // As an optimisation, even if more than one value is used it may be more
5145 // profitable to splat with one value then change some lanes.
5147 // Heuristically we decide to do this if the vector has a "dominant" value,
5148 // defined as splatted to more than half of the lanes.
5149 unsigned NumElts = VT.getVectorNumElements();
5150 bool isOnlyLowElement = true;
5151 bool usesOnlyOneValue = true;
5152 bool hasDominantValue = false;
5153 bool isConstant = true;
5155 // Map of the number of times a particular SDValue appears in the
5157 DenseMap<SDValue, unsigned> ValueCounts;
5159 for (unsigned i = 0; i < NumElts; ++i) {
5160 SDValue V = Op.getOperand(i);
5161 if (V.getOpcode() == ISD::UNDEF)
5164 isOnlyLowElement = false;
5165 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5168 ValueCounts.insert(std::make_pair(V, 0));
5169 unsigned &Count = ValueCounts[V];
5171 // Is this value dominant? (takes up more than half of the lanes)
5172 if (++Count > (NumElts / 2)) {
5173 hasDominantValue = true;
5177 if (ValueCounts.size() != 1)
5178 usesOnlyOneValue = false;
5179 if (!Value.getNode() && ValueCounts.size() > 0)
5180 Value = ValueCounts.begin()->first;
5182 if (ValueCounts.size() == 0)
5183 return DAG.getUNDEF(VT);
5185 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5186 // Keep going if we are hitting this case.
5187 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
5188 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5190 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5192 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
5193 // i32 and try again.
5194 if (hasDominantValue && EltSize <= 32) {
5198 // If we are VDUPing a value that comes directly from a vector, that will
5199 // cause an unnecessary move to and from a GPR, where instead we could
5200 // just use VDUPLANE. We can only do this if the lane being extracted
5201 // is at a constant index, as the VDUP from lane instructions only have
5202 // constant-index forms.
5203 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5204 isa<ConstantSDNode>(Value->getOperand(1))) {
5205 // We need to create a new undef vector to use for the VDUPLANE if the
5206 // size of the vector from which we get the value is different than the
5207 // size of the vector that we need to create. We will insert the element
5208 // such that the register coalescer will remove unnecessary copies.
5209 if (VT != Value->getOperand(0).getValueType()) {
5210 ConstantSDNode *constIndex;
5211 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
5212 assert(constIndex && "The index is not a constant!");
5213 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
5214 VT.getVectorNumElements();
5215 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5216 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5217 Value, DAG.getConstant(index, MVT::i32)),
5218 DAG.getConstant(index, MVT::i32));
5220 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5221 Value->getOperand(0), Value->getOperand(1));
5223 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5225 if (!usesOnlyOneValue) {
5226 // The dominant value was splatted as 'N', but we now have to insert
5227 // all differing elements.
5228 for (unsigned I = 0; I < NumElts; ++I) {
5229 if (Op.getOperand(I) == Value)
5231 SmallVector<SDValue, 3> Ops;
5233 Ops.push_back(Op.getOperand(I));
5234 Ops.push_back(DAG.getConstant(I, MVT::i32));
5235 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5240 if (VT.getVectorElementType().isFloatingPoint()) {
5241 SmallVector<SDValue, 8> Ops;
5242 for (unsigned i = 0; i < NumElts; ++i)
5243 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
5245 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
5246 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5247 Val = LowerBUILD_VECTOR(Val, DAG, ST);
5249 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5251 if (usesOnlyOneValue) {
5252 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
5253 if (isConstant && Val.getNode())
5254 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
5258 // If all elements are constants and the case above didn't get hit, fall back
5259 // to the default expansion, which will generate a load from the constant
5264 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5266 SDValue shuffle = ReconstructShuffle(Op, DAG);
5267 if (shuffle != SDValue())
5271 // Vectors with 32- or 64-bit elements can be built by directly assigning
5272 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5273 // will be legalized.
5274 if (EltSize >= 32) {
5275 // Do the expansion with floating-point types, since that is what the VFP
5276 // registers are defined to use, and since i64 is not legal.
5277 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5278 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5279 SmallVector<SDValue, 8> Ops;
5280 for (unsigned i = 0; i < NumElts; ++i)
5281 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
5282 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5283 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5286 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5287 // know the default expansion would otherwise fall back on something even
5288 // worse. For a vector with one or two non-undef values, that's
5289 // scalar_to_vector for the elements followed by a shuffle (provided the
5290 // shuffle is valid for the target) and materialization element by element
5291 // on the stack followed by a load for everything else.
5292 if (!isConstant && !usesOnlyOneValue) {
5293 SDValue Vec = DAG.getUNDEF(VT);
5294 for (unsigned i = 0 ; i < NumElts; ++i) {
5295 SDValue V = Op.getOperand(i);
5296 if (V.getOpcode() == ISD::UNDEF)
5298 SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
5299 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5307 // Gather data to see if the operation can be modelled as a
5308 // shuffle in combination with VEXTs.
5309 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
5310 SelectionDAG &DAG) const {
5312 EVT VT = Op.getValueType();
5313 unsigned NumElts = VT.getVectorNumElements();
5315 SmallVector<SDValue, 2> SourceVecs;
5316 SmallVector<unsigned, 2> MinElts;
5317 SmallVector<unsigned, 2> MaxElts;
5319 for (unsigned i = 0; i < NumElts; ++i) {
5320 SDValue V = Op.getOperand(i);
5321 if (V.getOpcode() == ISD::UNDEF)
5323 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
5324 // A shuffle can only come from building a vector from various
5325 // elements of other vectors.
5327 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
5328 VT.getVectorElementType()) {
5329 // This code doesn't know how to handle shuffles where the vector
5330 // element types do not match (this happens because type legalization
5331 // promotes the return type of EXTRACT_VECTOR_ELT).
5332 // FIXME: It might be appropriate to extend this code to handle
5333 // mismatched types.
5337 // Record this extraction against the appropriate vector if possible...
5338 SDValue SourceVec = V.getOperand(0);
5339 // If the element number isn't a constant, we can't effectively
5340 // analyze what's going on.
5341 if (!isa<ConstantSDNode>(V.getOperand(1)))
5343 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5344 bool FoundSource = false;
5345 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
5346 if (SourceVecs[j] == SourceVec) {
5347 if (MinElts[j] > EltNo)
5349 if (MaxElts[j] < EltNo)
5356 // Or record a new source if not...
5358 SourceVecs.push_back(SourceVec);
5359 MinElts.push_back(EltNo);
5360 MaxElts.push_back(EltNo);
5364 // Currently only do something sane when at most two source vectors
5366 if (SourceVecs.size() > 2)
5369 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
5370 int VEXTOffsets[2] = {0, 0};
5372 // This loop extracts the usage patterns of the source vectors
5373 // and prepares appropriate SDValues for a shuffle if possible.
5374 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5375 if (SourceVecs[i].getValueType() == VT) {
5376 // No VEXT necessary
5377 ShuffleSrcs[i] = SourceVecs[i];
5380 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5381 // It probably isn't worth padding out a smaller vector just to
5382 // break it down again in a shuffle.
5386 // Since only 64-bit and 128-bit vectors are legal on ARM and
5387 // we've eliminated the other cases...
5388 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5389 "unexpected vector sizes in ReconstructShuffle");
5391 if (MaxElts[i] - MinElts[i] >= NumElts) {
5392 // Span too large for a VEXT to cope
5396 if (MinElts[i] >= NumElts) {
5397 // The extraction can just take the second half
5398 VEXTOffsets[i] = NumElts;
5399 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5401 DAG.getIntPtrConstant(NumElts));
5402 } else if (MaxElts[i] < NumElts) {
5403 // The extraction can just take the first half
5405 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5407 DAG.getIntPtrConstant(0));
5409 // An actual VEXT is needed
5410 VEXTOffsets[i] = MinElts[i];
5411 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5413 DAG.getIntPtrConstant(0));
5414 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5416 DAG.getIntPtrConstant(NumElts));
5417 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5418 DAG.getConstant(VEXTOffsets[i], MVT::i32));
5422 SmallVector<int, 8> Mask;
5424 for (unsigned i = 0; i < NumElts; ++i) {
5425 SDValue Entry = Op.getOperand(i);
5426 if (Entry.getOpcode() == ISD::UNDEF) {
5431 SDValue ExtractVec = Entry.getOperand(0);
5432 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5433 .getOperand(1))->getSExtValue();
5434 if (ExtractVec == SourceVecs[0]) {
5435 Mask.push_back(ExtractElt - VEXTOffsets[0]);
5437 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5441 // Final check before we try to produce nonsense...
5442 if (isShuffleMaskLegal(Mask, VT))
5443 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5449 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5450 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5451 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5452 /// are assumed to be legal.
5454 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5456 if (VT.getVectorNumElements() == 4 &&
5457 (VT.is128BitVector() || VT.is64BitVector())) {
5458 unsigned PFIndexes[4];
5459 for (unsigned i = 0; i != 4; ++i) {
5463 PFIndexes[i] = M[i];
5466 // Compute the index in the perfect shuffle table.
5467 unsigned PFTableIndex =
5468 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5469 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5470 unsigned Cost = (PFEntry >> 30);
5477 unsigned Imm, WhichResult;
5479 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5480 return (EltSize >= 32 ||
5481 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5482 isVREVMask(M, VT, 64) ||
5483 isVREVMask(M, VT, 32) ||
5484 isVREVMask(M, VT, 16) ||
5485 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5486 isVTBLMask(M, VT) ||
5487 isVTRNMask(M, VT, WhichResult) ||
5488 isVUZPMask(M, VT, WhichResult) ||
5489 isVZIPMask(M, VT, WhichResult) ||
5490 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
5491 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
5492 isVZIP_v_undef_Mask(M, VT, WhichResult) ||
5493 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5496 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5497 /// the specified operations to build the shuffle.
5498 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5499 SDValue RHS, SelectionDAG &DAG,
5501 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5502 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5503 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5506 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5515 OP_VUZPL, // VUZP, left result
5516 OP_VUZPR, // VUZP, right result
5517 OP_VZIPL, // VZIP, left result
5518 OP_VZIPR, // VZIP, right result
5519 OP_VTRNL, // VTRN, left result
5520 OP_VTRNR // VTRN, right result
5523 if (OpNum == OP_COPY) {
5524 if (LHSID == (1*9+2)*9+3) return LHS;
5525 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5529 SDValue OpLHS, OpRHS;
5530 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5531 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5532 EVT VT = OpLHS.getValueType();
5535 default: llvm_unreachable("Unknown shuffle opcode!");
5537 // VREV divides the vector in half and swaps within the half.
5538 if (VT.getVectorElementType() == MVT::i32 ||
5539 VT.getVectorElementType() == MVT::f32)
5540 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5541 // vrev <4 x i16> -> VREV32
5542 if (VT.getVectorElementType() == MVT::i16)
5543 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5544 // vrev <4 x i8> -> VREV16
5545 assert(VT.getVectorElementType() == MVT::i8);
5546 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5551 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5552 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
5556 return DAG.getNode(ARMISD::VEXT, dl, VT,
5558 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
5561 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5562 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5565 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5566 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5569 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5570 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5574 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5575 ArrayRef<int> ShuffleMask,
5576 SelectionDAG &DAG) {
5577 // Check to see if we can use the VTBL instruction.
5578 SDValue V1 = Op.getOperand(0);
5579 SDValue V2 = Op.getOperand(1);
5582 SmallVector<SDValue, 8> VTBLMask;
5583 for (ArrayRef<int>::iterator
5584 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5585 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
5587 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5588 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5589 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5591 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5592 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5595 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5596 SelectionDAG &DAG) {
5598 SDValue OpLHS = Op.getOperand(0);
5599 EVT VT = OpLHS.getValueType();
5601 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5602 "Expect an v8i16/v16i8 type");
5603 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5604 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5605 // extract the first 8 bytes into the top double word and the last 8 bytes
5606 // into the bottom double word. The v8i16 case is similar.
5607 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5608 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5609 DAG.getConstant(ExtractNum, MVT::i32));
5612 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5613 SDValue V1 = Op.getOperand(0);
5614 SDValue V2 = Op.getOperand(1);
5616 EVT VT = Op.getValueType();
5617 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5619 // Convert shuffles that are directly supported on NEON to target-specific
5620 // DAG nodes, instead of keeping them as shuffles and matching them again
5621 // during code selection. This is more efficient and avoids the possibility
5622 // of inconsistencies between legalization and selection.
5623 // FIXME: floating-point vectors should be canonicalized to integer vectors
5624 // of the same time so that they get CSEd properly.
5625 ArrayRef<int> ShuffleMask = SVN->getMask();
5627 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5628 if (EltSize <= 32) {
5629 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5630 int Lane = SVN->getSplatIndex();
5631 // If this is undef splat, generate it via "just" vdup, if possible.
5632 if (Lane == -1) Lane = 0;
5634 // Test if V1 is a SCALAR_TO_VECTOR.
5635 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5636 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5638 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5639 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5641 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5642 !isa<ConstantSDNode>(V1.getOperand(0))) {
5643 bool IsScalarToVector = true;
5644 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5645 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5646 IsScalarToVector = false;
5649 if (IsScalarToVector)
5650 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5652 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5653 DAG.getConstant(Lane, MVT::i32));
5658 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5661 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5662 DAG.getConstant(Imm, MVT::i32));
5665 if (isVREVMask(ShuffleMask, VT, 64))
5666 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5667 if (isVREVMask(ShuffleMask, VT, 32))
5668 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5669 if (isVREVMask(ShuffleMask, VT, 16))
5670 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5672 if (V2->getOpcode() == ISD::UNDEF &&
5673 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5674 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5675 DAG.getConstant(Imm, MVT::i32));
5678 // Check for Neon shuffles that modify both input vectors in place.
5679 // If both results are used, i.e., if there are two shuffles with the same
5680 // source operands and with masks corresponding to both results of one of
5681 // these operations, DAG memoization will ensure that a single node is
5682 // used for both shuffles.
5683 unsigned WhichResult;
5684 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5685 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5686 V1, V2).getValue(WhichResult);
5687 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5688 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5689 V1, V2).getValue(WhichResult);
5690 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5691 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5692 V1, V2).getValue(WhichResult);
5694 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5695 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5696 V1, V1).getValue(WhichResult);
5697 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5698 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5699 V1, V1).getValue(WhichResult);
5700 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5701 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5702 V1, V1).getValue(WhichResult);
5705 // If the shuffle is not directly supported and it has 4 elements, use
5706 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5707 unsigned NumElts = VT.getVectorNumElements();
5709 unsigned PFIndexes[4];
5710 for (unsigned i = 0; i != 4; ++i) {
5711 if (ShuffleMask[i] < 0)
5714 PFIndexes[i] = ShuffleMask[i];
5717 // Compute the index in the perfect shuffle table.
5718 unsigned PFTableIndex =
5719 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5720 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5721 unsigned Cost = (PFEntry >> 30);
5724 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5727 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
5728 if (EltSize >= 32) {
5729 // Do the expansion with floating-point types, since that is what the VFP
5730 // registers are defined to use, and since i64 is not legal.
5731 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5732 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5733 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5734 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
5735 SmallVector<SDValue, 8> Ops;
5736 for (unsigned i = 0; i < NumElts; ++i) {
5737 if (ShuffleMask[i] < 0)
5738 Ops.push_back(DAG.getUNDEF(EltVT));
5740 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
5741 ShuffleMask[i] < (int)NumElts ? V1 : V2,
5742 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
5745 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5746 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5749 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
5750 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
5752 if (VT == MVT::v8i8) {
5753 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
5754 if (NewOp.getNode())
5761 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5762 // INSERT_VECTOR_ELT is legal only for immediate indexes.
5763 SDValue Lane = Op.getOperand(2);
5764 if (!isa<ConstantSDNode>(Lane))
5770 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5771 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
5772 SDValue Lane = Op.getOperand(1);
5773 if (!isa<ConstantSDNode>(Lane))
5776 SDValue Vec = Op.getOperand(0);
5777 if (Op.getValueType() == MVT::i32 &&
5778 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
5780 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5786 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5787 // The only time a CONCAT_VECTORS operation can have legal types is when
5788 // two 64-bit vectors are concatenated to a 128-bit vector.
5789 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
5790 "unexpected CONCAT_VECTORS");
5792 SDValue Val = DAG.getUNDEF(MVT::v2f64);
5793 SDValue Op0 = Op.getOperand(0);
5794 SDValue Op1 = Op.getOperand(1);
5795 if (Op0.getOpcode() != ISD::UNDEF)
5796 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5797 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
5798 DAG.getIntPtrConstant(0));
5799 if (Op1.getOpcode() != ISD::UNDEF)
5800 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5801 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
5802 DAG.getIntPtrConstant(1));
5803 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
5806 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
5807 /// element has been zero/sign-extended, depending on the isSigned parameter,
5808 /// from an integer type half its size.
5809 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
5811 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
5812 EVT VT = N->getValueType(0);
5813 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5814 SDNode *BVN = N->getOperand(0).getNode();
5815 if (BVN->getValueType(0) != MVT::v4i32 ||
5816 BVN->getOpcode() != ISD::BUILD_VECTOR)
5818 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5819 unsigned HiElt = 1 - LoElt;
5820 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
5821 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
5822 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
5823 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
5824 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
5827 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
5828 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
5831 if (Hi0->isNullValue() && Hi1->isNullValue())
5837 if (N->getOpcode() != ISD::BUILD_VECTOR)
5840 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5841 SDNode *Elt = N->getOperand(i).getNode();
5842 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
5843 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5844 unsigned HalfSize = EltSize / 2;
5846 if (!isIntN(HalfSize, C->getSExtValue()))
5849 if (!isUIntN(HalfSize, C->getZExtValue()))
5860 /// isSignExtended - Check if a node is a vector value that is sign-extended
5861 /// or a constant BUILD_VECTOR with sign-extended elements.
5862 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
5863 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5865 if (isExtendedBUILD_VECTOR(N, DAG, true))
5870 /// isZeroExtended - Check if a node is a vector value that is zero-extended
5871 /// or a constant BUILD_VECTOR with zero-extended elements.
5872 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
5873 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5875 if (isExtendedBUILD_VECTOR(N, DAG, false))
5880 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
5881 if (OrigVT.getSizeInBits() >= 64)
5884 assert(OrigVT.isSimple() && "Expecting a simple value type");
5886 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
5887 switch (OrigSimpleTy) {
5888 default: llvm_unreachable("Unexpected Vector Type");
5897 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
5898 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
5899 /// We insert the required extension here to get the vector to fill a D register.
5900 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
5903 unsigned ExtOpcode) {
5904 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
5905 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
5906 // 64-bits we need to insert a new extension so that it will be 64-bits.
5907 assert(ExtTy.is128BitVector() && "Unexpected extension size");
5908 if (OrigTy.getSizeInBits() >= 64)
5911 // Must extend size to at least 64 bits to be used as an operand for VMULL.
5912 EVT NewVT = getExtensionTo64Bits(OrigTy);
5914 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
5917 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
5918 /// does not do any sign/zero extension. If the original vector is less
5919 /// than 64 bits, an appropriate extension will be added after the load to
5920 /// reach a total size of 64 bits. We have to add the extension separately
5921 /// because ARM does not have a sign/zero extending load for vectors.
5922 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
5923 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
5925 // The load already has the right type.
5926 if (ExtendedTy == LD->getMemoryVT())
5927 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
5928 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
5929 LD->isNonTemporal(), LD->isInvariant(),
5930 LD->getAlignment());
5932 // We need to create a zextload/sextload. We cannot just create a load
5933 // followed by a zext/zext node because LowerMUL is also run during normal
5934 // operation legalization where we can't create illegal types.
5935 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
5936 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
5937 LD->getMemoryVT(), LD->isVolatile(), LD->isInvariant(),
5938 LD->isNonTemporal(), LD->getAlignment());
5941 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
5942 /// extending load, or BUILD_VECTOR with extended elements, return the
5943 /// unextended value. The unextended vector should be 64 bits so that it can
5944 /// be used as an operand to a VMULL instruction. If the original vector size
5945 /// before extension is less than 64 bits we add a an extension to resize
5946 /// the vector to 64 bits.
5947 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
5948 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
5949 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
5950 N->getOperand(0)->getValueType(0),
5954 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
5955 return SkipLoadExtensionForVMULL(LD, DAG);
5957 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
5958 // have been legalized as a BITCAST from v4i32.
5959 if (N->getOpcode() == ISD::BITCAST) {
5960 SDNode *BVN = N->getOperand(0).getNode();
5961 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5962 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5963 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5964 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
5965 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
5967 // Construct a new BUILD_VECTOR with elements truncated to half the size.
5968 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5969 EVT VT = N->getValueType(0);
5970 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
5971 unsigned NumElts = VT.getVectorNumElements();
5972 MVT TruncVT = MVT::getIntegerVT(EltSize);
5973 SmallVector<SDValue, 8> Ops;
5974 for (unsigned i = 0; i != NumElts; ++i) {
5975 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
5976 const APInt &CInt = C->getAPIntValue();
5977 // Element types smaller than 32 bits are not legal, so use i32 elements.
5978 // The values are implicitly truncated so sext vs. zext doesn't matter.
5979 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
5981 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
5982 MVT::getVectorVT(TruncVT, NumElts), Ops);
5985 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
5986 unsigned Opcode = N->getOpcode();
5987 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5988 SDNode *N0 = N->getOperand(0).getNode();
5989 SDNode *N1 = N->getOperand(1).getNode();
5990 return N0->hasOneUse() && N1->hasOneUse() &&
5991 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5996 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
5997 unsigned Opcode = N->getOpcode();
5998 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5999 SDNode *N0 = N->getOperand(0).getNode();
6000 SDNode *N1 = N->getOperand(1).getNode();
6001 return N0->hasOneUse() && N1->hasOneUse() &&
6002 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
6007 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
6008 // Multiplications are only custom-lowered for 128-bit vectors so that
6009 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
6010 EVT VT = Op.getValueType();
6011 assert(VT.is128BitVector() && VT.isInteger() &&
6012 "unexpected type for custom-lowering ISD::MUL");
6013 SDNode *N0 = Op.getOperand(0).getNode();
6014 SDNode *N1 = Op.getOperand(1).getNode();
6015 unsigned NewOpc = 0;
6017 bool isN0SExt = isSignExtended(N0, DAG);
6018 bool isN1SExt = isSignExtended(N1, DAG);
6019 if (isN0SExt && isN1SExt)
6020 NewOpc = ARMISD::VMULLs;
6022 bool isN0ZExt = isZeroExtended(N0, DAG);
6023 bool isN1ZExt = isZeroExtended(N1, DAG);
6024 if (isN0ZExt && isN1ZExt)
6025 NewOpc = ARMISD::VMULLu;
6026 else if (isN1SExt || isN1ZExt) {
6027 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
6028 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
6029 if (isN1SExt && isAddSubSExt(N0, DAG)) {
6030 NewOpc = ARMISD::VMULLs;
6032 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
6033 NewOpc = ARMISD::VMULLu;
6035 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
6037 NewOpc = ARMISD::VMULLu;
6043 if (VT == MVT::v2i64)
6044 // Fall through to expand this. It is not legal.
6047 // Other vector multiplications are legal.
6052 // Legalize to a VMULL instruction.
6055 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
6057 Op0 = SkipExtensionForVMULL(N0, DAG);
6058 assert(Op0.getValueType().is64BitVector() &&
6059 Op1.getValueType().is64BitVector() &&
6060 "unexpected types for extended operands to VMULL");
6061 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
6064 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
6065 // isel lowering to take advantage of no-stall back to back vmul + vmla.
6072 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
6073 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
6074 EVT Op1VT = Op1.getValueType();
6075 return DAG.getNode(N0->getOpcode(), DL, VT,
6076 DAG.getNode(NewOpc, DL, VT,
6077 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
6078 DAG.getNode(NewOpc, DL, VT,
6079 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
6083 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
6085 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
6086 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
6087 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
6088 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
6089 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
6090 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
6091 // Get reciprocal estimate.
6092 // float4 recip = vrecpeq_f32(yf);
6093 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6094 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
6095 // Because char has a smaller range than uchar, we can actually get away
6096 // without any newton steps. This requires that we use a weird bias
6097 // of 0xb000, however (again, this has been exhaustively tested).
6098 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
6099 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
6100 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
6101 Y = DAG.getConstant(0xb000, MVT::i32);
6102 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
6103 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
6104 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
6105 // Convert back to short.
6106 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
6107 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
6112 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
6114 // Convert to float.
6115 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
6116 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
6117 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
6118 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
6119 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6120 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6122 // Use reciprocal estimate and one refinement step.
6123 // float4 recip = vrecpeq_f32(yf);
6124 // recip *= vrecpsq_f32(yf, recip);
6125 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6126 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
6127 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6128 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6130 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6131 // Because short has a smaller range than ushort, we can actually get away
6132 // with only a single newton step. This requires that we use a weird bias
6133 // of 89, however (again, this has been exhaustively tested).
6134 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
6135 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6136 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6137 N1 = DAG.getConstant(0x89, MVT::i32);
6138 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6139 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6140 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6141 // Convert back to integer and return.
6142 // return vmovn_s32(vcvt_s32_f32(result));
6143 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6144 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6148 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
6149 EVT VT = Op.getValueType();
6150 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6151 "unexpected type for custom-lowering ISD::SDIV");
6154 SDValue N0 = Op.getOperand(0);
6155 SDValue N1 = Op.getOperand(1);
6158 if (VT == MVT::v8i8) {
6159 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
6160 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
6162 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6163 DAG.getIntPtrConstant(4));
6164 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6165 DAG.getIntPtrConstant(4));
6166 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6167 DAG.getIntPtrConstant(0));
6168 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6169 DAG.getIntPtrConstant(0));
6171 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
6172 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
6174 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6175 N0 = LowerCONCAT_VECTORS(N0, DAG);
6177 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
6180 return LowerSDIV_v4i16(N0, N1, dl, DAG);
6183 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
6184 EVT VT = Op.getValueType();
6185 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6186 "unexpected type for custom-lowering ISD::UDIV");
6189 SDValue N0 = Op.getOperand(0);
6190 SDValue N1 = Op.getOperand(1);
6193 if (VT == MVT::v8i8) {
6194 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
6195 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
6197 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6198 DAG.getIntPtrConstant(4));
6199 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6200 DAG.getIntPtrConstant(4));
6201 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6202 DAG.getIntPtrConstant(0));
6203 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6204 DAG.getIntPtrConstant(0));
6206 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
6207 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
6209 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6210 N0 = LowerCONCAT_VECTORS(N0, DAG);
6212 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
6213 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
6218 // v4i16 sdiv ... Convert to float.
6219 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
6220 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
6221 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
6222 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
6223 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6224 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6226 // Use reciprocal estimate and two refinement steps.
6227 // float4 recip = vrecpeq_f32(yf);
6228 // recip *= vrecpsq_f32(yf, recip);
6229 // recip *= vrecpsq_f32(yf, recip);
6230 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6231 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
6232 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6233 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6235 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6236 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6237 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6239 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6240 // Simply multiplying by the reciprocal estimate can leave us a few ulps
6241 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
6242 // and that it will never cause us to return an answer too large).
6243 // float4 result = as_float4(as_int4(xf*recip) + 2);
6244 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6245 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6246 N1 = DAG.getConstant(2, MVT::i32);
6247 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6248 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6249 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6250 // Convert back to integer and return.
6251 // return vmovn_u32(vcvt_s32_f32(result));
6252 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6253 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6257 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
6258 EVT VT = Op.getNode()->getValueType(0);
6259 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
6262 bool ExtraOp = false;
6263 switch (Op.getOpcode()) {
6264 default: llvm_unreachable("Invalid code");
6265 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6266 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6267 case ISD::SUBC: Opc = ARMISD::SUBC; break;
6268 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
6272 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6274 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6275 Op.getOperand(1), Op.getOperand(2));
6278 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
6279 assert(Subtarget->isTargetDarwin());
6281 // For iOS, we want to call an alternative entry point: __sincos_stret,
6282 // return values are passed via sret.
6284 SDValue Arg = Op.getOperand(0);
6285 EVT ArgVT = Arg.getValueType();
6286 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
6288 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6289 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6291 // Pair of floats / doubles used to pass the result.
6292 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
6294 // Create stack object for sret.
6295 const uint64_t ByteSize = TLI.getDataLayout()->getTypeAllocSize(RetTy);
6296 const unsigned StackAlign = TLI.getDataLayout()->getPrefTypeAlignment(RetTy);
6297 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
6298 SDValue SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
6304 Entry.Ty = RetTy->getPointerTo();
6305 Entry.isSExt = false;
6306 Entry.isZExt = false;
6307 Entry.isSRet = true;
6308 Args.push_back(Entry);
6312 Entry.isSExt = false;
6313 Entry.isZExt = false;
6314 Args.push_back(Entry);
6316 const char *LibcallName = (ArgVT == MVT::f64)
6317 ? "__sincos_stret" : "__sincosf_stret";
6318 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
6320 TargetLowering::CallLoweringInfo CLI(DAG);
6321 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
6322 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), Callee,
6324 .setDiscardResult();
6326 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
6328 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
6329 MachinePointerInfo(), false, false, false, 0);
6331 // Address of cos field.
6332 SDValue Add = DAG.getNode(ISD::ADD, dl, getPointerTy(), SRet,
6333 DAG.getIntPtrConstant(ArgVT.getStoreSize()));
6334 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
6335 MachinePointerInfo(), false, false, false, 0);
6337 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
6338 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
6339 LoadSin.getValue(0), LoadCos.getValue(0));
6342 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
6343 // Monotonic load/store is legal for all targets
6344 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
6347 // Acquire/Release load/store is not legal for targets without a
6348 // dmb or equivalent available.
6352 static void ReplaceREADCYCLECOUNTER(SDNode *N,
6353 SmallVectorImpl<SDValue> &Results,
6355 const ARMSubtarget *Subtarget) {
6357 SDValue Cycles32, OutChain;
6359 if (Subtarget->hasPerfMon()) {
6360 // Under Power Management extensions, the cycle-count is:
6361 // mrc p15, #0, <Rt>, c9, c13, #0
6362 SDValue Ops[] = { N->getOperand(0), // Chain
6363 DAG.getConstant(Intrinsic::arm_mrc, MVT::i32),
6364 DAG.getConstant(15, MVT::i32),
6365 DAG.getConstant(0, MVT::i32),
6366 DAG.getConstant(9, MVT::i32),
6367 DAG.getConstant(13, MVT::i32),
6368 DAG.getConstant(0, MVT::i32)
6371 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6372 DAG.getVTList(MVT::i32, MVT::Other), Ops);
6373 OutChain = Cycles32.getValue(1);
6375 // Intrinsic is defined to return 0 on unsupported platforms. Technically
6376 // there are older ARM CPUs that have implementation-specific ways of
6377 // obtaining this information (FIXME!).
6378 Cycles32 = DAG.getConstant(0, MVT::i32);
6379 OutChain = DAG.getEntryNode();
6383 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
6384 Cycles32, DAG.getConstant(0, MVT::i32));
6385 Results.push_back(Cycles64);
6386 Results.push_back(OutChain);
6389 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6390 switch (Op.getOpcode()) {
6391 default: llvm_unreachable("Don't know how to custom lower this!");
6392 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6393 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6394 case ISD::GlobalAddress:
6395 switch (Subtarget->getTargetTriple().getObjectFormat()) {
6396 default: llvm_unreachable("unknown object format");
6398 return LowerGlobalAddressWindows(Op, DAG);
6400 return LowerGlobalAddressELF(Op, DAG);
6402 return LowerGlobalAddressDarwin(Op, DAG);
6404 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6405 case ISD::SELECT: return LowerSELECT(Op, DAG);
6406 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6407 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6408 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6409 case ISD::VASTART: return LowerVASTART(Op, DAG);
6410 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6411 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6412 case ISD::SINT_TO_FP:
6413 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6414 case ISD::FP_TO_SINT:
6415 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6416 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6417 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6418 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6419 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6420 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6421 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6422 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6424 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6427 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6428 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6429 case ISD::SRL_PARTS:
6430 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6431 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6432 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6433 case ISD::SETCC: return LowerVSETCC(Op, DAG);
6434 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6435 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6436 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6437 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6438 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6439 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6440 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6441 case ISD::MUL: return LowerMUL(Op, DAG);
6442 case ISD::SDIV: return LowerSDIV(Op, DAG);
6443 case ISD::UDIV: return LowerUDIV(Op, DAG);
6447 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6452 return LowerXALUO(Op, DAG);
6453 case ISD::ATOMIC_LOAD:
6454 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6455 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6457 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6458 case ISD::DYNAMIC_STACKALLOC:
6459 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
6460 return LowerDYNAMIC_STACKALLOC(Op, DAG);
6461 llvm_unreachable("Don't know how to custom lower this!");
6462 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
6463 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
6467 /// ReplaceNodeResults - Replace the results of node with an illegal result
6468 /// type with new values built out of custom code.
6469 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6470 SmallVectorImpl<SDValue>&Results,
6471 SelectionDAG &DAG) const {
6473 switch (N->getOpcode()) {
6475 llvm_unreachable("Don't know how to custom expand this!");
6477 Res = ExpandBITCAST(N, DAG);
6481 Res = Expand64BitShift(N, DAG, Subtarget);
6483 case ISD::READCYCLECOUNTER:
6484 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6488 Results.push_back(Res);
6491 //===----------------------------------------------------------------------===//
6492 // ARM Scheduler Hooks
6493 //===----------------------------------------------------------------------===//
6495 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6496 /// registers the function context.
6497 void ARMTargetLowering::
6498 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6499 MachineBasicBlock *DispatchBB, int FI) const {
6500 const TargetInstrInfo *TII =
6501 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6502 DebugLoc dl = MI->getDebugLoc();
6503 MachineFunction *MF = MBB->getParent();
6504 MachineRegisterInfo *MRI = &MF->getRegInfo();
6505 MachineConstantPool *MCP = MF->getConstantPool();
6506 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6507 const Function *F = MF->getFunction();
6509 bool isThumb = Subtarget->isThumb();
6510 bool isThumb2 = Subtarget->isThumb2();
6512 unsigned PCLabelId = AFI->createPICLabelUId();
6513 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6514 ARMConstantPoolValue *CPV =
6515 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6516 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6518 const TargetRegisterClass *TRC = isThumb ?
6519 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6520 (const TargetRegisterClass*)&ARM::GPRRegClass;
6522 // Grab constant pool and fixed stack memory operands.
6523 MachineMemOperand *CPMMO =
6524 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6525 MachineMemOperand::MOLoad, 4, 4);
6527 MachineMemOperand *FIMMOSt =
6528 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6529 MachineMemOperand::MOStore, 4, 4);
6531 // Load the address of the dispatch MBB into the jump buffer.
6533 // Incoming value: jbuf
6534 // ldr.n r5, LCPI1_1
6537 // str r5, [$jbuf, #+4] ; &jbuf[1]
6538 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6539 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6540 .addConstantPoolIndex(CPI)
6541 .addMemOperand(CPMMO));
6542 // Set the low bit because of thumb mode.
6543 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6545 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6546 .addReg(NewVReg1, RegState::Kill)
6548 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6549 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6550 .addReg(NewVReg2, RegState::Kill)
6552 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6553 .addReg(NewVReg3, RegState::Kill)
6555 .addImm(36) // &jbuf[1] :: pc
6556 .addMemOperand(FIMMOSt));
6557 } else if (isThumb) {
6558 // Incoming value: jbuf
6559 // ldr.n r1, LCPI1_4
6563 // add r2, $jbuf, #+4 ; &jbuf[1]
6565 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6566 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6567 .addConstantPoolIndex(CPI)
6568 .addMemOperand(CPMMO));
6569 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6570 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6571 .addReg(NewVReg1, RegState::Kill)
6573 // Set the low bit because of thumb mode.
6574 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6575 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6576 .addReg(ARM::CPSR, RegState::Define)
6578 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6579 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6580 .addReg(ARM::CPSR, RegState::Define)
6581 .addReg(NewVReg2, RegState::Kill)
6582 .addReg(NewVReg3, RegState::Kill));
6583 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6584 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
6586 .addImm(36); // &jbuf[1] :: pc
6587 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6588 .addReg(NewVReg4, RegState::Kill)
6589 .addReg(NewVReg5, RegState::Kill)
6591 .addMemOperand(FIMMOSt));
6593 // Incoming value: jbuf
6596 // str r1, [$jbuf, #+4] ; &jbuf[1]
6597 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6598 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6599 .addConstantPoolIndex(CPI)
6601 .addMemOperand(CPMMO));
6602 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6603 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6604 .addReg(NewVReg1, RegState::Kill)
6605 .addImm(PCLabelId));
6606 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6607 .addReg(NewVReg2, RegState::Kill)
6609 .addImm(36) // &jbuf[1] :: pc
6610 .addMemOperand(FIMMOSt));
6614 MachineBasicBlock *ARMTargetLowering::
6615 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
6616 const TargetInstrInfo *TII =
6617 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6618 DebugLoc dl = MI->getDebugLoc();
6619 MachineFunction *MF = MBB->getParent();
6620 MachineRegisterInfo *MRI = &MF->getRegInfo();
6621 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6622 MachineFrameInfo *MFI = MF->getFrameInfo();
6623 int FI = MFI->getFunctionContextIndex();
6625 const TargetRegisterClass *TRC = Subtarget->isThumb() ?
6626 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6627 (const TargetRegisterClass*)&ARM::GPRnopcRegClass;
6629 // Get a mapping of the call site numbers to all of the landing pads they're
6631 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6632 unsigned MaxCSNum = 0;
6633 MachineModuleInfo &MMI = MF->getMMI();
6634 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6636 if (!BB->isLandingPad()) continue;
6638 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6640 for (MachineBasicBlock::iterator
6641 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6642 if (!II->isEHLabel()) continue;
6644 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6645 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6647 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6648 for (SmallVectorImpl<unsigned>::iterator
6649 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6650 CSI != CSE; ++CSI) {
6651 CallSiteNumToLPad[*CSI].push_back(BB);
6652 MaxCSNum = std::max(MaxCSNum, *CSI);
6658 // Get an ordered list of the machine basic blocks for the jump table.
6659 std::vector<MachineBasicBlock*> LPadList;
6660 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6661 LPadList.reserve(CallSiteNumToLPad.size());
6662 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6663 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6664 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6665 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6666 LPadList.push_back(*II);
6667 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6671 assert(!LPadList.empty() &&
6672 "No landing pad destinations for the dispatch jump table!");
6674 // Create the jump table and associated information.
6675 MachineJumpTableInfo *JTI =
6676 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6677 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6678 unsigned UId = AFI->createJumpTableUId();
6679 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
6681 // Create the MBBs for the dispatch code.
6683 // Shove the dispatch's address into the return slot in the function context.
6684 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6685 DispatchBB->setIsLandingPad();
6687 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6688 unsigned trap_opcode;
6689 if (Subtarget->isThumb())
6690 trap_opcode = ARM::tTRAP;
6692 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6694 BuildMI(TrapBB, dl, TII->get(trap_opcode));
6695 DispatchBB->addSuccessor(TrapBB);
6697 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6698 DispatchBB->addSuccessor(DispContBB);
6701 MF->insert(MF->end(), DispatchBB);
6702 MF->insert(MF->end(), DispContBB);
6703 MF->insert(MF->end(), TrapBB);
6705 // Insert code into the entry block that creates and registers the function
6707 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6709 MachineMemOperand *FIMMOLd =
6710 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6711 MachineMemOperand::MOLoad |
6712 MachineMemOperand::MOVolatile, 4, 4);
6714 MachineInstrBuilder MIB;
6715 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6717 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6718 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6720 // Add a register mask with no preserved registers. This results in all
6721 // registers being marked as clobbered.
6722 MIB.addRegMask(RI.getNoPreservedMask());
6724 unsigned NumLPads = LPadList.size();
6725 if (Subtarget->isThumb2()) {
6726 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6727 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6730 .addMemOperand(FIMMOLd));
6732 if (NumLPads < 256) {
6733 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6735 .addImm(LPadList.size()));
6737 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6738 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6739 .addImm(NumLPads & 0xFFFF));
6741 unsigned VReg2 = VReg1;
6742 if ((NumLPads & 0xFFFF0000) != 0) {
6743 VReg2 = MRI->createVirtualRegister(TRC);
6744 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6746 .addImm(NumLPads >> 16));
6749 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6754 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6759 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6760 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6761 .addJumpTableIndex(MJTI)
6764 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6767 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6768 .addReg(NewVReg3, RegState::Kill)
6770 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6772 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6773 .addReg(NewVReg4, RegState::Kill)
6775 .addJumpTableIndex(MJTI)
6777 } else if (Subtarget->isThumb()) {
6778 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6779 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6782 .addMemOperand(FIMMOLd));
6784 if (NumLPads < 256) {
6785 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6789 MachineConstantPool *ConstantPool = MF->getConstantPool();
6790 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6791 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6793 // MachineConstantPool wants an explicit alignment.
6794 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6796 Align = getDataLayout()->getTypeAllocSize(C->getType());
6797 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6799 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6800 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6801 .addReg(VReg1, RegState::Define)
6802 .addConstantPoolIndex(Idx));
6803 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6808 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
6813 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6814 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6815 .addReg(ARM::CPSR, RegState::Define)
6819 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6820 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6821 .addJumpTableIndex(MJTI)
6824 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6825 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6826 .addReg(ARM::CPSR, RegState::Define)
6827 .addReg(NewVReg2, RegState::Kill)
6830 MachineMemOperand *JTMMOLd =
6831 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6832 MachineMemOperand::MOLoad, 4, 4);
6834 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6835 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6836 .addReg(NewVReg4, RegState::Kill)
6838 .addMemOperand(JTMMOLd));
6840 unsigned NewVReg6 = NewVReg5;
6841 if (RelocM == Reloc::PIC_) {
6842 NewVReg6 = MRI->createVirtualRegister(TRC);
6843 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6844 .addReg(ARM::CPSR, RegState::Define)
6845 .addReg(NewVReg5, RegState::Kill)
6849 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
6850 .addReg(NewVReg6, RegState::Kill)
6851 .addJumpTableIndex(MJTI)
6854 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6855 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6858 .addMemOperand(FIMMOLd));
6860 if (NumLPads < 256) {
6861 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6864 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
6865 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6866 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6867 .addImm(NumLPads & 0xFFFF));
6869 unsigned VReg2 = VReg1;
6870 if ((NumLPads & 0xFFFF0000) != 0) {
6871 VReg2 = MRI->createVirtualRegister(TRC);
6872 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6874 .addImm(NumLPads >> 16));
6877 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6881 MachineConstantPool *ConstantPool = MF->getConstantPool();
6882 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6883 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6885 // MachineConstantPool wants an explicit alignment.
6886 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6888 Align = getDataLayout()->getTypeAllocSize(C->getType());
6889 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6891 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6892 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6893 .addReg(VReg1, RegState::Define)
6894 .addConstantPoolIndex(Idx)
6896 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6898 .addReg(VReg1, RegState::Kill));
6901 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
6906 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6908 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6910 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6911 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6912 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6913 .addJumpTableIndex(MJTI)
6916 MachineMemOperand *JTMMOLd =
6917 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6918 MachineMemOperand::MOLoad, 4, 4);
6919 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6921 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
6922 .addReg(NewVReg3, RegState::Kill)
6925 .addMemOperand(JTMMOLd));
6927 if (RelocM == Reloc::PIC_) {
6928 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
6929 .addReg(NewVReg5, RegState::Kill)
6931 .addJumpTableIndex(MJTI)
6934 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
6935 .addReg(NewVReg5, RegState::Kill)
6936 .addJumpTableIndex(MJTI)
6941 // Add the jump table entries as successors to the MBB.
6942 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
6943 for (std::vector<MachineBasicBlock*>::iterator
6944 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6945 MachineBasicBlock *CurMBB = *I;
6946 if (SeenMBBs.insert(CurMBB))
6947 DispContBB->addSuccessor(CurMBB);
6950 // N.B. the order the invoke BBs are processed in doesn't matter here.
6951 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
6952 SmallVector<MachineBasicBlock*, 64> MBBLPads;
6953 for (MachineBasicBlock *BB : InvokeBBs) {
6955 // Remove the landing pad successor from the invoke block and replace it
6956 // with the new dispatch block.
6957 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6959 while (!Successors.empty()) {
6960 MachineBasicBlock *SMBB = Successors.pop_back_val();
6961 if (SMBB->isLandingPad()) {
6962 BB->removeSuccessor(SMBB);
6963 MBBLPads.push_back(SMBB);
6967 BB->addSuccessor(DispatchBB);
6969 // Find the invoke call and mark all of the callee-saved registers as
6970 // 'implicit defined' so that they're spilled. This prevents code from
6971 // moving instructions to before the EH block, where they will never be
6973 for (MachineBasicBlock::reverse_iterator
6974 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6975 if (!II->isCall()) continue;
6977 DenseMap<unsigned, bool> DefRegs;
6978 for (MachineInstr::mop_iterator
6979 OI = II->operands_begin(), OE = II->operands_end();
6981 if (!OI->isReg()) continue;
6982 DefRegs[OI->getReg()] = true;
6985 MachineInstrBuilder MIB(*MF, &*II);
6987 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6988 unsigned Reg = SavedRegs[i];
6989 if (Subtarget->isThumb2() &&
6990 !ARM::tGPRRegClass.contains(Reg) &&
6991 !ARM::hGPRRegClass.contains(Reg))
6993 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
6995 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
6998 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
7005 // Mark all former landing pads as non-landing pads. The dispatch is the only
7007 for (SmallVectorImpl<MachineBasicBlock*>::iterator
7008 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
7009 (*I)->setIsLandingPad(false);
7011 // The instruction is gone now.
7012 MI->eraseFromParent();
7018 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
7019 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
7020 E = MBB->succ_end(); I != E; ++I)
7023 llvm_unreachable("Expecting a BB with two successors!");
7026 /// Return the load opcode for a given load size. If load size >= 8,
7027 /// neon opcode will be returned.
7028 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
7030 return LdSize == 16 ? ARM::VLD1q32wb_fixed
7031 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
7033 return LdSize == 4 ? ARM::tLDRi
7034 : LdSize == 2 ? ARM::tLDRHi
7035 : LdSize == 1 ? ARM::tLDRBi : 0;
7037 return LdSize == 4 ? ARM::t2LDR_POST
7038 : LdSize == 2 ? ARM::t2LDRH_POST
7039 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
7040 return LdSize == 4 ? ARM::LDR_POST_IMM
7041 : LdSize == 2 ? ARM::LDRH_POST
7042 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
7045 /// Return the store opcode for a given store size. If store size >= 8,
7046 /// neon opcode will be returned.
7047 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
7049 return StSize == 16 ? ARM::VST1q32wb_fixed
7050 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
7052 return StSize == 4 ? ARM::tSTRi
7053 : StSize == 2 ? ARM::tSTRHi
7054 : StSize == 1 ? ARM::tSTRBi : 0;
7056 return StSize == 4 ? ARM::t2STR_POST
7057 : StSize == 2 ? ARM::t2STRH_POST
7058 : StSize == 1 ? ARM::t2STRB_POST : 0;
7059 return StSize == 4 ? ARM::STR_POST_IMM
7060 : StSize == 2 ? ARM::STRH_POST
7061 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
7064 /// Emit a post-increment load operation with given size. The instructions
7065 /// will be added to BB at Pos.
7066 static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
7067 const TargetInstrInfo *TII, DebugLoc dl,
7068 unsigned LdSize, unsigned Data, unsigned AddrIn,
7069 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7070 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
7071 assert(LdOpc != 0 && "Should have a load opcode");
7073 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7074 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7076 } else if (IsThumb1) {
7077 // load + update AddrIn
7078 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7079 .addReg(AddrIn).addImm(0));
7080 MachineInstrBuilder MIB =
7081 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7082 MIB = AddDefaultT1CC(MIB);
7083 MIB.addReg(AddrIn).addImm(LdSize);
7084 AddDefaultPred(MIB);
7085 } else if (IsThumb2) {
7086 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7087 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7090 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7091 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7092 .addReg(0).addImm(LdSize));
7096 /// Emit a post-increment store operation with given size. The instructions
7097 /// will be added to BB at Pos.
7098 static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
7099 const TargetInstrInfo *TII, DebugLoc dl,
7100 unsigned StSize, unsigned Data, unsigned AddrIn,
7101 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7102 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
7103 assert(StOpc != 0 && "Should have a store opcode");
7105 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7106 .addReg(AddrIn).addImm(0).addReg(Data));
7107 } else if (IsThumb1) {
7108 // store + update AddrIn
7109 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
7110 .addReg(AddrIn).addImm(0));
7111 MachineInstrBuilder MIB =
7112 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7113 MIB = AddDefaultT1CC(MIB);
7114 MIB.addReg(AddrIn).addImm(StSize);
7115 AddDefaultPred(MIB);
7116 } else if (IsThumb2) {
7117 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7118 .addReg(Data).addReg(AddrIn).addImm(StSize));
7120 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7121 .addReg(Data).addReg(AddrIn).addReg(0)
7127 ARMTargetLowering::EmitStructByval(MachineInstr *MI,
7128 MachineBasicBlock *BB) const {
7129 // This pseudo instruction has 3 operands: dst, src, size
7130 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
7131 // Otherwise, we will generate unrolled scalar copies.
7132 const TargetInstrInfo *TII =
7133 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7134 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7135 MachineFunction::iterator It = BB;
7138 unsigned dest = MI->getOperand(0).getReg();
7139 unsigned src = MI->getOperand(1).getReg();
7140 unsigned SizeVal = MI->getOperand(2).getImm();
7141 unsigned Align = MI->getOperand(3).getImm();
7142 DebugLoc dl = MI->getDebugLoc();
7144 MachineFunction *MF = BB->getParent();
7145 MachineRegisterInfo &MRI = MF->getRegInfo();
7146 unsigned UnitSize = 0;
7147 const TargetRegisterClass *TRC = nullptr;
7148 const TargetRegisterClass *VecTRC = nullptr;
7150 bool IsThumb1 = Subtarget->isThumb1Only();
7151 bool IsThumb2 = Subtarget->isThumb2();
7155 } else if (Align & 2) {
7158 // Check whether we can use NEON instructions.
7159 if (!MF->getFunction()->getAttributes().
7160 hasAttribute(AttributeSet::FunctionIndex,
7161 Attribute::NoImplicitFloat) &&
7162 Subtarget->hasNEON()) {
7163 if ((Align % 16 == 0) && SizeVal >= 16)
7165 else if ((Align % 8 == 0) && SizeVal >= 8)
7168 // Can't use NEON instructions.
7173 // Select the correct opcode and register class for unit size load/store
7174 bool IsNeon = UnitSize >= 8;
7175 TRC = (IsThumb1 || IsThumb2) ? (const TargetRegisterClass *)&ARM::tGPRRegClass
7176 : (const TargetRegisterClass *)&ARM::GPRRegClass;
7178 VecTRC = UnitSize == 16
7179 ? (const TargetRegisterClass *)&ARM::DPairRegClass
7181 ? (const TargetRegisterClass *)&ARM::DPRRegClass
7184 unsigned BytesLeft = SizeVal % UnitSize;
7185 unsigned LoopSize = SizeVal - BytesLeft;
7187 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
7188 // Use LDR and STR to copy.
7189 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
7190 // [destOut] = STR_POST(scratch, destIn, UnitSize)
7191 unsigned srcIn = src;
7192 unsigned destIn = dest;
7193 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7194 unsigned srcOut = MRI.createVirtualRegister(TRC);
7195 unsigned destOut = MRI.createVirtualRegister(TRC);
7196 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7197 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7198 IsThumb1, IsThumb2);
7199 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7200 IsThumb1, IsThumb2);
7205 // Handle the leftover bytes with LDRB and STRB.
7206 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7207 // [destOut] = STRB_POST(scratch, destIn, 1)
7208 for (unsigned i = 0; i < BytesLeft; i++) {
7209 unsigned srcOut = MRI.createVirtualRegister(TRC);
7210 unsigned destOut = MRI.createVirtualRegister(TRC);
7211 unsigned scratch = MRI.createVirtualRegister(TRC);
7212 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7213 IsThumb1, IsThumb2);
7214 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7215 IsThumb1, IsThumb2);
7219 MI->eraseFromParent(); // The instruction is gone now.
7223 // Expand the pseudo op to a loop.
7226 // movw varEnd, # --> with thumb2
7228 // ldrcp varEnd, idx --> without thumb2
7229 // fallthrough --> loopMBB
7231 // PHI varPhi, varEnd, varLoop
7232 // PHI srcPhi, src, srcLoop
7233 // PHI destPhi, dst, destLoop
7234 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7235 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7236 // subs varLoop, varPhi, #UnitSize
7238 // fallthrough --> exitMBB
7240 // epilogue to handle left-over bytes
7241 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7242 // [destOut] = STRB_POST(scratch, destLoop, 1)
7243 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7244 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7245 MF->insert(It, loopMBB);
7246 MF->insert(It, exitMBB);
7248 // Transfer the remainder of BB and its successor edges to exitMBB.
7249 exitMBB->splice(exitMBB->begin(), BB,
7250 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7251 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7253 // Load an immediate to varEnd.
7254 unsigned varEnd = MRI.createVirtualRegister(TRC);
7256 unsigned Vtmp = varEnd;
7257 if ((LoopSize & 0xFFFF0000) != 0)
7258 Vtmp = MRI.createVirtualRegister(TRC);
7259 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), Vtmp)
7260 .addImm(LoopSize & 0xFFFF));
7262 if ((LoopSize & 0xFFFF0000) != 0)
7263 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
7264 .addReg(Vtmp).addImm(LoopSize >> 16));
7266 MachineConstantPool *ConstantPool = MF->getConstantPool();
7267 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7268 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7270 // MachineConstantPool wants an explicit alignment.
7271 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7273 Align = getDataLayout()->getTypeAllocSize(C->getType());
7274 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7277 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7278 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7280 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7281 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7283 BB->addSuccessor(loopMBB);
7285 // Generate the loop body:
7286 // varPhi = PHI(varLoop, varEnd)
7287 // srcPhi = PHI(srcLoop, src)
7288 // destPhi = PHI(destLoop, dst)
7289 MachineBasicBlock *entryBB = BB;
7291 unsigned varLoop = MRI.createVirtualRegister(TRC);
7292 unsigned varPhi = MRI.createVirtualRegister(TRC);
7293 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7294 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7295 unsigned destLoop = MRI.createVirtualRegister(TRC);
7296 unsigned destPhi = MRI.createVirtualRegister(TRC);
7298 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7299 .addReg(varLoop).addMBB(loopMBB)
7300 .addReg(varEnd).addMBB(entryBB);
7301 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7302 .addReg(srcLoop).addMBB(loopMBB)
7303 .addReg(src).addMBB(entryBB);
7304 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7305 .addReg(destLoop).addMBB(loopMBB)
7306 .addReg(dest).addMBB(entryBB);
7308 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7309 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7310 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7311 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7312 IsThumb1, IsThumb2);
7313 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7314 IsThumb1, IsThumb2);
7316 // Decrement loop variable by UnitSize.
7318 MachineInstrBuilder MIB =
7319 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7320 MIB = AddDefaultT1CC(MIB);
7321 MIB.addReg(varPhi).addImm(UnitSize);
7322 AddDefaultPred(MIB);
7324 MachineInstrBuilder MIB =
7325 BuildMI(*BB, BB->end(), dl,
7326 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7327 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7328 MIB->getOperand(5).setReg(ARM::CPSR);
7329 MIB->getOperand(5).setIsDef(true);
7331 BuildMI(*BB, BB->end(), dl,
7332 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7333 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7335 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7336 BB->addSuccessor(loopMBB);
7337 BB->addSuccessor(exitMBB);
7339 // Add epilogue to handle BytesLeft.
7341 MachineInstr *StartOfExit = exitMBB->begin();
7343 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7344 // [destOut] = STRB_POST(scratch, destLoop, 1)
7345 unsigned srcIn = srcLoop;
7346 unsigned destIn = destLoop;
7347 for (unsigned i = 0; i < BytesLeft; i++) {
7348 unsigned srcOut = MRI.createVirtualRegister(TRC);
7349 unsigned destOut = MRI.createVirtualRegister(TRC);
7350 unsigned scratch = MRI.createVirtualRegister(TRC);
7351 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7352 IsThumb1, IsThumb2);
7353 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7354 IsThumb1, IsThumb2);
7359 MI->eraseFromParent(); // The instruction is gone now.
7364 ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
7365 MachineBasicBlock *MBB) const {
7366 const TargetMachine &TM = getTargetMachine();
7367 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
7368 DebugLoc DL = MI->getDebugLoc();
7370 assert(Subtarget->isTargetWindows() &&
7371 "__chkstk is only supported on Windows");
7372 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
7374 // __chkstk takes the number of words to allocate on the stack in R4, and
7375 // returns the stack adjustment in number of bytes in R4. This will not
7376 // clober any other registers (other than the obvious lr).
7378 // Although, technically, IP should be considered a register which may be
7379 // clobbered, the call itself will not touch it. Windows on ARM is a pure
7380 // thumb-2 environment, so there is no interworking required. As a result, we
7381 // do not expect a veneer to be emitted by the linker, clobbering IP.
7383 // Each module receives its own copy of __chkstk, so no import thunk is
7384 // required, again, ensuring that IP is not clobbered.
7386 // Finally, although some linkers may theoretically provide a trampoline for
7387 // out of range calls (which is quite common due to a 32M range limitation of
7388 // branches for Thumb), we can generate the long-call version via
7389 // -mcmodel=large, alleviating the need for the trampoline which may clobber
7392 switch (TM.getCodeModel()) {
7393 case CodeModel::Small:
7394 case CodeModel::Medium:
7395 case CodeModel::Default:
7396 case CodeModel::Kernel:
7397 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
7398 .addImm((unsigned)ARMCC::AL).addReg(0)
7399 .addExternalSymbol("__chkstk")
7400 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7401 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7402 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7404 case CodeModel::Large:
7405 case CodeModel::JITDefault: {
7406 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
7407 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
7409 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
7410 .addExternalSymbol("__chkstk");
7411 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
7412 .addImm((unsigned)ARMCC::AL).addReg(0)
7413 .addReg(Reg, RegState::Kill)
7414 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7415 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7416 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7421 AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7423 .addReg(ARM::SP).addReg(ARM::R4)));
7425 MI->eraseFromParent();
7430 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7431 MachineBasicBlock *BB) const {
7432 const TargetInstrInfo *TII =
7433 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7434 DebugLoc dl = MI->getDebugLoc();
7435 bool isThumb2 = Subtarget->isThumb2();
7436 switch (MI->getOpcode()) {
7439 llvm_unreachable("Unexpected instr type to insert");
7441 // The Thumb2 pre-indexed stores have the same MI operands, they just
7442 // define them differently in the .td files from the isel patterns, so
7443 // they need pseudos.
7444 case ARM::t2STR_preidx:
7445 MI->setDesc(TII->get(ARM::t2STR_PRE));
7447 case ARM::t2STRB_preidx:
7448 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7450 case ARM::t2STRH_preidx:
7451 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7454 case ARM::STRi_preidx:
7455 case ARM::STRBi_preidx: {
7456 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7457 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7458 // Decode the offset.
7459 unsigned Offset = MI->getOperand(4).getImm();
7460 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7461 Offset = ARM_AM::getAM2Offset(Offset);
7465 MachineMemOperand *MMO = *MI->memoperands_begin();
7466 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7467 .addOperand(MI->getOperand(0)) // Rn_wb
7468 .addOperand(MI->getOperand(1)) // Rt
7469 .addOperand(MI->getOperand(2)) // Rn
7470 .addImm(Offset) // offset (skip GPR==zero_reg)
7471 .addOperand(MI->getOperand(5)) // pred
7472 .addOperand(MI->getOperand(6))
7473 .addMemOperand(MMO);
7474 MI->eraseFromParent();
7477 case ARM::STRr_preidx:
7478 case ARM::STRBr_preidx:
7479 case ARM::STRH_preidx: {
7481 switch (MI->getOpcode()) {
7482 default: llvm_unreachable("unexpected opcode!");
7483 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7484 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7485 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7487 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7488 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7489 MIB.addOperand(MI->getOperand(i));
7490 MI->eraseFromParent();
7494 case ARM::tMOVCCr_pseudo: {
7495 // To "insert" a SELECT_CC instruction, we actually have to insert the
7496 // diamond control-flow pattern. The incoming instruction knows the
7497 // destination vreg to set, the condition code register to branch on, the
7498 // true/false values to select between, and a branch opcode to use.
7499 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7500 MachineFunction::iterator It = BB;
7506 // cmpTY ccX, r1, r2
7508 // fallthrough --> copy0MBB
7509 MachineBasicBlock *thisMBB = BB;
7510 MachineFunction *F = BB->getParent();
7511 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7512 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7513 F->insert(It, copy0MBB);
7514 F->insert(It, sinkMBB);
7516 // Transfer the remainder of BB and its successor edges to sinkMBB.
7517 sinkMBB->splice(sinkMBB->begin(), BB,
7518 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7519 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7521 BB->addSuccessor(copy0MBB);
7522 BB->addSuccessor(sinkMBB);
7524 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7525 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7528 // %FalseValue = ...
7529 // # fallthrough to sinkMBB
7532 // Update machine-CFG edges
7533 BB->addSuccessor(sinkMBB);
7536 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7539 BuildMI(*BB, BB->begin(), dl,
7540 TII->get(ARM::PHI), MI->getOperand(0).getReg())
7541 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7542 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7544 MI->eraseFromParent(); // The pseudo instruction is gone now.
7549 case ARM::BCCZi64: {
7550 // If there is an unconditional branch to the other successor, remove it.
7551 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
7553 // Compare both parts that make up the double comparison separately for
7555 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7557 unsigned LHS1 = MI->getOperand(1).getReg();
7558 unsigned LHS2 = MI->getOperand(2).getReg();
7560 AddDefaultPred(BuildMI(BB, dl,
7561 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7562 .addReg(LHS1).addImm(0));
7563 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7564 .addReg(LHS2).addImm(0)
7565 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7567 unsigned RHS1 = MI->getOperand(3).getReg();
7568 unsigned RHS2 = MI->getOperand(4).getReg();
7569 AddDefaultPred(BuildMI(BB, dl,
7570 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7571 .addReg(LHS1).addReg(RHS1));
7572 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7573 .addReg(LHS2).addReg(RHS2)
7574 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7577 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7578 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7579 if (MI->getOperand(0).getImm() == ARMCC::NE)
7580 std::swap(destMBB, exitMBB);
7582 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7583 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7585 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7587 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7589 MI->eraseFromParent(); // The pseudo instruction is gone now.
7593 case ARM::Int_eh_sjlj_setjmp:
7594 case ARM::Int_eh_sjlj_setjmp_nofp:
7595 case ARM::tInt_eh_sjlj_setjmp:
7596 case ARM::t2Int_eh_sjlj_setjmp:
7597 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7598 EmitSjLjDispatchBlock(MI, BB);
7603 // To insert an ABS instruction, we have to insert the
7604 // diamond control-flow pattern. The incoming instruction knows the
7605 // source vreg to test against 0, the destination vreg to set,
7606 // the condition code register to branch on, the
7607 // true/false values to select between, and a branch opcode to use.
7612 // BCC (branch to SinkBB if V0 >= 0)
7613 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7614 // SinkBB: V1 = PHI(V2, V3)
7615 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7616 MachineFunction::iterator BBI = BB;
7618 MachineFunction *Fn = BB->getParent();
7619 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7620 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7621 Fn->insert(BBI, RSBBB);
7622 Fn->insert(BBI, SinkBB);
7624 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7625 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7626 bool isThumb2 = Subtarget->isThumb2();
7627 MachineRegisterInfo &MRI = Fn->getRegInfo();
7628 // In Thumb mode S must not be specified if source register is the SP or
7629 // PC and if destination register is the SP, so restrict register class
7630 unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
7631 (const TargetRegisterClass*)&ARM::rGPRRegClass :
7632 (const TargetRegisterClass*)&ARM::GPRRegClass);
7634 // Transfer the remainder of BB and its successor edges to sinkMBB.
7635 SinkBB->splice(SinkBB->begin(), BB,
7636 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7637 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7639 BB->addSuccessor(RSBBB);
7640 BB->addSuccessor(SinkBB);
7642 // fall through to SinkMBB
7643 RSBBB->addSuccessor(SinkBB);
7645 // insert a cmp at the end of BB
7646 AddDefaultPred(BuildMI(BB, dl,
7647 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7648 .addReg(ABSSrcReg).addImm(0));
7650 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7652 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7653 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7655 // insert rsbri in RSBBB
7656 // Note: BCC and rsbri will be converted into predicated rsbmi
7657 // by if-conversion pass
7658 BuildMI(*RSBBB, RSBBB->begin(), dl,
7659 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7660 .addReg(ABSSrcReg, RegState::Kill)
7661 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7663 // insert PHI in SinkBB,
7664 // reuse ABSDstReg to not change uses of ABS instruction
7665 BuildMI(*SinkBB, SinkBB->begin(), dl,
7666 TII->get(ARM::PHI), ABSDstReg)
7667 .addReg(NewRsbDstReg).addMBB(RSBBB)
7668 .addReg(ABSSrcReg).addMBB(BB);
7670 // remove ABS instruction
7671 MI->eraseFromParent();
7673 // return last added BB
7676 case ARM::COPY_STRUCT_BYVAL_I32:
7678 return EmitStructByval(MI, BB);
7679 case ARM::WIN__CHKSTK:
7680 return EmitLowered__chkstk(MI, BB);
7684 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7685 SDNode *Node) const {
7686 const MCInstrDesc *MCID = &MI->getDesc();
7687 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7688 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7689 // operand is still set to noreg. If needed, set the optional operand's
7690 // register to CPSR, and remove the redundant implicit def.
7692 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7694 // Rename pseudo opcodes.
7695 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7697 const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>(
7698 getTargetMachine().getSubtargetImpl()->getInstrInfo());
7699 MCID = &TII->get(NewOpc);
7701 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7702 "converted opcode should be the same except for cc_out");
7706 // Add the optional cc_out operand
7707 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7709 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7711 // Any ARM instruction that sets the 's' bit should specify an optional
7712 // "cc_out" operand in the last operand position.
7713 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7714 assert(!NewOpc && "Optional cc_out operand required");
7717 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7718 // since we already have an optional CPSR def.
7719 bool definesCPSR = false;
7720 bool deadCPSR = false;
7721 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7723 const MachineOperand &MO = MI->getOperand(i);
7724 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7728 MI->RemoveOperand(i);
7733 assert(!NewOpc && "Optional cc_out operand required");
7736 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
7738 assert(!MI->getOperand(ccOutIdx).getReg() &&
7739 "expect uninitialized optional cc_out operand");
7743 // If this instruction was defined with an optional CPSR def and its dag node
7744 // had a live implicit CPSR def, then activate the optional CPSR def.
7745 MachineOperand &MO = MI->getOperand(ccOutIdx);
7746 MO.setReg(ARM::CPSR);
7750 //===----------------------------------------------------------------------===//
7751 // ARM Optimization Hooks
7752 //===----------------------------------------------------------------------===//
7754 // Helper function that checks if N is a null or all ones constant.
7755 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
7756 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
7759 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
7762 // Return true if N is conditionally 0 or all ones.
7763 // Detects these expressions where cc is an i1 value:
7765 // (select cc 0, y) [AllOnes=0]
7766 // (select cc y, 0) [AllOnes=0]
7767 // (zext cc) [AllOnes=0]
7768 // (sext cc) [AllOnes=0/1]
7769 // (select cc -1, y) [AllOnes=1]
7770 // (select cc y, -1) [AllOnes=1]
7772 // Invert is set when N is the null/all ones constant when CC is false.
7773 // OtherOp is set to the alternative value of N.
7774 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
7775 SDValue &CC, bool &Invert,
7777 SelectionDAG &DAG) {
7778 switch (N->getOpcode()) {
7779 default: return false;
7781 CC = N->getOperand(0);
7782 SDValue N1 = N->getOperand(1);
7783 SDValue N2 = N->getOperand(2);
7784 if (isZeroOrAllOnes(N1, AllOnes)) {
7789 if (isZeroOrAllOnes(N2, AllOnes)) {
7796 case ISD::ZERO_EXTEND:
7797 // (zext cc) can never be the all ones value.
7801 case ISD::SIGN_EXTEND: {
7802 EVT VT = N->getValueType(0);
7803 CC = N->getOperand(0);
7804 if (CC.getValueType() != MVT::i1)
7808 // When looking for an AllOnes constant, N is an sext, and the 'other'
7810 OtherOp = DAG.getConstant(0, VT);
7811 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7812 // When looking for a 0 constant, N can be zext or sext.
7813 OtherOp = DAG.getConstant(1, VT);
7815 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
7821 // Combine a constant select operand into its use:
7823 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7824 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7825 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
7826 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7827 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
7829 // The transform is rejected if the select doesn't have a constant operand that
7830 // is null, or all ones when AllOnes is set.
7832 // Also recognize sext/zext from i1:
7834 // (add (zext cc), x) -> (select cc (add x, 1), x)
7835 // (add (sext cc), x) -> (select cc (add x, -1), x)
7837 // These transformations eventually create predicated instructions.
7839 // @param N The node to transform.
7840 // @param Slct The N operand that is a select.
7841 // @param OtherOp The other N operand (x above).
7842 // @param DCI Context.
7843 // @param AllOnes Require the select constant to be all ones instead of null.
7844 // @returns The new node, or SDValue() on failure.
7846 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
7847 TargetLowering::DAGCombinerInfo &DCI,
7848 bool AllOnes = false) {
7849 SelectionDAG &DAG = DCI.DAG;
7850 EVT VT = N->getValueType(0);
7851 SDValue NonConstantVal;
7854 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
7855 NonConstantVal, DAG))
7858 // Slct is now know to be the desired identity constant when CC is true.
7859 SDValue TrueVal = OtherOp;
7860 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
7861 OtherOp, NonConstantVal);
7862 // Unless SwapSelectOps says CC should be false.
7864 std::swap(TrueVal, FalseVal);
7866 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
7867 CCOp, TrueVal, FalseVal);
7870 // Attempt combineSelectAndUse on each operand of a commutative operator N.
7872 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
7873 TargetLowering::DAGCombinerInfo &DCI) {
7874 SDValue N0 = N->getOperand(0);
7875 SDValue N1 = N->getOperand(1);
7876 if (N0.getNode()->hasOneUse()) {
7877 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7878 if (Result.getNode())
7881 if (N1.getNode()->hasOneUse()) {
7882 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7883 if (Result.getNode())
7889 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
7890 // (only after legalization).
7891 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7892 TargetLowering::DAGCombinerInfo &DCI,
7893 const ARMSubtarget *Subtarget) {
7895 // Only perform optimization if after legalize, and if NEON is available. We
7896 // also expected both operands to be BUILD_VECTORs.
7897 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
7898 || N0.getOpcode() != ISD::BUILD_VECTOR
7899 || N1.getOpcode() != ISD::BUILD_VECTOR)
7902 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
7903 EVT VT = N->getValueType(0);
7904 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7907 // Check that the vector operands are of the right form.
7908 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7909 // operands, where N is the size of the formed vector.
7910 // Each EXTRACT_VECTOR should have the same input vector and odd or even
7911 // index such that we have a pair wise add pattern.
7913 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
7914 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7916 SDValue Vec = N0->getOperand(0)->getOperand(0);
7917 SDNode *V = Vec.getNode();
7918 unsigned nextIndex = 0;
7920 // For each operands to the ADD which are BUILD_VECTORs,
7921 // check to see if each of their operands are an EXTRACT_VECTOR with
7922 // the same vector and appropriate index.
7923 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7924 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7925 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7927 SDValue ExtVec0 = N0->getOperand(i);
7928 SDValue ExtVec1 = N1->getOperand(i);
7930 // First operand is the vector, verify its the same.
7931 if (V != ExtVec0->getOperand(0).getNode() ||
7932 V != ExtVec1->getOperand(0).getNode())
7935 // Second is the constant, verify its correct.
7936 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
7937 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
7939 // For the constant, we want to see all the even or all the odd.
7940 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
7941 || C1->getZExtValue() != nextIndex+1)
7950 // Create VPADDL node.
7951 SelectionDAG &DAG = DCI.DAG;
7952 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7954 // Build operand list.
7955 SmallVector<SDValue, 8> Ops;
7956 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
7957 TLI.getPointerTy()));
7959 // Input is the vector.
7962 // Get widened type and narrowed type.
7964 unsigned numElem = VT.getVectorNumElements();
7966 EVT inputLaneType = Vec.getValueType().getVectorElementType();
7967 switch (inputLaneType.getSimpleVT().SimpleTy) {
7968 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
7969 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
7970 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
7972 llvm_unreachable("Invalid vector element type for padd optimization.");
7975 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), widenType, Ops);
7976 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
7977 return DAG.getNode(ExtOp, SDLoc(N), VT, tmp);
7980 static SDValue findMUL_LOHI(SDValue V) {
7981 if (V->getOpcode() == ISD::UMUL_LOHI ||
7982 V->getOpcode() == ISD::SMUL_LOHI)
7987 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
7988 TargetLowering::DAGCombinerInfo &DCI,
7989 const ARMSubtarget *Subtarget) {
7991 if (Subtarget->isThumb1Only()) return SDValue();
7993 // Only perform the checks after legalize when the pattern is available.
7994 if (DCI.isBeforeLegalize()) return SDValue();
7996 // Look for multiply add opportunities.
7997 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
7998 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
7999 // a glue link from the first add to the second add.
8000 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8001 // a S/UMLAL instruction.
8004 // \ / \ [no multiline comment]
8010 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
8011 SDValue AddcOp0 = AddcNode->getOperand(0);
8012 SDValue AddcOp1 = AddcNode->getOperand(1);
8014 // Check if the two operands are from the same mul_lohi node.
8015 if (AddcOp0.getNode() == AddcOp1.getNode())
8018 assert(AddcNode->getNumValues() == 2 &&
8019 AddcNode->getValueType(0) == MVT::i32 &&
8020 "Expect ADDC with two result values. First: i32");
8022 // Check that we have a glued ADDC node.
8023 if (AddcNode->getValueType(1) != MVT::Glue)
8026 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
8027 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
8028 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
8029 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
8030 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
8033 // Look for the glued ADDE.
8034 SDNode* AddeNode = AddcNode->getGluedUser();
8038 // Make sure it is really an ADDE.
8039 if (AddeNode->getOpcode() != ISD::ADDE)
8042 assert(AddeNode->getNumOperands() == 3 &&
8043 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
8044 "ADDE node has the wrong inputs");
8046 // Check for the triangle shape.
8047 SDValue AddeOp0 = AddeNode->getOperand(0);
8048 SDValue AddeOp1 = AddeNode->getOperand(1);
8050 // Make sure that the ADDE operands are not coming from the same node.
8051 if (AddeOp0.getNode() == AddeOp1.getNode())
8054 // Find the MUL_LOHI node walking up ADDE's operands.
8055 bool IsLeftOperandMUL = false;
8056 SDValue MULOp = findMUL_LOHI(AddeOp0);
8057 if (MULOp == SDValue())
8058 MULOp = findMUL_LOHI(AddeOp1);
8060 IsLeftOperandMUL = true;
8061 if (MULOp == SDValue())
8064 // Figure out the right opcode.
8065 unsigned Opc = MULOp->getOpcode();
8066 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8068 // Figure out the high and low input values to the MLAL node.
8069 SDValue* HiMul = &MULOp;
8070 SDValue* HiAdd = nullptr;
8071 SDValue* LoMul = nullptr;
8072 SDValue* LowAdd = nullptr;
8074 if (IsLeftOperandMUL)
8080 if (AddcOp0->getOpcode() == Opc) {
8084 if (AddcOp1->getOpcode() == Opc) {
8092 if (LoMul->getNode() != HiMul->getNode())
8095 // Create the merged node.
8096 SelectionDAG &DAG = DCI.DAG;
8098 // Build operand list.
8099 SmallVector<SDValue, 8> Ops;
8100 Ops.push_back(LoMul->getOperand(0));
8101 Ops.push_back(LoMul->getOperand(1));
8102 Ops.push_back(*LowAdd);
8103 Ops.push_back(*HiAdd);
8105 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
8106 DAG.getVTList(MVT::i32, MVT::i32), Ops);
8108 // Replace the ADDs' nodes uses by the MLA node's values.
8109 SDValue HiMLALResult(MLALNode.getNode(), 1);
8110 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
8112 SDValue LoMLALResult(MLALNode.getNode(), 0);
8113 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
8115 // Return original node to notify the driver to stop replacing.
8116 SDValue resNode(AddcNode, 0);
8120 /// PerformADDCCombine - Target-specific dag combine transform from
8121 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
8122 static SDValue PerformADDCCombine(SDNode *N,
8123 TargetLowering::DAGCombinerInfo &DCI,
8124 const ARMSubtarget *Subtarget) {
8126 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8130 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
8131 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8132 /// called with the default operands, and if that fails, with commuted
8134 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8135 TargetLowering::DAGCombinerInfo &DCI,
8136 const ARMSubtarget *Subtarget){
8138 // Attempt to create vpaddl for this add.
8139 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8140 if (Result.getNode())
8143 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8144 if (N0.getNode()->hasOneUse()) {
8145 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8146 if (Result.getNode()) return Result;
8151 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
8153 static SDValue PerformADDCombine(SDNode *N,
8154 TargetLowering::DAGCombinerInfo &DCI,
8155 const ARMSubtarget *Subtarget) {
8156 SDValue N0 = N->getOperand(0);
8157 SDValue N1 = N->getOperand(1);
8159 // First try with the default operand order.
8160 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8161 if (Result.getNode())
8164 // If that didn't work, try again with the operands commuted.
8165 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8168 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
8170 static SDValue PerformSUBCombine(SDNode *N,
8171 TargetLowering::DAGCombinerInfo &DCI) {
8172 SDValue N0 = N->getOperand(0);
8173 SDValue N1 = N->getOperand(1);
8175 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8176 if (N1.getNode()->hasOneUse()) {
8177 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8178 if (Result.getNode()) return Result;
8184 /// PerformVMULCombine
8185 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
8186 /// special multiplier accumulator forwarding.
8192 // However, for (A + B) * (A + B),
8199 static SDValue PerformVMULCombine(SDNode *N,
8200 TargetLowering::DAGCombinerInfo &DCI,
8201 const ARMSubtarget *Subtarget) {
8202 if (!Subtarget->hasVMLxForwarding())
8205 SelectionDAG &DAG = DCI.DAG;
8206 SDValue N0 = N->getOperand(0);
8207 SDValue N1 = N->getOperand(1);
8208 unsigned Opcode = N0.getOpcode();
8209 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8210 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8211 Opcode = N1.getOpcode();
8212 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8213 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8221 EVT VT = N->getValueType(0);
8223 SDValue N00 = N0->getOperand(0);
8224 SDValue N01 = N0->getOperand(1);
8225 return DAG.getNode(Opcode, DL, VT,
8226 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8227 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8230 static SDValue PerformMULCombine(SDNode *N,
8231 TargetLowering::DAGCombinerInfo &DCI,
8232 const ARMSubtarget *Subtarget) {
8233 SelectionDAG &DAG = DCI.DAG;
8235 if (Subtarget->isThumb1Only())
8238 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8241 EVT VT = N->getValueType(0);
8242 if (VT.is64BitVector() || VT.is128BitVector())
8243 return PerformVMULCombine(N, DCI, Subtarget);
8247 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8251 int64_t MulAmt = C->getSExtValue();
8252 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
8254 ShiftAmt = ShiftAmt & (32 - 1);
8255 SDValue V = N->getOperand(0);
8259 MulAmt >>= ShiftAmt;
8262 if (isPowerOf2_32(MulAmt - 1)) {
8263 // (mul x, 2^N + 1) => (add (shl x, N), x)
8264 Res = DAG.getNode(ISD::ADD, DL, VT,
8266 DAG.getNode(ISD::SHL, DL, VT,
8268 DAG.getConstant(Log2_32(MulAmt - 1),
8270 } else if (isPowerOf2_32(MulAmt + 1)) {
8271 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8272 Res = DAG.getNode(ISD::SUB, DL, VT,
8273 DAG.getNode(ISD::SHL, DL, VT,
8275 DAG.getConstant(Log2_32(MulAmt + 1),
8281 uint64_t MulAmtAbs = -MulAmt;
8282 if (isPowerOf2_32(MulAmtAbs + 1)) {
8283 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8284 Res = DAG.getNode(ISD::SUB, DL, VT,
8286 DAG.getNode(ISD::SHL, DL, VT,
8288 DAG.getConstant(Log2_32(MulAmtAbs + 1),
8290 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8291 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8292 Res = DAG.getNode(ISD::ADD, DL, VT,
8294 DAG.getNode(ISD::SHL, DL, VT,
8296 DAG.getConstant(Log2_32(MulAmtAbs-1),
8298 Res = DAG.getNode(ISD::SUB, DL, VT,
8299 DAG.getConstant(0, MVT::i32),Res);
8306 Res = DAG.getNode(ISD::SHL, DL, VT,
8307 Res, DAG.getConstant(ShiftAmt, MVT::i32));
8309 // Do not add new nodes to DAG combiner worklist.
8310 DCI.CombineTo(N, Res, false);
8314 static SDValue PerformANDCombine(SDNode *N,
8315 TargetLowering::DAGCombinerInfo &DCI,
8316 const ARMSubtarget *Subtarget) {
8318 // Attempt to use immediate-form VBIC
8319 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8321 EVT VT = N->getValueType(0);
8322 SelectionDAG &DAG = DCI.DAG;
8324 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8327 APInt SplatBits, SplatUndef;
8328 unsigned SplatBitSize;
8331 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8332 if (SplatBitSize <= 64) {
8334 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8335 SplatUndef.getZExtValue(), SplatBitSize,
8336 DAG, VbicVT, VT.is128BitVector(),
8338 if (Val.getNode()) {
8340 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
8341 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
8342 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
8347 if (!Subtarget->isThumb1Only()) {
8348 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8349 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8350 if (Result.getNode())
8357 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8358 static SDValue PerformORCombine(SDNode *N,
8359 TargetLowering::DAGCombinerInfo &DCI,
8360 const ARMSubtarget *Subtarget) {
8361 // Attempt to use immediate-form VORR
8362 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8364 EVT VT = N->getValueType(0);
8365 SelectionDAG &DAG = DCI.DAG;
8367 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8370 APInt SplatBits, SplatUndef;
8371 unsigned SplatBitSize;
8373 if (BVN && Subtarget->hasNEON() &&
8374 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8375 if (SplatBitSize <= 64) {
8377 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8378 SplatUndef.getZExtValue(), SplatBitSize,
8379 DAG, VorrVT, VT.is128BitVector(),
8381 if (Val.getNode()) {
8383 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8384 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8385 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8390 if (!Subtarget->isThumb1Only()) {
8391 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8392 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8393 if (Result.getNode())
8397 // The code below optimizes (or (and X, Y), Z).
8398 // The AND operand needs to have a single user to make these optimizations
8400 SDValue N0 = N->getOperand(0);
8401 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8403 SDValue N1 = N->getOperand(1);
8405 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8406 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8407 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8409 unsigned SplatBitSize;
8412 APInt SplatBits0, SplatBits1;
8413 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8414 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8415 // Ensure that the second operand of both ands are constants
8416 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8417 HasAnyUndefs) && !HasAnyUndefs) {
8418 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8419 HasAnyUndefs) && !HasAnyUndefs) {
8420 // Ensure that the bit width of the constants are the same and that
8421 // the splat arguments are logical inverses as per the pattern we
8422 // are trying to simplify.
8423 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8424 SplatBits0 == ~SplatBits1) {
8425 // Canonicalize the vector type to make instruction selection
8427 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8428 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8432 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8438 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8441 // BFI is only available on V6T2+
8442 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8446 // 1) or (and A, mask), val => ARMbfi A, val, mask
8447 // iff (val & mask) == val
8449 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8450 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8451 // && mask == ~mask2
8452 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8453 // && ~mask == mask2
8454 // (i.e., copy a bitfield value into another bitfield of the same width)
8459 SDValue N00 = N0.getOperand(0);
8461 // The value and the mask need to be constants so we can verify this is
8462 // actually a bitfield set. If the mask is 0xffff, we can do better
8463 // via a movt instruction, so don't use BFI in that case.
8464 SDValue MaskOp = N0.getOperand(1);
8465 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8468 unsigned Mask = MaskC->getZExtValue();
8472 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8473 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8475 unsigned Val = N1C->getZExtValue();
8476 if ((Val & ~Mask) != Val)
8479 if (ARM::isBitFieldInvertedMask(Mask)) {
8480 Val >>= countTrailingZeros(~Mask);
8482 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8483 DAG.getConstant(Val, MVT::i32),
8484 DAG.getConstant(Mask, MVT::i32));
8486 // Do not add new nodes to DAG combiner worklist.
8487 DCI.CombineTo(N, Res, false);
8490 } else if (N1.getOpcode() == ISD::AND) {
8491 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8492 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8495 unsigned Mask2 = N11C->getZExtValue();
8497 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8499 if (ARM::isBitFieldInvertedMask(Mask) &&
8501 // The pack halfword instruction works better for masks that fit it,
8502 // so use that when it's available.
8503 if (Subtarget->hasT2ExtractPack() &&
8504 (Mask == 0xffff || Mask == 0xffff0000))
8507 unsigned amt = countTrailingZeros(Mask2);
8508 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8509 DAG.getConstant(amt, MVT::i32));
8510 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8511 DAG.getConstant(Mask, MVT::i32));
8512 // Do not add new nodes to DAG combiner worklist.
8513 DCI.CombineTo(N, Res, false);
8515 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8517 // The pack halfword instruction works better for masks that fit it,
8518 // so use that when it's available.
8519 if (Subtarget->hasT2ExtractPack() &&
8520 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8523 unsigned lsb = countTrailingZeros(Mask);
8524 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8525 DAG.getConstant(lsb, MVT::i32));
8526 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8527 DAG.getConstant(Mask2, MVT::i32));
8528 // Do not add new nodes to DAG combiner worklist.
8529 DCI.CombineTo(N, Res, false);
8534 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8535 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8536 ARM::isBitFieldInvertedMask(~Mask)) {
8537 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8538 // where lsb(mask) == #shamt and masked bits of B are known zero.
8539 SDValue ShAmt = N00.getOperand(1);
8540 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8541 unsigned LSB = countTrailingZeros(Mask);
8545 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8546 DAG.getConstant(~Mask, MVT::i32));
8548 // Do not add new nodes to DAG combiner worklist.
8549 DCI.CombineTo(N, Res, false);
8555 static SDValue PerformXORCombine(SDNode *N,
8556 TargetLowering::DAGCombinerInfo &DCI,
8557 const ARMSubtarget *Subtarget) {
8558 EVT VT = N->getValueType(0);
8559 SelectionDAG &DAG = DCI.DAG;
8561 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8564 if (!Subtarget->isThumb1Only()) {
8565 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8566 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8567 if (Result.getNode())
8574 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8575 /// the bits being cleared by the AND are not demanded by the BFI.
8576 static SDValue PerformBFICombine(SDNode *N,
8577 TargetLowering::DAGCombinerInfo &DCI) {
8578 SDValue N1 = N->getOperand(1);
8579 if (N1.getOpcode() == ISD::AND) {
8580 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8583 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8584 unsigned LSB = countTrailingZeros(~InvMask);
8585 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8586 unsigned Mask = (1 << Width)-1;
8587 unsigned Mask2 = N11C->getZExtValue();
8588 if ((Mask & (~Mask2)) == 0)
8589 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
8590 N->getOperand(0), N1.getOperand(0),
8596 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8597 /// ARMISD::VMOVRRD.
8598 static SDValue PerformVMOVRRDCombine(SDNode *N,
8599 TargetLowering::DAGCombinerInfo &DCI,
8600 const ARMSubtarget *Subtarget) {
8601 // vmovrrd(vmovdrr x, y) -> x,y
8602 SDValue InDouble = N->getOperand(0);
8603 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP())
8604 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8606 // vmovrrd(load f64) -> (load i32), (load i32)
8607 SDNode *InNode = InDouble.getNode();
8608 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8609 InNode->getValueType(0) == MVT::f64 &&
8610 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8611 !cast<LoadSDNode>(InNode)->isVolatile()) {
8612 // TODO: Should this be done for non-FrameIndex operands?
8613 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8615 SelectionDAG &DAG = DCI.DAG;
8617 SDValue BasePtr = LD->getBasePtr();
8618 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8619 LD->getPointerInfo(), LD->isVolatile(),
8620 LD->isNonTemporal(), LD->isInvariant(),
8621 LD->getAlignment());
8623 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8624 DAG.getConstant(4, MVT::i32));
8625 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8626 LD->getPointerInfo(), LD->isVolatile(),
8627 LD->isNonTemporal(), LD->isInvariant(),
8628 std::min(4U, LD->getAlignment() / 2));
8630 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8631 if (DCI.DAG.getTargetLoweringInfo().isBigEndian())
8632 std::swap (NewLD1, NewLD2);
8633 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8640 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8641 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8642 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8643 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8644 SDValue Op0 = N->getOperand(0);
8645 SDValue Op1 = N->getOperand(1);
8646 if (Op0.getOpcode() == ISD::BITCAST)
8647 Op0 = Op0.getOperand(0);
8648 if (Op1.getOpcode() == ISD::BITCAST)
8649 Op1 = Op1.getOperand(0);
8650 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8651 Op0.getNode() == Op1.getNode() &&
8652 Op0.getResNo() == 0 && Op1.getResNo() == 1)
8653 return DAG.getNode(ISD::BITCAST, SDLoc(N),
8654 N->getValueType(0), Op0.getOperand(0));
8658 /// PerformSTORECombine - Target-specific dag combine xforms for
8660 static SDValue PerformSTORECombine(SDNode *N,
8661 TargetLowering::DAGCombinerInfo &DCI) {
8662 StoreSDNode *St = cast<StoreSDNode>(N);
8663 if (St->isVolatile())
8666 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
8667 // pack all of the elements in one place. Next, store to memory in fewer
8669 SDValue StVal = St->getValue();
8670 EVT VT = StVal.getValueType();
8671 if (St->isTruncatingStore() && VT.isVector()) {
8672 SelectionDAG &DAG = DCI.DAG;
8673 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8674 EVT StVT = St->getMemoryVT();
8675 unsigned NumElems = VT.getVectorNumElements();
8676 assert(StVT != VT && "Cannot truncate to the same type");
8677 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
8678 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
8680 // From, To sizes and ElemCount must be pow of two
8681 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
8683 // We are going to use the original vector elt for storing.
8684 // Accumulated smaller vector elements must be a multiple of the store size.
8685 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
8687 unsigned SizeRatio = FromEltSz / ToEltSz;
8688 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
8690 // Create a type on which we perform the shuffle.
8691 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
8692 NumElems*SizeRatio);
8693 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
8696 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
8697 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
8698 for (unsigned i = 0; i < NumElems; ++i)
8699 ShuffleVec[i] = TLI.isBigEndian() ? (i+1) * SizeRatio - 1 : i * SizeRatio;
8701 // Can't shuffle using an illegal type.
8702 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
8704 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
8705 DAG.getUNDEF(WideVec.getValueType()),
8707 // At this point all of the data is stored at the bottom of the
8708 // register. We now need to save it to mem.
8710 // Find the largest store unit
8711 MVT StoreType = MVT::i8;
8712 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
8713 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
8714 MVT Tp = (MVT::SimpleValueType)tp;
8715 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
8718 // Didn't find a legal store type.
8719 if (!TLI.isTypeLegal(StoreType))
8722 // Bitcast the original vector into a vector of store-size units
8723 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
8724 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
8725 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
8726 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
8727 SmallVector<SDValue, 8> Chains;
8728 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
8729 TLI.getPointerTy());
8730 SDValue BasePtr = St->getBasePtr();
8732 // Perform one or more big stores into memory.
8733 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
8734 for (unsigned I = 0; I < E; I++) {
8735 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
8736 StoreType, ShuffWide,
8737 DAG.getIntPtrConstant(I));
8738 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
8739 St->getPointerInfo(), St->isVolatile(),
8740 St->isNonTemporal(), St->getAlignment());
8741 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
8743 Chains.push_back(Ch);
8745 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
8748 if (!ISD::isNormalStore(St))
8751 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
8752 // ARM stores of arguments in the same cache line.
8753 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
8754 StVal.getNode()->hasOneUse()) {
8755 SelectionDAG &DAG = DCI.DAG;
8756 bool isBigEndian = DAG.getTargetLoweringInfo().isBigEndian();
8758 SDValue BasePtr = St->getBasePtr();
8759 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
8760 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
8761 BasePtr, St->getPointerInfo(), St->isVolatile(),
8762 St->isNonTemporal(), St->getAlignment());
8764 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8765 DAG.getConstant(4, MVT::i32));
8766 return DAG.getStore(NewST1.getValue(0), DL,
8767 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
8768 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
8769 St->isNonTemporal(),
8770 std::min(4U, St->getAlignment() / 2));
8773 if (StVal.getValueType() != MVT::i64 ||
8774 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8777 // Bitcast an i64 store extracted from a vector to f64.
8778 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8779 SelectionDAG &DAG = DCI.DAG;
8781 SDValue IntVec = StVal.getOperand(0);
8782 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8783 IntVec.getValueType().getVectorNumElements());
8784 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
8785 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8786 Vec, StVal.getOperand(1));
8788 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
8789 // Make the DAGCombiner fold the bitcasts.
8790 DCI.AddToWorklist(Vec.getNode());
8791 DCI.AddToWorklist(ExtElt.getNode());
8792 DCI.AddToWorklist(V.getNode());
8793 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
8794 St->getPointerInfo(), St->isVolatile(),
8795 St->isNonTemporal(), St->getAlignment(),
8799 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8800 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
8801 /// i64 vector to have f64 elements, since the value can then be loaded
8802 /// directly into a VFP register.
8803 static bool hasNormalLoadOperand(SDNode *N) {
8804 unsigned NumElts = N->getValueType(0).getVectorNumElements();
8805 for (unsigned i = 0; i < NumElts; ++i) {
8806 SDNode *Elt = N->getOperand(i).getNode();
8807 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8813 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8814 /// ISD::BUILD_VECTOR.
8815 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8816 TargetLowering::DAGCombinerInfo &DCI,
8817 const ARMSubtarget *Subtarget) {
8818 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8819 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
8820 // into a pair of GPRs, which is fine when the value is used as a scalar,
8821 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8822 SelectionDAG &DAG = DCI.DAG;
8823 if (N->getNumOperands() == 2) {
8824 SDValue RV = PerformVMOVDRRCombine(N, DAG);
8829 // Load i64 elements as f64 values so that type legalization does not split
8830 // them up into i32 values.
8831 EVT VT = N->getValueType(0);
8832 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8835 SmallVector<SDValue, 8> Ops;
8836 unsigned NumElts = VT.getVectorNumElements();
8837 for (unsigned i = 0; i < NumElts; ++i) {
8838 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8840 // Make the DAGCombiner fold the bitcast.
8841 DCI.AddToWorklist(V.getNode());
8843 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8844 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
8845 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8848 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
8850 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8851 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
8852 // At that time, we may have inserted bitcasts from integer to float.
8853 // If these bitcasts have survived DAGCombine, change the lowering of this
8854 // BUILD_VECTOR in something more vector friendly, i.e., that does not
8855 // force to use floating point types.
8857 // Make sure we can change the type of the vector.
8858 // This is possible iff:
8859 // 1. The vector is only used in a bitcast to a integer type. I.e.,
8860 // 1.1. Vector is used only once.
8861 // 1.2. Use is a bit convert to an integer type.
8862 // 2. The size of its operands are 32-bits (64-bits are not legal).
8863 EVT VT = N->getValueType(0);
8864 EVT EltVT = VT.getVectorElementType();
8866 // Check 1.1. and 2.
8867 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
8870 // By construction, the input type must be float.
8871 assert(EltVT == MVT::f32 && "Unexpected type!");
8874 SDNode *Use = *N->use_begin();
8875 if (Use->getOpcode() != ISD::BITCAST ||
8876 Use->getValueType(0).isFloatingPoint())
8879 // Check profitability.
8880 // Model is, if more than half of the relevant operands are bitcast from
8881 // i32, turn the build_vector into a sequence of insert_vector_elt.
8882 // Relevant operands are everything that is not statically
8883 // (i.e., at compile time) bitcasted.
8884 unsigned NumOfBitCastedElts = 0;
8885 unsigned NumElts = VT.getVectorNumElements();
8886 unsigned NumOfRelevantElts = NumElts;
8887 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
8888 SDValue Elt = N->getOperand(Idx);
8889 if (Elt->getOpcode() == ISD::BITCAST) {
8890 // Assume only bit cast to i32 will go away.
8891 if (Elt->getOperand(0).getValueType() == MVT::i32)
8892 ++NumOfBitCastedElts;
8893 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
8894 // Constants are statically casted, thus do not count them as
8895 // relevant operands.
8896 --NumOfRelevantElts;
8899 // Check if more than half of the elements require a non-free bitcast.
8900 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
8903 SelectionDAG &DAG = DCI.DAG;
8904 // Create the new vector type.
8905 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
8906 // Check if the type is legal.
8907 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8908 if (!TLI.isTypeLegal(VecVT))
8912 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
8913 // => BITCAST INSERT_VECTOR_ELT
8914 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
8916 SDValue Vec = DAG.getUNDEF(VecVT);
8918 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
8919 SDValue V = N->getOperand(Idx);
8920 if (V.getOpcode() == ISD::UNDEF)
8922 if (V.getOpcode() == ISD::BITCAST &&
8923 V->getOperand(0).getValueType() == MVT::i32)
8924 // Fold obvious case.
8925 V = V.getOperand(0);
8927 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
8928 // Make the DAGCombiner fold the bitcasts.
8929 DCI.AddToWorklist(V.getNode());
8931 SDValue LaneIdx = DAG.getConstant(Idx, MVT::i32);
8932 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
8934 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
8935 // Make the DAGCombiner fold the bitcasts.
8936 DCI.AddToWorklist(Vec.getNode());
8940 /// PerformInsertEltCombine - Target-specific dag combine xforms for
8941 /// ISD::INSERT_VECTOR_ELT.
8942 static SDValue PerformInsertEltCombine(SDNode *N,
8943 TargetLowering::DAGCombinerInfo &DCI) {
8944 // Bitcast an i64 load inserted into a vector to f64.
8945 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8946 EVT VT = N->getValueType(0);
8947 SDNode *Elt = N->getOperand(1).getNode();
8948 if (VT.getVectorElementType() != MVT::i64 ||
8949 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
8952 SelectionDAG &DAG = DCI.DAG;
8954 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8955 VT.getVectorNumElements());
8956 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
8957 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
8958 // Make the DAGCombiner fold the bitcasts.
8959 DCI.AddToWorklist(Vec.getNode());
8960 DCI.AddToWorklist(V.getNode());
8961 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
8962 Vec, V, N->getOperand(2));
8963 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
8966 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
8967 /// ISD::VECTOR_SHUFFLE.
8968 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
8969 // The LLVM shufflevector instruction does not require the shuffle mask
8970 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
8971 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
8972 // operands do not match the mask length, they are extended by concatenating
8973 // them with undef vectors. That is probably the right thing for other
8974 // targets, but for NEON it is better to concatenate two double-register
8975 // size vector operands into a single quad-register size vector. Do that
8976 // transformation here:
8977 // shuffle(concat(v1, undef), concat(v2, undef)) ->
8978 // shuffle(concat(v1, v2), undef)
8979 SDValue Op0 = N->getOperand(0);
8980 SDValue Op1 = N->getOperand(1);
8981 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8982 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8983 Op0.getNumOperands() != 2 ||
8984 Op1.getNumOperands() != 2)
8986 SDValue Concat0Op1 = Op0.getOperand(1);
8987 SDValue Concat1Op1 = Op1.getOperand(1);
8988 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8989 Concat1Op1.getOpcode() != ISD::UNDEF)
8991 // Skip the transformation if any of the types are illegal.
8992 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8993 EVT VT = N->getValueType(0);
8994 if (!TLI.isTypeLegal(VT) ||
8995 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
8996 !TLI.isTypeLegal(Concat1Op1.getValueType()))
8999 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
9000 Op0.getOperand(0), Op1.getOperand(0));
9001 // Translate the shuffle mask.
9002 SmallVector<int, 16> NewMask;
9003 unsigned NumElts = VT.getVectorNumElements();
9004 unsigned HalfElts = NumElts/2;
9005 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9006 for (unsigned n = 0; n < NumElts; ++n) {
9007 int MaskElt = SVN->getMaskElt(n);
9009 if (MaskElt < (int)HalfElts)
9011 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
9012 NewElt = HalfElts + MaskElt - NumElts;
9013 NewMask.push_back(NewElt);
9015 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
9016 DAG.getUNDEF(VT), NewMask.data());
9019 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
9020 /// NEON load/store intrinsics to merge base address updates.
9021 static SDValue CombineBaseUpdate(SDNode *N,
9022 TargetLowering::DAGCombinerInfo &DCI) {
9023 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9026 SelectionDAG &DAG = DCI.DAG;
9027 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
9028 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
9029 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
9030 SDValue Addr = N->getOperand(AddrOpIdx);
9032 // Search for a use of the address operand that is an increment.
9033 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
9034 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
9036 if (User->getOpcode() != ISD::ADD ||
9037 UI.getUse().getResNo() != Addr.getResNo())
9040 // Check that the add is independent of the load/store. Otherwise, folding
9041 // it would create a cycle.
9042 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
9045 // Find the new opcode for the updating load/store.
9047 bool isLaneOp = false;
9048 unsigned NewOpc = 0;
9049 unsigned NumVecs = 0;
9051 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9053 default: llvm_unreachable("unexpected intrinsic for Neon base update");
9054 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
9056 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
9058 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
9060 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
9062 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
9063 NumVecs = 2; isLaneOp = true; break;
9064 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
9065 NumVecs = 3; isLaneOp = true; break;
9066 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
9067 NumVecs = 4; isLaneOp = true; break;
9068 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
9069 NumVecs = 1; isLoad = false; break;
9070 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
9071 NumVecs = 2; isLoad = false; break;
9072 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
9073 NumVecs = 3; isLoad = false; break;
9074 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
9075 NumVecs = 4; isLoad = false; break;
9076 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
9077 NumVecs = 2; isLoad = false; isLaneOp = true; break;
9078 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
9079 NumVecs = 3; isLoad = false; isLaneOp = true; break;
9080 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
9081 NumVecs = 4; isLoad = false; isLaneOp = true; break;
9085 switch (N->getOpcode()) {
9086 default: llvm_unreachable("unexpected opcode for Neon base update");
9087 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
9088 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
9089 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
9093 // Find the size of memory referenced by the load/store.
9096 VecTy = N->getValueType(0);
9098 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
9099 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
9101 NumBytes /= VecTy.getVectorNumElements();
9103 // If the increment is a constant, it must match the memory ref size.
9104 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
9105 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
9106 uint64_t IncVal = CInc->getZExtValue();
9107 if (IncVal != NumBytes)
9109 } else if (NumBytes >= 3 * 16) {
9110 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
9111 // separate instructions that make it harder to use a non-constant update.
9115 // Create the new updating load/store node.
9117 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
9119 for (n = 0; n < NumResultVecs; ++n)
9121 Tys[n++] = MVT::i32;
9122 Tys[n] = MVT::Other;
9123 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
9124 SmallVector<SDValue, 8> Ops;
9125 Ops.push_back(N->getOperand(0)); // incoming chain
9126 Ops.push_back(N->getOperand(AddrOpIdx));
9128 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
9129 Ops.push_back(N->getOperand(i));
9131 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
9132 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
9133 Ops, MemInt->getMemoryVT(),
9134 MemInt->getMemOperand());
9137 std::vector<SDValue> NewResults;
9138 for (unsigned i = 0; i < NumResultVecs; ++i) {
9139 NewResults.push_back(SDValue(UpdN.getNode(), i));
9141 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
9142 DCI.CombineTo(N, NewResults);
9143 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9150 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
9151 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
9152 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
9154 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9155 SelectionDAG &DAG = DCI.DAG;
9156 EVT VT = N->getValueType(0);
9157 // vldN-dup instructions only support 64-bit vectors for N > 1.
9158 if (!VT.is64BitVector())
9161 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
9162 SDNode *VLD = N->getOperand(0).getNode();
9163 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
9165 unsigned NumVecs = 0;
9166 unsigned NewOpc = 0;
9167 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
9168 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9170 NewOpc = ARMISD::VLD2DUP;
9171 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9173 NewOpc = ARMISD::VLD3DUP;
9174 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9176 NewOpc = ARMISD::VLD4DUP;
9181 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
9182 // numbers match the load.
9183 unsigned VLDLaneNo =
9184 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
9185 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9187 // Ignore uses of the chain result.
9188 if (UI.getUse().getResNo() == NumVecs)
9191 if (User->getOpcode() != ARMISD::VDUPLANE ||
9192 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9196 // Create the vldN-dup node.
9199 for (n = 0; n < NumVecs; ++n)
9201 Tys[n] = MVT::Other;
9202 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1));
9203 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9204 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
9205 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
9206 Ops, VLDMemInt->getMemoryVT(),
9207 VLDMemInt->getMemOperand());
9210 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9212 unsigned ResNo = UI.getUse().getResNo();
9213 // Ignore uses of the chain result.
9214 if (ResNo == NumVecs)
9217 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9220 // Now the vldN-lane intrinsic is dead except for its chain result.
9221 // Update uses of the chain.
9222 std::vector<SDValue> VLDDupResults;
9223 for (unsigned n = 0; n < NumVecs; ++n)
9224 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9225 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9226 DCI.CombineTo(VLD, VLDDupResults);
9231 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
9232 /// ARMISD::VDUPLANE.
9233 static SDValue PerformVDUPLANECombine(SDNode *N,
9234 TargetLowering::DAGCombinerInfo &DCI) {
9235 SDValue Op = N->getOperand(0);
9237 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9238 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9239 if (CombineVLDDUP(N, DCI))
9240 return SDValue(N, 0);
9242 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9243 // redundant. Ignore bit_converts for now; element sizes are checked below.
9244 while (Op.getOpcode() == ISD::BITCAST)
9245 Op = Op.getOperand(0);
9246 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
9249 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9250 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9251 // The canonical VMOV for a zero vector uses a 32-bit element size.
9252 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9254 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9256 EVT VT = N->getValueType(0);
9257 if (EltSize > VT.getVectorElementType().getSizeInBits())
9260 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9263 // isConstVecPow2 - Return true if each vector element is a power of 2, all
9264 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
9265 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
9269 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
9271 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
9276 APFloat APF = C->getValueAPF();
9277 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
9278 != APFloat::opOK || !isExact)
9281 c0 = (I == 0) ? cN : c0;
9282 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
9289 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
9290 /// can replace combinations of VMUL and VCVT (floating-point to integer)
9291 /// when the VMUL has a constant operand that is a power of 2.
9293 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9294 /// vmul.f32 d16, d17, d16
9295 /// vcvt.s32.f32 d16, d16
9297 /// vcvt.s32.f32 d16, d16, #3
9298 static SDValue PerformVCVTCombine(SDNode *N,
9299 TargetLowering::DAGCombinerInfo &DCI,
9300 const ARMSubtarget *Subtarget) {
9301 SelectionDAG &DAG = DCI.DAG;
9302 SDValue Op = N->getOperand(0);
9304 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9305 Op.getOpcode() != ISD::FMUL)
9309 SDValue N0 = Op->getOperand(0);
9310 SDValue ConstVec = Op->getOperand(1);
9311 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
9313 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9314 !isConstVecPow2(ConstVec, isSigned, C))
9317 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9318 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9319 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9320 // These instructions only exist converting from f32 to i32. We can handle
9321 // smaller integers by generating an extra truncate, but larger ones would
9326 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9327 Intrinsic::arm_neon_vcvtfp2fxu;
9328 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9329 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9330 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9331 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
9332 DAG.getConstant(Log2_64(C), MVT::i32));
9334 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9335 FixConv = DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), FixConv);
9340 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
9341 /// can replace combinations of VCVT (integer to floating-point) and VDIV
9342 /// when the VDIV has a constant operand that is a power of 2.
9344 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9345 /// vcvt.f32.s32 d16, d16
9346 /// vdiv.f32 d16, d17, d16
9348 /// vcvt.f32.s32 d16, d16, #3
9349 static SDValue PerformVDIVCombine(SDNode *N,
9350 TargetLowering::DAGCombinerInfo &DCI,
9351 const ARMSubtarget *Subtarget) {
9352 SelectionDAG &DAG = DCI.DAG;
9353 SDValue Op = N->getOperand(0);
9354 unsigned OpOpcode = Op.getNode()->getOpcode();
9356 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9357 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
9361 SDValue ConstVec = N->getOperand(1);
9362 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
9364 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9365 !isConstVecPow2(ConstVec, isSigned, C))
9368 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9369 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9370 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9371 // These instructions only exist converting from i32 to f32. We can handle
9372 // smaller integers by generating an extra extend, but larger ones would
9377 SDValue ConvInput = Op.getOperand(0);
9378 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9379 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9380 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
9381 SDLoc(N), NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9384 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
9385 Intrinsic::arm_neon_vcvtfxu2fp;
9386 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9388 DAG.getConstant(IntrinsicOpcode, MVT::i32),
9389 ConvInput, DAG.getConstant(Log2_64(C), MVT::i32));
9392 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
9393 /// operand of a vector shift operation, where all the elements of the
9394 /// build_vector must have the same constant integer value.
9395 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
9396 // Ignore bit_converts.
9397 while (Op.getOpcode() == ISD::BITCAST)
9398 Op = Op.getOperand(0);
9399 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
9400 APInt SplatBits, SplatUndef;
9401 unsigned SplatBitSize;
9403 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
9404 HasAnyUndefs, ElementBits) ||
9405 SplatBitSize > ElementBits)
9407 Cnt = SplatBits.getSExtValue();
9411 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
9412 /// operand of a vector shift left operation. That value must be in the range:
9413 /// 0 <= Value < ElementBits for a left shift; or
9414 /// 0 <= Value <= ElementBits for a long left shift.
9415 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
9416 assert(VT.isVector() && "vector shift count is not a vector type");
9417 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9418 if (! getVShiftImm(Op, ElementBits, Cnt))
9420 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
9423 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
9424 /// operand of a vector shift right operation. For a shift opcode, the value
9425 /// is positive, but for an intrinsic the value count must be negative. The
9426 /// absolute value must be in the range:
9427 /// 1 <= |Value| <= ElementBits for a right shift; or
9428 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
9429 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
9431 assert(VT.isVector() && "vector shift count is not a vector type");
9432 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9433 if (! getVShiftImm(Op, ElementBits, Cnt))
9437 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
9440 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
9441 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
9442 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9445 // Don't do anything for most intrinsics.
9448 // Vector shifts: check for immediate versions and lower them.
9449 // Note: This is done during DAG combining instead of DAG legalizing because
9450 // the build_vectors for 64-bit vector element shift counts are generally
9451 // not legal, and it is hard to see their values after they get legalized to
9452 // loads from a constant pool.
9453 case Intrinsic::arm_neon_vshifts:
9454 case Intrinsic::arm_neon_vshiftu:
9455 case Intrinsic::arm_neon_vrshifts:
9456 case Intrinsic::arm_neon_vrshiftu:
9457 case Intrinsic::arm_neon_vrshiftn:
9458 case Intrinsic::arm_neon_vqshifts:
9459 case Intrinsic::arm_neon_vqshiftu:
9460 case Intrinsic::arm_neon_vqshiftsu:
9461 case Intrinsic::arm_neon_vqshiftns:
9462 case Intrinsic::arm_neon_vqshiftnu:
9463 case Intrinsic::arm_neon_vqshiftnsu:
9464 case Intrinsic::arm_neon_vqrshiftns:
9465 case Intrinsic::arm_neon_vqrshiftnu:
9466 case Intrinsic::arm_neon_vqrshiftnsu: {
9467 EVT VT = N->getOperand(1).getValueType();
9469 unsigned VShiftOpc = 0;
9472 case Intrinsic::arm_neon_vshifts:
9473 case Intrinsic::arm_neon_vshiftu:
9474 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9475 VShiftOpc = ARMISD::VSHL;
9478 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9479 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9480 ARMISD::VSHRs : ARMISD::VSHRu);
9485 case Intrinsic::arm_neon_vrshifts:
9486 case Intrinsic::arm_neon_vrshiftu:
9487 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9491 case Intrinsic::arm_neon_vqshifts:
9492 case Intrinsic::arm_neon_vqshiftu:
9493 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9497 case Intrinsic::arm_neon_vqshiftsu:
9498 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9500 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9502 case Intrinsic::arm_neon_vrshiftn:
9503 case Intrinsic::arm_neon_vqshiftns:
9504 case Intrinsic::arm_neon_vqshiftnu:
9505 case Intrinsic::arm_neon_vqshiftnsu:
9506 case Intrinsic::arm_neon_vqrshiftns:
9507 case Intrinsic::arm_neon_vqrshiftnu:
9508 case Intrinsic::arm_neon_vqrshiftnsu:
9509 // Narrowing shifts require an immediate right shift.
9510 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9512 llvm_unreachable("invalid shift count for narrowing vector shift "
9516 llvm_unreachable("unhandled vector shift");
9520 case Intrinsic::arm_neon_vshifts:
9521 case Intrinsic::arm_neon_vshiftu:
9522 // Opcode already set above.
9524 case Intrinsic::arm_neon_vrshifts:
9525 VShiftOpc = ARMISD::VRSHRs; break;
9526 case Intrinsic::arm_neon_vrshiftu:
9527 VShiftOpc = ARMISD::VRSHRu; break;
9528 case Intrinsic::arm_neon_vrshiftn:
9529 VShiftOpc = ARMISD::VRSHRN; break;
9530 case Intrinsic::arm_neon_vqshifts:
9531 VShiftOpc = ARMISD::VQSHLs; break;
9532 case Intrinsic::arm_neon_vqshiftu:
9533 VShiftOpc = ARMISD::VQSHLu; break;
9534 case Intrinsic::arm_neon_vqshiftsu:
9535 VShiftOpc = ARMISD::VQSHLsu; break;
9536 case Intrinsic::arm_neon_vqshiftns:
9537 VShiftOpc = ARMISD::VQSHRNs; break;
9538 case Intrinsic::arm_neon_vqshiftnu:
9539 VShiftOpc = ARMISD::VQSHRNu; break;
9540 case Intrinsic::arm_neon_vqshiftnsu:
9541 VShiftOpc = ARMISD::VQSHRNsu; break;
9542 case Intrinsic::arm_neon_vqrshiftns:
9543 VShiftOpc = ARMISD::VQRSHRNs; break;
9544 case Intrinsic::arm_neon_vqrshiftnu:
9545 VShiftOpc = ARMISD::VQRSHRNu; break;
9546 case Intrinsic::arm_neon_vqrshiftnsu:
9547 VShiftOpc = ARMISD::VQRSHRNsu; break;
9550 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9551 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
9554 case Intrinsic::arm_neon_vshiftins: {
9555 EVT VT = N->getOperand(1).getValueType();
9557 unsigned VShiftOpc = 0;
9559 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9560 VShiftOpc = ARMISD::VSLI;
9561 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9562 VShiftOpc = ARMISD::VSRI;
9564 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9567 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9568 N->getOperand(1), N->getOperand(2),
9569 DAG.getConstant(Cnt, MVT::i32));
9572 case Intrinsic::arm_neon_vqrshifts:
9573 case Intrinsic::arm_neon_vqrshiftu:
9574 // No immediate versions of these to check for.
9581 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
9582 /// lowers them. As with the vector shift intrinsics, this is done during DAG
9583 /// combining instead of DAG legalizing because the build_vectors for 64-bit
9584 /// vector element shift counts are generally not legal, and it is hard to see
9585 /// their values after they get legalized to loads from a constant pool.
9586 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9587 const ARMSubtarget *ST) {
9588 EVT VT = N->getValueType(0);
9589 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9590 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9591 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9592 SDValue N1 = N->getOperand(1);
9593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9594 SDValue N0 = N->getOperand(0);
9595 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9596 DAG.MaskedValueIsZero(N0.getOperand(0),
9597 APInt::getHighBitsSet(32, 16)))
9598 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9602 // Nothing to be done for scalar shifts.
9603 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9604 if (!VT.isVector() || !TLI.isTypeLegal(VT))
9607 assert(ST->hasNEON() && "unexpected vector shift");
9610 switch (N->getOpcode()) {
9611 default: llvm_unreachable("unexpected shift opcode");
9614 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
9615 return DAG.getNode(ARMISD::VSHL, SDLoc(N), VT, N->getOperand(0),
9616 DAG.getConstant(Cnt, MVT::i32));
9621 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
9622 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9623 ARMISD::VSHRs : ARMISD::VSHRu);
9624 return DAG.getNode(VShiftOpc, SDLoc(N), VT, N->getOperand(0),
9625 DAG.getConstant(Cnt, MVT::i32));
9631 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
9632 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
9633 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
9634 const ARMSubtarget *ST) {
9635 SDValue N0 = N->getOperand(0);
9637 // Check for sign- and zero-extensions of vector extract operations of 8-
9638 // and 16-bit vector elements. NEON supports these directly. They are
9639 // handled during DAG combining because type legalization will promote them
9640 // to 32-bit types and it is messy to recognize the operations after that.
9641 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9642 SDValue Vec = N0.getOperand(0);
9643 SDValue Lane = N0.getOperand(1);
9644 EVT VT = N->getValueType(0);
9645 EVT EltVT = N0.getValueType();
9646 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9648 if (VT == MVT::i32 &&
9649 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
9650 TLI.isTypeLegal(Vec.getValueType()) &&
9651 isa<ConstantSDNode>(Lane)) {
9654 switch (N->getOpcode()) {
9655 default: llvm_unreachable("unexpected opcode");
9656 case ISD::SIGN_EXTEND:
9657 Opc = ARMISD::VGETLANEs;
9659 case ISD::ZERO_EXTEND:
9660 case ISD::ANY_EXTEND:
9661 Opc = ARMISD::VGETLANEu;
9664 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
9671 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
9672 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
9673 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
9674 const ARMSubtarget *ST) {
9675 // If the target supports NEON, try to use vmax/vmin instructions for f32
9676 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
9677 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
9678 // a NaN; only do the transformation when it matches that behavior.
9680 // For now only do this when using NEON for FP operations; if using VFP, it
9681 // is not obvious that the benefit outweighs the cost of switching to the
9683 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
9684 N->getValueType(0) != MVT::f32)
9687 SDValue CondLHS = N->getOperand(0);
9688 SDValue CondRHS = N->getOperand(1);
9689 SDValue LHS = N->getOperand(2);
9690 SDValue RHS = N->getOperand(3);
9691 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9693 unsigned Opcode = 0;
9695 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
9696 IsReversed = false; // x CC y ? x : y
9697 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
9698 IsReversed = true ; // x CC y ? y : x
9712 // If LHS is NaN, an ordered comparison will be false and the result will
9713 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
9714 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9715 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
9716 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9718 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
9719 // will return -0, so vmin can only be used for unsafe math or if one of
9720 // the operands is known to be nonzero.
9721 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
9722 !DAG.getTarget().Options.UnsafeFPMath &&
9723 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9725 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
9734 // If LHS is NaN, an ordered comparison will be false and the result will
9735 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
9736 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9737 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
9738 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9740 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
9741 // will return +0, so vmax can only be used for unsafe math or if one of
9742 // the operands is known to be nonzero.
9743 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
9744 !DAG.getTarget().Options.UnsafeFPMath &&
9745 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9747 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
9753 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
9756 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
9758 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
9759 SDValue Cmp = N->getOperand(4);
9760 if (Cmp.getOpcode() != ARMISD::CMPZ)
9761 // Only looking at EQ and NE cases.
9764 EVT VT = N->getValueType(0);
9766 SDValue LHS = Cmp.getOperand(0);
9767 SDValue RHS = Cmp.getOperand(1);
9768 SDValue FalseVal = N->getOperand(0);
9769 SDValue TrueVal = N->getOperand(1);
9770 SDValue ARMcc = N->getOperand(2);
9771 ARMCC::CondCodes CC =
9772 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
9790 /// FIXME: Turn this into a target neutral optimization?
9792 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
9793 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
9794 N->getOperand(3), Cmp);
9795 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
9797 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
9798 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9799 N->getOperand(3), NewCmp);
9802 if (Res.getNode()) {
9803 APInt KnownZero, KnownOne;
9804 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
9805 // Capture demanded bits information that would be otherwise lost.
9806 if (KnownZero == 0xfffffffe)
9807 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9808 DAG.getValueType(MVT::i1));
9809 else if (KnownZero == 0xffffff00)
9810 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9811 DAG.getValueType(MVT::i8));
9812 else if (KnownZero == 0xffff0000)
9813 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9814 DAG.getValueType(MVT::i16));
9820 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
9821 DAGCombinerInfo &DCI) const {
9822 switch (N->getOpcode()) {
9824 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
9825 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
9826 case ISD::SUB: return PerformSUBCombine(N, DCI);
9827 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
9828 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
9829 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
9830 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
9831 case ARMISD::BFI: return PerformBFICombine(N, DCI);
9832 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
9833 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
9834 case ISD::STORE: return PerformSTORECombine(N, DCI);
9835 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
9836 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
9837 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
9838 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
9839 case ISD::FP_TO_SINT:
9840 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
9841 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
9842 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
9845 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
9846 case ISD::SIGN_EXTEND:
9847 case ISD::ZERO_EXTEND:
9848 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
9849 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
9850 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
9851 case ARMISD::VLD2DUP:
9852 case ARMISD::VLD3DUP:
9853 case ARMISD::VLD4DUP:
9854 return CombineBaseUpdate(N, DCI);
9855 case ARMISD::BUILD_VECTOR:
9856 return PerformARMBUILD_VECTORCombine(N, DCI);
9857 case ISD::INTRINSIC_VOID:
9858 case ISD::INTRINSIC_W_CHAIN:
9859 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9860 case Intrinsic::arm_neon_vld1:
9861 case Intrinsic::arm_neon_vld2:
9862 case Intrinsic::arm_neon_vld3:
9863 case Intrinsic::arm_neon_vld4:
9864 case Intrinsic::arm_neon_vld2lane:
9865 case Intrinsic::arm_neon_vld3lane:
9866 case Intrinsic::arm_neon_vld4lane:
9867 case Intrinsic::arm_neon_vst1:
9868 case Intrinsic::arm_neon_vst2:
9869 case Intrinsic::arm_neon_vst3:
9870 case Intrinsic::arm_neon_vst4:
9871 case Intrinsic::arm_neon_vst2lane:
9872 case Intrinsic::arm_neon_vst3lane:
9873 case Intrinsic::arm_neon_vst4lane:
9874 return CombineBaseUpdate(N, DCI);
9882 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
9884 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9887 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9891 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
9892 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
9894 switch (VT.getSimpleVT().SimpleTy) {
9900 // Unaligned access can use (for example) LRDB, LRDH, LDR
9901 if (AllowsUnaligned) {
9903 *Fast = Subtarget->hasV7Ops();
9910 // For any little-endian targets with neon, we can support unaligned ld/st
9911 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
9912 // A big-endian target may also explicitly support unaligned accesses
9913 if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
9923 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
9924 unsigned AlignCheck) {
9925 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
9926 (DstAlign == 0 || DstAlign % AlignCheck == 0));
9929 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
9930 unsigned DstAlign, unsigned SrcAlign,
9931 bool IsMemset, bool ZeroMemset,
9933 MachineFunction &MF) const {
9934 const Function *F = MF.getFunction();
9936 // See if we can use NEON instructions for this...
9937 if ((!IsMemset || ZeroMemset) &&
9938 Subtarget->hasNEON() &&
9939 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
9940 Attribute::NoImplicitFloat)) {
9943 (memOpAlign(SrcAlign, DstAlign, 16) ||
9944 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) {
9946 } else if (Size >= 8 &&
9947 (memOpAlign(SrcAlign, DstAlign, 8) ||
9948 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) &&
9954 // Lowering to i32/i16 if the size permits.
9960 // Let the target-independent logic figure it out.
9964 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9965 if (Val.getOpcode() != ISD::LOAD)
9968 EVT VT1 = Val.getValueType();
9969 if (!VT1.isSimple() || !VT1.isInteger() ||
9970 !VT2.isSimple() || !VT2.isInteger())
9973 switch (VT1.getSimpleVT().SimpleTy) {
9978 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
9985 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
9986 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9989 if (!isTypeLegal(EVT::getEVT(Ty1)))
9992 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
9994 // Assuming the caller doesn't have a zeroext or signext return parameter,
9995 // truncation all the way down to i1 is valid.
10000 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
10004 unsigned Scale = 1;
10005 switch (VT.getSimpleVT().SimpleTy) {
10006 default: return false;
10021 if ((V & (Scale - 1)) != 0)
10024 return V == (V & ((1LL << 5) - 1));
10027 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
10028 const ARMSubtarget *Subtarget) {
10029 bool isNeg = false;
10035 switch (VT.getSimpleVT().SimpleTy) {
10036 default: return false;
10041 // + imm12 or - imm8
10043 return V == (V & ((1LL << 8) - 1));
10044 return V == (V & ((1LL << 12) - 1));
10047 // Same as ARM mode. FIXME: NEON?
10048 if (!Subtarget->hasVFP2())
10053 return V == (V & ((1LL << 8) - 1));
10057 /// isLegalAddressImmediate - Return true if the integer value can be used
10058 /// as the offset of the target addressing mode for load / store of the
10060 static bool isLegalAddressImmediate(int64_t V, EVT VT,
10061 const ARMSubtarget *Subtarget) {
10065 if (!VT.isSimple())
10068 if (Subtarget->isThumb1Only())
10069 return isLegalT1AddressImmediate(V, VT);
10070 else if (Subtarget->isThumb2())
10071 return isLegalT2AddressImmediate(V, VT, Subtarget);
10076 switch (VT.getSimpleVT().SimpleTy) {
10077 default: return false;
10082 return V == (V & ((1LL << 12) - 1));
10085 return V == (V & ((1LL << 8) - 1));
10088 if (!Subtarget->hasVFP2()) // FIXME: NEON?
10093 return V == (V & ((1LL << 8) - 1));
10097 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
10099 int Scale = AM.Scale;
10103 switch (VT.getSimpleVT().SimpleTy) {
10104 default: return false;
10112 Scale = Scale & ~1;
10113 return Scale == 2 || Scale == 4 || Scale == 8;
10116 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10120 // Note, we allow "void" uses (basically, uses that aren't loads or
10121 // stores), because arm allows folding a scale into many arithmetic
10122 // operations. This should be made more precise and revisited later.
10124 // Allow r << imm, but the imm has to be a multiple of two.
10125 if (Scale & 1) return false;
10126 return isPowerOf2_32(Scale);
10130 /// isLegalAddressingMode - Return true if the addressing mode represented
10131 /// by AM is legal for this target, for a load/store of the specified type.
10132 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10134 EVT VT = getValueType(Ty, true);
10135 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10138 // Can never fold addr of global into load/store.
10142 switch (AM.Scale) {
10143 case 0: // no scale reg, must be "r+i" or "r", or "i".
10146 if (Subtarget->isThumb1Only())
10150 // ARM doesn't support any R+R*scale+imm addr modes.
10154 if (!VT.isSimple())
10157 if (Subtarget->isThumb2())
10158 return isLegalT2ScaledAddressingMode(AM, VT);
10160 int Scale = AM.Scale;
10161 switch (VT.getSimpleVT().SimpleTy) {
10162 default: return false;
10166 if (Scale < 0) Scale = -Scale;
10170 return isPowerOf2_32(Scale & ~1);
10174 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10179 // Note, we allow "void" uses (basically, uses that aren't loads or
10180 // stores), because arm allows folding a scale into many arithmetic
10181 // operations. This should be made more precise and revisited later.
10183 // Allow r << imm, but the imm has to be a multiple of two.
10184 if (Scale & 1) return false;
10185 return isPowerOf2_32(Scale);
10191 /// isLegalICmpImmediate - Return true if the specified immediate is legal
10192 /// icmp immediate, that is the target has icmp instructions which can compare
10193 /// a register against the immediate without having to materialize the
10194 /// immediate into a register.
10195 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
10196 // Thumb2 and ARM modes can use cmn for negative immediates.
10197 if (!Subtarget->isThumb())
10198 return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
10199 if (Subtarget->isThumb2())
10200 return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
10201 // Thumb1 doesn't have cmn, and only 8-bit immediates.
10202 return Imm >= 0 && Imm <= 255;
10205 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
10206 /// *or sub* immediate, that is the target has add or sub instructions which can
10207 /// add a register with the immediate without having to materialize the
10208 /// immediate into a register.
10209 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10210 // Same encoding for add/sub, just flip the sign.
10211 int64_t AbsImm = llvm::abs64(Imm);
10212 if (!Subtarget->isThumb())
10213 return ARM_AM::getSOImmVal(AbsImm) != -1;
10214 if (Subtarget->isThumb2())
10215 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10216 // Thumb1 only has 8-bit unsigned immediate.
10217 return AbsImm >= 0 && AbsImm <= 255;
10220 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
10221 bool isSEXTLoad, SDValue &Base,
10222 SDValue &Offset, bool &isInc,
10223 SelectionDAG &DAG) {
10224 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10227 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
10228 // AddressingMode 3
10229 Base = Ptr->getOperand(0);
10230 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10231 int RHSC = (int)RHS->getZExtValue();
10232 if (RHSC < 0 && RHSC > -256) {
10233 assert(Ptr->getOpcode() == ISD::ADD);
10235 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10239 isInc = (Ptr->getOpcode() == ISD::ADD);
10240 Offset = Ptr->getOperand(1);
10242 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
10243 // AddressingMode 2
10244 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10245 int RHSC = (int)RHS->getZExtValue();
10246 if (RHSC < 0 && RHSC > -0x1000) {
10247 assert(Ptr->getOpcode() == ISD::ADD);
10249 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10250 Base = Ptr->getOperand(0);
10255 if (Ptr->getOpcode() == ISD::ADD) {
10257 ARM_AM::ShiftOpc ShOpcVal=
10258 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
10259 if (ShOpcVal != ARM_AM::no_shift) {
10260 Base = Ptr->getOperand(1);
10261 Offset = Ptr->getOperand(0);
10263 Base = Ptr->getOperand(0);
10264 Offset = Ptr->getOperand(1);
10269 isInc = (Ptr->getOpcode() == ISD::ADD);
10270 Base = Ptr->getOperand(0);
10271 Offset = Ptr->getOperand(1);
10275 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
10279 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
10280 bool isSEXTLoad, SDValue &Base,
10281 SDValue &Offset, bool &isInc,
10282 SelectionDAG &DAG) {
10283 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10286 Base = Ptr->getOperand(0);
10287 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10288 int RHSC = (int)RHS->getZExtValue();
10289 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
10290 assert(Ptr->getOpcode() == ISD::ADD);
10292 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10294 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
10295 isInc = Ptr->getOpcode() == ISD::ADD;
10296 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
10304 /// getPreIndexedAddressParts - returns true by value, base pointer and
10305 /// offset pointer and addressing mode by reference if the node's address
10306 /// can be legally represented as pre-indexed load / store address.
10308 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10310 ISD::MemIndexedMode &AM,
10311 SelectionDAG &DAG) const {
10312 if (Subtarget->isThumb1Only())
10317 bool isSEXTLoad = false;
10318 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10319 Ptr = LD->getBasePtr();
10320 VT = LD->getMemoryVT();
10321 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10322 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10323 Ptr = ST->getBasePtr();
10324 VT = ST->getMemoryVT();
10329 bool isLegal = false;
10330 if (Subtarget->isThumb2())
10331 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10332 Offset, isInc, DAG);
10334 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10335 Offset, isInc, DAG);
10339 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10343 /// getPostIndexedAddressParts - returns true by value, base pointer and
10344 /// offset pointer and addressing mode by reference if this node can be
10345 /// combined with a load / store to form a post-indexed load / store.
10346 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
10349 ISD::MemIndexedMode &AM,
10350 SelectionDAG &DAG) const {
10351 if (Subtarget->isThumb1Only())
10356 bool isSEXTLoad = false;
10357 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10358 VT = LD->getMemoryVT();
10359 Ptr = LD->getBasePtr();
10360 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10361 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10362 VT = ST->getMemoryVT();
10363 Ptr = ST->getBasePtr();
10368 bool isLegal = false;
10369 if (Subtarget->isThumb2())
10370 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10373 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10379 // Swap base ptr and offset to catch more post-index load / store when
10380 // it's legal. In Thumb2 mode, offset must be an immediate.
10381 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10382 !Subtarget->isThumb2())
10383 std::swap(Base, Offset);
10385 // Post-indexed load / store update the base pointer.
10390 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10394 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10397 const SelectionDAG &DAG,
10398 unsigned Depth) const {
10399 unsigned BitWidth = KnownOne.getBitWidth();
10400 KnownZero = KnownOne = APInt(BitWidth, 0);
10401 switch (Op.getOpcode()) {
10407 // These nodes' second result is a boolean
10408 if (Op.getResNo() == 0)
10410 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10412 case ARMISD::CMOV: {
10413 // Bits are known zero/one if known on the LHS and RHS.
10414 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
10415 if (KnownZero == 0 && KnownOne == 0) return;
10417 APInt KnownZeroRHS, KnownOneRHS;
10418 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
10419 KnownZero &= KnownZeroRHS;
10420 KnownOne &= KnownOneRHS;
10423 case ISD::INTRINSIC_W_CHAIN: {
10424 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
10425 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
10428 case Intrinsic::arm_ldaex:
10429 case Intrinsic::arm_ldrex: {
10430 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
10431 unsigned MemBits = VT.getScalarType().getSizeInBits();
10432 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
10440 //===----------------------------------------------------------------------===//
10441 // ARM Inline Assembly Support
10442 //===----------------------------------------------------------------------===//
10444 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10445 // Looking for "rev" which is V6+.
10446 if (!Subtarget->hasV6Ops())
10449 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10450 std::string AsmStr = IA->getAsmString();
10451 SmallVector<StringRef, 4> AsmPieces;
10452 SplitString(AsmStr, AsmPieces, ";\n");
10454 switch (AsmPieces.size()) {
10455 default: return false;
10457 AsmStr = AsmPieces[0];
10459 SplitString(AsmStr, AsmPieces, " \t,");
10462 if (AsmPieces.size() == 3 &&
10463 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10464 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10465 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10466 if (Ty && Ty->getBitWidth() == 32)
10467 return IntrinsicLowering::LowerToByteSwap(CI);
10475 /// getConstraintType - Given a constraint letter, return the type of
10476 /// constraint it is for this target.
10477 ARMTargetLowering::ConstraintType
10478 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
10479 if (Constraint.size() == 1) {
10480 switch (Constraint[0]) {
10482 case 'l': return C_RegisterClass;
10483 case 'w': return C_RegisterClass;
10484 case 'h': return C_RegisterClass;
10485 case 'x': return C_RegisterClass;
10486 case 't': return C_RegisterClass;
10487 case 'j': return C_Other; // Constant for movw.
10488 // An address with a single base register. Due to the way we
10489 // currently handle addresses it is the same as an 'r' memory constraint.
10490 case 'Q': return C_Memory;
10492 } else if (Constraint.size() == 2) {
10493 switch (Constraint[0]) {
10495 // All 'U+' constraints are addresses.
10496 case 'U': return C_Memory;
10499 return TargetLowering::getConstraintType(Constraint);
10502 /// Examine constraint type and operand type and determine a weight value.
10503 /// This object must already have been set up with the operand type
10504 /// and the current alternative constraint selected.
10505 TargetLowering::ConstraintWeight
10506 ARMTargetLowering::getSingleConstraintMatchWeight(
10507 AsmOperandInfo &info, const char *constraint) const {
10508 ConstraintWeight weight = CW_Invalid;
10509 Value *CallOperandVal = info.CallOperandVal;
10510 // If we don't have a value, we can't do a match,
10511 // but allow it at the lowest weight.
10512 if (!CallOperandVal)
10514 Type *type = CallOperandVal->getType();
10515 // Look at the constraint type.
10516 switch (*constraint) {
10518 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10521 if (type->isIntegerTy()) {
10522 if (Subtarget->isThumb())
10523 weight = CW_SpecificReg;
10525 weight = CW_Register;
10529 if (type->isFloatingPointTy())
10530 weight = CW_Register;
10536 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10538 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10540 if (Constraint.size() == 1) {
10541 // GCC ARM Constraint Letters
10542 switch (Constraint[0]) {
10543 case 'l': // Low regs or general regs.
10544 if (Subtarget->isThumb())
10545 return RCPair(0U, &ARM::tGPRRegClass);
10546 return RCPair(0U, &ARM::GPRRegClass);
10547 case 'h': // High regs or no regs.
10548 if (Subtarget->isThumb())
10549 return RCPair(0U, &ARM::hGPRRegClass);
10552 if (Subtarget->isThumb1Only())
10553 return RCPair(0U, &ARM::tGPRRegClass);
10554 return RCPair(0U, &ARM::GPRRegClass);
10556 if (VT == MVT::Other)
10558 if (VT == MVT::f32)
10559 return RCPair(0U, &ARM::SPRRegClass);
10560 if (VT.getSizeInBits() == 64)
10561 return RCPair(0U, &ARM::DPRRegClass);
10562 if (VT.getSizeInBits() == 128)
10563 return RCPair(0U, &ARM::QPRRegClass);
10566 if (VT == MVT::Other)
10568 if (VT == MVT::f32)
10569 return RCPair(0U, &ARM::SPR_8RegClass);
10570 if (VT.getSizeInBits() == 64)
10571 return RCPair(0U, &ARM::DPR_8RegClass);
10572 if (VT.getSizeInBits() == 128)
10573 return RCPair(0U, &ARM::QPR_8RegClass);
10576 if (VT == MVT::f32)
10577 return RCPair(0U, &ARM::SPRRegClass);
10581 if (StringRef("{cc}").equals_lower(Constraint))
10582 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10584 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10587 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10588 /// vector. If it is invalid, don't add anything to Ops.
10589 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10590 std::string &Constraint,
10591 std::vector<SDValue>&Ops,
10592 SelectionDAG &DAG) const {
10595 // Currently only support length 1 constraints.
10596 if (Constraint.length() != 1) return;
10598 char ConstraintLetter = Constraint[0];
10599 switch (ConstraintLetter) {
10602 case 'I': case 'J': case 'K': case 'L':
10603 case 'M': case 'N': case 'O':
10604 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10608 int64_t CVal64 = C->getSExtValue();
10609 int CVal = (int) CVal64;
10610 // None of these constraints allow values larger than 32 bits. Check
10611 // that the value fits in an int.
10612 if (CVal != CVal64)
10615 switch (ConstraintLetter) {
10617 // Constant suitable for movw, must be between 0 and
10619 if (Subtarget->hasV6T2Ops())
10620 if (CVal >= 0 && CVal <= 65535)
10624 if (Subtarget->isThumb1Only()) {
10625 // This must be a constant between 0 and 255, for ADD
10627 if (CVal >= 0 && CVal <= 255)
10629 } else if (Subtarget->isThumb2()) {
10630 // A constant that can be used as an immediate value in a
10631 // data-processing instruction.
10632 if (ARM_AM::getT2SOImmVal(CVal) != -1)
10635 // A constant that can be used as an immediate value in a
10636 // data-processing instruction.
10637 if (ARM_AM::getSOImmVal(CVal) != -1)
10643 if (Subtarget->isThumb()) { // FIXME thumb2
10644 // This must be a constant between -255 and -1, for negated ADD
10645 // immediates. This can be used in GCC with an "n" modifier that
10646 // prints the negated value, for use with SUB instructions. It is
10647 // not useful otherwise but is implemented for compatibility.
10648 if (CVal >= -255 && CVal <= -1)
10651 // This must be a constant between -4095 and 4095. It is not clear
10652 // what this constraint is intended for. Implemented for
10653 // compatibility with GCC.
10654 if (CVal >= -4095 && CVal <= 4095)
10660 if (Subtarget->isThumb1Only()) {
10661 // A 32-bit value where only one byte has a nonzero value. Exclude
10662 // zero to match GCC. This constraint is used by GCC internally for
10663 // constants that can be loaded with a move/shift combination.
10664 // It is not useful otherwise but is implemented for compatibility.
10665 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10667 } else if (Subtarget->isThumb2()) {
10668 // A constant whose bitwise inverse can be used as an immediate
10669 // value in a data-processing instruction. This can be used in GCC
10670 // with a "B" modifier that prints the inverted value, for use with
10671 // BIC and MVN instructions. It is not useful otherwise but is
10672 // implemented for compatibility.
10673 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10676 // A constant whose bitwise inverse can be used as an immediate
10677 // value in a data-processing instruction. This can be used in GCC
10678 // with a "B" modifier that prints the inverted value, for use with
10679 // BIC and MVN instructions. It is not useful otherwise but is
10680 // implemented for compatibility.
10681 if (ARM_AM::getSOImmVal(~CVal) != -1)
10687 if (Subtarget->isThumb1Only()) {
10688 // This must be a constant between -7 and 7,
10689 // for 3-operand ADD/SUB immediate instructions.
10690 if (CVal >= -7 && CVal < 7)
10692 } else if (Subtarget->isThumb2()) {
10693 // A constant whose negation can be used as an immediate value in a
10694 // data-processing instruction. This can be used in GCC with an "n"
10695 // modifier that prints the negated value, for use with SUB
10696 // instructions. It is not useful otherwise but is implemented for
10698 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10701 // A constant whose negation can be used as an immediate value in a
10702 // data-processing instruction. This can be used in GCC with an "n"
10703 // modifier that prints the negated value, for use with SUB
10704 // instructions. It is not useful otherwise but is implemented for
10706 if (ARM_AM::getSOImmVal(-CVal) != -1)
10712 if (Subtarget->isThumb()) { // FIXME thumb2
10713 // This must be a multiple of 4 between 0 and 1020, for
10714 // ADD sp + immediate.
10715 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10718 // A power of two or a constant between 0 and 32. This is used in
10719 // GCC for the shift amount on shifted register operands, but it is
10720 // useful in general for any shift amounts.
10721 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10727 if (Subtarget->isThumb()) { // FIXME thumb2
10728 // This must be a constant between 0 and 31, for shift amounts.
10729 if (CVal >= 0 && CVal <= 31)
10735 if (Subtarget->isThumb()) { // FIXME thumb2
10736 // This must be a multiple of 4 between -508 and 508, for
10737 // ADD/SUB sp = sp + immediate.
10738 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
10743 Result = DAG.getTargetConstant(CVal, Op.getValueType());
10747 if (Result.getNode()) {
10748 Ops.push_back(Result);
10751 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10754 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
10755 assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
10756 unsigned Opcode = Op->getOpcode();
10757 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
10758 "Invalid opcode for Div/Rem lowering");
10759 bool isSigned = (Opcode == ISD::SDIVREM);
10760 EVT VT = Op->getValueType(0);
10761 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
10764 switch (VT.getSimpleVT().SimpleTy) {
10765 default: llvm_unreachable("Unexpected request for libcall!");
10766 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
10767 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
10768 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
10769 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
10772 SDValue InChain = DAG.getEntryNode();
10774 TargetLowering::ArgListTy Args;
10775 TargetLowering::ArgListEntry Entry;
10776 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
10777 EVT ArgVT = Op->getOperand(i).getValueType();
10778 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10779 Entry.Node = Op->getOperand(i);
10781 Entry.isSExt = isSigned;
10782 Entry.isZExt = !isSigned;
10783 Args.push_back(Entry);
10786 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
10789 Type *RetTy = (Type*)StructType::get(Ty, Ty, NULL);
10792 TargetLowering::CallLoweringInfo CLI(DAG);
10793 CLI.setDebugLoc(dl).setChain(InChain)
10794 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
10795 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
10797 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
10798 return CallInfo.first;
10802 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
10803 assert(Subtarget->isTargetWindows() && "unsupported target platform");
10807 SDValue Chain = Op.getOperand(0);
10808 SDValue Size = Op.getOperand(1);
10810 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
10811 DAG.getConstant(2, MVT::i32));
10814 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
10815 Flag = Chain.getValue(1);
10817 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10818 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
10820 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
10821 Chain = NewSP.getValue(1);
10823 SDValue Ops[2] = { NewSP, Chain };
10824 return DAG.getMergeValues(Ops, DL);
10827 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
10828 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&
10829 "Unexpected type for custom-lowering FP_EXTEND");
10832 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
10834 SDValue SrcVal = Op.getOperand(0);
10835 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10836 /*isSigned*/ false, SDLoc(Op)).first;
10839 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
10840 assert(Op.getOperand(0).getValueType() == MVT::f64 &&
10841 Subtarget->isFPOnlySP() &&
10842 "Unexpected type for custom-lowering FP_ROUND");
10845 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
10847 SDValue SrcVal = Op.getOperand(0);
10848 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10849 /*isSigned*/ false, SDLoc(Op)).first;
10853 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10854 // The ARM target isn't yet aware of offsets.
10858 bool ARM::isBitFieldInvertedMask(unsigned v) {
10859 if (v == 0xffffffff)
10862 // there can be 1's on either or both "outsides", all the "inside"
10863 // bits must be 0's
10864 unsigned TO = CountTrailingOnes_32(v);
10865 unsigned LO = CountLeadingOnes_32(v);
10866 v = (v >> TO) << TO;
10867 v = (v << LO) >> LO;
10871 /// isFPImmLegal - Returns true if the target can instruction select the
10872 /// specified FP immediate natively. If false, the legalizer will
10873 /// materialize the FP immediate as a load from a constant pool.
10874 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
10875 if (!Subtarget->hasVFP3())
10877 if (VT == MVT::f32)
10878 return ARM_AM::getFP32Imm(Imm) != -1;
10879 if (VT == MVT::f64 && !Subtarget->isFPOnlySP())
10880 return ARM_AM::getFP64Imm(Imm) != -1;
10884 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
10885 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
10886 /// specified in the intrinsic calls.
10887 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
10889 unsigned Intrinsic) const {
10890 switch (Intrinsic) {
10891 case Intrinsic::arm_neon_vld1:
10892 case Intrinsic::arm_neon_vld2:
10893 case Intrinsic::arm_neon_vld3:
10894 case Intrinsic::arm_neon_vld4:
10895 case Intrinsic::arm_neon_vld2lane:
10896 case Intrinsic::arm_neon_vld3lane:
10897 case Intrinsic::arm_neon_vld4lane: {
10898 Info.opc = ISD::INTRINSIC_W_CHAIN;
10899 // Conservatively set memVT to the entire set of vectors loaded.
10900 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
10901 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10902 Info.ptrVal = I.getArgOperand(0);
10904 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10905 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10906 Info.vol = false; // volatile loads with NEON intrinsics not supported
10907 Info.readMem = true;
10908 Info.writeMem = false;
10911 case Intrinsic::arm_neon_vst1:
10912 case Intrinsic::arm_neon_vst2:
10913 case Intrinsic::arm_neon_vst3:
10914 case Intrinsic::arm_neon_vst4:
10915 case Intrinsic::arm_neon_vst2lane:
10916 case Intrinsic::arm_neon_vst3lane:
10917 case Intrinsic::arm_neon_vst4lane: {
10918 Info.opc = ISD::INTRINSIC_VOID;
10919 // Conservatively set memVT to the entire set of vectors stored.
10920 unsigned NumElts = 0;
10921 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
10922 Type *ArgTy = I.getArgOperand(ArgI)->getType();
10923 if (!ArgTy->isVectorTy())
10925 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
10927 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10928 Info.ptrVal = I.getArgOperand(0);
10930 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10931 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10932 Info.vol = false; // volatile stores with NEON intrinsics not supported
10933 Info.readMem = false;
10934 Info.writeMem = true;
10937 case Intrinsic::arm_ldaex:
10938 case Intrinsic::arm_ldrex: {
10939 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
10940 Info.opc = ISD::INTRINSIC_W_CHAIN;
10941 Info.memVT = MVT::getVT(PtrTy->getElementType());
10942 Info.ptrVal = I.getArgOperand(0);
10944 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10946 Info.readMem = true;
10947 Info.writeMem = false;
10950 case Intrinsic::arm_stlex:
10951 case Intrinsic::arm_strex: {
10952 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
10953 Info.opc = ISD::INTRINSIC_W_CHAIN;
10954 Info.memVT = MVT::getVT(PtrTy->getElementType());
10955 Info.ptrVal = I.getArgOperand(1);
10957 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10959 Info.readMem = false;
10960 Info.writeMem = true;
10963 case Intrinsic::arm_stlexd:
10964 case Intrinsic::arm_strexd: {
10965 Info.opc = ISD::INTRINSIC_W_CHAIN;
10966 Info.memVT = MVT::i64;
10967 Info.ptrVal = I.getArgOperand(2);
10971 Info.readMem = false;
10972 Info.writeMem = true;
10975 case Intrinsic::arm_ldaexd:
10976 case Intrinsic::arm_ldrexd: {
10977 Info.opc = ISD::INTRINSIC_W_CHAIN;
10978 Info.memVT = MVT::i64;
10979 Info.ptrVal = I.getArgOperand(0);
10983 Info.readMem = true;
10984 Info.writeMem = false;
10994 /// \brief Returns true if it is beneficial to convert a load of a constant
10995 /// to just the constant itself.
10996 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
10998 assert(Ty->isIntegerTy());
11000 unsigned Bits = Ty->getPrimitiveSizeInBits();
11001 if (Bits == 0 || Bits > 32)
11006 bool ARMTargetLowering::hasLoadLinkedStoreConditional() const { return true; }
11008 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
11009 ARM_MB::MemBOpt Domain) const {
11010 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11012 // First, if the target has no DMB, see what fallback we can use.
11013 if (!Subtarget->hasDataBarrier()) {
11014 // Some ARMv6 cpus can support data barriers with an mcr instruction.
11015 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
11017 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
11018 Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
11019 Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0),
11020 Builder.getInt32(0), Builder.getInt32(7),
11021 Builder.getInt32(10), Builder.getInt32(5)};
11022 return Builder.CreateCall(MCR, args);
11024 // Instead of using barriers, atomic accesses on these subtargets use
11026 llvm_unreachable("makeDMB on a target so old that it has no barriers");
11029 Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
11030 // Only a full system barrier exists in the M-class architectures.
11031 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
11032 Constant *CDomain = Builder.getInt32(Domain);
11033 return Builder.CreateCall(DMB, CDomain);
11037 // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
11038 Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
11039 AtomicOrdering Ord, bool IsStore,
11040 bool IsLoad) const {
11041 if (!getInsertFencesForAtomic())
11047 llvm_unreachable("Invalid fence: unordered/non-atomic");
11050 return nullptr; // Nothing to do
11051 case SequentiallyConsistent:
11053 return nullptr; // Nothing to do
11056 case AcquireRelease:
11057 if (Subtarget->isSwift())
11058 return makeDMB(Builder, ARM_MB::ISHST);
11059 // FIXME: add a comment with a link to documentation justifying this.
11061 return makeDMB(Builder, ARM_MB::ISH);
11063 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
11066 Instruction* ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
11067 AtomicOrdering Ord, bool IsStore,
11068 bool IsLoad) const {
11069 if (!getInsertFencesForAtomic())
11075 llvm_unreachable("Invalid fence: unordered/not-atomic");
11078 return nullptr; // Nothing to do
11080 case AcquireRelease:
11081 case SequentiallyConsistent:
11082 return makeDMB(Builder, ARM_MB::ISH);
11084 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
11087 // Loads and stores less than 64-bits are already atomic; ones above that
11088 // are doomed anyway, so defer to the default libcall and blame the OS when
11089 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11090 // anything for those.
11091 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
11092 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
11093 return (Size == 64) && !Subtarget->isMClass();
11096 // Loads and stores less than 64-bits are already atomic; ones above that
11097 // are doomed anyway, so defer to the default libcall and blame the OS when
11098 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11099 // anything for those.
11100 // FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
11101 // guarantee, see DDI0406C ARM architecture reference manual,
11102 // sections A8.8.72-74 LDRD)
11103 bool ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
11104 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
11105 return (Size == 64) && !Subtarget->isMClass();
11108 // For the real atomic operations, we have ldrex/strex up to 32 bits,
11109 // and up to 64 bits on the non-M profiles
11110 bool ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
11111 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
11112 return Size <= (Subtarget->isMClass() ? 32U : 64U);
11115 // This has so far only been implemented for MachO.
11116 bool ARMTargetLowering::useLoadStackGuardNode() const {
11117 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO;
11120 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
11121 unsigned &Cost) const {
11122 // If we do not have NEON, vector types are not natively supported.
11123 if (!Subtarget->hasNEON())
11126 // Floating point values and vector values map to the same register file.
11127 // Therefore, althought we could do a store extract of a vector type, this is
11128 // better to leave at float as we have more freedom in the addressing mode for
11130 if (VectorTy->isFPOrFPVectorTy())
11133 // If the index is unknown at compile time, this is very expensive to lower
11134 // and it is not possible to combine the store with the extract.
11135 if (!isa<ConstantInt>(Idx))
11138 assert(VectorTy->isVectorTy() && "VectorTy is not a vector type");
11139 unsigned BitWidth = cast<VectorType>(VectorTy)->getBitWidth();
11140 // We can do a store + vector extract on any vector that fits perfectly in a D
11142 if (BitWidth == 64 || BitWidth == 128) {
11149 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
11150 AtomicOrdering Ord) const {
11151 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11152 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
11153 bool IsAcquire = isAtLeastAcquire(Ord);
11155 // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
11156 // intrinsic must return {i32, i32} and we have to recombine them into a
11157 // single i64 here.
11158 if (ValTy->getPrimitiveSizeInBits() == 64) {
11159 Intrinsic::ID Int =
11160 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
11161 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
11163 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11164 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
11166 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
11167 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
11168 if (!Subtarget->isLittle())
11169 std::swap (Lo, Hi);
11170 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
11171 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
11172 return Builder.CreateOr(
11173 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
11176 Type *Tys[] = { Addr->getType() };
11177 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
11178 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
11180 return Builder.CreateTruncOrBitCast(
11181 Builder.CreateCall(Ldrex, Addr),
11182 cast<PointerType>(Addr->getType())->getElementType());
11185 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
11187 AtomicOrdering Ord) const {
11188 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11189 bool IsRelease = isAtLeastRelease(Ord);
11191 // Since the intrinsics must have legal type, the i64 intrinsics take two
11192 // parameters: "i32, i32". We must marshal Val into the appropriate form
11193 // before the call.
11194 if (Val->getType()->getPrimitiveSizeInBits() == 64) {
11195 Intrinsic::ID Int =
11196 IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
11197 Function *Strex = Intrinsic::getDeclaration(M, Int);
11198 Type *Int32Ty = Type::getInt32Ty(M->getContext());
11200 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
11201 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
11202 if (!Subtarget->isLittle())
11203 std::swap (Lo, Hi);
11204 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11205 return Builder.CreateCall3(Strex, Lo, Hi, Addr);
11208 Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
11209 Type *Tys[] = { Addr->getType() };
11210 Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
11212 return Builder.CreateCall2(
11213 Strex, Builder.CreateZExtOrBitCast(
11214 Val, Strex->getFunctionType()->getParamType(0)),
11226 static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
11227 uint64_t &Members) {
11228 if (const StructType *ST = dyn_cast<StructType>(Ty)) {
11229 for (unsigned i = 0; i < ST->getNumElements(); ++i) {
11230 uint64_t SubMembers = 0;
11231 if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers))
11233 Members += SubMembers;
11235 } else if (const ArrayType *AT = dyn_cast<ArrayType>(Ty)) {
11236 uint64_t SubMembers = 0;
11237 if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers))
11239 Members += SubMembers * AT->getNumElements();
11240 } else if (Ty->isFloatTy()) {
11241 if (Base != HA_UNKNOWN && Base != HA_FLOAT)
11245 } else if (Ty->isDoubleTy()) {
11246 if (Base != HA_UNKNOWN && Base != HA_DOUBLE)
11250 } else if (const VectorType *VT = dyn_cast<VectorType>(Ty)) {
11257 return VT->getBitWidth() == 64;
11259 return VT->getBitWidth() == 128;
11261 switch (VT->getBitWidth()) {
11274 return (Members > 0 && Members <= 4);
11277 /// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate.
11278 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
11279 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
11280 if (getEffectiveCallingConv(CallConv, isVarArg) !=
11281 CallingConv::ARM_AAPCS_VFP)
11284 HABaseType Base = HA_UNKNOWN;
11285 uint64_t Members = 0;
11286 bool result = isHomogeneousAggregate(Ty, Base, Members);
11287 DEBUG(dbgs() << "isHA: " << result << " "; Ty->dump());