1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
75 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
76 EVT PromotedBitwiseVT) {
77 if (VT != PromotedLdStVT) {
78 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
79 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
80 PromotedLdStVT.getSimpleVT());
82 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
83 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
84 PromotedLdStVT.getSimpleVT());
87 EVT ElemTy = VT.getVectorElementType();
88 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
89 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
90 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
91 if (ElemTy != MVT::i32) {
92 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
93 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
95 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
97 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
98 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
99 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
100 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
101 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
103 if (VT.isInteger()) {
104 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
105 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
106 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
107 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
108 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
109 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
110 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
111 setTruncStoreAction(VT.getSimpleVT(),
112 (MVT::SimpleValueType)InnerVT, Expand);
114 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
116 // Promote all bit-wise operations.
117 if (VT.isInteger() && VT != PromotedBitwiseVT) {
118 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
121 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
122 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
123 PromotedBitwiseVT.getSimpleVT());
124 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
125 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
126 PromotedBitwiseVT.getSimpleVT());
129 // Neon does not support vector divide/remainder operations.
130 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
133 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
134 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
135 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
138 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
139 addRegisterClass(VT, ARM::DPRRegisterClass);
140 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
143 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
144 addRegisterClass(VT, ARM::QPRRegisterClass);
145 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
148 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
149 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
150 return new TargetLoweringObjectFileMachO();
152 return new ARMElfTargetObjectFile();
155 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
156 : TargetLowering(TM, createTLOF(TM)) {
157 Subtarget = &TM.getSubtarget<ARMSubtarget>();
158 RegInfo = TM.getRegisterInfo();
159 Itins = TM.getInstrItineraryData();
161 if (Subtarget->isTargetDarwin()) {
162 // Uses VFP for Thumb libfuncs if available.
163 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
164 // Single-precision floating-point arithmetic.
165 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
166 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
167 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
168 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
170 // Double-precision floating-point arithmetic.
171 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
172 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
173 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
174 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
176 // Single-precision comparisons.
177 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
178 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
179 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
180 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
181 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
182 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
183 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
184 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
186 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
193 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
195 // Double-precision comparisons.
196 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
197 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
198 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
199 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
200 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
201 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
202 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
203 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
205 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
214 // Floating-point to integer conversions.
215 // i64 conversions are done via library routines even when generating VFP
216 // instructions, so use the same ones.
217 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
218 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
219 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
220 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
222 // Conversions between floating types.
223 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
224 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
226 // Integer to floating-point conversions.
227 // i64 conversions are done via library routines even when generating VFP
228 // instructions, so use the same ones.
229 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
230 // e.g., __floatunsidf vs. __floatunssidfvfp.
231 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
232 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
233 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
234 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
238 // These libcalls are not available in 32-bit.
239 setLibcallName(RTLIB::SHL_I128, 0);
240 setLibcallName(RTLIB::SRL_I128, 0);
241 setLibcallName(RTLIB::SRA_I128, 0);
243 if (Subtarget->isAAPCS_ABI()) {
244 // Double-precision floating-point arithmetic helper functions
245 // RTABI chapter 4.1.2, Table 2
246 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
247 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
248 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
249 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
250 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
251 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
252 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
253 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
255 // Double-precision floating-point comparison helper functions
256 // RTABI chapter 4.1.2, Table 3
257 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
258 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
259 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
260 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
261 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
262 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
263 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
264 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
265 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
266 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
267 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
268 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
269 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
270 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
271 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
272 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
273 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
278 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
279 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
280 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
282 // Single-precision floating-point arithmetic helper functions
283 // RTABI chapter 4.1.2, Table 4
284 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
285 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
286 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
287 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
288 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
289 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
290 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
291 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
293 // Single-precision floating-point comparison helper functions
294 // RTABI chapter 4.1.2, Table 5
295 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
296 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
297 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
298 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
299 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
300 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
301 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
302 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
303 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
304 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
305 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
306 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
307 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
308 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
309 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
310 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
311 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
316 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
317 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
318 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
320 // Floating-point to integer conversions.
321 // RTABI chapter 4.1.2, Table 6
322 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
323 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
324 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
325 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
326 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
327 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
328 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
329 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
330 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
339 // Conversions between floating types.
340 // RTABI chapter 4.1.2, Table 7
341 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
342 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
343 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
344 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
346 // Integer to floating-point conversions.
347 // RTABI chapter 4.1.2, Table 8
348 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
349 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
350 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
351 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
352 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
353 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
354 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
355 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
356 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
361 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
362 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
363 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
365 // Long long helper functions
366 // RTABI chapter 4.2, Table 9
367 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
368 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
369 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
370 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
371 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
372 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
373 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
376 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
380 // Integer division functions
381 // RTABI chapter 4.3.1
382 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
383 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
384 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
385 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
386 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
387 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
388 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
391 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
393 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
396 if (Subtarget->isThumb1Only())
397 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
399 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
400 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
401 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
402 if (!Subtarget->isFPOnlySP())
403 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
405 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
408 if (Subtarget->hasNEON()) {
409 addDRTypeForNEON(MVT::v2f32);
410 addDRTypeForNEON(MVT::v8i8);
411 addDRTypeForNEON(MVT::v4i16);
412 addDRTypeForNEON(MVT::v2i32);
413 addDRTypeForNEON(MVT::v1i64);
415 addQRTypeForNEON(MVT::v4f32);
416 addQRTypeForNEON(MVT::v2f64);
417 addQRTypeForNEON(MVT::v16i8);
418 addQRTypeForNEON(MVT::v8i16);
419 addQRTypeForNEON(MVT::v4i32);
420 addQRTypeForNEON(MVT::v2i64);
422 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
423 // neither Neon nor VFP support any arithmetic operations on it.
424 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
425 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
426 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
427 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
428 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
429 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
430 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
431 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
432 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
433 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
434 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
435 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
436 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
437 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
438 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
439 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
440 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
441 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
442 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
443 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
444 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
445 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
446 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
447 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
449 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
451 // Neon does not support some operations on v1i64 and v2i64 types.
452 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
453 // Custom handling for some quad-vector types to detect VMULL.
454 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
455 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
456 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
457 // Custom handling for some vector types to avoid expensive expansions
458 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
459 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
460 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
461 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
462 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
463 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
464 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
465 // a destination type that is wider than the source.
466 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
467 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
469 setTargetDAGCombine(ISD::INTRINSIC_VOID);
470 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
471 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
472 setTargetDAGCombine(ISD::SHL);
473 setTargetDAGCombine(ISD::SRL);
474 setTargetDAGCombine(ISD::SRA);
475 setTargetDAGCombine(ISD::SIGN_EXTEND);
476 setTargetDAGCombine(ISD::ZERO_EXTEND);
477 setTargetDAGCombine(ISD::ANY_EXTEND);
478 setTargetDAGCombine(ISD::SELECT_CC);
479 setTargetDAGCombine(ISD::BUILD_VECTOR);
480 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
481 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
482 setTargetDAGCombine(ISD::STORE);
485 computeRegisterProperties();
487 // ARM does not have f32 extending load.
488 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
490 // ARM does not have i1 sign extending load.
491 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
493 // ARM supports all 4 flavors of integer indexed load / store.
494 if (!Subtarget->isThumb1Only()) {
495 for (unsigned im = (unsigned)ISD::PRE_INC;
496 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
497 setIndexedLoadAction(im, MVT::i1, Legal);
498 setIndexedLoadAction(im, MVT::i8, Legal);
499 setIndexedLoadAction(im, MVT::i16, Legal);
500 setIndexedLoadAction(im, MVT::i32, Legal);
501 setIndexedStoreAction(im, MVT::i1, Legal);
502 setIndexedStoreAction(im, MVT::i8, Legal);
503 setIndexedStoreAction(im, MVT::i16, Legal);
504 setIndexedStoreAction(im, MVT::i32, Legal);
508 // i64 operation support.
509 if (Subtarget->isThumb1Only()) {
510 setOperationAction(ISD::MUL, MVT::i64, Expand);
511 setOperationAction(ISD::MULHU, MVT::i32, Expand);
512 setOperationAction(ISD::MULHS, MVT::i32, Expand);
513 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
514 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
516 setOperationAction(ISD::MUL, MVT::i64, Expand);
517 setOperationAction(ISD::MULHU, MVT::i32, Expand);
518 if (!Subtarget->hasV6Ops())
519 setOperationAction(ISD::MULHS, MVT::i32, Expand);
521 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
522 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
523 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
524 setOperationAction(ISD::SRL, MVT::i64, Custom);
525 setOperationAction(ISD::SRA, MVT::i64, Custom);
527 // ARM does not have ROTL.
528 setOperationAction(ISD::ROTL, MVT::i32, Expand);
529 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
530 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
531 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
532 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
534 // Only ARMv6 has BSWAP.
535 if (!Subtarget->hasV6Ops())
536 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
538 // These are expanded into libcalls.
539 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
540 // v7M has a hardware divider
541 setOperationAction(ISD::SDIV, MVT::i32, Expand);
542 setOperationAction(ISD::UDIV, MVT::i32, Expand);
544 setOperationAction(ISD::SREM, MVT::i32, Expand);
545 setOperationAction(ISD::UREM, MVT::i32, Expand);
546 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
547 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
549 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
550 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
551 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
552 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
553 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
555 setOperationAction(ISD::TRAP, MVT::Other, Legal);
557 // Use the default implementation.
558 setOperationAction(ISD::VASTART, MVT::Other, Custom);
559 setOperationAction(ISD::VAARG, MVT::Other, Expand);
560 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
561 setOperationAction(ISD::VAEND, MVT::Other, Expand);
562 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
563 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
564 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
565 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
566 setExceptionPointerRegister(ARM::R0);
567 setExceptionSelectorRegister(ARM::R1);
569 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
570 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
571 // the default expansion.
572 if (Subtarget->hasDataBarrier() ||
573 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
574 // membarrier needs custom lowering; the rest are legal and handled
576 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
578 // Set them all for expansion, which will force libcalls.
579 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
580 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
581 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
582 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
583 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
585 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
587 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
588 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
589 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
590 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
591 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
592 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
593 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
600 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
601 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
602 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
603 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
604 // Since the libcalls include locking, fold in the fences
605 setShouldFoldAtomicFences(true);
607 // 64-bit versions are always libcalls (for now)
608 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
609 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
610 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
611 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
612 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
613 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
614 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
615 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
617 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
619 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
620 if (!Subtarget->hasV6Ops()) {
621 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
622 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
624 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
626 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
627 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
628 // iff target supports vfp2.
629 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
630 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
633 // We want to custom lower some of our intrinsics.
634 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
635 if (Subtarget->isTargetDarwin()) {
636 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
637 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
638 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
641 setOperationAction(ISD::SETCC, MVT::i32, Expand);
642 setOperationAction(ISD::SETCC, MVT::f32, Expand);
643 setOperationAction(ISD::SETCC, MVT::f64, Expand);
644 setOperationAction(ISD::SELECT, MVT::i32, Custom);
645 setOperationAction(ISD::SELECT, MVT::f32, Custom);
646 setOperationAction(ISD::SELECT, MVT::f64, Custom);
647 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
648 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
649 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
651 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
652 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
653 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
654 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
655 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
657 // We don't support sin/cos/fmod/copysign/pow
658 setOperationAction(ISD::FSIN, MVT::f64, Expand);
659 setOperationAction(ISD::FSIN, MVT::f32, Expand);
660 setOperationAction(ISD::FCOS, MVT::f32, Expand);
661 setOperationAction(ISD::FCOS, MVT::f64, Expand);
662 setOperationAction(ISD::FREM, MVT::f64, Expand);
663 setOperationAction(ISD::FREM, MVT::f32, Expand);
664 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
665 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
666 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
668 setOperationAction(ISD::FPOW, MVT::f64, Expand);
669 setOperationAction(ISD::FPOW, MVT::f32, Expand);
671 // Various VFP goodness
672 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
673 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
674 if (Subtarget->hasVFP2()) {
675 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
676 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
677 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
678 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
680 // Special handling for half-precision FP.
681 if (!Subtarget->hasFP16()) {
682 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
683 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
687 // We have target-specific dag combine patterns for the following nodes:
688 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
689 setTargetDAGCombine(ISD::ADD);
690 setTargetDAGCombine(ISD::SUB);
691 setTargetDAGCombine(ISD::MUL);
693 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
694 setTargetDAGCombine(ISD::OR);
695 if (Subtarget->hasNEON())
696 setTargetDAGCombine(ISD::AND);
698 setStackPointerRegisterToSaveRestore(ARM::SP);
700 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
701 setSchedulingPreference(Sched::RegPressure);
703 setSchedulingPreference(Sched::Hybrid);
705 //// temporary - rewrite interface to use type
706 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
708 // On ARM arguments smaller than 4 bytes are extended, so all arguments
709 // are at least 4 bytes aligned.
710 setMinStackArgumentAlignment(4);
712 benefitFromCodePlacementOpt = true;
715 // FIXME: It might make sense to define the representative register class as the
716 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
717 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
718 // SPR's representative would be DPR_VFP2. This should work well if register
719 // pressure tracking were modified such that a register use would increment the
720 // pressure of the register class's representative and all of it's super
721 // classes' representatives transitively. We have not implemented this because
722 // of the difficulty prior to coalescing of modeling operand register classes
723 // due to the common occurence of cross class copies and subregister insertions
725 std::pair<const TargetRegisterClass*, uint8_t>
726 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
727 const TargetRegisterClass *RRC = 0;
729 switch (VT.getSimpleVT().SimpleTy) {
731 return TargetLowering::findRepresentativeClass(VT);
732 // Use DPR as representative register class for all floating point
733 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
734 // the cost is 1 for both f32 and f64.
735 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
736 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
737 RRC = ARM::DPRRegisterClass;
738 // When NEON is used for SP, only half of the register file is available
739 // because operations that define both SP and DP results will be constrained
740 // to the VFP2 class (D0-D15). We currently model this constraint prior to
741 // coalescing by double-counting the SP regs. See the FIXME above.
742 if (Subtarget->useNEONForSinglePrecisionFP())
745 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
746 case MVT::v4f32: case MVT::v2f64:
747 RRC = ARM::DPRRegisterClass;
751 RRC = ARM::DPRRegisterClass;
755 RRC = ARM::DPRRegisterClass;
759 return std::make_pair(RRC, Cost);
762 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
765 case ARMISD::Wrapper: return "ARMISD::Wrapper";
766 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
767 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
768 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
769 case ARMISD::CALL: return "ARMISD::CALL";
770 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
771 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
772 case ARMISD::tCALL: return "ARMISD::tCALL";
773 case ARMISD::BRCOND: return "ARMISD::BRCOND";
774 case ARMISD::BR_JT: return "ARMISD::BR_JT";
775 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
776 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
777 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
778 case ARMISD::CMP: return "ARMISD::CMP";
779 case ARMISD::CMPZ: return "ARMISD::CMPZ";
780 case ARMISD::CMPFP: return "ARMISD::CMPFP";
781 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
782 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
783 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
784 case ARMISD::CMOV: return "ARMISD::CMOV";
786 case ARMISD::RBIT: return "ARMISD::RBIT";
788 case ARMISD::FTOSI: return "ARMISD::FTOSI";
789 case ARMISD::FTOUI: return "ARMISD::FTOUI";
790 case ARMISD::SITOF: return "ARMISD::SITOF";
791 case ARMISD::UITOF: return "ARMISD::UITOF";
793 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
794 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
795 case ARMISD::RRX: return "ARMISD::RRX";
797 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
798 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
800 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
801 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
802 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
804 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
806 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
808 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
810 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
811 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
813 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
815 case ARMISD::VCEQ: return "ARMISD::VCEQ";
816 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
817 case ARMISD::VCGE: return "ARMISD::VCGE";
818 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
819 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
820 case ARMISD::VCGEU: return "ARMISD::VCGEU";
821 case ARMISD::VCGT: return "ARMISD::VCGT";
822 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
823 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
824 case ARMISD::VCGTU: return "ARMISD::VCGTU";
825 case ARMISD::VTST: return "ARMISD::VTST";
827 case ARMISD::VSHL: return "ARMISD::VSHL";
828 case ARMISD::VSHRs: return "ARMISD::VSHRs";
829 case ARMISD::VSHRu: return "ARMISD::VSHRu";
830 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
831 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
832 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
833 case ARMISD::VSHRN: return "ARMISD::VSHRN";
834 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
835 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
836 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
837 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
838 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
839 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
840 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
841 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
842 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
843 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
844 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
845 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
846 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
847 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
848 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
849 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
850 case ARMISD::VDUP: return "ARMISD::VDUP";
851 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
852 case ARMISD::VEXT: return "ARMISD::VEXT";
853 case ARMISD::VREV64: return "ARMISD::VREV64";
854 case ARMISD::VREV32: return "ARMISD::VREV32";
855 case ARMISD::VREV16: return "ARMISD::VREV16";
856 case ARMISD::VZIP: return "ARMISD::VZIP";
857 case ARMISD::VUZP: return "ARMISD::VUZP";
858 case ARMISD::VTRN: return "ARMISD::VTRN";
859 case ARMISD::VTBL1: return "ARMISD::VTBL1";
860 case ARMISD::VTBL2: return "ARMISD::VTBL2";
861 case ARMISD::VMULLs: return "ARMISD::VMULLs";
862 case ARMISD::VMULLu: return "ARMISD::VMULLu";
863 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
864 case ARMISD::FMAX: return "ARMISD::FMAX";
865 case ARMISD::FMIN: return "ARMISD::FMIN";
866 case ARMISD::BFI: return "ARMISD::BFI";
867 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
868 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
869 case ARMISD::VBSL: return "ARMISD::VBSL";
870 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
871 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
872 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
873 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
874 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
875 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
876 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
877 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
878 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
879 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
880 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
881 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
882 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
883 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
884 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
885 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
886 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
887 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
888 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
889 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
893 /// getRegClassFor - Return the register class that should be used for the
894 /// specified value type.
895 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
896 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
897 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
898 // load / store 4 to 8 consecutive D registers.
899 if (Subtarget->hasNEON()) {
900 if (VT == MVT::v4i64)
901 return ARM::QQPRRegisterClass;
902 else if (VT == MVT::v8i64)
903 return ARM::QQQQPRRegisterClass;
905 return TargetLowering::getRegClassFor(VT);
908 // Create a fast isel object.
910 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
911 return ARM::createFastISel(funcInfo);
914 /// getFunctionAlignment - Return the Log2 alignment of this function.
915 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
916 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
919 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
920 /// be used for loads / stores from the global.
921 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
922 return (Subtarget->isThumb1Only() ? 127 : 4095);
925 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
926 unsigned NumVals = N->getNumValues();
928 return Sched::RegPressure;
930 for (unsigned i = 0; i != NumVals; ++i) {
931 EVT VT = N->getValueType(i);
932 if (VT == MVT::Glue || VT == MVT::Other)
934 if (VT.isFloatingPoint() || VT.isVector())
935 return Sched::Latency;
938 if (!N->isMachineOpcode())
939 return Sched::RegPressure;
941 // Load are scheduled for latency even if there instruction itinerary
943 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
944 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
946 if (TID.getNumDefs() == 0)
947 return Sched::RegPressure;
948 if (!Itins->isEmpty() &&
949 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
950 return Sched::Latency;
952 return Sched::RegPressure;
955 //===----------------------------------------------------------------------===//
957 //===----------------------------------------------------------------------===//
959 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
960 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
962 default: llvm_unreachable("Unknown condition code!");
963 case ISD::SETNE: return ARMCC::NE;
964 case ISD::SETEQ: return ARMCC::EQ;
965 case ISD::SETGT: return ARMCC::GT;
966 case ISD::SETGE: return ARMCC::GE;
967 case ISD::SETLT: return ARMCC::LT;
968 case ISD::SETLE: return ARMCC::LE;
969 case ISD::SETUGT: return ARMCC::HI;
970 case ISD::SETUGE: return ARMCC::HS;
971 case ISD::SETULT: return ARMCC::LO;
972 case ISD::SETULE: return ARMCC::LS;
976 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
977 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
978 ARMCC::CondCodes &CondCode2) {
979 CondCode2 = ARMCC::AL;
981 default: llvm_unreachable("Unknown FP condition!");
983 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
985 case ISD::SETOGT: CondCode = ARMCC::GT; break;
987 case ISD::SETOGE: CondCode = ARMCC::GE; break;
988 case ISD::SETOLT: CondCode = ARMCC::MI; break;
989 case ISD::SETOLE: CondCode = ARMCC::LS; break;
990 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
991 case ISD::SETO: CondCode = ARMCC::VC; break;
992 case ISD::SETUO: CondCode = ARMCC::VS; break;
993 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
994 case ISD::SETUGT: CondCode = ARMCC::HI; break;
995 case ISD::SETUGE: CondCode = ARMCC::PL; break;
997 case ISD::SETULT: CondCode = ARMCC::LT; break;
999 case ISD::SETULE: CondCode = ARMCC::LE; break;
1001 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1005 //===----------------------------------------------------------------------===//
1006 // Calling Convention Implementation
1007 //===----------------------------------------------------------------------===//
1009 #include "ARMGenCallingConv.inc"
1011 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1012 /// given CallingConvention value.
1013 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1015 bool isVarArg) const {
1018 llvm_unreachable("Unsupported calling convention");
1019 case CallingConv::Fast:
1020 if (Subtarget->hasVFP2() && !isVarArg) {
1021 if (!Subtarget->isAAPCS_ABI())
1022 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1023 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1024 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1027 case CallingConv::C: {
1028 // Use target triple & subtarget features to do actual dispatch.
1029 if (!Subtarget->isAAPCS_ABI())
1030 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1031 else if (Subtarget->hasVFP2() &&
1032 FloatABIType == FloatABI::Hard && !isVarArg)
1033 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1034 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1036 case CallingConv::ARM_AAPCS_VFP:
1037 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1038 case CallingConv::ARM_AAPCS:
1039 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1040 case CallingConv::ARM_APCS:
1041 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1045 /// LowerCallResult - Lower the result values of a call into the
1046 /// appropriate copies out of appropriate physical registers.
1048 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1049 CallingConv::ID CallConv, bool isVarArg,
1050 const SmallVectorImpl<ISD::InputArg> &Ins,
1051 DebugLoc dl, SelectionDAG &DAG,
1052 SmallVectorImpl<SDValue> &InVals) const {
1054 // Assign locations to each value returned by this call.
1055 SmallVector<CCValAssign, 16> RVLocs;
1056 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1057 RVLocs, *DAG.getContext());
1058 CCInfo.AnalyzeCallResult(Ins,
1059 CCAssignFnForNode(CallConv, /* Return*/ true,
1062 // Copy all of the result registers out of their specified physreg.
1063 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1064 CCValAssign VA = RVLocs[i];
1067 if (VA.needsCustom()) {
1068 // Handle f64 or half of a v2f64.
1069 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1071 Chain = Lo.getValue(1);
1072 InFlag = Lo.getValue(2);
1073 VA = RVLocs[++i]; // skip ahead to next loc
1074 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1076 Chain = Hi.getValue(1);
1077 InFlag = Hi.getValue(2);
1078 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1080 if (VA.getLocVT() == MVT::v2f64) {
1081 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1082 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1083 DAG.getConstant(0, MVT::i32));
1085 VA = RVLocs[++i]; // skip ahead to next loc
1086 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1087 Chain = Lo.getValue(1);
1088 InFlag = Lo.getValue(2);
1089 VA = RVLocs[++i]; // skip ahead to next loc
1090 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1091 Chain = Hi.getValue(1);
1092 InFlag = Hi.getValue(2);
1093 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1094 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1095 DAG.getConstant(1, MVT::i32));
1098 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1100 Chain = Val.getValue(1);
1101 InFlag = Val.getValue(2);
1104 switch (VA.getLocInfo()) {
1105 default: llvm_unreachable("Unknown loc info!");
1106 case CCValAssign::Full: break;
1107 case CCValAssign::BCvt:
1108 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1112 InVals.push_back(Val);
1118 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1119 /// by "Src" to address "Dst" of size "Size". Alignment information is
1120 /// specified by the specific parameter attribute. The copy will be passed as
1121 /// a byval function parameter.
1122 /// Sometimes what we are copying is the end of a larger object, the part that
1123 /// does not fit in registers.
1125 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1126 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1128 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1129 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1130 /*isVolatile=*/false, /*AlwaysInline=*/false,
1131 MachinePointerInfo(0), MachinePointerInfo(0));
1134 /// LowerMemOpCallTo - Store the argument to the stack.
1136 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1137 SDValue StackPtr, SDValue Arg,
1138 DebugLoc dl, SelectionDAG &DAG,
1139 const CCValAssign &VA,
1140 ISD::ArgFlagsTy Flags) const {
1141 unsigned LocMemOffset = VA.getLocMemOffset();
1142 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1143 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1144 if (Flags.isByVal())
1145 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1147 return DAG.getStore(Chain, dl, Arg, PtrOff,
1148 MachinePointerInfo::getStack(LocMemOffset),
1152 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1153 SDValue Chain, SDValue &Arg,
1154 RegsToPassVector &RegsToPass,
1155 CCValAssign &VA, CCValAssign &NextVA,
1157 SmallVector<SDValue, 8> &MemOpChains,
1158 ISD::ArgFlagsTy Flags) const {
1160 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1161 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1162 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1164 if (NextVA.isRegLoc())
1165 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1167 assert(NextVA.isMemLoc());
1168 if (StackPtr.getNode() == 0)
1169 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1171 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1177 /// LowerCall - Lowering a call into a callseq_start <-
1178 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1181 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1182 CallingConv::ID CallConv, bool isVarArg,
1184 const SmallVectorImpl<ISD::OutputArg> &Outs,
1185 const SmallVectorImpl<SDValue> &OutVals,
1186 const SmallVectorImpl<ISD::InputArg> &Ins,
1187 DebugLoc dl, SelectionDAG &DAG,
1188 SmallVectorImpl<SDValue> &InVals) const {
1189 MachineFunction &MF = DAG.getMachineFunction();
1190 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1191 bool IsSibCall = false;
1192 // Temporarily disable tail calls so things don't break.
1193 if (!EnableARMTailCalls)
1196 // Check if it's really possible to do a tail call.
1197 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1198 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1199 Outs, OutVals, Ins, DAG);
1200 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1201 // detected sibcalls.
1208 // Analyze operands of the call, assigning locations to each operand.
1209 SmallVector<CCValAssign, 16> ArgLocs;
1210 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1212 CCInfo.AnalyzeCallOperands(Outs,
1213 CCAssignFnForNode(CallConv, /* Return*/ false,
1216 // Get a count of how many bytes are to be pushed on the stack.
1217 unsigned NumBytes = CCInfo.getNextStackOffset();
1219 // For tail calls, memory operands are available in our caller's stack.
1223 // Adjust the stack pointer for the new arguments...
1224 // These operations are automatically eliminated by the prolog/epilog pass
1226 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1228 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1230 RegsToPassVector RegsToPass;
1231 SmallVector<SDValue, 8> MemOpChains;
1233 // Walk the register/memloc assignments, inserting copies/loads. In the case
1234 // of tail call optimization, arguments are handled later.
1235 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1237 ++i, ++realArgIdx) {
1238 CCValAssign &VA = ArgLocs[i];
1239 SDValue Arg = OutVals[realArgIdx];
1240 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1241 bool isByVal = Flags.isByVal();
1243 // Promote the value if needed.
1244 switch (VA.getLocInfo()) {
1245 default: llvm_unreachable("Unknown loc info!");
1246 case CCValAssign::Full: break;
1247 case CCValAssign::SExt:
1248 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1250 case CCValAssign::ZExt:
1251 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1253 case CCValAssign::AExt:
1254 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1256 case CCValAssign::BCvt:
1257 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1261 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1262 if (VA.needsCustom()) {
1263 if (VA.getLocVT() == MVT::v2f64) {
1264 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1265 DAG.getConstant(0, MVT::i32));
1266 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1267 DAG.getConstant(1, MVT::i32));
1269 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1270 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1272 VA = ArgLocs[++i]; // skip ahead to next loc
1273 if (VA.isRegLoc()) {
1274 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1275 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1277 assert(VA.isMemLoc());
1279 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1280 dl, DAG, VA, Flags));
1283 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1284 StackPtr, MemOpChains, Flags);
1286 } else if (VA.isRegLoc()) {
1287 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1288 } else if (!IsSibCall || isByVal) {
1289 assert(VA.isMemLoc());
1291 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1292 dl, DAG, VA, Flags));
1296 if (!MemOpChains.empty())
1297 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1298 &MemOpChains[0], MemOpChains.size());
1300 // Build a sequence of copy-to-reg nodes chained together with token chain
1301 // and flag operands which copy the outgoing args into the appropriate regs.
1303 // Tail call byval lowering might overwrite argument registers so in case of
1304 // tail call optimization the copies to registers are lowered later.
1306 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1307 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1308 RegsToPass[i].second, InFlag);
1309 InFlag = Chain.getValue(1);
1312 // For tail calls lower the arguments to the 'real' stack slot.
1314 // Force all the incoming stack arguments to be loaded from the stack
1315 // before any new outgoing arguments are stored to the stack, because the
1316 // outgoing stack slots may alias the incoming argument stack slots, and
1317 // the alias isn't otherwise explicit. This is slightly more conservative
1318 // than necessary, because it means that each store effectively depends
1319 // on every argument instead of just those arguments it would clobber.
1321 // Do not flag preceeding copytoreg stuff together with the following stuff.
1323 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1324 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1325 RegsToPass[i].second, InFlag);
1326 InFlag = Chain.getValue(1);
1331 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1332 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1333 // node so that legalize doesn't hack it.
1334 bool isDirect = false;
1335 bool isARMFunc = false;
1336 bool isLocalARMFunc = false;
1337 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1339 if (EnableARMLongCalls) {
1340 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1341 && "long-calls with non-static relocation model!");
1342 // Handle a global address or an external symbol. If it's not one of
1343 // those, the target's already in a register, so we don't need to do
1345 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1346 const GlobalValue *GV = G->getGlobal();
1347 // Create a constant pool entry for the callee address
1348 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1349 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1352 // Get the address of the callee into a register
1353 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1354 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1355 Callee = DAG.getLoad(getPointerTy(), dl,
1356 DAG.getEntryNode(), CPAddr,
1357 MachinePointerInfo::getConstantPool(),
1359 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1360 const char *Sym = S->getSymbol();
1362 // Create a constant pool entry for the callee address
1363 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1364 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1365 Sym, ARMPCLabelIndex, 0);
1366 // Get the address of the callee into a register
1367 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1368 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1369 Callee = DAG.getLoad(getPointerTy(), dl,
1370 DAG.getEntryNode(), CPAddr,
1371 MachinePointerInfo::getConstantPool(),
1374 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1375 const GlobalValue *GV = G->getGlobal();
1377 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1378 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1379 getTargetMachine().getRelocationModel() != Reloc::Static;
1380 isARMFunc = !Subtarget->isThumb() || isStub;
1381 // ARM call to a local ARM function is predicable.
1382 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1383 // tBX takes a register source operand.
1384 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1385 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1386 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1389 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1390 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1391 Callee = DAG.getLoad(getPointerTy(), dl,
1392 DAG.getEntryNode(), CPAddr,
1393 MachinePointerInfo::getConstantPool(),
1395 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1396 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1397 getPointerTy(), Callee, PICLabel);
1399 // On ELF targets for PIC code, direct calls should go through the PLT
1400 unsigned OpFlags = 0;
1401 if (Subtarget->isTargetELF() &&
1402 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1403 OpFlags = ARMII::MO_PLT;
1404 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1406 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1408 bool isStub = Subtarget->isTargetDarwin() &&
1409 getTargetMachine().getRelocationModel() != Reloc::Static;
1410 isARMFunc = !Subtarget->isThumb() || isStub;
1411 // tBX takes a register source operand.
1412 const char *Sym = S->getSymbol();
1413 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1414 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1415 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1416 Sym, ARMPCLabelIndex, 4);
1417 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1418 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1419 Callee = DAG.getLoad(getPointerTy(), dl,
1420 DAG.getEntryNode(), CPAddr,
1421 MachinePointerInfo::getConstantPool(),
1423 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1424 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1425 getPointerTy(), Callee, PICLabel);
1427 unsigned OpFlags = 0;
1428 // On ELF targets for PIC code, direct calls should go through the PLT
1429 if (Subtarget->isTargetELF() &&
1430 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1431 OpFlags = ARMII::MO_PLT;
1432 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1436 // FIXME: handle tail calls differently.
1438 if (Subtarget->isThumb()) {
1439 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1440 CallOpc = ARMISD::CALL_NOLINK;
1442 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1444 CallOpc = (isDirect || Subtarget->hasV5TOps())
1445 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1446 : ARMISD::CALL_NOLINK;
1449 std::vector<SDValue> Ops;
1450 Ops.push_back(Chain);
1451 Ops.push_back(Callee);
1453 // Add argument registers to the end of the list so that they are known live
1455 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1456 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1457 RegsToPass[i].second.getValueType()));
1459 if (InFlag.getNode())
1460 Ops.push_back(InFlag);
1462 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1464 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1466 // Returns a chain and a flag for retval copy to use.
1467 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1468 InFlag = Chain.getValue(1);
1470 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1471 DAG.getIntPtrConstant(0, true), InFlag);
1473 InFlag = Chain.getValue(1);
1475 // Handle result values, copying them out of physregs into vregs that we
1477 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1481 /// HandleByVal - Every parameter *after* a byval parameter is passed
1482 /// on the stack. Confiscate all the parameter registers to insure
1485 llvm::ARMTargetLowering::HandleByVal(CCState *State) const {
1486 static const unsigned RegList1[] = {
1487 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1489 do {} while (State->AllocateReg(RegList1, 4));
1492 /// MatchingStackOffset - Return true if the given stack call argument is
1493 /// already available in the same position (relatively) of the caller's
1494 /// incoming argument stack.
1496 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1497 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1498 const ARMInstrInfo *TII) {
1499 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1501 if (Arg.getOpcode() == ISD::CopyFromReg) {
1502 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1503 if (!TargetRegisterInfo::isVirtualRegister(VR))
1505 MachineInstr *Def = MRI->getVRegDef(VR);
1508 if (!Flags.isByVal()) {
1509 if (!TII->isLoadFromStackSlot(Def, FI))
1514 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1515 if (Flags.isByVal())
1516 // ByVal argument is passed in as a pointer but it's now being
1517 // dereferenced. e.g.
1518 // define @foo(%struct.X* %A) {
1519 // tail call @bar(%struct.X* byval %A)
1522 SDValue Ptr = Ld->getBasePtr();
1523 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1526 FI = FINode->getIndex();
1530 assert(FI != INT_MAX);
1531 if (!MFI->isFixedObjectIndex(FI))
1533 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1536 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1537 /// for tail call optimization. Targets which want to do tail call
1538 /// optimization should implement this function.
1540 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1541 CallingConv::ID CalleeCC,
1543 bool isCalleeStructRet,
1544 bool isCallerStructRet,
1545 const SmallVectorImpl<ISD::OutputArg> &Outs,
1546 const SmallVectorImpl<SDValue> &OutVals,
1547 const SmallVectorImpl<ISD::InputArg> &Ins,
1548 SelectionDAG& DAG) const {
1549 const Function *CallerF = DAG.getMachineFunction().getFunction();
1550 CallingConv::ID CallerCC = CallerF->getCallingConv();
1551 bool CCMatch = CallerCC == CalleeCC;
1553 // Look for obvious safe cases to perform tail call optimization that do not
1554 // require ABI changes. This is what gcc calls sibcall.
1556 // Do not sibcall optimize vararg calls unless the call site is not passing
1558 if (isVarArg && !Outs.empty())
1561 // Also avoid sibcall optimization if either caller or callee uses struct
1562 // return semantics.
1563 if (isCalleeStructRet || isCallerStructRet)
1566 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1567 // emitEpilogue is not ready for them.
1568 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1569 // LR. This means if we need to reload LR, it takes an extra instructions,
1570 // which outweighs the value of the tail call; but here we don't know yet
1571 // whether LR is going to be used. Probably the right approach is to
1572 // generate the tail call here and turn it back into CALL/RET in
1573 // emitEpilogue if LR is used.
1575 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1576 // but we need to make sure there are enough registers; the only valid
1577 // registers are the 4 used for parameters. We don't currently do this
1579 if (Subtarget->isThumb1Only())
1582 // If the calling conventions do not match, then we'd better make sure the
1583 // results are returned in the same way as what the caller expects.
1585 SmallVector<CCValAssign, 16> RVLocs1;
1586 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1587 RVLocs1, *DAG.getContext());
1588 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1590 SmallVector<CCValAssign, 16> RVLocs2;
1591 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1592 RVLocs2, *DAG.getContext());
1593 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1595 if (RVLocs1.size() != RVLocs2.size())
1597 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1598 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1600 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1602 if (RVLocs1[i].isRegLoc()) {
1603 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1606 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1612 // If the callee takes no arguments then go on to check the results of the
1614 if (!Outs.empty()) {
1615 // Check if stack adjustment is needed. For now, do not do this if any
1616 // argument is passed on the stack.
1617 SmallVector<CCValAssign, 16> ArgLocs;
1618 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1619 ArgLocs, *DAG.getContext());
1620 CCInfo.AnalyzeCallOperands(Outs,
1621 CCAssignFnForNode(CalleeCC, false, isVarArg));
1622 if (CCInfo.getNextStackOffset()) {
1623 MachineFunction &MF = DAG.getMachineFunction();
1625 // Check if the arguments are already laid out in the right way as
1626 // the caller's fixed stack objects.
1627 MachineFrameInfo *MFI = MF.getFrameInfo();
1628 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1629 const ARMInstrInfo *TII =
1630 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1631 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1633 ++i, ++realArgIdx) {
1634 CCValAssign &VA = ArgLocs[i];
1635 EVT RegVT = VA.getLocVT();
1636 SDValue Arg = OutVals[realArgIdx];
1637 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1638 if (VA.getLocInfo() == CCValAssign::Indirect)
1640 if (VA.needsCustom()) {
1641 // f64 and vector types are split into multiple registers or
1642 // register/stack-slot combinations. The types will not match
1643 // the registers; give up on memory f64 refs until we figure
1644 // out what to do about this.
1647 if (!ArgLocs[++i].isRegLoc())
1649 if (RegVT == MVT::v2f64) {
1650 if (!ArgLocs[++i].isRegLoc())
1652 if (!ArgLocs[++i].isRegLoc())
1655 } else if (!VA.isRegLoc()) {
1656 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1668 ARMTargetLowering::LowerReturn(SDValue Chain,
1669 CallingConv::ID CallConv, bool isVarArg,
1670 const SmallVectorImpl<ISD::OutputArg> &Outs,
1671 const SmallVectorImpl<SDValue> &OutVals,
1672 DebugLoc dl, SelectionDAG &DAG) const {
1674 // CCValAssign - represent the assignment of the return value to a location.
1675 SmallVector<CCValAssign, 16> RVLocs;
1677 // CCState - Info about the registers and stack slots.
1678 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1681 // Analyze outgoing return values.
1682 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1685 // If this is the first return lowered for this function, add
1686 // the regs to the liveout set for the function.
1687 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1688 for (unsigned i = 0; i != RVLocs.size(); ++i)
1689 if (RVLocs[i].isRegLoc())
1690 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1695 // Copy the result values into the output registers.
1696 for (unsigned i = 0, realRVLocIdx = 0;
1698 ++i, ++realRVLocIdx) {
1699 CCValAssign &VA = RVLocs[i];
1700 assert(VA.isRegLoc() && "Can only return in registers!");
1702 SDValue Arg = OutVals[realRVLocIdx];
1704 switch (VA.getLocInfo()) {
1705 default: llvm_unreachable("Unknown loc info!");
1706 case CCValAssign::Full: break;
1707 case CCValAssign::BCvt:
1708 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1712 if (VA.needsCustom()) {
1713 if (VA.getLocVT() == MVT::v2f64) {
1714 // Extract the first half and return it in two registers.
1715 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1716 DAG.getConstant(0, MVT::i32));
1717 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1718 DAG.getVTList(MVT::i32, MVT::i32), Half);
1720 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1721 Flag = Chain.getValue(1);
1722 VA = RVLocs[++i]; // skip ahead to next loc
1723 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1724 HalfGPRs.getValue(1), Flag);
1725 Flag = Chain.getValue(1);
1726 VA = RVLocs[++i]; // skip ahead to next loc
1728 // Extract the 2nd half and fall through to handle it as an f64 value.
1729 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1730 DAG.getConstant(1, MVT::i32));
1732 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1734 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1735 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1736 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1737 Flag = Chain.getValue(1);
1738 VA = RVLocs[++i]; // skip ahead to next loc
1739 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1742 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1744 // Guarantee that all emitted copies are
1745 // stuck together, avoiding something bad.
1746 Flag = Chain.getValue(1);
1751 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1753 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1758 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1759 if (N->getNumValues() != 1)
1761 if (!N->hasNUsesOfValue(1, 0))
1764 unsigned NumCopies = 0;
1766 SDNode *Use = *N->use_begin();
1767 if (Use->getOpcode() == ISD::CopyToReg) {
1768 Copies[NumCopies++] = Use;
1769 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1770 // f64 returned in a pair of GPRs.
1771 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1773 if (UI->getOpcode() != ISD::CopyToReg)
1775 Copies[UI.getUse().getResNo()] = *UI;
1778 } else if (Use->getOpcode() == ISD::BITCAST) {
1779 // f32 returned in a single GPR.
1780 if (!Use->hasNUsesOfValue(1, 0))
1782 Use = *Use->use_begin();
1783 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1785 Copies[NumCopies++] = Use;
1790 if (NumCopies != 1 && NumCopies != 2)
1793 bool HasRet = false;
1794 for (unsigned i = 0; i < NumCopies; ++i) {
1795 SDNode *Copy = Copies[i];
1796 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1798 if (UI->getOpcode() == ISD::CopyToReg) {
1800 if (Use == Copies[0] || Use == Copies[1])
1804 if (UI->getOpcode() != ARMISD::RET_FLAG)
1813 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1814 if (!EnableARMTailCalls)
1817 if (!CI->isTailCall())
1820 return !Subtarget->isThumb1Only();
1823 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1824 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1825 // one of the above mentioned nodes. It has to be wrapped because otherwise
1826 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1827 // be used to form addressing mode. These wrapped nodes will be selected
1829 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1830 EVT PtrVT = Op.getValueType();
1831 // FIXME there is no actual debug info here
1832 DebugLoc dl = Op.getDebugLoc();
1833 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1835 if (CP->isMachineConstantPoolEntry())
1836 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1837 CP->getAlignment());
1839 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1840 CP->getAlignment());
1841 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1844 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1845 return MachineJumpTableInfo::EK_Inline;
1848 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1849 SelectionDAG &DAG) const {
1850 MachineFunction &MF = DAG.getMachineFunction();
1851 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1852 unsigned ARMPCLabelIndex = 0;
1853 DebugLoc DL = Op.getDebugLoc();
1854 EVT PtrVT = getPointerTy();
1855 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1856 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1858 if (RelocM == Reloc::Static) {
1859 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1861 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1862 ARMPCLabelIndex = AFI->createPICLabelUId();
1863 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1864 ARMCP::CPBlockAddress,
1866 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1868 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1869 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1870 MachinePointerInfo::getConstantPool(),
1872 if (RelocM == Reloc::Static)
1874 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1875 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1878 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1880 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1881 SelectionDAG &DAG) const {
1882 DebugLoc dl = GA->getDebugLoc();
1883 EVT PtrVT = getPointerTy();
1884 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1885 MachineFunction &MF = DAG.getMachineFunction();
1886 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1887 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1888 ARMConstantPoolValue *CPV =
1889 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1890 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1891 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1892 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1893 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1894 MachinePointerInfo::getConstantPool(),
1896 SDValue Chain = Argument.getValue(1);
1898 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1899 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1901 // call __tls_get_addr.
1904 Entry.Node = Argument;
1905 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1906 Args.push_back(Entry);
1907 // FIXME: is there useful debug info available here?
1908 std::pair<SDValue, SDValue> CallResult =
1909 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1910 false, false, false, false,
1911 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1912 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1913 return CallResult.first;
1916 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1917 // "local exec" model.
1919 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1920 SelectionDAG &DAG) const {
1921 const GlobalValue *GV = GA->getGlobal();
1922 DebugLoc dl = GA->getDebugLoc();
1924 SDValue Chain = DAG.getEntryNode();
1925 EVT PtrVT = getPointerTy();
1926 // Get the Thread Pointer
1927 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1929 if (GV->isDeclaration()) {
1930 MachineFunction &MF = DAG.getMachineFunction();
1931 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1932 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1933 // Initial exec model.
1934 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1935 ARMConstantPoolValue *CPV =
1936 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1937 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1938 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1939 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1940 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1941 MachinePointerInfo::getConstantPool(),
1943 Chain = Offset.getValue(1);
1945 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1946 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1948 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1949 MachinePointerInfo::getConstantPool(),
1953 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
1954 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1955 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1956 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1957 MachinePointerInfo::getConstantPool(),
1961 // The address of the thread local variable is the add of the thread
1962 // pointer with the offset of the variable.
1963 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1967 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1968 // TODO: implement the "local dynamic" model
1969 assert(Subtarget->isTargetELF() &&
1970 "TLS not implemented for non-ELF targets");
1971 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1972 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1973 // otherwise use the "Local Exec" TLS Model
1974 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1975 return LowerToTLSGeneralDynamicModel(GA, DAG);
1977 return LowerToTLSExecModels(GA, DAG);
1980 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1981 SelectionDAG &DAG) const {
1982 EVT PtrVT = getPointerTy();
1983 DebugLoc dl = Op.getDebugLoc();
1984 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1985 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1986 if (RelocM == Reloc::PIC_) {
1987 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1988 ARMConstantPoolValue *CPV =
1989 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
1990 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1991 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1992 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1994 MachinePointerInfo::getConstantPool(),
1996 SDValue Chain = Result.getValue(1);
1997 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1998 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2000 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2001 MachinePointerInfo::getGOT(), false, false, 0);
2005 // If we have T2 ops, we can materialize the address directly via movt/movw
2006 // pair. This is always cheaper.
2007 if (Subtarget->useMovt()) {
2009 // FIXME: Once remat is capable of dealing with instructions with register
2010 // operands, expand this into two nodes.
2011 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2012 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2014 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2015 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2016 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2017 MachinePointerInfo::getConstantPool(),
2022 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2023 SelectionDAG &DAG) const {
2024 EVT PtrVT = getPointerTy();
2025 DebugLoc dl = Op.getDebugLoc();
2026 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2027 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2028 MachineFunction &MF = DAG.getMachineFunction();
2029 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2031 if (Subtarget->useMovt()) {
2033 // FIXME: Once remat is capable of dealing with instructions with register
2034 // operands, expand this into two nodes.
2035 if (RelocM == Reloc::Static)
2036 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2037 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2039 unsigned Wrapper = (RelocM == Reloc::PIC_)
2040 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2041 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2042 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2043 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2044 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2045 MachinePointerInfo::getGOT(), false, false, 0);
2049 unsigned ARMPCLabelIndex = 0;
2051 if (RelocM == Reloc::Static) {
2052 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2054 ARMPCLabelIndex = AFI->createPICLabelUId();
2055 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2056 ARMConstantPoolValue *CPV =
2057 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
2058 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2060 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2062 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2063 MachinePointerInfo::getConstantPool(),
2065 SDValue Chain = Result.getValue(1);
2067 if (RelocM == Reloc::PIC_) {
2068 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2069 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2072 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2073 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2079 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2080 SelectionDAG &DAG) const {
2081 assert(Subtarget->isTargetELF() &&
2082 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2083 MachineFunction &MF = DAG.getMachineFunction();
2084 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2085 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2086 EVT PtrVT = getPointerTy();
2087 DebugLoc dl = Op.getDebugLoc();
2088 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2089 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2090 "_GLOBAL_OFFSET_TABLE_",
2091 ARMPCLabelIndex, PCAdj);
2092 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2093 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2094 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2095 MachinePointerInfo::getConstantPool(),
2097 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2098 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2102 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2104 DebugLoc dl = Op.getDebugLoc();
2105 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2106 Op.getOperand(0), Op.getOperand(1));
2110 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2111 DebugLoc dl = Op.getDebugLoc();
2112 SDValue Val = DAG.getConstant(0, MVT::i32);
2113 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2114 Op.getOperand(1), Val);
2118 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2119 DebugLoc dl = Op.getDebugLoc();
2120 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2121 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2125 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2126 const ARMSubtarget *Subtarget) const {
2127 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2128 DebugLoc dl = Op.getDebugLoc();
2130 default: return SDValue(); // Don't custom lower most intrinsics.
2131 case Intrinsic::arm_thread_pointer: {
2132 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2133 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2135 case Intrinsic::eh_sjlj_lsda: {
2136 MachineFunction &MF = DAG.getMachineFunction();
2137 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2138 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2139 EVT PtrVT = getPointerTy();
2140 DebugLoc dl = Op.getDebugLoc();
2141 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2143 unsigned PCAdj = (RelocM != Reloc::PIC_)
2144 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2145 ARMConstantPoolValue *CPV =
2146 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2147 ARMCP::CPLSDA, PCAdj);
2148 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2149 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2151 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2152 MachinePointerInfo::getConstantPool(),
2155 if (RelocM == Reloc::PIC_) {
2156 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2157 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2161 case Intrinsic::arm_neon_vmulls:
2162 case Intrinsic::arm_neon_vmullu: {
2163 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2164 ? ARMISD::VMULLs : ARMISD::VMULLu;
2165 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2166 Op.getOperand(1), Op.getOperand(2));
2171 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2172 const ARMSubtarget *Subtarget) {
2173 DebugLoc dl = Op.getDebugLoc();
2174 if (!Subtarget->hasDataBarrier()) {
2175 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2176 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2178 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2179 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2180 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2181 DAG.getConstant(0, MVT::i32));
2184 SDValue Op5 = Op.getOperand(5);
2185 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2186 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2187 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2188 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2190 ARM_MB::MemBOpt DMBOpt;
2191 if (isDeviceBarrier)
2192 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2194 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2195 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2196 DAG.getConstant(DMBOpt, MVT::i32));
2199 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2200 const ARMSubtarget *Subtarget) {
2201 // ARM pre v5TE and Thumb1 does not have preload instructions.
2202 if (!(Subtarget->isThumb2() ||
2203 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2204 // Just preserve the chain.
2205 return Op.getOperand(0);
2207 DebugLoc dl = Op.getDebugLoc();
2208 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2210 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2211 // ARMv7 with MP extension has PLDW.
2212 return Op.getOperand(0);
2214 if (Subtarget->isThumb())
2216 isRead = ~isRead & 1;
2217 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2219 // Currently there is no intrinsic that matches pli.
2220 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2221 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2222 DAG.getConstant(isData, MVT::i32));
2225 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2226 MachineFunction &MF = DAG.getMachineFunction();
2227 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2229 // vastart just stores the address of the VarArgsFrameIndex slot into the
2230 // memory location argument.
2231 DebugLoc dl = Op.getDebugLoc();
2232 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2233 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2234 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2235 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2236 MachinePointerInfo(SV), false, false, 0);
2240 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2241 SDValue &Root, SelectionDAG &DAG,
2242 DebugLoc dl) const {
2243 MachineFunction &MF = DAG.getMachineFunction();
2244 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2246 TargetRegisterClass *RC;
2247 if (AFI->isThumb1OnlyFunction())
2248 RC = ARM::tGPRRegisterClass;
2250 RC = ARM::GPRRegisterClass;
2252 // Transform the arguments stored in physical registers into virtual ones.
2253 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2254 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2257 if (NextVA.isMemLoc()) {
2258 MachineFrameInfo *MFI = MF.getFrameInfo();
2259 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2261 // Create load node to retrieve arguments from the stack.
2262 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2263 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2264 MachinePointerInfo::getFixedStack(FI),
2267 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2268 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2271 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2275 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2276 CallingConv::ID CallConv, bool isVarArg,
2277 const SmallVectorImpl<ISD::InputArg>
2279 DebugLoc dl, SelectionDAG &DAG,
2280 SmallVectorImpl<SDValue> &InVals)
2283 MachineFunction &MF = DAG.getMachineFunction();
2284 MachineFrameInfo *MFI = MF.getFrameInfo();
2286 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2288 // Assign locations to all of the incoming arguments.
2289 SmallVector<CCValAssign, 16> ArgLocs;
2290 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2292 CCInfo.AnalyzeFormalArguments(Ins,
2293 CCAssignFnForNode(CallConv, /* Return*/ false,
2296 SmallVector<SDValue, 16> ArgValues;
2297 int lastInsIndex = -1;
2300 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2301 CCValAssign &VA = ArgLocs[i];
2303 // Arguments stored in registers.
2304 if (VA.isRegLoc()) {
2305 EVT RegVT = VA.getLocVT();
2307 if (VA.needsCustom()) {
2308 // f64 and vector types are split up into multiple registers or
2309 // combinations of registers and stack slots.
2310 if (VA.getLocVT() == MVT::v2f64) {
2311 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2313 VA = ArgLocs[++i]; // skip ahead to next loc
2315 if (VA.isMemLoc()) {
2316 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2317 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2318 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2319 MachinePointerInfo::getFixedStack(FI),
2322 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2325 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2326 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2327 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2328 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2329 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2331 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2334 TargetRegisterClass *RC;
2336 if (RegVT == MVT::f32)
2337 RC = ARM::SPRRegisterClass;
2338 else if (RegVT == MVT::f64)
2339 RC = ARM::DPRRegisterClass;
2340 else if (RegVT == MVT::v2f64)
2341 RC = ARM::QPRRegisterClass;
2342 else if (RegVT == MVT::i32)
2343 RC = (AFI->isThumb1OnlyFunction() ?
2344 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2346 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2348 // Transform the arguments in physical registers into virtual ones.
2349 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2350 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2353 // If this is an 8 or 16-bit value, it is really passed promoted
2354 // to 32 bits. Insert an assert[sz]ext to capture this, then
2355 // truncate to the right size.
2356 switch (VA.getLocInfo()) {
2357 default: llvm_unreachable("Unknown loc info!");
2358 case CCValAssign::Full: break;
2359 case CCValAssign::BCvt:
2360 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2362 case CCValAssign::SExt:
2363 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2364 DAG.getValueType(VA.getValVT()));
2365 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2367 case CCValAssign::ZExt:
2368 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2369 DAG.getValueType(VA.getValVT()));
2370 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2374 InVals.push_back(ArgValue);
2376 } else { // VA.isRegLoc()
2379 assert(VA.isMemLoc());
2380 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2382 int index = ArgLocs[i].getValNo();
2384 // Some Ins[] entries become multiple ArgLoc[] entries.
2385 // Process them only once.
2386 if (index != lastInsIndex)
2388 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2389 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2390 // changed with more analysis.
2391 // In case of tail call optimization mark all arguments mutable. Since they
2392 // could be overwritten by lowering of arguments in case of a tail call.
2393 if (Flags.isByVal()) {
2394 unsigned Bytes = Flags.getByValSize();
2395 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2396 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), false);
2397 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2399 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2400 VA.getLocMemOffset(), true);
2402 // Create load nodes to retrieve arguments from the stack.
2403 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2404 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2405 MachinePointerInfo::getFixedStack(FI),
2408 lastInsIndex = index;
2415 static const unsigned GPRArgRegs[] = {
2416 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2419 unsigned NumGPRs = CCInfo.getFirstUnallocated
2420 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2422 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2423 unsigned VARegSize = (4 - NumGPRs) * 4;
2424 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2425 unsigned ArgOffset = CCInfo.getNextStackOffset();
2426 if (VARegSaveSize) {
2427 // If this function is vararg, store any remaining integer argument regs
2428 // to their spots on the stack so that they may be loaded by deferencing
2429 // the result of va_next.
2430 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2431 AFI->setVarArgsFrameIndex(
2432 MFI->CreateFixedObject(VARegSaveSize,
2433 ArgOffset + VARegSaveSize - VARegSize,
2435 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2438 SmallVector<SDValue, 4> MemOps;
2439 for (; NumGPRs < 4; ++NumGPRs) {
2440 TargetRegisterClass *RC;
2441 if (AFI->isThumb1OnlyFunction())
2442 RC = ARM::tGPRRegisterClass;
2444 RC = ARM::GPRRegisterClass;
2446 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2447 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2449 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2450 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2452 MemOps.push_back(Store);
2453 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2454 DAG.getConstant(4, getPointerTy()));
2456 if (!MemOps.empty())
2457 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2458 &MemOps[0], MemOps.size());
2460 // This will point to the next argument passed via stack.
2461 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2467 /// isFloatingPointZero - Return true if this is +0.0.
2468 static bool isFloatingPointZero(SDValue Op) {
2469 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2470 return CFP->getValueAPF().isPosZero();
2471 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2472 // Maybe this has already been legalized into the constant pool?
2473 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2474 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2475 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2476 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2477 return CFP->getValueAPF().isPosZero();
2483 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2484 /// the given operands.
2486 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2487 SDValue &ARMcc, SelectionDAG &DAG,
2488 DebugLoc dl) const {
2489 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2490 unsigned C = RHSC->getZExtValue();
2491 if (!isLegalICmpImmediate(C)) {
2492 // Constant does not fit, try adjusting it by one?
2497 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2498 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2499 RHS = DAG.getConstant(C-1, MVT::i32);
2504 if (C != 0 && isLegalICmpImmediate(C-1)) {
2505 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2506 RHS = DAG.getConstant(C-1, MVT::i32);
2511 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2512 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2513 RHS = DAG.getConstant(C+1, MVT::i32);
2518 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2519 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2520 RHS = DAG.getConstant(C+1, MVT::i32);
2527 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2528 ARMISD::NodeType CompareType;
2531 CompareType = ARMISD::CMP;
2536 CompareType = ARMISD::CMPZ;
2539 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2540 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2543 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2545 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2546 DebugLoc dl) const {
2548 if (!isFloatingPointZero(RHS))
2549 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2551 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2552 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2555 /// duplicateCmp - Glue values can have only one use, so this function
2556 /// duplicates a comparison node.
2558 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2559 unsigned Opc = Cmp.getOpcode();
2560 DebugLoc DL = Cmp.getDebugLoc();
2561 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2562 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2564 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2565 Cmp = Cmp.getOperand(0);
2566 Opc = Cmp.getOpcode();
2567 if (Opc == ARMISD::CMPFP)
2568 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2570 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2571 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2573 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2576 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2577 SDValue Cond = Op.getOperand(0);
2578 SDValue SelectTrue = Op.getOperand(1);
2579 SDValue SelectFalse = Op.getOperand(2);
2580 DebugLoc dl = Op.getDebugLoc();
2584 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2585 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2587 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2588 const ConstantSDNode *CMOVTrue =
2589 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2590 const ConstantSDNode *CMOVFalse =
2591 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2593 if (CMOVTrue && CMOVFalse) {
2594 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2595 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2599 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2601 False = SelectFalse;
2602 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2607 if (True.getNode() && False.getNode()) {
2608 EVT VT = Cond.getValueType();
2609 SDValue ARMcc = Cond.getOperand(2);
2610 SDValue CCR = Cond.getOperand(3);
2611 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2612 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2617 return DAG.getSelectCC(dl, Cond,
2618 DAG.getConstant(0, Cond.getValueType()),
2619 SelectTrue, SelectFalse, ISD::SETNE);
2622 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2623 EVT VT = Op.getValueType();
2624 SDValue LHS = Op.getOperand(0);
2625 SDValue RHS = Op.getOperand(1);
2626 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2627 SDValue TrueVal = Op.getOperand(2);
2628 SDValue FalseVal = Op.getOperand(3);
2629 DebugLoc dl = Op.getDebugLoc();
2631 if (LHS.getValueType() == MVT::i32) {
2633 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2634 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2635 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2638 ARMCC::CondCodes CondCode, CondCode2;
2639 FPCCToARMCC(CC, CondCode, CondCode2);
2641 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2642 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2643 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2644 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2646 if (CondCode2 != ARMCC::AL) {
2647 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2648 // FIXME: Needs another CMP because flag can have but one use.
2649 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2650 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2651 Result, TrueVal, ARMcc2, CCR, Cmp2);
2656 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2657 /// to morph to an integer compare sequence.
2658 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2659 const ARMSubtarget *Subtarget) {
2660 SDNode *N = Op.getNode();
2661 if (!N->hasOneUse())
2662 // Otherwise it requires moving the value from fp to integer registers.
2664 if (!N->getNumValues())
2666 EVT VT = Op.getValueType();
2667 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2668 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2669 // vmrs are very slow, e.g. cortex-a8.
2672 if (isFloatingPointZero(Op)) {
2676 return ISD::isNormalLoad(N);
2679 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2680 if (isFloatingPointZero(Op))
2681 return DAG.getConstant(0, MVT::i32);
2683 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2684 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2685 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2686 Ld->isVolatile(), Ld->isNonTemporal(),
2687 Ld->getAlignment());
2689 llvm_unreachable("Unknown VFP cmp argument!");
2692 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2693 SDValue &RetVal1, SDValue &RetVal2) {
2694 if (isFloatingPointZero(Op)) {
2695 RetVal1 = DAG.getConstant(0, MVT::i32);
2696 RetVal2 = DAG.getConstant(0, MVT::i32);
2700 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2701 SDValue Ptr = Ld->getBasePtr();
2702 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2703 Ld->getChain(), Ptr,
2704 Ld->getPointerInfo(),
2705 Ld->isVolatile(), Ld->isNonTemporal(),
2706 Ld->getAlignment());
2708 EVT PtrType = Ptr.getValueType();
2709 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2710 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2711 PtrType, Ptr, DAG.getConstant(4, PtrType));
2712 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2713 Ld->getChain(), NewPtr,
2714 Ld->getPointerInfo().getWithOffset(4),
2715 Ld->isVolatile(), Ld->isNonTemporal(),
2720 llvm_unreachable("Unknown VFP cmp argument!");
2723 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2724 /// f32 and even f64 comparisons to integer ones.
2726 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2727 SDValue Chain = Op.getOperand(0);
2728 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2729 SDValue LHS = Op.getOperand(2);
2730 SDValue RHS = Op.getOperand(3);
2731 SDValue Dest = Op.getOperand(4);
2732 DebugLoc dl = Op.getDebugLoc();
2734 bool SeenZero = false;
2735 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2736 canChangeToInt(RHS, SeenZero, Subtarget) &&
2737 // If one of the operand is zero, it's safe to ignore the NaN case since
2738 // we only care about equality comparisons.
2739 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2740 // If unsafe fp math optimization is enabled and there are no other uses of
2741 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2742 // to an integer comparison.
2743 if (CC == ISD::SETOEQ)
2745 else if (CC == ISD::SETUNE)
2749 if (LHS.getValueType() == MVT::f32) {
2750 LHS = bitcastf32Toi32(LHS, DAG);
2751 RHS = bitcastf32Toi32(RHS, DAG);
2752 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2753 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2754 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2755 Chain, Dest, ARMcc, CCR, Cmp);
2760 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2761 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2762 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2763 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2764 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2765 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2766 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2772 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2773 SDValue Chain = Op.getOperand(0);
2774 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2775 SDValue LHS = Op.getOperand(2);
2776 SDValue RHS = Op.getOperand(3);
2777 SDValue Dest = Op.getOperand(4);
2778 DebugLoc dl = Op.getDebugLoc();
2780 if (LHS.getValueType() == MVT::i32) {
2782 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2783 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2784 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2785 Chain, Dest, ARMcc, CCR, Cmp);
2788 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2791 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2792 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2793 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2794 if (Result.getNode())
2798 ARMCC::CondCodes CondCode, CondCode2;
2799 FPCCToARMCC(CC, CondCode, CondCode2);
2801 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2802 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2803 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2804 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2805 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2806 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2807 if (CondCode2 != ARMCC::AL) {
2808 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2809 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2810 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2815 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2816 SDValue Chain = Op.getOperand(0);
2817 SDValue Table = Op.getOperand(1);
2818 SDValue Index = Op.getOperand(2);
2819 DebugLoc dl = Op.getDebugLoc();
2821 EVT PTy = getPointerTy();
2822 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2823 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2824 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2825 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2826 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2827 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2828 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2829 if (Subtarget->isThumb2()) {
2830 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2831 // which does another jump to the destination. This also makes it easier
2832 // to translate it to TBB / TBH later.
2833 // FIXME: This might not work if the function is extremely large.
2834 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2835 Addr, Op.getOperand(2), JTI, UId);
2837 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2838 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2839 MachinePointerInfo::getJumpTable(),
2841 Chain = Addr.getValue(1);
2842 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2843 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2845 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2846 MachinePointerInfo::getJumpTable(), false, false, 0);
2847 Chain = Addr.getValue(1);
2848 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2852 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2853 DebugLoc dl = Op.getDebugLoc();
2856 switch (Op.getOpcode()) {
2858 assert(0 && "Invalid opcode!");
2859 case ISD::FP_TO_SINT:
2860 Opc = ARMISD::FTOSI;
2862 case ISD::FP_TO_UINT:
2863 Opc = ARMISD::FTOUI;
2866 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2867 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2870 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2871 EVT VT = Op.getValueType();
2872 DebugLoc dl = Op.getDebugLoc();
2874 EVT OperandVT = Op.getOperand(0).getValueType();
2875 assert(OperandVT == MVT::v4i16 && "Invalid type for custom lowering!");
2876 if (VT != MVT::v4f32)
2877 return DAG.UnrollVectorOp(Op.getNode());
2881 switch (Op.getOpcode()) {
2883 assert(0 && "Invalid opcode!");
2884 case ISD::SINT_TO_FP:
2885 CastOpc = ISD::SIGN_EXTEND;
2886 Opc = ISD::SINT_TO_FP;
2888 case ISD::UINT_TO_FP:
2889 CastOpc = ISD::ZERO_EXTEND;
2890 Opc = ISD::UINT_TO_FP;
2894 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
2895 return DAG.getNode(Opc, dl, VT, Op);
2898 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2899 EVT VT = Op.getValueType();
2901 return LowerVectorINT_TO_FP(Op, DAG);
2903 DebugLoc dl = Op.getDebugLoc();
2906 switch (Op.getOpcode()) {
2908 assert(0 && "Invalid opcode!");
2909 case ISD::SINT_TO_FP:
2910 Opc = ARMISD::SITOF;
2912 case ISD::UINT_TO_FP:
2913 Opc = ARMISD::UITOF;
2917 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
2918 return DAG.getNode(Opc, dl, VT, Op);
2921 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2922 // Implement fcopysign with a fabs and a conditional fneg.
2923 SDValue Tmp0 = Op.getOperand(0);
2924 SDValue Tmp1 = Op.getOperand(1);
2925 DebugLoc dl = Op.getDebugLoc();
2926 EVT VT = Op.getValueType();
2927 EVT SrcVT = Tmp1.getValueType();
2928 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
2929 Tmp0.getOpcode() == ARMISD::VMOVDRR;
2930 bool UseNEON = !InGPR && Subtarget->hasNEON();
2933 // Use VBSL to copy the sign bit.
2934 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
2935 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
2936 DAG.getTargetConstant(EncodedVal, MVT::i32));
2937 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
2939 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
2940 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
2941 DAG.getConstant(32, MVT::i32));
2942 else /*if (VT == MVT::f32)*/
2943 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
2944 if (SrcVT == MVT::f32) {
2945 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
2947 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
2948 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
2949 DAG.getConstant(32, MVT::i32));
2951 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
2952 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
2954 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
2956 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
2957 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
2958 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
2960 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
2961 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
2962 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
2963 if (VT == MVT::f32) {
2964 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
2965 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
2966 DAG.getConstant(0, MVT::i32));
2968 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
2974 // Bitcast operand 1 to i32.
2975 if (SrcVT == MVT::f64)
2976 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
2977 &Tmp1, 1).getValue(1);
2978 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
2980 // Or in the signbit with integer operations.
2981 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
2982 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
2983 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
2984 if (VT == MVT::f32) {
2985 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
2986 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
2987 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
2988 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
2991 // f64: Or the high part with signbit and then combine two parts.
2992 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
2994 SDValue Lo = Tmp0.getValue(0);
2995 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
2996 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
2997 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3000 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3001 MachineFunction &MF = DAG.getMachineFunction();
3002 MachineFrameInfo *MFI = MF.getFrameInfo();
3003 MFI->setReturnAddressIsTaken(true);
3005 EVT VT = Op.getValueType();
3006 DebugLoc dl = Op.getDebugLoc();
3007 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3009 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3010 SDValue Offset = DAG.getConstant(4, MVT::i32);
3011 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3012 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3013 MachinePointerInfo(), false, false, 0);
3016 // Return LR, which contains the return address. Mark it an implicit live-in.
3017 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3018 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3021 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3022 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3023 MFI->setFrameAddressIsTaken(true);
3025 EVT VT = Op.getValueType();
3026 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3027 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3028 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3029 ? ARM::R7 : ARM::R11;
3030 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3032 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3033 MachinePointerInfo(),
3038 /// ExpandBITCAST - If the target supports VFP, this function is called to
3039 /// expand a bit convert where either the source or destination type is i64 to
3040 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3041 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3042 /// vectors), since the legalizer won't know what to do with that.
3043 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3044 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3045 DebugLoc dl = N->getDebugLoc();
3046 SDValue Op = N->getOperand(0);
3048 // This function is only supposed to be called for i64 types, either as the
3049 // source or destination of the bit convert.
3050 EVT SrcVT = Op.getValueType();
3051 EVT DstVT = N->getValueType(0);
3052 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3053 "ExpandBITCAST called for non-i64 type");
3055 // Turn i64->f64 into VMOVDRR.
3056 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3057 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3058 DAG.getConstant(0, MVT::i32));
3059 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3060 DAG.getConstant(1, MVT::i32));
3061 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3062 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3065 // Turn f64->i64 into VMOVRRD.
3066 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3067 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3068 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3069 // Merge the pieces into a single i64 value.
3070 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3076 /// getZeroVector - Returns a vector of specified type with all zero elements.
3077 /// Zero vectors are used to represent vector negation and in those cases
3078 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3079 /// not support i64 elements, so sometimes the zero vectors will need to be
3080 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3082 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3083 assert(VT.isVector() && "Expected a vector type");
3084 // The canonical modified immediate encoding of a zero vector is....0!
3085 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3086 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3087 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3088 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3091 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3092 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3093 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3094 SelectionDAG &DAG) const {
3095 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3096 EVT VT = Op.getValueType();
3097 unsigned VTBits = VT.getSizeInBits();
3098 DebugLoc dl = Op.getDebugLoc();
3099 SDValue ShOpLo = Op.getOperand(0);
3100 SDValue ShOpHi = Op.getOperand(1);
3101 SDValue ShAmt = Op.getOperand(2);
3103 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3105 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3107 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3108 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3109 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3110 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3111 DAG.getConstant(VTBits, MVT::i32));
3112 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3113 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3114 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3116 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3117 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3119 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3120 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3123 SDValue Ops[2] = { Lo, Hi };
3124 return DAG.getMergeValues(Ops, 2, dl);
3127 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3128 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3129 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3130 SelectionDAG &DAG) const {
3131 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3132 EVT VT = Op.getValueType();
3133 unsigned VTBits = VT.getSizeInBits();
3134 DebugLoc dl = Op.getDebugLoc();
3135 SDValue ShOpLo = Op.getOperand(0);
3136 SDValue ShOpHi = Op.getOperand(1);
3137 SDValue ShAmt = Op.getOperand(2);
3140 assert(Op.getOpcode() == ISD::SHL_PARTS);
3141 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3142 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3143 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3144 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3145 DAG.getConstant(VTBits, MVT::i32));
3146 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3147 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3149 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3150 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3151 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3153 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3154 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3157 SDValue Ops[2] = { Lo, Hi };
3158 return DAG.getMergeValues(Ops, 2, dl);
3161 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3162 SelectionDAG &DAG) const {
3163 // The rounding mode is in bits 23:22 of the FPSCR.
3164 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3165 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3166 // so that the shift + and get folded into a bitfield extract.
3167 DebugLoc dl = Op.getDebugLoc();
3168 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3169 DAG.getConstant(Intrinsic::arm_get_fpscr,
3171 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3172 DAG.getConstant(1U << 22, MVT::i32));
3173 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3174 DAG.getConstant(22, MVT::i32));
3175 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3176 DAG.getConstant(3, MVT::i32));
3179 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3180 const ARMSubtarget *ST) {
3181 EVT VT = N->getValueType(0);
3182 DebugLoc dl = N->getDebugLoc();
3184 if (!ST->hasV6T2Ops())
3187 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3188 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3191 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3192 const ARMSubtarget *ST) {
3193 EVT VT = N->getValueType(0);
3194 DebugLoc dl = N->getDebugLoc();
3199 // Lower vector shifts on NEON to use VSHL.
3200 assert(ST->hasNEON() && "unexpected vector shift");
3202 // Left shifts translate directly to the vshiftu intrinsic.
3203 if (N->getOpcode() == ISD::SHL)
3204 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3205 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3206 N->getOperand(0), N->getOperand(1));
3208 assert((N->getOpcode() == ISD::SRA ||
3209 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3211 // NEON uses the same intrinsics for both left and right shifts. For
3212 // right shifts, the shift amounts are negative, so negate the vector of
3214 EVT ShiftVT = N->getOperand(1).getValueType();
3215 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3216 getZeroVector(ShiftVT, DAG, dl),
3218 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3219 Intrinsic::arm_neon_vshifts :
3220 Intrinsic::arm_neon_vshiftu);
3221 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3222 DAG.getConstant(vshiftInt, MVT::i32),
3223 N->getOperand(0), NegatedCount);
3226 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3227 const ARMSubtarget *ST) {
3228 EVT VT = N->getValueType(0);
3229 DebugLoc dl = N->getDebugLoc();
3231 // We can get here for a node like i32 = ISD::SHL i32, i64
3235 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3236 "Unknown shift to lower!");
3238 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3239 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3240 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3243 // If we are in thumb mode, we don't have RRX.
3244 if (ST->isThumb1Only()) return SDValue();
3246 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3247 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3248 DAG.getConstant(0, MVT::i32));
3249 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3250 DAG.getConstant(1, MVT::i32));
3252 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3253 // captures the result into a carry flag.
3254 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3255 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3257 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3258 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3260 // Merge the pieces into a single i64 value.
3261 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3264 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3265 SDValue TmpOp0, TmpOp1;
3266 bool Invert = false;
3270 SDValue Op0 = Op.getOperand(0);
3271 SDValue Op1 = Op.getOperand(1);
3272 SDValue CC = Op.getOperand(2);
3273 EVT VT = Op.getValueType();
3274 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3275 DebugLoc dl = Op.getDebugLoc();
3277 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3278 switch (SetCCOpcode) {
3279 default: llvm_unreachable("Illegal FP comparison"); break;
3281 case ISD::SETNE: Invert = true; // Fallthrough
3283 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3285 case ISD::SETLT: Swap = true; // Fallthrough
3287 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3289 case ISD::SETLE: Swap = true; // Fallthrough
3291 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3292 case ISD::SETUGE: Swap = true; // Fallthrough
3293 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3294 case ISD::SETUGT: Swap = true; // Fallthrough
3295 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3296 case ISD::SETUEQ: Invert = true; // Fallthrough
3298 // Expand this to (OLT | OGT).
3302 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3303 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3305 case ISD::SETUO: Invert = true; // Fallthrough
3307 // Expand this to (OLT | OGE).
3311 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3312 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3316 // Integer comparisons.
3317 switch (SetCCOpcode) {
3318 default: llvm_unreachable("Illegal integer comparison"); break;
3319 case ISD::SETNE: Invert = true;
3320 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3321 case ISD::SETLT: Swap = true;
3322 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3323 case ISD::SETLE: Swap = true;
3324 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3325 case ISD::SETULT: Swap = true;
3326 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3327 case ISD::SETULE: Swap = true;
3328 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3331 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3332 if (Opc == ARMISD::VCEQ) {
3335 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3337 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3340 // Ignore bitconvert.
3341 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3342 AndOp = AndOp.getOperand(0);
3344 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3346 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3347 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3354 std::swap(Op0, Op1);
3356 // If one of the operands is a constant vector zero, attempt to fold the
3357 // comparison to a specialized compare-against-zero form.
3359 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3361 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3362 if (Opc == ARMISD::VCGE)
3363 Opc = ARMISD::VCLEZ;
3364 else if (Opc == ARMISD::VCGT)
3365 Opc = ARMISD::VCLTZ;
3370 if (SingleOp.getNode()) {
3373 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3375 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3377 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3379 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3381 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3383 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3386 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3390 Result = DAG.getNOT(dl, Result, VT);
3395 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3396 /// valid vector constant for a NEON instruction with a "modified immediate"
3397 /// operand (e.g., VMOV). If so, return the encoded value.
3398 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3399 unsigned SplatBitSize, SelectionDAG &DAG,
3400 EVT &VT, bool is128Bits, NEONModImmType type) {
3401 unsigned OpCmode, Imm;
3403 // SplatBitSize is set to the smallest size that splats the vector, so a
3404 // zero vector will always have SplatBitSize == 8. However, NEON modified
3405 // immediate instructions others than VMOV do not support the 8-bit encoding
3406 // of a zero vector, and the default encoding of zero is supposed to be the
3411 switch (SplatBitSize) {
3413 if (type != VMOVModImm)
3415 // Any 1-byte value is OK. Op=0, Cmode=1110.
3416 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3419 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3423 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3424 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3425 if ((SplatBits & ~0xff) == 0) {
3426 // Value = 0x00nn: Op=x, Cmode=100x.
3431 if ((SplatBits & ~0xff00) == 0) {
3432 // Value = 0xnn00: Op=x, Cmode=101x.
3434 Imm = SplatBits >> 8;
3440 // NEON's 32-bit VMOV supports splat values where:
3441 // * only one byte is nonzero, or
3442 // * the least significant byte is 0xff and the second byte is nonzero, or
3443 // * the least significant 2 bytes are 0xff and the third is nonzero.
3444 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3445 if ((SplatBits & ~0xff) == 0) {
3446 // Value = 0x000000nn: Op=x, Cmode=000x.
3451 if ((SplatBits & ~0xff00) == 0) {
3452 // Value = 0x0000nn00: Op=x, Cmode=001x.
3454 Imm = SplatBits >> 8;
3457 if ((SplatBits & ~0xff0000) == 0) {
3458 // Value = 0x00nn0000: Op=x, Cmode=010x.
3460 Imm = SplatBits >> 16;
3463 if ((SplatBits & ~0xff000000) == 0) {
3464 // Value = 0xnn000000: Op=x, Cmode=011x.
3466 Imm = SplatBits >> 24;
3470 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3471 if (type == OtherModImm) return SDValue();
3473 if ((SplatBits & ~0xffff) == 0 &&
3474 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3475 // Value = 0x0000nnff: Op=x, Cmode=1100.
3477 Imm = SplatBits >> 8;
3482 if ((SplatBits & ~0xffffff) == 0 &&
3483 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3484 // Value = 0x00nnffff: Op=x, Cmode=1101.
3486 Imm = SplatBits >> 16;
3487 SplatBits |= 0xffff;
3491 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3492 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3493 // VMOV.I32. A (very) minor optimization would be to replicate the value
3494 // and fall through here to test for a valid 64-bit splat. But, then the
3495 // caller would also need to check and handle the change in size.
3499 if (type != VMOVModImm)
3501 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3502 uint64_t BitMask = 0xff;
3504 unsigned ImmMask = 1;
3506 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3507 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3510 } else if ((SplatBits & BitMask) != 0) {
3516 // Op=1, Cmode=1110.
3519 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3524 llvm_unreachable("unexpected size for isNEONModifiedImm");
3528 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3529 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3532 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3533 bool &ReverseVEXT, unsigned &Imm) {
3534 unsigned NumElts = VT.getVectorNumElements();
3535 ReverseVEXT = false;
3537 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3543 // If this is a VEXT shuffle, the immediate value is the index of the first
3544 // element. The other shuffle indices must be the successive elements after
3546 unsigned ExpectedElt = Imm;
3547 for (unsigned i = 1; i < NumElts; ++i) {
3548 // Increment the expected index. If it wraps around, it may still be
3549 // a VEXT but the source vectors must be swapped.
3551 if (ExpectedElt == NumElts * 2) {
3556 if (M[i] < 0) continue; // ignore UNDEF indices
3557 if (ExpectedElt != static_cast<unsigned>(M[i]))
3561 // Adjust the index value if the source operands will be swapped.
3568 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3569 /// instruction with the specified blocksize. (The order of the elements
3570 /// within each block of the vector is reversed.)
3571 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3572 unsigned BlockSize) {
3573 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3574 "Only possible block sizes for VREV are: 16, 32, 64");
3576 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3580 unsigned NumElts = VT.getVectorNumElements();
3581 unsigned BlockElts = M[0] + 1;
3582 // If the first shuffle index is UNDEF, be optimistic.
3584 BlockElts = BlockSize / EltSz;
3586 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3589 for (unsigned i = 0; i < NumElts; ++i) {
3590 if (M[i] < 0) continue; // ignore UNDEF indices
3591 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3598 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3599 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3600 // range, then 0 is placed into the resulting vector. So pretty much any mask
3601 // of 8 elements can work here.
3602 return VT == MVT::v8i8 && M.size() == 8;
3605 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3606 unsigned &WhichResult) {
3607 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3611 unsigned NumElts = VT.getVectorNumElements();
3612 WhichResult = (M[0] == 0 ? 0 : 1);
3613 for (unsigned i = 0; i < NumElts; i += 2) {
3614 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3615 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3621 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3622 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3623 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3624 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3625 unsigned &WhichResult) {
3626 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3630 unsigned NumElts = VT.getVectorNumElements();
3631 WhichResult = (M[0] == 0 ? 0 : 1);
3632 for (unsigned i = 0; i < NumElts; i += 2) {
3633 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3634 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3640 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3641 unsigned &WhichResult) {
3642 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3646 unsigned NumElts = VT.getVectorNumElements();
3647 WhichResult = (M[0] == 0 ? 0 : 1);
3648 for (unsigned i = 0; i != NumElts; ++i) {
3649 if (M[i] < 0) continue; // ignore UNDEF indices
3650 if ((unsigned) M[i] != 2 * i + WhichResult)
3654 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3655 if (VT.is64BitVector() && EltSz == 32)
3661 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3662 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3663 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3664 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3665 unsigned &WhichResult) {
3666 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3670 unsigned Half = VT.getVectorNumElements() / 2;
3671 WhichResult = (M[0] == 0 ? 0 : 1);
3672 for (unsigned j = 0; j != 2; ++j) {
3673 unsigned Idx = WhichResult;
3674 for (unsigned i = 0; i != Half; ++i) {
3675 int MIdx = M[i + j * Half];
3676 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3682 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3683 if (VT.is64BitVector() && EltSz == 32)
3689 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3690 unsigned &WhichResult) {
3691 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3695 unsigned NumElts = VT.getVectorNumElements();
3696 WhichResult = (M[0] == 0 ? 0 : 1);
3697 unsigned Idx = WhichResult * NumElts / 2;
3698 for (unsigned i = 0; i != NumElts; i += 2) {
3699 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3700 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3705 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3706 if (VT.is64BitVector() && EltSz == 32)
3712 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3713 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3714 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3715 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3716 unsigned &WhichResult) {
3717 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3721 unsigned NumElts = VT.getVectorNumElements();
3722 WhichResult = (M[0] == 0 ? 0 : 1);
3723 unsigned Idx = WhichResult * NumElts / 2;
3724 for (unsigned i = 0; i != NumElts; i += 2) {
3725 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3726 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3731 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3732 if (VT.is64BitVector() && EltSz == 32)
3738 // If N is an integer constant that can be moved into a register in one
3739 // instruction, return an SDValue of such a constant (will become a MOV
3740 // instruction). Otherwise return null.
3741 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3742 const ARMSubtarget *ST, DebugLoc dl) {
3744 if (!isa<ConstantSDNode>(N))
3746 Val = cast<ConstantSDNode>(N)->getZExtValue();
3748 if (ST->isThumb1Only()) {
3749 if (Val <= 255 || ~Val <= 255)
3750 return DAG.getConstant(Val, MVT::i32);
3752 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3753 return DAG.getConstant(Val, MVT::i32);
3758 // If this is a case we can't handle, return null and let the default
3759 // expansion code take care of it.
3760 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3761 const ARMSubtarget *ST) const {
3762 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3763 DebugLoc dl = Op.getDebugLoc();
3764 EVT VT = Op.getValueType();
3766 APInt SplatBits, SplatUndef;
3767 unsigned SplatBitSize;
3769 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3770 if (SplatBitSize <= 64) {
3771 // Check if an immediate VMOV works.
3773 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3774 SplatUndef.getZExtValue(), SplatBitSize,
3775 DAG, VmovVT, VT.is128BitVector(),
3777 if (Val.getNode()) {
3778 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3779 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3782 // Try an immediate VMVN.
3783 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3784 ((1LL << SplatBitSize) - 1));
3785 Val = isNEONModifiedImm(NegatedImm,
3786 SplatUndef.getZExtValue(), SplatBitSize,
3787 DAG, VmovVT, VT.is128BitVector(),
3789 if (Val.getNode()) {
3790 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3791 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3796 // Scan through the operands to see if only one value is used.
3797 unsigned NumElts = VT.getVectorNumElements();
3798 bool isOnlyLowElement = true;
3799 bool usesOnlyOneValue = true;
3800 bool isConstant = true;
3802 for (unsigned i = 0; i < NumElts; ++i) {
3803 SDValue V = Op.getOperand(i);
3804 if (V.getOpcode() == ISD::UNDEF)
3807 isOnlyLowElement = false;
3808 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3811 if (!Value.getNode())
3813 else if (V != Value)
3814 usesOnlyOneValue = false;
3817 if (!Value.getNode())
3818 return DAG.getUNDEF(VT);
3820 if (isOnlyLowElement)
3821 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3823 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3825 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3826 // i32 and try again.
3827 if (usesOnlyOneValue && EltSize <= 32) {
3829 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3830 if (VT.getVectorElementType().isFloatingPoint()) {
3831 SmallVector<SDValue, 8> Ops;
3832 for (unsigned i = 0; i < NumElts; ++i)
3833 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3835 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3836 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3837 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3839 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3841 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3843 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3846 // If all elements are constants and the case above didn't get hit, fall back
3847 // to the default expansion, which will generate a load from the constant
3852 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
3854 SDValue shuffle = ReconstructShuffle(Op, DAG);
3855 if (shuffle != SDValue())
3859 // Vectors with 32- or 64-bit elements can be built by directly assigning
3860 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3861 // will be legalized.
3862 if (EltSize >= 32) {
3863 // Do the expansion with floating-point types, since that is what the VFP
3864 // registers are defined to use, and since i64 is not legal.
3865 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3866 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3867 SmallVector<SDValue, 8> Ops;
3868 for (unsigned i = 0; i < NumElts; ++i)
3869 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3870 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3871 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3877 // Gather data to see if the operation can be modelled as a
3878 // shuffle in combination with VEXTs.
3879 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
3880 SelectionDAG &DAG) const {
3881 DebugLoc dl = Op.getDebugLoc();
3882 EVT VT = Op.getValueType();
3883 unsigned NumElts = VT.getVectorNumElements();
3885 SmallVector<SDValue, 2> SourceVecs;
3886 SmallVector<unsigned, 2> MinElts;
3887 SmallVector<unsigned, 2> MaxElts;
3889 for (unsigned i = 0; i < NumElts; ++i) {
3890 SDValue V = Op.getOperand(i);
3891 if (V.getOpcode() == ISD::UNDEF)
3893 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
3894 // A shuffle can only come from building a vector from various
3895 // elements of other vectors.
3899 // Record this extraction against the appropriate vector if possible...
3900 SDValue SourceVec = V.getOperand(0);
3901 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
3902 bool FoundSource = false;
3903 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
3904 if (SourceVecs[j] == SourceVec) {
3905 if (MinElts[j] > EltNo)
3907 if (MaxElts[j] < EltNo)
3914 // Or record a new source if not...
3916 SourceVecs.push_back(SourceVec);
3917 MinElts.push_back(EltNo);
3918 MaxElts.push_back(EltNo);
3922 // Currently only do something sane when at most two source vectors
3924 if (SourceVecs.size() > 2)
3927 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
3928 int VEXTOffsets[2] = {0, 0};
3930 // This loop extracts the usage patterns of the source vectors
3931 // and prepares appropriate SDValues for a shuffle if possible.
3932 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
3933 if (SourceVecs[i].getValueType() == VT) {
3934 // No VEXT necessary
3935 ShuffleSrcs[i] = SourceVecs[i];
3938 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
3939 // It probably isn't worth padding out a smaller vector just to
3940 // break it down again in a shuffle.
3944 // Since only 64-bit and 128-bit vectors are legal on ARM and
3945 // we've eliminated the other cases...
3946 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
3947 "unexpected vector sizes in ReconstructShuffle");
3949 if (MaxElts[i] - MinElts[i] >= NumElts) {
3950 // Span too large for a VEXT to cope
3954 if (MinElts[i] >= NumElts) {
3955 // The extraction can just take the second half
3956 VEXTOffsets[i] = NumElts;
3957 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3959 DAG.getIntPtrConstant(NumElts));
3960 } else if (MaxElts[i] < NumElts) {
3961 // The extraction can just take the first half
3963 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3965 DAG.getIntPtrConstant(0));
3967 // An actual VEXT is needed
3968 VEXTOffsets[i] = MinElts[i];
3969 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3971 DAG.getIntPtrConstant(0));
3972 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3974 DAG.getIntPtrConstant(NumElts));
3975 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
3976 DAG.getConstant(VEXTOffsets[i], MVT::i32));
3980 SmallVector<int, 8> Mask;
3982 for (unsigned i = 0; i < NumElts; ++i) {
3983 SDValue Entry = Op.getOperand(i);
3984 if (Entry.getOpcode() == ISD::UNDEF) {
3989 SDValue ExtractVec = Entry.getOperand(0);
3990 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
3991 .getOperand(1))->getSExtValue();
3992 if (ExtractVec == SourceVecs[0]) {
3993 Mask.push_back(ExtractElt - VEXTOffsets[0]);
3995 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
3999 // Final check before we try to produce nonsense...
4000 if (isShuffleMaskLegal(Mask, VT))
4001 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4007 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4008 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4009 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4010 /// are assumed to be legal.
4012 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4014 if (VT.getVectorNumElements() == 4 &&
4015 (VT.is128BitVector() || VT.is64BitVector())) {
4016 unsigned PFIndexes[4];
4017 for (unsigned i = 0; i != 4; ++i) {
4021 PFIndexes[i] = M[i];
4024 // Compute the index in the perfect shuffle table.
4025 unsigned PFTableIndex =
4026 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4027 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4028 unsigned Cost = (PFEntry >> 30);
4035 unsigned Imm, WhichResult;
4037 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4038 return (EltSize >= 32 ||
4039 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4040 isVREVMask(M, VT, 64) ||
4041 isVREVMask(M, VT, 32) ||
4042 isVREVMask(M, VT, 16) ||
4043 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4044 isVTBLMask(M, VT) ||
4045 isVTRNMask(M, VT, WhichResult) ||
4046 isVUZPMask(M, VT, WhichResult) ||
4047 isVZIPMask(M, VT, WhichResult) ||
4048 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4049 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4050 isVZIP_v_undef_Mask(M, VT, WhichResult));
4053 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4054 /// the specified operations to build the shuffle.
4055 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4056 SDValue RHS, SelectionDAG &DAG,
4058 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4059 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4060 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4063 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4072 OP_VUZPL, // VUZP, left result
4073 OP_VUZPR, // VUZP, right result
4074 OP_VZIPL, // VZIP, left result
4075 OP_VZIPR, // VZIP, right result
4076 OP_VTRNL, // VTRN, left result
4077 OP_VTRNR // VTRN, right result
4080 if (OpNum == OP_COPY) {
4081 if (LHSID == (1*9+2)*9+3) return LHS;
4082 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4086 SDValue OpLHS, OpRHS;
4087 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4088 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4089 EVT VT = OpLHS.getValueType();
4092 default: llvm_unreachable("Unknown shuffle opcode!");
4094 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4099 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4100 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4104 return DAG.getNode(ARMISD::VEXT, dl, VT,
4106 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4109 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4110 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4113 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4114 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4117 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4118 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4122 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4123 SmallVectorImpl<int> &ShuffleMask,
4124 SelectionDAG &DAG) {
4125 // Check to see if we can use the VTBL instruction.
4126 SDValue V1 = Op.getOperand(0);
4127 SDValue V2 = Op.getOperand(1);
4128 DebugLoc DL = Op.getDebugLoc();
4130 SmallVector<SDValue, 8> VTBLMask;
4131 for (SmallVectorImpl<int>::iterator
4132 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4133 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4135 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4136 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4137 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4140 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4141 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4145 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4146 SDValue V1 = Op.getOperand(0);
4147 SDValue V2 = Op.getOperand(1);
4148 DebugLoc dl = Op.getDebugLoc();
4149 EVT VT = Op.getValueType();
4150 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4151 SmallVector<int, 8> ShuffleMask;
4153 // Convert shuffles that are directly supported on NEON to target-specific
4154 // DAG nodes, instead of keeping them as shuffles and matching them again
4155 // during code selection. This is more efficient and avoids the possibility
4156 // of inconsistencies between legalization and selection.
4157 // FIXME: floating-point vectors should be canonicalized to integer vectors
4158 // of the same time so that they get CSEd properly.
4159 SVN->getMask(ShuffleMask);
4161 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4162 if (EltSize <= 32) {
4163 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4164 int Lane = SVN->getSplatIndex();
4165 // If this is undef splat, generate it via "just" vdup, if possible.
4166 if (Lane == -1) Lane = 0;
4168 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4169 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4171 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4172 DAG.getConstant(Lane, MVT::i32));
4177 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4180 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4181 DAG.getConstant(Imm, MVT::i32));
4184 if (isVREVMask(ShuffleMask, VT, 64))
4185 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4186 if (isVREVMask(ShuffleMask, VT, 32))
4187 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4188 if (isVREVMask(ShuffleMask, VT, 16))
4189 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4191 // Check for Neon shuffles that modify both input vectors in place.
4192 // If both results are used, i.e., if there are two shuffles with the same
4193 // source operands and with masks corresponding to both results of one of
4194 // these operations, DAG memoization will ensure that a single node is
4195 // used for both shuffles.
4196 unsigned WhichResult;
4197 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4198 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4199 V1, V2).getValue(WhichResult);
4200 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4201 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4202 V1, V2).getValue(WhichResult);
4203 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4204 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4205 V1, V2).getValue(WhichResult);
4207 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4208 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4209 V1, V1).getValue(WhichResult);
4210 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4211 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4212 V1, V1).getValue(WhichResult);
4213 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4214 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4215 V1, V1).getValue(WhichResult);
4218 // If the shuffle is not directly supported and it has 4 elements, use
4219 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4220 unsigned NumElts = VT.getVectorNumElements();
4222 unsigned PFIndexes[4];
4223 for (unsigned i = 0; i != 4; ++i) {
4224 if (ShuffleMask[i] < 0)
4227 PFIndexes[i] = ShuffleMask[i];
4230 // Compute the index in the perfect shuffle table.
4231 unsigned PFTableIndex =
4232 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4233 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4234 unsigned Cost = (PFEntry >> 30);
4237 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4240 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4241 if (EltSize >= 32) {
4242 // Do the expansion with floating-point types, since that is what the VFP
4243 // registers are defined to use, and since i64 is not legal.
4244 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4245 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4246 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4247 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4248 SmallVector<SDValue, 8> Ops;
4249 for (unsigned i = 0; i < NumElts; ++i) {
4250 if (ShuffleMask[i] < 0)
4251 Ops.push_back(DAG.getUNDEF(EltVT));
4253 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4254 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4255 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4258 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4259 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4262 if (VT == MVT::v8i8) {
4263 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4264 if (NewOp.getNode())
4271 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4272 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4273 SDValue Lane = Op.getOperand(1);
4274 if (!isa<ConstantSDNode>(Lane))
4277 SDValue Vec = Op.getOperand(0);
4278 if (Op.getValueType() == MVT::i32 &&
4279 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4280 DebugLoc dl = Op.getDebugLoc();
4281 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4287 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4288 // The only time a CONCAT_VECTORS operation can have legal types is when
4289 // two 64-bit vectors are concatenated to a 128-bit vector.
4290 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4291 "unexpected CONCAT_VECTORS");
4292 DebugLoc dl = Op.getDebugLoc();
4293 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4294 SDValue Op0 = Op.getOperand(0);
4295 SDValue Op1 = Op.getOperand(1);
4296 if (Op0.getOpcode() != ISD::UNDEF)
4297 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4298 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4299 DAG.getIntPtrConstant(0));
4300 if (Op1.getOpcode() != ISD::UNDEF)
4301 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4302 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4303 DAG.getIntPtrConstant(1));
4304 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4307 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4308 /// element has been zero/sign-extended, depending on the isSigned parameter,
4309 /// from an integer type half its size.
4310 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4312 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4313 EVT VT = N->getValueType(0);
4314 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4315 SDNode *BVN = N->getOperand(0).getNode();
4316 if (BVN->getValueType(0) != MVT::v4i32 ||
4317 BVN->getOpcode() != ISD::BUILD_VECTOR)
4319 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4320 unsigned HiElt = 1 - LoElt;
4321 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4322 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4323 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4324 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4325 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4328 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4329 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4332 if (Hi0->isNullValue() && Hi1->isNullValue())
4338 if (N->getOpcode() != ISD::BUILD_VECTOR)
4341 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4342 SDNode *Elt = N->getOperand(i).getNode();
4343 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4344 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4345 unsigned HalfSize = EltSize / 2;
4347 int64_t SExtVal = C->getSExtValue();
4348 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4351 if ((C->getZExtValue() >> HalfSize) != 0)
4362 /// isSignExtended - Check if a node is a vector value that is sign-extended
4363 /// or a constant BUILD_VECTOR with sign-extended elements.
4364 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4365 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4367 if (isExtendedBUILD_VECTOR(N, DAG, true))
4372 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4373 /// or a constant BUILD_VECTOR with zero-extended elements.
4374 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4375 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4377 if (isExtendedBUILD_VECTOR(N, DAG, false))
4382 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4383 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4384 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4385 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4386 return N->getOperand(0);
4387 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4388 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4389 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4390 LD->isNonTemporal(), LD->getAlignment());
4391 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4392 // have been legalized as a BITCAST from v4i32.
4393 if (N->getOpcode() == ISD::BITCAST) {
4394 SDNode *BVN = N->getOperand(0).getNode();
4395 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4396 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4397 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4398 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4399 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4401 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4402 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4403 EVT VT = N->getValueType(0);
4404 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4405 unsigned NumElts = VT.getVectorNumElements();
4406 MVT TruncVT = MVT::getIntegerVT(EltSize);
4407 SmallVector<SDValue, 8> Ops;
4408 for (unsigned i = 0; i != NumElts; ++i) {
4409 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4410 const APInt &CInt = C->getAPIntValue();
4411 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4413 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4414 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4417 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4418 unsigned Opcode = N->getOpcode();
4419 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4420 SDNode *N0 = N->getOperand(0).getNode();
4421 SDNode *N1 = N->getOperand(1).getNode();
4422 return N0->hasOneUse() && N1->hasOneUse() &&
4423 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4428 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4429 unsigned Opcode = N->getOpcode();
4430 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4431 SDNode *N0 = N->getOperand(0).getNode();
4432 SDNode *N1 = N->getOperand(1).getNode();
4433 return N0->hasOneUse() && N1->hasOneUse() &&
4434 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4439 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4440 // Multiplications are only custom-lowered for 128-bit vectors so that
4441 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4442 EVT VT = Op.getValueType();
4443 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4444 SDNode *N0 = Op.getOperand(0).getNode();
4445 SDNode *N1 = Op.getOperand(1).getNode();
4446 unsigned NewOpc = 0;
4448 bool isN0SExt = isSignExtended(N0, DAG);
4449 bool isN1SExt = isSignExtended(N1, DAG);
4450 if (isN0SExt && isN1SExt)
4451 NewOpc = ARMISD::VMULLs;
4453 bool isN0ZExt = isZeroExtended(N0, DAG);
4454 bool isN1ZExt = isZeroExtended(N1, DAG);
4455 if (isN0ZExt && isN1ZExt)
4456 NewOpc = ARMISD::VMULLu;
4457 else if (isN1SExt || isN1ZExt) {
4458 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4459 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4460 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4461 NewOpc = ARMISD::VMULLs;
4463 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4464 NewOpc = ARMISD::VMULLu;
4466 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4468 NewOpc = ARMISD::VMULLu;
4474 if (VT == MVT::v2i64)
4475 // Fall through to expand this. It is not legal.
4478 // Other vector multiplications are legal.
4483 // Legalize to a VMULL instruction.
4484 DebugLoc DL = Op.getDebugLoc();
4486 SDValue Op1 = SkipExtension(N1, DAG);
4488 Op0 = SkipExtension(N0, DAG);
4489 assert(Op0.getValueType().is64BitVector() &&
4490 Op1.getValueType().is64BitVector() &&
4491 "unexpected types for extended operands to VMULL");
4492 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4495 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4496 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4503 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4504 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4505 EVT Op1VT = Op1.getValueType();
4506 return DAG.getNode(N0->getOpcode(), DL, VT,
4507 DAG.getNode(NewOpc, DL, VT,
4508 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4509 DAG.getNode(NewOpc, DL, VT,
4510 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4514 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4516 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4517 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4518 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4519 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4520 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4521 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4522 // Get reciprocal estimate.
4523 // float4 recip = vrecpeq_f32(yf);
4524 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4525 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4526 // Because char has a smaller range than uchar, we can actually get away
4527 // without any newton steps. This requires that we use a weird bias
4528 // of 0xb000, however (again, this has been exhaustively tested).
4529 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4530 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4531 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4532 Y = DAG.getConstant(0xb000, MVT::i32);
4533 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4534 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4535 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4536 // Convert back to short.
4537 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4538 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4543 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4545 // Convert to float.
4546 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4547 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4548 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4549 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4550 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4551 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4553 // Use reciprocal estimate and one refinement step.
4554 // float4 recip = vrecpeq_f32(yf);
4555 // recip *= vrecpsq_f32(yf, recip);
4556 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4557 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4558 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4559 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4561 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4562 // Because short has a smaller range than ushort, we can actually get away
4563 // with only a single newton step. This requires that we use a weird bias
4564 // of 89, however (again, this has been exhaustively tested).
4565 // float4 result = as_float4(as_int4(xf*recip) + 89);
4566 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4567 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4568 N1 = DAG.getConstant(89, MVT::i32);
4569 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4570 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4571 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4572 // Convert back to integer and return.
4573 // return vmovn_s32(vcvt_s32_f32(result));
4574 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4575 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4579 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4580 EVT VT = Op.getValueType();
4581 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4582 "unexpected type for custom-lowering ISD::SDIV");
4584 DebugLoc dl = Op.getDebugLoc();
4585 SDValue N0 = Op.getOperand(0);
4586 SDValue N1 = Op.getOperand(1);
4589 if (VT == MVT::v8i8) {
4590 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4591 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4593 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4594 DAG.getIntPtrConstant(4));
4595 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4596 DAG.getIntPtrConstant(4));
4597 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4598 DAG.getIntPtrConstant(0));
4599 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4600 DAG.getIntPtrConstant(0));
4602 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4603 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4605 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4606 N0 = LowerCONCAT_VECTORS(N0, DAG);
4608 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4611 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4614 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4615 EVT VT = Op.getValueType();
4616 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4617 "unexpected type for custom-lowering ISD::UDIV");
4619 DebugLoc dl = Op.getDebugLoc();
4620 SDValue N0 = Op.getOperand(0);
4621 SDValue N1 = Op.getOperand(1);
4624 if (VT == MVT::v8i8) {
4625 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4626 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4628 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4629 DAG.getIntPtrConstant(4));
4630 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4631 DAG.getIntPtrConstant(4));
4632 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4633 DAG.getIntPtrConstant(0));
4634 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4635 DAG.getIntPtrConstant(0));
4637 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4638 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4640 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4641 N0 = LowerCONCAT_VECTORS(N0, DAG);
4643 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4644 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4649 // v4i16 sdiv ... Convert to float.
4650 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4651 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4652 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4653 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4654 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4655 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4657 // Use reciprocal estimate and two refinement steps.
4658 // float4 recip = vrecpeq_f32(yf);
4659 // recip *= vrecpsq_f32(yf, recip);
4660 // recip *= vrecpsq_f32(yf, recip);
4661 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4662 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4663 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4664 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4666 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4667 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4668 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4670 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4671 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4672 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4673 // and that it will never cause us to return an answer too large).
4674 // float4 result = as_float4(as_int4(xf*recip) + 89);
4675 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4676 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4677 N1 = DAG.getConstant(2, MVT::i32);
4678 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4679 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4680 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4681 // Convert back to integer and return.
4682 // return vmovn_u32(vcvt_s32_f32(result));
4683 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4684 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4688 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4689 switch (Op.getOpcode()) {
4690 default: llvm_unreachable("Don't know how to custom lower this!");
4691 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4692 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4693 case ISD::GlobalAddress:
4694 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4695 LowerGlobalAddressELF(Op, DAG);
4696 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4697 case ISD::SELECT: return LowerSELECT(Op, DAG);
4698 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4699 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4700 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4701 case ISD::VASTART: return LowerVASTART(Op, DAG);
4702 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4703 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4704 case ISD::SINT_TO_FP:
4705 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4706 case ISD::FP_TO_SINT:
4707 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4708 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4709 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4710 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4711 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4712 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4713 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4714 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4715 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4717 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4720 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4721 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4722 case ISD::SRL_PARTS:
4723 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4724 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4725 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4726 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4727 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4728 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4729 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4730 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4731 case ISD::MUL: return LowerMUL(Op, DAG);
4732 case ISD::SDIV: return LowerSDIV(Op, DAG);
4733 case ISD::UDIV: return LowerUDIV(Op, DAG);
4738 /// ReplaceNodeResults - Replace the results of node with an illegal result
4739 /// type with new values built out of custom code.
4740 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4741 SmallVectorImpl<SDValue>&Results,
4742 SelectionDAG &DAG) const {
4744 switch (N->getOpcode()) {
4746 llvm_unreachable("Don't know how to custom expand this!");
4749 Res = ExpandBITCAST(N, DAG);
4753 Res = Expand64BitShift(N, DAG, Subtarget);
4757 Results.push_back(Res);
4760 //===----------------------------------------------------------------------===//
4761 // ARM Scheduler Hooks
4762 //===----------------------------------------------------------------------===//
4765 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4766 MachineBasicBlock *BB,
4767 unsigned Size) const {
4768 unsigned dest = MI->getOperand(0).getReg();
4769 unsigned ptr = MI->getOperand(1).getReg();
4770 unsigned oldval = MI->getOperand(2).getReg();
4771 unsigned newval = MI->getOperand(3).getReg();
4772 unsigned scratch = BB->getParent()->getRegInfo()
4773 .createVirtualRegister(ARM::GPRRegisterClass);
4774 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4775 DebugLoc dl = MI->getDebugLoc();
4776 bool isThumb2 = Subtarget->isThumb2();
4778 unsigned ldrOpc, strOpc;
4780 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4782 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4783 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4786 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4787 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4790 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4791 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4795 MachineFunction *MF = BB->getParent();
4796 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4797 MachineFunction::iterator It = BB;
4798 ++It; // insert the new blocks after the current block
4800 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4801 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4802 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4803 MF->insert(It, loop1MBB);
4804 MF->insert(It, loop2MBB);
4805 MF->insert(It, exitMBB);
4807 // Transfer the remainder of BB and its successor edges to exitMBB.
4808 exitMBB->splice(exitMBB->begin(), BB,
4809 llvm::next(MachineBasicBlock::iterator(MI)),
4811 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4815 // fallthrough --> loop1MBB
4816 BB->addSuccessor(loop1MBB);
4819 // ldrex dest, [ptr]
4823 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4824 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4825 .addReg(dest).addReg(oldval));
4826 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4827 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4828 BB->addSuccessor(loop2MBB);
4829 BB->addSuccessor(exitMBB);
4832 // strex scratch, newval, [ptr]
4836 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4838 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4839 .addReg(scratch).addImm(0));
4840 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4841 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4842 BB->addSuccessor(loop1MBB);
4843 BB->addSuccessor(exitMBB);
4849 MI->eraseFromParent(); // The instruction is gone now.
4855 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4856 unsigned Size, unsigned BinOpcode) const {
4857 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4858 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4860 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4861 MachineFunction *MF = BB->getParent();
4862 MachineFunction::iterator It = BB;
4865 unsigned dest = MI->getOperand(0).getReg();
4866 unsigned ptr = MI->getOperand(1).getReg();
4867 unsigned incr = MI->getOperand(2).getReg();
4868 DebugLoc dl = MI->getDebugLoc();
4870 bool isThumb2 = Subtarget->isThumb2();
4871 unsigned ldrOpc, strOpc;
4873 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4875 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4876 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4879 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4880 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4883 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4884 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4888 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4889 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4890 MF->insert(It, loopMBB);
4891 MF->insert(It, exitMBB);
4893 // Transfer the remainder of BB and its successor edges to exitMBB.
4894 exitMBB->splice(exitMBB->begin(), BB,
4895 llvm::next(MachineBasicBlock::iterator(MI)),
4897 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4899 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4900 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4901 unsigned scratch2 = (!BinOpcode) ? incr :
4902 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4906 // fallthrough --> loopMBB
4907 BB->addSuccessor(loopMBB);
4911 // <binop> scratch2, dest, incr
4912 // strex scratch, scratch2, ptr
4915 // fallthrough --> exitMBB
4917 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4919 // operand order needs to go the other way for NAND
4920 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4921 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4922 addReg(incr).addReg(dest)).addReg(0);
4924 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4925 addReg(dest).addReg(incr)).addReg(0);
4928 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4930 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4931 .addReg(scratch).addImm(0));
4932 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4933 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4935 BB->addSuccessor(loopMBB);
4936 BB->addSuccessor(exitMBB);
4942 MI->eraseFromParent(); // The instruction is gone now.
4948 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4949 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4950 E = MBB->succ_end(); I != E; ++I)
4953 llvm_unreachable("Expecting a BB with two successors!");
4957 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4958 MachineBasicBlock *BB) const {
4959 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4960 DebugLoc dl = MI->getDebugLoc();
4961 bool isThumb2 = Subtarget->isThumb2();
4962 switch (MI->getOpcode()) {
4965 llvm_unreachable("Unexpected instr type to insert");
4967 case ARM::ATOMIC_LOAD_ADD_I8:
4968 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4969 case ARM::ATOMIC_LOAD_ADD_I16:
4970 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4971 case ARM::ATOMIC_LOAD_ADD_I32:
4972 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4974 case ARM::ATOMIC_LOAD_AND_I8:
4975 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4976 case ARM::ATOMIC_LOAD_AND_I16:
4977 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4978 case ARM::ATOMIC_LOAD_AND_I32:
4979 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4981 case ARM::ATOMIC_LOAD_OR_I8:
4982 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4983 case ARM::ATOMIC_LOAD_OR_I16:
4984 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4985 case ARM::ATOMIC_LOAD_OR_I32:
4986 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4988 case ARM::ATOMIC_LOAD_XOR_I8:
4989 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4990 case ARM::ATOMIC_LOAD_XOR_I16:
4991 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4992 case ARM::ATOMIC_LOAD_XOR_I32:
4993 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4995 case ARM::ATOMIC_LOAD_NAND_I8:
4996 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4997 case ARM::ATOMIC_LOAD_NAND_I16:
4998 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4999 case ARM::ATOMIC_LOAD_NAND_I32:
5000 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5002 case ARM::ATOMIC_LOAD_SUB_I8:
5003 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5004 case ARM::ATOMIC_LOAD_SUB_I16:
5005 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5006 case ARM::ATOMIC_LOAD_SUB_I32:
5007 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5009 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
5010 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
5011 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
5013 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
5014 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
5015 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
5017 case ARM::tMOVCCr_pseudo: {
5018 // To "insert" a SELECT_CC instruction, we actually have to insert the
5019 // diamond control-flow pattern. The incoming instruction knows the
5020 // destination vreg to set, the condition code register to branch on, the
5021 // true/false values to select between, and a branch opcode to use.
5022 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5023 MachineFunction::iterator It = BB;
5029 // cmpTY ccX, r1, r2
5031 // fallthrough --> copy0MBB
5032 MachineBasicBlock *thisMBB = BB;
5033 MachineFunction *F = BB->getParent();
5034 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
5035 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
5036 F->insert(It, copy0MBB);
5037 F->insert(It, sinkMBB);
5039 // Transfer the remainder of BB and its successor edges to sinkMBB.
5040 sinkMBB->splice(sinkMBB->begin(), BB,
5041 llvm::next(MachineBasicBlock::iterator(MI)),
5043 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5045 BB->addSuccessor(copy0MBB);
5046 BB->addSuccessor(sinkMBB);
5048 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
5049 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
5052 // %FalseValue = ...
5053 // # fallthrough to sinkMBB
5056 // Update machine-CFG edges
5057 BB->addSuccessor(sinkMBB);
5060 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5063 BuildMI(*BB, BB->begin(), dl,
5064 TII->get(ARM::PHI), MI->getOperand(0).getReg())
5065 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5066 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5068 MI->eraseFromParent(); // The pseudo instruction is gone now.
5073 case ARM::BCCZi64: {
5074 // If there is an unconditional branch to the other successor, remove it.
5075 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
5077 // Compare both parts that make up the double comparison separately for
5079 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
5081 unsigned LHS1 = MI->getOperand(1).getReg();
5082 unsigned LHS2 = MI->getOperand(2).getReg();
5084 AddDefaultPred(BuildMI(BB, dl,
5085 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5086 .addReg(LHS1).addImm(0));
5087 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5088 .addReg(LHS2).addImm(0)
5089 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5091 unsigned RHS1 = MI->getOperand(3).getReg();
5092 unsigned RHS2 = MI->getOperand(4).getReg();
5093 AddDefaultPred(BuildMI(BB, dl,
5094 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5095 .addReg(LHS1).addReg(RHS1));
5096 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5097 .addReg(LHS2).addReg(RHS2)
5098 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5101 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
5102 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
5103 if (MI->getOperand(0).getImm() == ARMCC::NE)
5104 std::swap(destMBB, exitMBB);
5106 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5107 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
5108 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
5111 MI->eraseFromParent(); // The pseudo instruction is gone now.
5117 //===----------------------------------------------------------------------===//
5118 // ARM Optimization Hooks
5119 //===----------------------------------------------------------------------===//
5122 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
5123 TargetLowering::DAGCombinerInfo &DCI) {
5124 SelectionDAG &DAG = DCI.DAG;
5125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5126 EVT VT = N->getValueType(0);
5127 unsigned Opc = N->getOpcode();
5128 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
5129 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
5130 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
5131 ISD::CondCode CC = ISD::SETCC_INVALID;
5134 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
5136 SDValue CCOp = Slct.getOperand(0);
5137 if (CCOp.getOpcode() == ISD::SETCC)
5138 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
5141 bool DoXform = false;
5143 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
5146 if (LHS.getOpcode() == ISD::Constant &&
5147 cast<ConstantSDNode>(LHS)->isNullValue()) {
5149 } else if (CC != ISD::SETCC_INVALID &&
5150 RHS.getOpcode() == ISD::Constant &&
5151 cast<ConstantSDNode>(RHS)->isNullValue()) {
5152 std::swap(LHS, RHS);
5153 SDValue Op0 = Slct.getOperand(0);
5154 EVT OpVT = isSlctCC ? Op0.getValueType() :
5155 Op0.getOperand(0).getValueType();
5156 bool isInt = OpVT.isInteger();
5157 CC = ISD::getSetCCInverse(CC, isInt);
5159 if (!TLI.isCondCodeLegal(CC, OpVT))
5160 return SDValue(); // Inverse operator isn't legal.
5167 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
5169 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
5170 Slct.getOperand(0), Slct.getOperand(1), CC);
5171 SDValue CCOp = Slct.getOperand(0);
5173 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
5174 CCOp.getOperand(0), CCOp.getOperand(1), CC);
5175 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
5176 CCOp, OtherOp, Result);
5181 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
5182 /// operands N0 and N1. This is a helper for PerformADDCombine that is
5183 /// called with the default operands, and if that fails, with commuted
5185 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
5186 TargetLowering::DAGCombinerInfo &DCI) {
5187 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
5188 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
5189 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
5190 if (Result.getNode()) return Result;
5195 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
5197 static SDValue PerformADDCombine(SDNode *N,
5198 TargetLowering::DAGCombinerInfo &DCI) {
5199 SDValue N0 = N->getOperand(0);
5200 SDValue N1 = N->getOperand(1);
5202 // First try with the default operand order.
5203 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
5204 if (Result.getNode())
5207 // If that didn't work, try again with the operands commuted.
5208 return PerformADDCombineWithOperands(N, N1, N0, DCI);
5211 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
5213 static SDValue PerformSUBCombine(SDNode *N,
5214 TargetLowering::DAGCombinerInfo &DCI) {
5215 SDValue N0 = N->getOperand(0);
5216 SDValue N1 = N->getOperand(1);
5218 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
5219 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
5220 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
5221 if (Result.getNode()) return Result;
5227 static SDValue PerformMULCombine(SDNode *N,
5228 TargetLowering::DAGCombinerInfo &DCI,
5229 const ARMSubtarget *Subtarget) {
5230 SelectionDAG &DAG = DCI.DAG;
5232 if (Subtarget->isThumb1Only())
5235 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5238 EVT VT = N->getValueType(0);
5242 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
5246 uint64_t MulAmt = C->getZExtValue();
5247 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
5248 ShiftAmt = ShiftAmt & (32 - 1);
5249 SDValue V = N->getOperand(0);
5250 DebugLoc DL = N->getDebugLoc();
5253 MulAmt >>= ShiftAmt;
5254 if (isPowerOf2_32(MulAmt - 1)) {
5255 // (mul x, 2^N + 1) => (add (shl x, N), x)
5256 Res = DAG.getNode(ISD::ADD, DL, VT,
5257 V, DAG.getNode(ISD::SHL, DL, VT,
5258 V, DAG.getConstant(Log2_32(MulAmt-1),
5260 } else if (isPowerOf2_32(MulAmt + 1)) {
5261 // (mul x, 2^N - 1) => (sub (shl x, N), x)
5262 Res = DAG.getNode(ISD::SUB, DL, VT,
5263 DAG.getNode(ISD::SHL, DL, VT,
5264 V, DAG.getConstant(Log2_32(MulAmt+1),
5271 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
5272 DAG.getConstant(ShiftAmt, MVT::i32));
5274 // Do not add new nodes to DAG combiner worklist.
5275 DCI.CombineTo(N, Res, false);
5279 static SDValue PerformANDCombine(SDNode *N,
5280 TargetLowering::DAGCombinerInfo &DCI) {
5282 // Attempt to use immediate-form VBIC
5283 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5284 DebugLoc dl = N->getDebugLoc();
5285 EVT VT = N->getValueType(0);
5286 SelectionDAG &DAG = DCI.DAG;
5288 APInt SplatBits, SplatUndef;
5289 unsigned SplatBitSize;
5292 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5293 if (SplatBitSize <= 64) {
5295 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
5296 SplatUndef.getZExtValue(), SplatBitSize,
5297 DAG, VbicVT, VT.is128BitVector(),
5299 if (Val.getNode()) {
5301 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
5302 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
5303 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
5311 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
5312 static SDValue PerformORCombine(SDNode *N,
5313 TargetLowering::DAGCombinerInfo &DCI,
5314 const ARMSubtarget *Subtarget) {
5315 // Attempt to use immediate-form VORR
5316 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5317 DebugLoc dl = N->getDebugLoc();
5318 EVT VT = N->getValueType(0);
5319 SelectionDAG &DAG = DCI.DAG;
5321 APInt SplatBits, SplatUndef;
5322 unsigned SplatBitSize;
5324 if (BVN && Subtarget->hasNEON() &&
5325 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5326 if (SplatBitSize <= 64) {
5328 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5329 SplatUndef.getZExtValue(), SplatBitSize,
5330 DAG, VorrVT, VT.is128BitVector(),
5332 if (Val.getNode()) {
5334 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
5335 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
5336 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
5341 SDValue N0 = N->getOperand(0);
5342 if (N0.getOpcode() != ISD::AND)
5344 SDValue N1 = N->getOperand(1);
5346 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
5347 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
5348 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
5350 unsigned SplatBitSize;
5353 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
5355 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
5356 HasAnyUndefs) && !HasAnyUndefs) {
5357 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
5359 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
5360 HasAnyUndefs) && !HasAnyUndefs &&
5361 SplatBits0 == ~SplatBits1) {
5362 // Canonicalize the vector type to make instruction selection simpler.
5363 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5364 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
5365 N0->getOperand(1), N0->getOperand(0),
5367 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
5372 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
5375 // BFI is only available on V6T2+
5376 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
5379 DebugLoc DL = N->getDebugLoc();
5380 // 1) or (and A, mask), val => ARMbfi A, val, mask
5381 // iff (val & mask) == val
5383 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5384 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
5385 // && mask == ~mask2
5386 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
5387 // && ~mask == mask2
5388 // (i.e., copy a bitfield value into another bitfield of the same width)
5393 SDValue N00 = N0.getOperand(0);
5395 // The value and the mask need to be constants so we can verify this is
5396 // actually a bitfield set. If the mask is 0xffff, we can do better
5397 // via a movt instruction, so don't use BFI in that case.
5398 SDValue MaskOp = N0.getOperand(1);
5399 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
5402 unsigned Mask = MaskC->getZExtValue();
5406 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
5407 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5409 unsigned Val = N1C->getZExtValue();
5410 if ((Val & ~Mask) != Val)
5413 if (ARM::isBitFieldInvertedMask(Mask)) {
5414 Val >>= CountTrailingZeros_32(~Mask);
5416 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
5417 DAG.getConstant(Val, MVT::i32),
5418 DAG.getConstant(Mask, MVT::i32));
5420 // Do not add new nodes to DAG combiner worklist.
5421 DCI.CombineTo(N, Res, false);
5424 } else if (N1.getOpcode() == ISD::AND) {
5425 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5426 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5429 unsigned Mask2 = N11C->getZExtValue();
5431 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
5433 if (ARM::isBitFieldInvertedMask(Mask) &&
5435 // The pack halfword instruction works better for masks that fit it,
5436 // so use that when it's available.
5437 if (Subtarget->hasT2ExtractPack() &&
5438 (Mask == 0xffff || Mask == 0xffff0000))
5441 unsigned amt = CountTrailingZeros_32(Mask2);
5442 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
5443 DAG.getConstant(amt, MVT::i32));
5444 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
5445 DAG.getConstant(Mask, MVT::i32));
5446 // Do not add new nodes to DAG combiner worklist.
5447 DCI.CombineTo(N, Res, false);
5449 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
5451 // The pack halfword instruction works better for masks that fit it,
5452 // so use that when it's available.
5453 if (Subtarget->hasT2ExtractPack() &&
5454 (Mask2 == 0xffff || Mask2 == 0xffff0000))
5457 unsigned lsb = CountTrailingZeros_32(Mask);
5458 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
5459 DAG.getConstant(lsb, MVT::i32));
5460 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
5461 DAG.getConstant(Mask2, MVT::i32));
5462 // Do not add new nodes to DAG combiner worklist.
5463 DCI.CombineTo(N, Res, false);
5468 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
5469 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
5470 ARM::isBitFieldInvertedMask(~Mask)) {
5471 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
5472 // where lsb(mask) == #shamt and masked bits of B are known zero.
5473 SDValue ShAmt = N00.getOperand(1);
5474 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5475 unsigned LSB = CountTrailingZeros_32(Mask);
5479 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
5480 DAG.getConstant(~Mask, MVT::i32));
5482 // Do not add new nodes to DAG combiner worklist.
5483 DCI.CombineTo(N, Res, false);
5489 /// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff
5491 static SDValue PerformBFICombine(SDNode *N,
5492 TargetLowering::DAGCombinerInfo &DCI) {
5493 SDValue N1 = N->getOperand(1);
5494 if (N1.getOpcode() == ISD::AND) {
5495 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5498 unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
5499 unsigned Mask2 = N11C->getZExtValue();
5500 if ((Mask & Mask2) == Mask2)
5501 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
5502 N->getOperand(0), N1.getOperand(0),
5508 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
5509 /// ARMISD::VMOVRRD.
5510 static SDValue PerformVMOVRRDCombine(SDNode *N,
5511 TargetLowering::DAGCombinerInfo &DCI) {
5512 // vmovrrd(vmovdrr x, y) -> x,y
5513 SDValue InDouble = N->getOperand(0);
5514 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
5515 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
5519 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
5520 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
5521 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
5522 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
5523 SDValue Op0 = N->getOperand(0);
5524 SDValue Op1 = N->getOperand(1);
5525 if (Op0.getOpcode() == ISD::BITCAST)
5526 Op0 = Op0.getOperand(0);
5527 if (Op1.getOpcode() == ISD::BITCAST)
5528 Op1 = Op1.getOperand(0);
5529 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
5530 Op0.getNode() == Op1.getNode() &&
5531 Op0.getResNo() == 0 && Op1.getResNo() == 1)
5532 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5533 N->getValueType(0), Op0.getOperand(0));
5537 /// PerformSTORECombine - Target-specific dag combine xforms for
5539 static SDValue PerformSTORECombine(SDNode *N,
5540 TargetLowering::DAGCombinerInfo &DCI) {
5541 // Bitcast an i64 store extracted from a vector to f64.
5542 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5543 StoreSDNode *St = cast<StoreSDNode>(N);
5544 SDValue StVal = St->getValue();
5545 if (!ISD::isNormalStore(St) || St->isVolatile() ||
5546 StVal.getValueType() != MVT::i64 ||
5547 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5550 SelectionDAG &DAG = DCI.DAG;
5551 DebugLoc dl = StVal.getDebugLoc();
5552 SDValue IntVec = StVal.getOperand(0);
5553 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5554 IntVec.getValueType().getVectorNumElements());
5555 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
5556 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5557 Vec, StVal.getOperand(1));
5558 dl = N->getDebugLoc();
5559 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
5560 // Make the DAGCombiner fold the bitcasts.
5561 DCI.AddToWorklist(Vec.getNode());
5562 DCI.AddToWorklist(ExtElt.getNode());
5563 DCI.AddToWorklist(V.getNode());
5564 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
5565 St->getPointerInfo(), St->isVolatile(),
5566 St->isNonTemporal(), St->getAlignment(),
5570 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
5571 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
5572 /// i64 vector to have f64 elements, since the value can then be loaded
5573 /// directly into a VFP register.
5574 static bool hasNormalLoadOperand(SDNode *N) {
5575 unsigned NumElts = N->getValueType(0).getVectorNumElements();
5576 for (unsigned i = 0; i < NumElts; ++i) {
5577 SDNode *Elt = N->getOperand(i).getNode();
5578 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
5584 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
5585 /// ISD::BUILD_VECTOR.
5586 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
5587 TargetLowering::DAGCombinerInfo &DCI){
5588 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
5589 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
5590 // into a pair of GPRs, which is fine when the value is used as a scalar,
5591 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
5592 SelectionDAG &DAG = DCI.DAG;
5593 if (N->getNumOperands() == 2) {
5594 SDValue RV = PerformVMOVDRRCombine(N, DAG);
5599 // Load i64 elements as f64 values so that type legalization does not split
5600 // them up into i32 values.
5601 EVT VT = N->getValueType(0);
5602 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
5604 DebugLoc dl = N->getDebugLoc();
5605 SmallVector<SDValue, 8> Ops;
5606 unsigned NumElts = VT.getVectorNumElements();
5607 for (unsigned i = 0; i < NumElts; ++i) {
5608 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
5610 // Make the DAGCombiner fold the bitcast.
5611 DCI.AddToWorklist(V.getNode());
5613 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
5614 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
5615 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
5618 /// PerformInsertEltCombine - Target-specific dag combine xforms for
5619 /// ISD::INSERT_VECTOR_ELT.
5620 static SDValue PerformInsertEltCombine(SDNode *N,
5621 TargetLowering::DAGCombinerInfo &DCI) {
5622 // Bitcast an i64 load inserted into a vector to f64.
5623 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5624 EVT VT = N->getValueType(0);
5625 SDNode *Elt = N->getOperand(1).getNode();
5626 if (VT.getVectorElementType() != MVT::i64 ||
5627 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
5630 SelectionDAG &DAG = DCI.DAG;
5631 DebugLoc dl = N->getDebugLoc();
5632 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5633 VT.getVectorNumElements());
5634 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
5635 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
5636 // Make the DAGCombiner fold the bitcasts.
5637 DCI.AddToWorklist(Vec.getNode());
5638 DCI.AddToWorklist(V.getNode());
5639 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
5640 Vec, V, N->getOperand(2));
5641 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
5644 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
5645 /// ISD::VECTOR_SHUFFLE.
5646 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
5647 // The LLVM shufflevector instruction does not require the shuffle mask
5648 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
5649 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
5650 // operands do not match the mask length, they are extended by concatenating
5651 // them with undef vectors. That is probably the right thing for other
5652 // targets, but for NEON it is better to concatenate two double-register
5653 // size vector operands into a single quad-register size vector. Do that
5654 // transformation here:
5655 // shuffle(concat(v1, undef), concat(v2, undef)) ->
5656 // shuffle(concat(v1, v2), undef)
5657 SDValue Op0 = N->getOperand(0);
5658 SDValue Op1 = N->getOperand(1);
5659 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
5660 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
5661 Op0.getNumOperands() != 2 ||
5662 Op1.getNumOperands() != 2)
5664 SDValue Concat0Op1 = Op0.getOperand(1);
5665 SDValue Concat1Op1 = Op1.getOperand(1);
5666 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
5667 Concat1Op1.getOpcode() != ISD::UNDEF)
5669 // Skip the transformation if any of the types are illegal.
5670 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5671 EVT VT = N->getValueType(0);
5672 if (!TLI.isTypeLegal(VT) ||
5673 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
5674 !TLI.isTypeLegal(Concat1Op1.getValueType()))
5677 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
5678 Op0.getOperand(0), Op1.getOperand(0));
5679 // Translate the shuffle mask.
5680 SmallVector<int, 16> NewMask;
5681 unsigned NumElts = VT.getVectorNumElements();
5682 unsigned HalfElts = NumElts/2;
5683 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
5684 for (unsigned n = 0; n < NumElts; ++n) {
5685 int MaskElt = SVN->getMaskElt(n);
5687 if (MaskElt < (int)HalfElts)
5689 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
5690 NewElt = HalfElts + MaskElt - NumElts;
5691 NewMask.push_back(NewElt);
5693 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
5694 DAG.getUNDEF(VT), NewMask.data());
5697 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
5698 /// NEON load/store intrinsics to merge base address updates.
5699 static SDValue CombineBaseUpdate(SDNode *N,
5700 TargetLowering::DAGCombinerInfo &DCI) {
5701 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5704 SelectionDAG &DAG = DCI.DAG;
5705 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
5706 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
5707 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
5708 SDValue Addr = N->getOperand(AddrOpIdx);
5710 // Search for a use of the address operand that is an increment.
5711 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
5712 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
5714 if (User->getOpcode() != ISD::ADD ||
5715 UI.getUse().getResNo() != Addr.getResNo())
5718 // Check that the add is independent of the load/store. Otherwise, folding
5719 // it would create a cycle.
5720 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
5723 // Find the new opcode for the updating load/store.
5725 bool isLaneOp = false;
5726 unsigned NewOpc = 0;
5727 unsigned NumVecs = 0;
5729 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
5731 default: assert(0 && "unexpected intrinsic for Neon base update");
5732 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
5734 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
5736 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
5738 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
5740 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
5741 NumVecs = 2; isLaneOp = true; break;
5742 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
5743 NumVecs = 3; isLaneOp = true; break;
5744 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
5745 NumVecs = 4; isLaneOp = true; break;
5746 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
5747 NumVecs = 1; isLoad = false; break;
5748 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
5749 NumVecs = 2; isLoad = false; break;
5750 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
5751 NumVecs = 3; isLoad = false; break;
5752 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
5753 NumVecs = 4; isLoad = false; break;
5754 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
5755 NumVecs = 2; isLoad = false; isLaneOp = true; break;
5756 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
5757 NumVecs = 3; isLoad = false; isLaneOp = true; break;
5758 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
5759 NumVecs = 4; isLoad = false; isLaneOp = true; break;
5763 switch (N->getOpcode()) {
5764 default: assert(0 && "unexpected opcode for Neon base update");
5765 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
5766 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
5767 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
5771 // Find the size of memory referenced by the load/store.
5774 VecTy = N->getValueType(0);
5776 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
5777 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
5779 NumBytes /= VecTy.getVectorNumElements();
5781 // If the increment is a constant, it must match the memory ref size.
5782 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
5783 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
5784 uint64_t IncVal = CInc->getZExtValue();
5785 if (IncVal != NumBytes)
5787 } else if (NumBytes >= 3 * 16) {
5788 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
5789 // separate instructions that make it harder to use a non-constant update.
5793 // Create the new updating load/store node.
5795 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
5797 for (n = 0; n < NumResultVecs; ++n)
5799 Tys[n++] = MVT::i32;
5800 Tys[n] = MVT::Other;
5801 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
5802 SmallVector<SDValue, 8> Ops;
5803 Ops.push_back(N->getOperand(0)); // incoming chain
5804 Ops.push_back(N->getOperand(AddrOpIdx));
5806 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
5807 Ops.push_back(N->getOperand(i));
5809 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
5810 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
5811 Ops.data(), Ops.size(),
5812 MemInt->getMemoryVT(),
5813 MemInt->getMemOperand());
5816 std::vector<SDValue> NewResults;
5817 for (unsigned i = 0; i < NumResultVecs; ++i) {
5818 NewResults.push_back(SDValue(UpdN.getNode(), i));
5820 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
5821 DCI.CombineTo(N, NewResults);
5822 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
5829 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
5830 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
5831 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
5833 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
5834 SelectionDAG &DAG = DCI.DAG;
5835 EVT VT = N->getValueType(0);
5836 // vldN-dup instructions only support 64-bit vectors for N > 1.
5837 if (!VT.is64BitVector())
5840 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
5841 SDNode *VLD = N->getOperand(0).getNode();
5842 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
5844 unsigned NumVecs = 0;
5845 unsigned NewOpc = 0;
5846 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
5847 if (IntNo == Intrinsic::arm_neon_vld2lane) {
5849 NewOpc = ARMISD::VLD2DUP;
5850 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
5852 NewOpc = ARMISD::VLD3DUP;
5853 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
5855 NewOpc = ARMISD::VLD4DUP;
5860 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
5861 // numbers match the load.
5862 unsigned VLDLaneNo =
5863 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
5864 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
5866 // Ignore uses of the chain result.
5867 if (UI.getUse().getResNo() == NumVecs)
5870 if (User->getOpcode() != ARMISD::VDUPLANE ||
5871 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
5875 // Create the vldN-dup node.
5878 for (n = 0; n < NumVecs; ++n)
5880 Tys[n] = MVT::Other;
5881 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
5882 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
5883 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
5884 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
5885 Ops, 2, VLDMemInt->getMemoryVT(),
5886 VLDMemInt->getMemOperand());
5889 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
5891 unsigned ResNo = UI.getUse().getResNo();
5892 // Ignore uses of the chain result.
5893 if (ResNo == NumVecs)
5896 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
5899 // Now the vldN-lane intrinsic is dead except for its chain result.
5900 // Update uses of the chain.
5901 std::vector<SDValue> VLDDupResults;
5902 for (unsigned n = 0; n < NumVecs; ++n)
5903 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
5904 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
5905 DCI.CombineTo(VLD, VLDDupResults);
5910 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
5911 /// ARMISD::VDUPLANE.
5912 static SDValue PerformVDUPLANECombine(SDNode *N,
5913 TargetLowering::DAGCombinerInfo &DCI) {
5914 SDValue Op = N->getOperand(0);
5916 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
5917 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
5918 if (CombineVLDDUP(N, DCI))
5919 return SDValue(N, 0);
5921 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
5922 // redundant. Ignore bit_converts for now; element sizes are checked below.
5923 while (Op.getOpcode() == ISD::BITCAST)
5924 Op = Op.getOperand(0);
5925 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
5928 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
5929 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
5930 // The canonical VMOV for a zero vector uses a 32-bit element size.
5931 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5933 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
5935 EVT VT = N->getValueType(0);
5936 if (EltSize > VT.getVectorElementType().getSizeInBits())
5939 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
5942 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5943 /// operand of a vector shift operation, where all the elements of the
5944 /// build_vector must have the same constant integer value.
5945 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5946 // Ignore bit_converts.
5947 while (Op.getOpcode() == ISD::BITCAST)
5948 Op = Op.getOperand(0);
5949 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5950 APInt SplatBits, SplatUndef;
5951 unsigned SplatBitSize;
5953 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5954 HasAnyUndefs, ElementBits) ||
5955 SplatBitSize > ElementBits)
5957 Cnt = SplatBits.getSExtValue();
5961 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5962 /// operand of a vector shift left operation. That value must be in the range:
5963 /// 0 <= Value < ElementBits for a left shift; or
5964 /// 0 <= Value <= ElementBits for a long left shift.
5965 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5966 assert(VT.isVector() && "vector shift count is not a vector type");
5967 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5968 if (! getVShiftImm(Op, ElementBits, Cnt))
5970 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
5973 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5974 /// operand of a vector shift right operation. For a shift opcode, the value
5975 /// is positive, but for an intrinsic the value count must be negative. The
5976 /// absolute value must be in the range:
5977 /// 1 <= |Value| <= ElementBits for a right shift; or
5978 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5979 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5981 assert(VT.isVector() && "vector shift count is not a vector type");
5982 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5983 if (! getVShiftImm(Op, ElementBits, Cnt))
5987 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
5990 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
5991 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
5992 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5995 // Don't do anything for most intrinsics.
5998 // Vector shifts: check for immediate versions and lower them.
5999 // Note: This is done during DAG combining instead of DAG legalizing because
6000 // the build_vectors for 64-bit vector element shift counts are generally
6001 // not legal, and it is hard to see their values after they get legalized to
6002 // loads from a constant pool.
6003 case Intrinsic::arm_neon_vshifts:
6004 case Intrinsic::arm_neon_vshiftu:
6005 case Intrinsic::arm_neon_vshiftls:
6006 case Intrinsic::arm_neon_vshiftlu:
6007 case Intrinsic::arm_neon_vshiftn:
6008 case Intrinsic::arm_neon_vrshifts:
6009 case Intrinsic::arm_neon_vrshiftu:
6010 case Intrinsic::arm_neon_vrshiftn:
6011 case Intrinsic::arm_neon_vqshifts:
6012 case Intrinsic::arm_neon_vqshiftu:
6013 case Intrinsic::arm_neon_vqshiftsu:
6014 case Intrinsic::arm_neon_vqshiftns:
6015 case Intrinsic::arm_neon_vqshiftnu:
6016 case Intrinsic::arm_neon_vqshiftnsu:
6017 case Intrinsic::arm_neon_vqrshiftns:
6018 case Intrinsic::arm_neon_vqrshiftnu:
6019 case Intrinsic::arm_neon_vqrshiftnsu: {
6020 EVT VT = N->getOperand(1).getValueType();
6022 unsigned VShiftOpc = 0;
6025 case Intrinsic::arm_neon_vshifts:
6026 case Intrinsic::arm_neon_vshiftu:
6027 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
6028 VShiftOpc = ARMISD::VSHL;
6031 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
6032 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
6033 ARMISD::VSHRs : ARMISD::VSHRu);
6038 case Intrinsic::arm_neon_vshiftls:
6039 case Intrinsic::arm_neon_vshiftlu:
6040 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
6042 llvm_unreachable("invalid shift count for vshll intrinsic");
6044 case Intrinsic::arm_neon_vrshifts:
6045 case Intrinsic::arm_neon_vrshiftu:
6046 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
6050 case Intrinsic::arm_neon_vqshifts:
6051 case Intrinsic::arm_neon_vqshiftu:
6052 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6056 case Intrinsic::arm_neon_vqshiftsu:
6057 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6059 llvm_unreachable("invalid shift count for vqshlu intrinsic");
6061 case Intrinsic::arm_neon_vshiftn:
6062 case Intrinsic::arm_neon_vrshiftn:
6063 case Intrinsic::arm_neon_vqshiftns:
6064 case Intrinsic::arm_neon_vqshiftnu:
6065 case Intrinsic::arm_neon_vqshiftnsu:
6066 case Intrinsic::arm_neon_vqrshiftns:
6067 case Intrinsic::arm_neon_vqrshiftnu:
6068 case Intrinsic::arm_neon_vqrshiftnsu:
6069 // Narrowing shifts require an immediate right shift.
6070 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
6072 llvm_unreachable("invalid shift count for narrowing vector shift "
6076 llvm_unreachable("unhandled vector shift");
6080 case Intrinsic::arm_neon_vshifts:
6081 case Intrinsic::arm_neon_vshiftu:
6082 // Opcode already set above.
6084 case Intrinsic::arm_neon_vshiftls:
6085 case Intrinsic::arm_neon_vshiftlu:
6086 if (Cnt == VT.getVectorElementType().getSizeInBits())
6087 VShiftOpc = ARMISD::VSHLLi;
6089 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
6090 ARMISD::VSHLLs : ARMISD::VSHLLu);
6092 case Intrinsic::arm_neon_vshiftn:
6093 VShiftOpc = ARMISD::VSHRN; break;
6094 case Intrinsic::arm_neon_vrshifts:
6095 VShiftOpc = ARMISD::VRSHRs; break;
6096 case Intrinsic::arm_neon_vrshiftu:
6097 VShiftOpc = ARMISD::VRSHRu; break;
6098 case Intrinsic::arm_neon_vrshiftn:
6099 VShiftOpc = ARMISD::VRSHRN; break;
6100 case Intrinsic::arm_neon_vqshifts:
6101 VShiftOpc = ARMISD::VQSHLs; break;
6102 case Intrinsic::arm_neon_vqshiftu:
6103 VShiftOpc = ARMISD::VQSHLu; break;
6104 case Intrinsic::arm_neon_vqshiftsu:
6105 VShiftOpc = ARMISD::VQSHLsu; break;
6106 case Intrinsic::arm_neon_vqshiftns:
6107 VShiftOpc = ARMISD::VQSHRNs; break;
6108 case Intrinsic::arm_neon_vqshiftnu:
6109 VShiftOpc = ARMISD::VQSHRNu; break;
6110 case Intrinsic::arm_neon_vqshiftnsu:
6111 VShiftOpc = ARMISD::VQSHRNsu; break;
6112 case Intrinsic::arm_neon_vqrshiftns:
6113 VShiftOpc = ARMISD::VQRSHRNs; break;
6114 case Intrinsic::arm_neon_vqrshiftnu:
6115 VShiftOpc = ARMISD::VQRSHRNu; break;
6116 case Intrinsic::arm_neon_vqrshiftnsu:
6117 VShiftOpc = ARMISD::VQRSHRNsu; break;
6120 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6121 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
6124 case Intrinsic::arm_neon_vshiftins: {
6125 EVT VT = N->getOperand(1).getValueType();
6127 unsigned VShiftOpc = 0;
6129 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
6130 VShiftOpc = ARMISD::VSLI;
6131 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
6132 VShiftOpc = ARMISD::VSRI;
6134 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
6137 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6138 N->getOperand(1), N->getOperand(2),
6139 DAG.getConstant(Cnt, MVT::i32));
6142 case Intrinsic::arm_neon_vqrshifts:
6143 case Intrinsic::arm_neon_vqrshiftu:
6144 // No immediate versions of these to check for.
6151 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
6152 /// lowers them. As with the vector shift intrinsics, this is done during DAG
6153 /// combining instead of DAG legalizing because the build_vectors for 64-bit
6154 /// vector element shift counts are generally not legal, and it is hard to see
6155 /// their values after they get legalized to loads from a constant pool.
6156 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
6157 const ARMSubtarget *ST) {
6158 EVT VT = N->getValueType(0);
6160 // Nothing to be done for scalar shifts.
6161 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6162 if (!VT.isVector() || !TLI.isTypeLegal(VT))
6165 assert(ST->hasNEON() && "unexpected vector shift");
6168 switch (N->getOpcode()) {
6169 default: llvm_unreachable("unexpected shift opcode");
6172 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
6173 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
6174 DAG.getConstant(Cnt, MVT::i32));
6179 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
6180 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
6181 ARMISD::VSHRs : ARMISD::VSHRu);
6182 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
6183 DAG.getConstant(Cnt, MVT::i32));
6189 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
6190 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
6191 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
6192 const ARMSubtarget *ST) {
6193 SDValue N0 = N->getOperand(0);
6195 // Check for sign- and zero-extensions of vector extract operations of 8-
6196 // and 16-bit vector elements. NEON supports these directly. They are
6197 // handled during DAG combining because type legalization will promote them
6198 // to 32-bit types and it is messy to recognize the operations after that.
6199 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6200 SDValue Vec = N0.getOperand(0);
6201 SDValue Lane = N0.getOperand(1);
6202 EVT VT = N->getValueType(0);
6203 EVT EltVT = N0.getValueType();
6204 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6206 if (VT == MVT::i32 &&
6207 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
6208 TLI.isTypeLegal(Vec.getValueType()) &&
6209 isa<ConstantSDNode>(Lane)) {
6212 switch (N->getOpcode()) {
6213 default: llvm_unreachable("unexpected opcode");
6214 case ISD::SIGN_EXTEND:
6215 Opc = ARMISD::VGETLANEs;
6217 case ISD::ZERO_EXTEND:
6218 case ISD::ANY_EXTEND:
6219 Opc = ARMISD::VGETLANEu;
6222 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
6229 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
6230 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
6231 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
6232 const ARMSubtarget *ST) {
6233 // If the target supports NEON, try to use vmax/vmin instructions for f32
6234 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
6235 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
6236 // a NaN; only do the transformation when it matches that behavior.
6238 // For now only do this when using NEON for FP operations; if using VFP, it
6239 // is not obvious that the benefit outweighs the cost of switching to the
6241 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
6242 N->getValueType(0) != MVT::f32)
6245 SDValue CondLHS = N->getOperand(0);
6246 SDValue CondRHS = N->getOperand(1);
6247 SDValue LHS = N->getOperand(2);
6248 SDValue RHS = N->getOperand(3);
6249 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
6251 unsigned Opcode = 0;
6253 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
6254 IsReversed = false; // x CC y ? x : y
6255 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
6256 IsReversed = true ; // x CC y ? y : x
6270 // If LHS is NaN, an ordered comparison will be false and the result will
6271 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
6272 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6273 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
6274 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6276 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
6277 // will return -0, so vmin can only be used for unsafe math or if one of
6278 // the operands is known to be nonzero.
6279 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
6281 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6283 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
6292 // If LHS is NaN, an ordered comparison will be false and the result will
6293 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
6294 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6295 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
6296 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6298 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
6299 // will return +0, so vmax can only be used for unsafe math or if one of
6300 // the operands is known to be nonzero.
6301 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
6303 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6305 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
6311 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
6314 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
6315 DAGCombinerInfo &DCI) const {
6316 switch (N->getOpcode()) {
6318 case ISD::ADD: return PerformADDCombine(N, DCI);
6319 case ISD::SUB: return PerformSUBCombine(N, DCI);
6320 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
6321 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
6322 case ISD::AND: return PerformANDCombine(N, DCI);
6323 case ARMISD::BFI: return PerformBFICombine(N, DCI);
6324 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
6325 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
6326 case ISD::STORE: return PerformSTORECombine(N, DCI);
6327 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
6328 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
6329 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
6330 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
6331 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
6334 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
6335 case ISD::SIGN_EXTEND:
6336 case ISD::ZERO_EXTEND:
6337 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
6338 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
6339 case ARMISD::VLD2DUP:
6340 case ARMISD::VLD3DUP:
6341 case ARMISD::VLD4DUP:
6342 return CombineBaseUpdate(N, DCI);
6343 case ISD::INTRINSIC_VOID:
6344 case ISD::INTRINSIC_W_CHAIN:
6345 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
6346 case Intrinsic::arm_neon_vld1:
6347 case Intrinsic::arm_neon_vld2:
6348 case Intrinsic::arm_neon_vld3:
6349 case Intrinsic::arm_neon_vld4:
6350 case Intrinsic::arm_neon_vld2lane:
6351 case Intrinsic::arm_neon_vld3lane:
6352 case Intrinsic::arm_neon_vld4lane:
6353 case Intrinsic::arm_neon_vst1:
6354 case Intrinsic::arm_neon_vst2:
6355 case Intrinsic::arm_neon_vst3:
6356 case Intrinsic::arm_neon_vst4:
6357 case Intrinsic::arm_neon_vst2lane:
6358 case Intrinsic::arm_neon_vst3lane:
6359 case Intrinsic::arm_neon_vst4lane:
6360 return CombineBaseUpdate(N, DCI);
6368 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
6370 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
6373 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
6374 if (!Subtarget->allowsUnalignedMem())
6377 switch (VT.getSimpleVT().SimpleTy) {
6384 // FIXME: VLD1 etc with standard alignment is legal.
6388 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
6393 switch (VT.getSimpleVT().SimpleTy) {
6394 default: return false;
6409 if ((V & (Scale - 1)) != 0)
6412 return V == (V & ((1LL << 5) - 1));
6415 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
6416 const ARMSubtarget *Subtarget) {
6423 switch (VT.getSimpleVT().SimpleTy) {
6424 default: return false;
6429 // + imm12 or - imm8
6431 return V == (V & ((1LL << 8) - 1));
6432 return V == (V & ((1LL << 12) - 1));
6435 // Same as ARM mode. FIXME: NEON?
6436 if (!Subtarget->hasVFP2())
6441 return V == (V & ((1LL << 8) - 1));
6445 /// isLegalAddressImmediate - Return true if the integer value can be used
6446 /// as the offset of the target addressing mode for load / store of the
6448 static bool isLegalAddressImmediate(int64_t V, EVT VT,
6449 const ARMSubtarget *Subtarget) {
6456 if (Subtarget->isThumb1Only())
6457 return isLegalT1AddressImmediate(V, VT);
6458 else if (Subtarget->isThumb2())
6459 return isLegalT2AddressImmediate(V, VT, Subtarget);
6464 switch (VT.getSimpleVT().SimpleTy) {
6465 default: return false;
6470 return V == (V & ((1LL << 12) - 1));
6473 return V == (V & ((1LL << 8) - 1));
6476 if (!Subtarget->hasVFP2()) // FIXME: NEON?
6481 return V == (V & ((1LL << 8) - 1));
6485 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
6487 int Scale = AM.Scale;
6491 switch (VT.getSimpleVT().SimpleTy) {
6492 default: return false;
6501 return Scale == 2 || Scale == 4 || Scale == 8;
6504 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6508 // Note, we allow "void" uses (basically, uses that aren't loads or
6509 // stores), because arm allows folding a scale into many arithmetic
6510 // operations. This should be made more precise and revisited later.
6512 // Allow r << imm, but the imm has to be a multiple of two.
6513 if (Scale & 1) return false;
6514 return isPowerOf2_32(Scale);
6518 /// isLegalAddressingMode - Return true if the addressing mode represented
6519 /// by AM is legal for this target, for a load/store of the specified type.
6520 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
6521 const Type *Ty) const {
6522 EVT VT = getValueType(Ty, true);
6523 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
6526 // Can never fold addr of global into load/store.
6531 case 0: // no scale reg, must be "r+i" or "r", or "i".
6534 if (Subtarget->isThumb1Only())
6538 // ARM doesn't support any R+R*scale+imm addr modes.
6545 if (Subtarget->isThumb2())
6546 return isLegalT2ScaledAddressingMode(AM, VT);
6548 int Scale = AM.Scale;
6549 switch (VT.getSimpleVT().SimpleTy) {
6550 default: return false;
6554 if (Scale < 0) Scale = -Scale;
6558 return isPowerOf2_32(Scale & ~1);
6562 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6567 // Note, we allow "void" uses (basically, uses that aren't loads or
6568 // stores), because arm allows folding a scale into many arithmetic
6569 // operations. This should be made more precise and revisited later.
6571 // Allow r << imm, but the imm has to be a multiple of two.
6572 if (Scale & 1) return false;
6573 return isPowerOf2_32(Scale);
6580 /// isLegalICmpImmediate - Return true if the specified immediate is legal
6581 /// icmp immediate, that is the target has icmp instructions which can compare
6582 /// a register against the immediate without having to materialize the
6583 /// immediate into a register.
6584 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
6585 if (!Subtarget->isThumb())
6586 return ARM_AM::getSOImmVal(Imm) != -1;
6587 if (Subtarget->isThumb2())
6588 return ARM_AM::getT2SOImmVal(Imm) != -1;
6589 return Imm >= 0 && Imm <= 255;
6592 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
6593 bool isSEXTLoad, SDValue &Base,
6594 SDValue &Offset, bool &isInc,
6595 SelectionDAG &DAG) {
6596 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
6599 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
6601 Base = Ptr->getOperand(0);
6602 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6603 int RHSC = (int)RHS->getZExtValue();
6604 if (RHSC < 0 && RHSC > -256) {
6605 assert(Ptr->getOpcode() == ISD::ADD);
6607 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6611 isInc = (Ptr->getOpcode() == ISD::ADD);
6612 Offset = Ptr->getOperand(1);
6614 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
6616 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6617 int RHSC = (int)RHS->getZExtValue();
6618 if (RHSC < 0 && RHSC > -0x1000) {
6619 assert(Ptr->getOpcode() == ISD::ADD);
6621 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6622 Base = Ptr->getOperand(0);
6627 if (Ptr->getOpcode() == ISD::ADD) {
6629 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
6630 if (ShOpcVal != ARM_AM::no_shift) {
6631 Base = Ptr->getOperand(1);
6632 Offset = Ptr->getOperand(0);
6634 Base = Ptr->getOperand(0);
6635 Offset = Ptr->getOperand(1);
6640 isInc = (Ptr->getOpcode() == ISD::ADD);
6641 Base = Ptr->getOperand(0);
6642 Offset = Ptr->getOperand(1);
6646 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
6650 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
6651 bool isSEXTLoad, SDValue &Base,
6652 SDValue &Offset, bool &isInc,
6653 SelectionDAG &DAG) {
6654 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
6657 Base = Ptr->getOperand(0);
6658 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6659 int RHSC = (int)RHS->getZExtValue();
6660 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
6661 assert(Ptr->getOpcode() == ISD::ADD);
6663 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6665 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
6666 isInc = Ptr->getOpcode() == ISD::ADD;
6667 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
6675 /// getPreIndexedAddressParts - returns true by value, base pointer and
6676 /// offset pointer and addressing mode by reference if the node's address
6677 /// can be legally represented as pre-indexed load / store address.
6679 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
6681 ISD::MemIndexedMode &AM,
6682 SelectionDAG &DAG) const {
6683 if (Subtarget->isThumb1Only())
6688 bool isSEXTLoad = false;
6689 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6690 Ptr = LD->getBasePtr();
6691 VT = LD->getMemoryVT();
6692 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
6693 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6694 Ptr = ST->getBasePtr();
6695 VT = ST->getMemoryVT();
6700 bool isLegal = false;
6701 if (Subtarget->isThumb2())
6702 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6703 Offset, isInc, DAG);
6705 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6706 Offset, isInc, DAG);
6710 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
6714 /// getPostIndexedAddressParts - returns true by value, base pointer and
6715 /// offset pointer and addressing mode by reference if this node can be
6716 /// combined with a load / store to form a post-indexed load / store.
6717 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
6720 ISD::MemIndexedMode &AM,
6721 SelectionDAG &DAG) const {
6722 if (Subtarget->isThumb1Only())
6727 bool isSEXTLoad = false;
6728 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6729 VT = LD->getMemoryVT();
6730 Ptr = LD->getBasePtr();
6731 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
6732 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6733 VT = ST->getMemoryVT();
6734 Ptr = ST->getBasePtr();
6739 bool isLegal = false;
6740 if (Subtarget->isThumb2())
6741 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6744 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6750 // Swap base ptr and offset to catch more post-index load / store when
6751 // it's legal. In Thumb2 mode, offset must be an immediate.
6752 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
6753 !Subtarget->isThumb2())
6754 std::swap(Base, Offset);
6756 // Post-indexed load / store update the base pointer.
6761 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
6765 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6769 const SelectionDAG &DAG,
6770 unsigned Depth) const {
6771 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
6772 switch (Op.getOpcode()) {
6774 case ARMISD::CMOV: {
6775 // Bits are known zero/one if known on the LHS and RHS.
6776 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
6777 if (KnownZero == 0 && KnownOne == 0) return;
6779 APInt KnownZeroRHS, KnownOneRHS;
6780 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
6781 KnownZeroRHS, KnownOneRHS, Depth+1);
6782 KnownZero &= KnownZeroRHS;
6783 KnownOne &= KnownOneRHS;
6789 //===----------------------------------------------------------------------===//
6790 // ARM Inline Assembly Support
6791 //===----------------------------------------------------------------------===//
6793 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
6794 // Looking for "rev" which is V6+.
6795 if (!Subtarget->hasV6Ops())
6798 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
6799 std::string AsmStr = IA->getAsmString();
6800 SmallVector<StringRef, 4> AsmPieces;
6801 SplitString(AsmStr, AsmPieces, ";\n");
6803 switch (AsmPieces.size()) {
6804 default: return false;
6806 AsmStr = AsmPieces[0];
6808 SplitString(AsmStr, AsmPieces, " \t,");
6811 if (AsmPieces.size() == 3 &&
6812 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
6813 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
6814 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
6815 if (Ty && Ty->getBitWidth() == 32)
6816 return IntrinsicLowering::LowerToByteSwap(CI);
6824 /// getConstraintType - Given a constraint letter, return the type of
6825 /// constraint it is for this target.
6826 ARMTargetLowering::ConstraintType
6827 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
6828 if (Constraint.size() == 1) {
6829 switch (Constraint[0]) {
6831 case 'l': return C_RegisterClass;
6832 case 'w': return C_RegisterClass;
6835 return TargetLowering::getConstraintType(Constraint);
6838 /// Examine constraint type and operand type and determine a weight value.
6839 /// This object must already have been set up with the operand type
6840 /// and the current alternative constraint selected.
6841 TargetLowering::ConstraintWeight
6842 ARMTargetLowering::getSingleConstraintMatchWeight(
6843 AsmOperandInfo &info, const char *constraint) const {
6844 ConstraintWeight weight = CW_Invalid;
6845 Value *CallOperandVal = info.CallOperandVal;
6846 // If we don't have a value, we can't do a match,
6847 // but allow it at the lowest weight.
6848 if (CallOperandVal == NULL)
6850 const Type *type = CallOperandVal->getType();
6851 // Look at the constraint type.
6852 switch (*constraint) {
6854 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
6857 if (type->isIntegerTy()) {
6858 if (Subtarget->isThumb())
6859 weight = CW_SpecificReg;
6861 weight = CW_Register;
6865 if (type->isFloatingPointTy())
6866 weight = CW_Register;
6872 std::pair<unsigned, const TargetRegisterClass*>
6873 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6875 if (Constraint.size() == 1) {
6876 // GCC ARM Constraint Letters
6877 switch (Constraint[0]) {
6879 if (Subtarget->isThumb())
6880 return std::make_pair(0U, ARM::tGPRRegisterClass);
6882 return std::make_pair(0U, ARM::GPRRegisterClass);
6884 return std::make_pair(0U, ARM::GPRRegisterClass);
6887 return std::make_pair(0U, ARM::SPRRegisterClass);
6888 if (VT.getSizeInBits() == 64)
6889 return std::make_pair(0U, ARM::DPRRegisterClass);
6890 if (VT.getSizeInBits() == 128)
6891 return std::make_pair(0U, ARM::QPRRegisterClass);
6895 if (StringRef("{cc}").equals_lower(Constraint))
6896 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
6898 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6901 std::vector<unsigned> ARMTargetLowering::
6902 getRegClassForInlineAsmConstraint(const std::string &Constraint,
6904 if (Constraint.size() != 1)
6905 return std::vector<unsigned>();
6907 switch (Constraint[0]) { // GCC ARM Constraint Letters
6910 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
6911 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
6914 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
6915 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
6916 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
6917 ARM::R12, ARM::LR, 0);
6920 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
6921 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
6922 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
6923 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
6924 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
6925 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
6926 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
6927 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
6928 if (VT.getSizeInBits() == 64)
6929 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
6930 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
6931 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
6932 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
6933 if (VT.getSizeInBits() == 128)
6934 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
6935 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
6939 return std::vector<unsigned>();
6942 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6943 /// vector. If it is invalid, don't add anything to Ops.
6944 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
6946 std::vector<SDValue>&Ops,
6947 SelectionDAG &DAG) const {
6948 SDValue Result(0, 0);
6950 switch (Constraint) {
6952 case 'I': case 'J': case 'K': case 'L':
6953 case 'M': case 'N': case 'O':
6954 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
6958 int64_t CVal64 = C->getSExtValue();
6959 int CVal = (int) CVal64;
6960 // None of these constraints allow values larger than 32 bits. Check
6961 // that the value fits in an int.
6965 switch (Constraint) {
6967 if (Subtarget->isThumb1Only()) {
6968 // This must be a constant between 0 and 255, for ADD
6970 if (CVal >= 0 && CVal <= 255)
6972 } else if (Subtarget->isThumb2()) {
6973 // A constant that can be used as an immediate value in a
6974 // data-processing instruction.
6975 if (ARM_AM::getT2SOImmVal(CVal) != -1)
6978 // A constant that can be used as an immediate value in a
6979 // data-processing instruction.
6980 if (ARM_AM::getSOImmVal(CVal) != -1)
6986 if (Subtarget->isThumb()) { // FIXME thumb2
6987 // This must be a constant between -255 and -1, for negated ADD
6988 // immediates. This can be used in GCC with an "n" modifier that
6989 // prints the negated value, for use with SUB instructions. It is
6990 // not useful otherwise but is implemented for compatibility.
6991 if (CVal >= -255 && CVal <= -1)
6994 // This must be a constant between -4095 and 4095. It is not clear
6995 // what this constraint is intended for. Implemented for
6996 // compatibility with GCC.
6997 if (CVal >= -4095 && CVal <= 4095)
7003 if (Subtarget->isThumb1Only()) {
7004 // A 32-bit value where only one byte has a nonzero value. Exclude
7005 // zero to match GCC. This constraint is used by GCC internally for
7006 // constants that can be loaded with a move/shift combination.
7007 // It is not useful otherwise but is implemented for compatibility.
7008 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
7010 } else if (Subtarget->isThumb2()) {
7011 // A constant whose bitwise inverse can be used as an immediate
7012 // value in a data-processing instruction. This can be used in GCC
7013 // with a "B" modifier that prints the inverted value, for use with
7014 // BIC and MVN instructions. It is not useful otherwise but is
7015 // implemented for compatibility.
7016 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
7019 // A constant whose bitwise inverse can be used as an immediate
7020 // value in a data-processing instruction. This can be used in GCC
7021 // with a "B" modifier that prints the inverted value, for use with
7022 // BIC and MVN instructions. It is not useful otherwise but is
7023 // implemented for compatibility.
7024 if (ARM_AM::getSOImmVal(~CVal) != -1)
7030 if (Subtarget->isThumb1Only()) {
7031 // This must be a constant between -7 and 7,
7032 // for 3-operand ADD/SUB immediate instructions.
7033 if (CVal >= -7 && CVal < 7)
7035 } else if (Subtarget->isThumb2()) {
7036 // A constant whose negation can be used as an immediate value in a
7037 // data-processing instruction. This can be used in GCC with an "n"
7038 // modifier that prints the negated value, for use with SUB
7039 // instructions. It is not useful otherwise but is implemented for
7041 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
7044 // A constant whose negation can be used as an immediate value in a
7045 // data-processing instruction. This can be used in GCC with an "n"
7046 // modifier that prints the negated value, for use with SUB
7047 // instructions. It is not useful otherwise but is implemented for
7049 if (ARM_AM::getSOImmVal(-CVal) != -1)
7055 if (Subtarget->isThumb()) { // FIXME thumb2
7056 // This must be a multiple of 4 between 0 and 1020, for
7057 // ADD sp + immediate.
7058 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
7061 // A power of two or a constant between 0 and 32. This is used in
7062 // GCC for the shift amount on shifted register operands, but it is
7063 // useful in general for any shift amounts.
7064 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
7070 if (Subtarget->isThumb()) { // FIXME thumb2
7071 // This must be a constant between 0 and 31, for shift amounts.
7072 if (CVal >= 0 && CVal <= 31)
7078 if (Subtarget->isThumb()) { // FIXME thumb2
7079 // This must be a multiple of 4 between -508 and 508, for
7080 // ADD/SUB sp = sp + immediate.
7081 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
7086 Result = DAG.getTargetConstant(CVal, Op.getValueType());
7090 if (Result.getNode()) {
7091 Ops.push_back(Result);
7094 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7098 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7099 // The ARM target isn't yet aware of offsets.
7103 int ARM::getVFPf32Imm(const APFloat &FPImm) {
7104 APInt Imm = FPImm.bitcastToAPInt();
7105 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
7106 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
7107 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
7109 // We can handle 4 bits of mantissa.
7110 // mantissa = (16+UInt(e:f:g:h))/16.
7111 if (Mantissa & 0x7ffff)
7114 if ((Mantissa & 0xf) != Mantissa)
7117 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7118 if (Exp < -3 || Exp > 4)
7120 Exp = ((Exp+3) & 0x7) ^ 4;
7122 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7125 int ARM::getVFPf64Imm(const APFloat &FPImm) {
7126 APInt Imm = FPImm.bitcastToAPInt();
7127 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
7128 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
7129 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
7131 // We can handle 4 bits of mantissa.
7132 // mantissa = (16+UInt(e:f:g:h))/16.
7133 if (Mantissa & 0xffffffffffffLL)
7136 if ((Mantissa & 0xf) != Mantissa)
7139 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7140 if (Exp < -3 || Exp > 4)
7142 Exp = ((Exp+3) & 0x7) ^ 4;
7144 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7147 bool ARM::isBitFieldInvertedMask(unsigned v) {
7148 if (v == 0xffffffff)
7150 // there can be 1's on either or both "outsides", all the "inside"
7152 unsigned int lsb = 0, msb = 31;
7153 while (v & (1 << msb)) --msb;
7154 while (v & (1 << lsb)) ++lsb;
7155 for (unsigned int i = lsb; i <= msb; ++i) {
7162 /// isFPImmLegal - Returns true if the target can instruction select the
7163 /// specified FP immediate natively. If false, the legalizer will
7164 /// materialize the FP immediate as a load from a constant pool.
7165 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
7166 if (!Subtarget->hasVFP3())
7169 return ARM::getVFPf32Imm(Imm) != -1;
7171 return ARM::getVFPf64Imm(Imm) != -1;
7175 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
7176 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
7177 /// specified in the intrinsic calls.
7178 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
7180 unsigned Intrinsic) const {
7181 switch (Intrinsic) {
7182 case Intrinsic::arm_neon_vld1:
7183 case Intrinsic::arm_neon_vld2:
7184 case Intrinsic::arm_neon_vld3:
7185 case Intrinsic::arm_neon_vld4:
7186 case Intrinsic::arm_neon_vld2lane:
7187 case Intrinsic::arm_neon_vld3lane:
7188 case Intrinsic::arm_neon_vld4lane: {
7189 Info.opc = ISD::INTRINSIC_W_CHAIN;
7190 // Conservatively set memVT to the entire set of vectors loaded.
7191 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
7192 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7193 Info.ptrVal = I.getArgOperand(0);
7195 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7196 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7197 Info.vol = false; // volatile loads with NEON intrinsics not supported
7198 Info.readMem = true;
7199 Info.writeMem = false;
7202 case Intrinsic::arm_neon_vst1:
7203 case Intrinsic::arm_neon_vst2:
7204 case Intrinsic::arm_neon_vst3:
7205 case Intrinsic::arm_neon_vst4:
7206 case Intrinsic::arm_neon_vst2lane:
7207 case Intrinsic::arm_neon_vst3lane:
7208 case Intrinsic::arm_neon_vst4lane: {
7209 Info.opc = ISD::INTRINSIC_VOID;
7210 // Conservatively set memVT to the entire set of vectors stored.
7211 unsigned NumElts = 0;
7212 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
7213 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
7214 if (!ArgTy->isVectorTy())
7216 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
7218 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7219 Info.ptrVal = I.getArgOperand(0);
7221 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7222 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7223 Info.vol = false; // volatile stores with NEON intrinsics not supported
7224 Info.readMem = false;
7225 Info.writeMem = true;