1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Instruction.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Type.h"
33 #include "llvm/CodeGen/CallingConvLower.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/MC/MCSectionMachO.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/ADT/VectorExtras.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
52 STATISTIC(NumTailCalls, "Number of tail calls");
54 // This option should go away when tail calls fully work.
56 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
57 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions."),
65 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
66 CCValAssign::LocInfo &LocInfo,
67 ISD::ArgFlagsTy &ArgFlags,
69 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
70 CCValAssign::LocInfo &LocInfo,
71 ISD::ArgFlagsTy &ArgFlags,
73 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
74 CCValAssign::LocInfo &LocInfo,
75 ISD::ArgFlagsTy &ArgFlags,
77 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
78 CCValAssign::LocInfo &LocInfo,
79 ISD::ArgFlagsTy &ArgFlags,
82 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
83 EVT PromotedBitwiseVT) {
84 if (VT != PromotedLdStVT) {
85 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
86 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
87 PromotedLdStVT.getSimpleVT());
89 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
90 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
91 PromotedLdStVT.getSimpleVT());
94 EVT ElemTy = VT.getVectorElementType();
95 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
96 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
97 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
98 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
99 if (ElemTy != MVT::i32) {
100 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
101 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
103 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
105 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
106 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
107 if (llvm::ModelWithRegSequence())
108 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
110 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
112 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
114 if (VT.isInteger()) {
115 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
116 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
117 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
120 // Promote all bit-wise operations.
121 if (VT.isInteger() && VT != PromotedBitwiseVT) {
122 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
123 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
124 PromotedBitwiseVT.getSimpleVT());
125 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
126 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
127 PromotedBitwiseVT.getSimpleVT());
128 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
129 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
130 PromotedBitwiseVT.getSimpleVT());
133 // Neon does not support vector divide/remainder operations.
134 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
135 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
136 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
137 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
138 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
139 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
142 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
143 addRegisterClass(VT, ARM::DPRRegisterClass);
144 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
147 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
148 addRegisterClass(VT, ARM::QPRRegisterClass);
149 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
152 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
153 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
154 return new TargetLoweringObjectFileMachO();
156 return new ARMElfTargetObjectFile();
159 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
160 : TargetLowering(TM, createTLOF(TM)) {
161 Subtarget = &TM.getSubtarget<ARMSubtarget>();
163 if (Subtarget->isTargetDarwin()) {
164 // Uses VFP for Thumb libfuncs if available.
165 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
166 // Single-precision floating-point arithmetic.
167 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
168 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
169 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
170 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
172 // Double-precision floating-point arithmetic.
173 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
174 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
175 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
176 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
178 // Single-precision comparisons.
179 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
180 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
181 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
182 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
183 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
184 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
185 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
186 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
188 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
193 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
194 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
195 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
197 // Double-precision comparisons.
198 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
199 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
200 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
201 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
202 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
203 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
204 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
205 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
207 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
216 // Floating-point to integer conversions.
217 // i64 conversions are done via library routines even when generating VFP
218 // instructions, so use the same ones.
219 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
220 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
221 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
222 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
224 // Conversions between floating types.
225 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
226 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
228 // Integer to floating-point conversions.
229 // i64 conversions are done via library routines even when generating VFP
230 // instructions, so use the same ones.
231 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
232 // e.g., __floatunsidf vs. __floatunssidfvfp.
233 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
234 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
235 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
236 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
240 // These libcalls are not available in 32-bit.
241 setLibcallName(RTLIB::SHL_I128, 0);
242 setLibcallName(RTLIB::SRL_I128, 0);
243 setLibcallName(RTLIB::SRA_I128, 0);
245 // Libcalls should use the AAPCS base standard ABI, even if hard float
246 // is in effect, as per the ARM RTABI specification, section 4.1.2.
247 if (Subtarget->isAAPCS_ABI()) {
248 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
249 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
250 CallingConv::ARM_AAPCS);
254 if (Subtarget->isThumb1Only())
255 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
257 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
258 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
259 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
260 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
262 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
265 if (Subtarget->hasNEON()) {
266 addDRTypeForNEON(MVT::v2f32);
267 addDRTypeForNEON(MVT::v8i8);
268 addDRTypeForNEON(MVT::v4i16);
269 addDRTypeForNEON(MVT::v2i32);
270 addDRTypeForNEON(MVT::v1i64);
272 addQRTypeForNEON(MVT::v4f32);
273 addQRTypeForNEON(MVT::v2f64);
274 addQRTypeForNEON(MVT::v16i8);
275 addQRTypeForNEON(MVT::v8i16);
276 addQRTypeForNEON(MVT::v4i32);
277 addQRTypeForNEON(MVT::v2i64);
279 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
280 // neither Neon nor VFP support any arithmetic operations on it.
281 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
282 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
283 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
284 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
285 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
286 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
287 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
288 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
289 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
290 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
291 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
292 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
293 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
294 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
295 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
296 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
297 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
298 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
299 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
300 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
301 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
302 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
303 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
304 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
306 // Neon does not support some operations on v1i64 and v2i64 types.
307 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
308 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
309 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
310 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
312 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
313 setTargetDAGCombine(ISD::SHL);
314 setTargetDAGCombine(ISD::SRL);
315 setTargetDAGCombine(ISD::SRA);
316 setTargetDAGCombine(ISD::SIGN_EXTEND);
317 setTargetDAGCombine(ISD::ZERO_EXTEND);
318 setTargetDAGCombine(ISD::ANY_EXTEND);
319 setTargetDAGCombine(ISD::SELECT_CC);
322 computeRegisterProperties();
324 // ARM does not have f32 extending load.
325 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
327 // ARM does not have i1 sign extending load.
328 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
330 // ARM supports all 4 flavors of integer indexed load / store.
331 if (!Subtarget->isThumb1Only()) {
332 for (unsigned im = (unsigned)ISD::PRE_INC;
333 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
334 setIndexedLoadAction(im, MVT::i1, Legal);
335 setIndexedLoadAction(im, MVT::i8, Legal);
336 setIndexedLoadAction(im, MVT::i16, Legal);
337 setIndexedLoadAction(im, MVT::i32, Legal);
338 setIndexedStoreAction(im, MVT::i1, Legal);
339 setIndexedStoreAction(im, MVT::i8, Legal);
340 setIndexedStoreAction(im, MVT::i16, Legal);
341 setIndexedStoreAction(im, MVT::i32, Legal);
345 // i64 operation support.
346 if (Subtarget->isThumb1Only()) {
347 setOperationAction(ISD::MUL, MVT::i64, Expand);
348 setOperationAction(ISD::MULHU, MVT::i32, Expand);
349 setOperationAction(ISD::MULHS, MVT::i32, Expand);
350 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
351 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
353 setOperationAction(ISD::MUL, MVT::i64, Expand);
354 setOperationAction(ISD::MULHU, MVT::i32, Expand);
355 if (!Subtarget->hasV6Ops())
356 setOperationAction(ISD::MULHS, MVT::i32, Expand);
358 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
359 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
360 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
361 setOperationAction(ISD::SRL, MVT::i64, Custom);
362 setOperationAction(ISD::SRA, MVT::i64, Custom);
364 // ARM does not have ROTL.
365 setOperationAction(ISD::ROTL, MVT::i32, Expand);
366 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
367 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
368 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
369 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
371 // Only ARMv6 has BSWAP.
372 if (!Subtarget->hasV6Ops())
373 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
375 // These are expanded into libcalls.
376 if (!Subtarget->hasDivide()) {
377 // v7M has a hardware divider
378 setOperationAction(ISD::SDIV, MVT::i32, Expand);
379 setOperationAction(ISD::UDIV, MVT::i32, Expand);
381 setOperationAction(ISD::SREM, MVT::i32, Expand);
382 setOperationAction(ISD::UREM, MVT::i32, Expand);
383 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
384 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
386 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
387 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
388 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
389 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
390 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
392 setOperationAction(ISD::TRAP, MVT::Other, Legal);
394 // Use the default implementation.
395 setOperationAction(ISD::VASTART, MVT::Other, Custom);
396 setOperationAction(ISD::VAARG, MVT::Other, Expand);
397 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
398 setOperationAction(ISD::VAEND, MVT::Other, Expand);
399 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
400 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
401 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
402 // FIXME: Shouldn't need this, since no register is used, but the legalizer
403 // doesn't yet know how to not do that for SjLj.
404 setExceptionSelectorRegister(ARM::R0);
405 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
406 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
408 // If the subtarget does not have extract instructions, sign_extend_inreg
409 // needs to be expanded. Extract is available in ARM mode on v6 and up,
410 // and on most Thumb2 implementations.
411 if ((!Subtarget->isThumb() && !Subtarget->hasV6Ops())
412 || (Subtarget->isThumb2() && !Subtarget->hasT2ExtractPack())) {
413 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
414 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
416 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
418 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
419 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
420 // iff target supports vfp2.
421 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
423 // We want to custom lower some of our intrinsics.
424 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
426 setOperationAction(ISD::SETCC, MVT::i32, Expand);
427 setOperationAction(ISD::SETCC, MVT::f32, Expand);
428 setOperationAction(ISD::SETCC, MVT::f64, Expand);
429 setOperationAction(ISD::SELECT, MVT::i32, Expand);
430 setOperationAction(ISD::SELECT, MVT::f32, Expand);
431 setOperationAction(ISD::SELECT, MVT::f64, Expand);
432 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
433 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
434 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
436 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
437 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
438 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
439 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
440 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
442 // We don't support sin/cos/fmod/copysign/pow
443 setOperationAction(ISD::FSIN, MVT::f64, Expand);
444 setOperationAction(ISD::FSIN, MVT::f32, Expand);
445 setOperationAction(ISD::FCOS, MVT::f32, Expand);
446 setOperationAction(ISD::FCOS, MVT::f64, Expand);
447 setOperationAction(ISD::FREM, MVT::f64, Expand);
448 setOperationAction(ISD::FREM, MVT::f32, Expand);
449 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
450 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
451 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
453 setOperationAction(ISD::FPOW, MVT::f64, Expand);
454 setOperationAction(ISD::FPOW, MVT::f32, Expand);
456 // Various VFP goodness
457 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
458 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
459 if (Subtarget->hasVFP2()) {
460 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
461 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
462 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
463 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
465 // Special handling for half-precision FP.
466 if (!Subtarget->hasFP16()) {
467 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
468 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
472 // We have target-specific dag combine patterns for the following nodes:
473 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
474 setTargetDAGCombine(ISD::ADD);
475 setTargetDAGCombine(ISD::SUB);
476 setTargetDAGCombine(ISD::MUL);
478 setStackPointerRegisterToSaveRestore(ARM::SP);
480 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
481 setSchedulingPreference(Sched::RegPressure);
483 setSchedulingPreference(Sched::Hybrid);
485 // FIXME: If-converter should use instruction latency to determine
486 // profitability rather than relying on fixed limits.
487 if (Subtarget->getCPUString() == "generic") {
488 // Generic (and overly aggressive) if-conversion limits.
489 setIfCvtBlockSizeLimit(10);
490 setIfCvtDupBlockSizeLimit(2);
491 } else if (Subtarget->hasV7Ops()) {
492 setIfCvtBlockSizeLimit(3);
493 setIfCvtDupBlockSizeLimit(1);
494 } else if (Subtarget->hasV6Ops()) {
495 setIfCvtBlockSizeLimit(2);
496 setIfCvtDupBlockSizeLimit(1);
498 setIfCvtBlockSizeLimit(3);
499 setIfCvtDupBlockSizeLimit(2);
502 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
503 // Do not enable CodePlacementOpt for now: it currently runs after the
504 // ARMConstantIslandPass and messes up branch relaxation and placement
505 // of constant islands.
506 // benefitFromCodePlacementOpt = true;
509 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
512 case ARMISD::Wrapper: return "ARMISD::Wrapper";
513 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
514 case ARMISD::CALL: return "ARMISD::CALL";
515 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
516 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
517 case ARMISD::tCALL: return "ARMISD::tCALL";
518 case ARMISD::BRCOND: return "ARMISD::BRCOND";
519 case ARMISD::BR_JT: return "ARMISD::BR_JT";
520 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
521 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
522 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
523 case ARMISD::CMP: return "ARMISD::CMP";
524 case ARMISD::CMPZ: return "ARMISD::CMPZ";
525 case ARMISD::CMPFP: return "ARMISD::CMPFP";
526 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
527 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
528 case ARMISD::CMOV: return "ARMISD::CMOV";
529 case ARMISD::CNEG: return "ARMISD::CNEG";
531 case ARMISD::RBIT: return "ARMISD::RBIT";
533 case ARMISD::FTOSI: return "ARMISD::FTOSI";
534 case ARMISD::FTOUI: return "ARMISD::FTOUI";
535 case ARMISD::SITOF: return "ARMISD::SITOF";
536 case ARMISD::UITOF: return "ARMISD::UITOF";
538 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
539 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
540 case ARMISD::RRX: return "ARMISD::RRX";
542 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
543 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
545 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
546 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
548 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
550 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
552 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
554 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
555 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
557 case ARMISD::VCEQ: return "ARMISD::VCEQ";
558 case ARMISD::VCGE: return "ARMISD::VCGE";
559 case ARMISD::VCGEU: return "ARMISD::VCGEU";
560 case ARMISD::VCGT: return "ARMISD::VCGT";
561 case ARMISD::VCGTU: return "ARMISD::VCGTU";
562 case ARMISD::VTST: return "ARMISD::VTST";
564 case ARMISD::VSHL: return "ARMISD::VSHL";
565 case ARMISD::VSHRs: return "ARMISD::VSHRs";
566 case ARMISD::VSHRu: return "ARMISD::VSHRu";
567 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
568 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
569 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
570 case ARMISD::VSHRN: return "ARMISD::VSHRN";
571 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
572 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
573 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
574 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
575 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
576 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
577 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
578 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
579 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
580 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
581 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
582 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
583 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
584 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
585 case ARMISD::VDUP: return "ARMISD::VDUP";
586 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
587 case ARMISD::VEXT: return "ARMISD::VEXT";
588 case ARMISD::VREV64: return "ARMISD::VREV64";
589 case ARMISD::VREV32: return "ARMISD::VREV32";
590 case ARMISD::VREV16: return "ARMISD::VREV16";
591 case ARMISD::VZIP: return "ARMISD::VZIP";
592 case ARMISD::VUZP: return "ARMISD::VUZP";
593 case ARMISD::VTRN: return "ARMISD::VTRN";
594 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
595 case ARMISD::FMAX: return "ARMISD::FMAX";
596 case ARMISD::FMIN: return "ARMISD::FMIN";
600 /// getRegClassFor - Return the register class that should be used for the
601 /// specified value type.
602 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
603 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
604 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
605 // load / store 4 to 8 consecutive D registers.
606 if (Subtarget->hasNEON()) {
607 if (VT == MVT::v4i64)
608 return ARM::QQPRRegisterClass;
609 else if (VT == MVT::v8i64)
610 return ARM::QQQQPRRegisterClass;
612 return TargetLowering::getRegClassFor(VT);
615 /// getFunctionAlignment - Return the Log2 alignment of this function.
616 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
617 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
620 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
621 unsigned NumVals = N->getNumValues();
623 return Sched::RegPressure;
625 for (unsigned i = 0; i != NumVals; ++i) {
626 EVT VT = N->getValueType(i);
627 if (VT.isFloatingPoint() || VT.isVector())
628 return Sched::Latency;
631 if (!N->isMachineOpcode())
632 return Sched::RegPressure;
634 // Load are scheduled for latency even if there instruction itinerary
636 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
637 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
639 return Sched::Latency;
641 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
642 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
643 return Sched::Latency;
644 return Sched::RegPressure;
647 //===----------------------------------------------------------------------===//
649 //===----------------------------------------------------------------------===//
651 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
652 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
654 default: llvm_unreachable("Unknown condition code!");
655 case ISD::SETNE: return ARMCC::NE;
656 case ISD::SETEQ: return ARMCC::EQ;
657 case ISD::SETGT: return ARMCC::GT;
658 case ISD::SETGE: return ARMCC::GE;
659 case ISD::SETLT: return ARMCC::LT;
660 case ISD::SETLE: return ARMCC::LE;
661 case ISD::SETUGT: return ARMCC::HI;
662 case ISD::SETUGE: return ARMCC::HS;
663 case ISD::SETULT: return ARMCC::LO;
664 case ISD::SETULE: return ARMCC::LS;
668 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
669 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
670 ARMCC::CondCodes &CondCode2) {
671 CondCode2 = ARMCC::AL;
673 default: llvm_unreachable("Unknown FP condition!");
675 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
677 case ISD::SETOGT: CondCode = ARMCC::GT; break;
679 case ISD::SETOGE: CondCode = ARMCC::GE; break;
680 case ISD::SETOLT: CondCode = ARMCC::MI; break;
681 case ISD::SETOLE: CondCode = ARMCC::LS; break;
682 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
683 case ISD::SETO: CondCode = ARMCC::VC; break;
684 case ISD::SETUO: CondCode = ARMCC::VS; break;
685 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
686 case ISD::SETUGT: CondCode = ARMCC::HI; break;
687 case ISD::SETUGE: CondCode = ARMCC::PL; break;
689 case ISD::SETULT: CondCode = ARMCC::LT; break;
691 case ISD::SETULE: CondCode = ARMCC::LE; break;
693 case ISD::SETUNE: CondCode = ARMCC::NE; break;
697 //===----------------------------------------------------------------------===//
698 // Calling Convention Implementation
699 //===----------------------------------------------------------------------===//
701 #include "ARMGenCallingConv.inc"
703 // APCS f64 is in register pairs, possibly split to stack
704 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
705 CCValAssign::LocInfo &LocInfo,
706 CCState &State, bool CanFail) {
707 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
709 // Try to get the first register.
710 if (unsigned Reg = State.AllocateReg(RegList, 4))
711 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
713 // For the 2nd half of a v2f64, do not fail.
717 // Put the whole thing on the stack.
718 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
719 State.AllocateStack(8, 4),
724 // Try to get the second register.
725 if (unsigned Reg = State.AllocateReg(RegList, 4))
726 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
728 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
729 State.AllocateStack(4, 4),
734 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
735 CCValAssign::LocInfo &LocInfo,
736 ISD::ArgFlagsTy &ArgFlags,
738 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
740 if (LocVT == MVT::v2f64 &&
741 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
743 return true; // we handled it
746 // AAPCS f64 is in aligned register pairs
747 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
748 CCValAssign::LocInfo &LocInfo,
749 CCState &State, bool CanFail) {
750 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
751 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
753 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
755 // For the 2nd half of a v2f64, do not just fail.
759 // Put the whole thing on the stack.
760 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
761 State.AllocateStack(8, 8),
767 for (i = 0; i < 2; ++i)
768 if (HiRegList[i] == Reg)
771 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
772 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
777 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
778 CCValAssign::LocInfo &LocInfo,
779 ISD::ArgFlagsTy &ArgFlags,
781 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
783 if (LocVT == MVT::v2f64 &&
784 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
786 return true; // we handled it
789 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
790 CCValAssign::LocInfo &LocInfo, CCState &State) {
791 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
792 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
794 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
796 return false; // we didn't handle it
799 for (i = 0; i < 2; ++i)
800 if (HiRegList[i] == Reg)
803 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
804 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
809 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
810 CCValAssign::LocInfo &LocInfo,
811 ISD::ArgFlagsTy &ArgFlags,
813 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
815 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
817 return true; // we handled it
820 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
821 CCValAssign::LocInfo &LocInfo,
822 ISD::ArgFlagsTy &ArgFlags,
824 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
828 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
829 /// given CallingConvention value.
830 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
832 bool isVarArg) const {
835 llvm_unreachable("Unsupported calling convention");
837 case CallingConv::Fast:
838 // Use target triple & subtarget features to do actual dispatch.
839 if (Subtarget->isAAPCS_ABI()) {
840 if (Subtarget->hasVFP2() &&
841 FloatABIType == FloatABI::Hard && !isVarArg)
842 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
844 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
846 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
847 case CallingConv::ARM_AAPCS_VFP:
848 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
849 case CallingConv::ARM_AAPCS:
850 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
851 case CallingConv::ARM_APCS:
852 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
856 /// LowerCallResult - Lower the result values of a call into the
857 /// appropriate copies out of appropriate physical registers.
859 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
860 CallingConv::ID CallConv, bool isVarArg,
861 const SmallVectorImpl<ISD::InputArg> &Ins,
862 DebugLoc dl, SelectionDAG &DAG,
863 SmallVectorImpl<SDValue> &InVals) const {
865 // Assign locations to each value returned by this call.
866 SmallVector<CCValAssign, 16> RVLocs;
867 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
868 RVLocs, *DAG.getContext());
869 CCInfo.AnalyzeCallResult(Ins,
870 CCAssignFnForNode(CallConv, /* Return*/ true,
873 // Copy all of the result registers out of their specified physreg.
874 for (unsigned i = 0; i != RVLocs.size(); ++i) {
875 CCValAssign VA = RVLocs[i];
878 if (VA.needsCustom()) {
879 // Handle f64 or half of a v2f64.
880 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
882 Chain = Lo.getValue(1);
883 InFlag = Lo.getValue(2);
884 VA = RVLocs[++i]; // skip ahead to next loc
885 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
887 Chain = Hi.getValue(1);
888 InFlag = Hi.getValue(2);
889 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
891 if (VA.getLocVT() == MVT::v2f64) {
892 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
893 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
894 DAG.getConstant(0, MVT::i32));
896 VA = RVLocs[++i]; // skip ahead to next loc
897 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
898 Chain = Lo.getValue(1);
899 InFlag = Lo.getValue(2);
900 VA = RVLocs[++i]; // skip ahead to next loc
901 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
902 Chain = Hi.getValue(1);
903 InFlag = Hi.getValue(2);
904 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
905 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
906 DAG.getConstant(1, MVT::i32));
909 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
911 Chain = Val.getValue(1);
912 InFlag = Val.getValue(2);
915 switch (VA.getLocInfo()) {
916 default: llvm_unreachable("Unknown loc info!");
917 case CCValAssign::Full: break;
918 case CCValAssign::BCvt:
919 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
923 InVals.push_back(Val);
929 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
930 /// by "Src" to address "Dst" of size "Size". Alignment information is
931 /// specified by the specific parameter attribute. The copy will be passed as
932 /// a byval function parameter.
933 /// Sometimes what we are copying is the end of a larger object, the part that
934 /// does not fit in registers.
936 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
937 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
939 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
940 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
941 /*isVolatile=*/false, /*AlwaysInline=*/false,
945 /// LowerMemOpCallTo - Store the argument to the stack.
947 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
948 SDValue StackPtr, SDValue Arg,
949 DebugLoc dl, SelectionDAG &DAG,
950 const CCValAssign &VA,
951 ISD::ArgFlagsTy Flags) const {
952 unsigned LocMemOffset = VA.getLocMemOffset();
953 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
954 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
955 if (Flags.isByVal()) {
956 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
958 return DAG.getStore(Chain, dl, Arg, PtrOff,
959 PseudoSourceValue::getStack(), LocMemOffset,
963 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
964 SDValue Chain, SDValue &Arg,
965 RegsToPassVector &RegsToPass,
966 CCValAssign &VA, CCValAssign &NextVA,
968 SmallVector<SDValue, 8> &MemOpChains,
969 ISD::ArgFlagsTy Flags) const {
971 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
972 DAG.getVTList(MVT::i32, MVT::i32), Arg);
973 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
975 if (NextVA.isRegLoc())
976 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
978 assert(NextVA.isMemLoc());
979 if (StackPtr.getNode() == 0)
980 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
982 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
988 /// LowerCall - Lowering a call into a callseq_start <-
989 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
992 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
993 CallingConv::ID CallConv, bool isVarArg,
995 const SmallVectorImpl<ISD::OutputArg> &Outs,
996 const SmallVectorImpl<ISD::InputArg> &Ins,
997 DebugLoc dl, SelectionDAG &DAG,
998 SmallVectorImpl<SDValue> &InVals) const {
999 MachineFunction &MF = DAG.getMachineFunction();
1000 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1001 bool IsSibCall = false;
1002 // Temporarily disable tail calls so things don't break.
1003 if (!EnableARMTailCalls)
1006 // Check if it's really possible to do a tail call.
1007 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1008 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1010 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1011 // detected sibcalls.
1018 // Analyze operands of the call, assigning locations to each operand.
1019 SmallVector<CCValAssign, 16> ArgLocs;
1020 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1022 CCInfo.AnalyzeCallOperands(Outs,
1023 CCAssignFnForNode(CallConv, /* Return*/ false,
1026 // Get a count of how many bytes are to be pushed on the stack.
1027 unsigned NumBytes = CCInfo.getNextStackOffset();
1029 // For tail calls, memory operands are available in our caller's stack.
1033 // Adjust the stack pointer for the new arguments...
1034 // These operations are automatically eliminated by the prolog/epilog pass
1036 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1038 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1040 RegsToPassVector RegsToPass;
1041 SmallVector<SDValue, 8> MemOpChains;
1043 // Walk the register/memloc assignments, inserting copies/loads. In the case
1044 // of tail call optimization, arguments are handled later.
1045 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1047 ++i, ++realArgIdx) {
1048 CCValAssign &VA = ArgLocs[i];
1049 SDValue Arg = Outs[realArgIdx].Val;
1050 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1052 // Promote the value if needed.
1053 switch (VA.getLocInfo()) {
1054 default: llvm_unreachable("Unknown loc info!");
1055 case CCValAssign::Full: break;
1056 case CCValAssign::SExt:
1057 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1059 case CCValAssign::ZExt:
1060 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1062 case CCValAssign::AExt:
1063 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1065 case CCValAssign::BCvt:
1066 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1070 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1071 if (VA.needsCustom()) {
1072 if (VA.getLocVT() == MVT::v2f64) {
1073 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1074 DAG.getConstant(0, MVT::i32));
1075 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1076 DAG.getConstant(1, MVT::i32));
1078 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1079 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1081 VA = ArgLocs[++i]; // skip ahead to next loc
1082 if (VA.isRegLoc()) {
1083 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1084 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1086 assert(VA.isMemLoc());
1088 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1089 dl, DAG, VA, Flags));
1092 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1093 StackPtr, MemOpChains, Flags);
1095 } else if (VA.isRegLoc()) {
1096 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1098 assert(VA.isMemLoc());
1100 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1101 dl, DAG, VA, Flags));
1105 if (!MemOpChains.empty())
1106 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1107 &MemOpChains[0], MemOpChains.size());
1109 // Build a sequence of copy-to-reg nodes chained together with token chain
1110 // and flag operands which copy the outgoing args into the appropriate regs.
1112 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1113 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1114 RegsToPass[i].second, InFlag);
1115 InFlag = Chain.getValue(1);
1118 // For tail calls lower the arguments to the 'real' stack slot.
1120 // Force all the incoming stack arguments to be loaded from the stack
1121 // before any new outgoing arguments are stored to the stack, because the
1122 // outgoing stack slots may alias the incoming argument stack slots, and
1123 // the alias isn't otherwise explicit. This is slightly more conservative
1124 // than necessary, because it means that each store effectively depends
1125 // on every argument instead of just those arguments it would clobber.
1127 // Do not flag preceeding copytoreg stuff together with the following stuff.
1129 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1130 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1131 RegsToPass[i].second, InFlag);
1132 InFlag = Chain.getValue(1);
1137 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1138 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1139 // node so that legalize doesn't hack it.
1140 bool isDirect = false;
1141 bool isARMFunc = false;
1142 bool isLocalARMFunc = false;
1143 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1145 if (EnableARMLongCalls) {
1146 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1147 && "long-calls with non-static relocation model!");
1148 // Handle a global address or an external symbol. If it's not one of
1149 // those, the target's already in a register, so we don't need to do
1151 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1152 const GlobalValue *GV = G->getGlobal();
1153 // Create a constant pool entry for the callee address
1154 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1155 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1158 // Get the address of the callee into a register
1159 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1160 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1161 Callee = DAG.getLoad(getPointerTy(), dl,
1162 DAG.getEntryNode(), CPAddr,
1163 PseudoSourceValue::getConstantPool(), 0,
1165 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1166 const char *Sym = S->getSymbol();
1168 // Create a constant pool entry for the callee address
1169 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1170 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1171 Sym, ARMPCLabelIndex, 0);
1172 // Get the address of the callee into a register
1173 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1174 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1175 Callee = DAG.getLoad(getPointerTy(), dl,
1176 DAG.getEntryNode(), CPAddr,
1177 PseudoSourceValue::getConstantPool(), 0,
1180 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1181 const GlobalValue *GV = G->getGlobal();
1183 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1184 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1185 getTargetMachine().getRelocationModel() != Reloc::Static;
1186 isARMFunc = !Subtarget->isThumb() || isStub;
1187 // ARM call to a local ARM function is predicable.
1188 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
1189 // tBX takes a register source operand.
1190 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1191 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1192 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1195 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1196 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1197 Callee = DAG.getLoad(getPointerTy(), dl,
1198 DAG.getEntryNode(), CPAddr,
1199 PseudoSourceValue::getConstantPool(), 0,
1201 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1202 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1203 getPointerTy(), Callee, PICLabel);
1205 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
1206 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1208 bool isStub = Subtarget->isTargetDarwin() &&
1209 getTargetMachine().getRelocationModel() != Reloc::Static;
1210 isARMFunc = !Subtarget->isThumb() || isStub;
1211 // tBX takes a register source operand.
1212 const char *Sym = S->getSymbol();
1213 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1214 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1215 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1216 Sym, ARMPCLabelIndex, 4);
1217 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1218 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1219 Callee = DAG.getLoad(getPointerTy(), dl,
1220 DAG.getEntryNode(), CPAddr,
1221 PseudoSourceValue::getConstantPool(), 0,
1223 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1224 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1225 getPointerTy(), Callee, PICLabel);
1227 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1230 // FIXME: handle tail calls differently.
1232 if (Subtarget->isThumb()) {
1233 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1234 CallOpc = ARMISD::CALL_NOLINK;
1236 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1238 CallOpc = (isDirect || Subtarget->hasV5TOps())
1239 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1240 : ARMISD::CALL_NOLINK;
1242 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1243 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1244 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1245 InFlag = Chain.getValue(1);
1248 std::vector<SDValue> Ops;
1249 Ops.push_back(Chain);
1250 Ops.push_back(Callee);
1252 // Add argument registers to the end of the list so that they are known live
1254 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1255 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1256 RegsToPass[i].second.getValueType()));
1258 if (InFlag.getNode())
1259 Ops.push_back(InFlag);
1261 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1263 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1265 // Returns a chain and a flag for retval copy to use.
1266 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1267 InFlag = Chain.getValue(1);
1269 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1270 DAG.getIntPtrConstant(0, true), InFlag);
1272 InFlag = Chain.getValue(1);
1274 // Handle result values, copying them out of physregs into vregs that we
1276 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1280 /// MatchingStackOffset - Return true if the given stack call argument is
1281 /// already available in the same position (relatively) of the caller's
1282 /// incoming argument stack.
1284 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1285 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1286 const ARMInstrInfo *TII) {
1287 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1289 if (Arg.getOpcode() == ISD::CopyFromReg) {
1290 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1291 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1293 MachineInstr *Def = MRI->getVRegDef(VR);
1296 if (!Flags.isByVal()) {
1297 if (!TII->isLoadFromStackSlot(Def, FI))
1300 // unsigned Opcode = Def->getOpcode();
1301 // if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
1302 // Def->getOperand(1).isFI()) {
1303 // FI = Def->getOperand(1).getIndex();
1304 // Bytes = Flags.getByValSize();
1308 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1309 if (Flags.isByVal())
1310 // ByVal argument is passed in as a pointer but it's now being
1311 // dereferenced. e.g.
1312 // define @foo(%struct.X* %A) {
1313 // tail call @bar(%struct.X* byval %A)
1316 SDValue Ptr = Ld->getBasePtr();
1317 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1320 FI = FINode->getIndex();
1324 assert(FI != INT_MAX);
1325 if (!MFI->isFixedObjectIndex(FI))
1327 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1330 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1331 /// for tail call optimization. Targets which want to do tail call
1332 /// optimization should implement this function.
1334 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1335 CallingConv::ID CalleeCC,
1337 bool isCalleeStructRet,
1338 bool isCallerStructRet,
1339 const SmallVectorImpl<ISD::OutputArg> &Outs,
1340 const SmallVectorImpl<ISD::InputArg> &Ins,
1341 SelectionDAG& DAG) const {
1343 const Function *CallerF = DAG.getMachineFunction().getFunction();
1344 CallingConv::ID CallerCC = CallerF->getCallingConv();
1345 bool CCMatch = CallerCC == CalleeCC;
1347 // Look for obvious safe cases to perform tail call optimization that do not
1348 // require ABI changes. This is what gcc calls sibcall.
1350 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
1351 // emit a special epilogue.
1352 // Not sure yet if this is true on ARM.
1353 //?? if (RegInfo->needsStackRealignment(MF))
1356 // Do not sibcall optimize vararg calls unless the call site is not passing any
1358 if (isVarArg && !Outs.empty())
1361 // Also avoid sibcall optimization if either caller or callee uses struct
1362 // return semantics.
1363 if (isCalleeStructRet || isCallerStructRet)
1366 // If the calling conventions do not match, then we'd better make sure the
1367 // results are returned in the same way as what the caller expects.
1369 SmallVector<CCValAssign, 16> RVLocs1;
1370 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1371 RVLocs1, *DAG.getContext());
1372 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1374 SmallVector<CCValAssign, 16> RVLocs2;
1375 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1376 RVLocs2, *DAG.getContext());
1377 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1379 if (RVLocs1.size() != RVLocs2.size())
1381 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1382 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1384 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1386 if (RVLocs1[i].isRegLoc()) {
1387 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1390 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1396 // If the callee takes no arguments then go on to check the results of the
1398 if (!Outs.empty()) {
1399 // Check if stack adjustment is needed. For now, do not do this if any
1400 // argument is passed on the stack.
1401 SmallVector<CCValAssign, 16> ArgLocs;
1402 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1403 ArgLocs, *DAG.getContext());
1404 CCInfo.AnalyzeCallOperands(Outs,
1405 CCAssignFnForNode(CalleeCC, false, isVarArg));
1406 if (CCInfo.getNextStackOffset()) {
1407 MachineFunction &MF = DAG.getMachineFunction();
1409 // Check if the arguments are already laid out in the right way as
1410 // the caller's fixed stack objects.
1411 MachineFrameInfo *MFI = MF.getFrameInfo();
1412 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1413 const ARMInstrInfo *TII =
1414 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1415 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1417 ++i, ++realArgIdx) {
1418 CCValAssign &VA = ArgLocs[i];
1419 EVT RegVT = VA.getLocVT();
1420 SDValue Arg = Outs[realArgIdx].Val;
1421 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1422 if (VA.getLocInfo() == CCValAssign::Indirect)
1424 if (VA.needsCustom()) {
1425 // f64 and vector types are split into multiple registers or
1426 // register/stack-slot combinations. The types will not match
1427 // the registers; give up on memory f64 refs until we figure
1428 // out what to do about this.
1431 if (!ArgLocs[++i].isRegLoc())
1433 if (RegVT == MVT::v2f64) {
1434 if (!ArgLocs[++i].isRegLoc())
1436 if (!ArgLocs[++i].isRegLoc())
1439 } else if (!VA.isRegLoc()) {
1440 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1452 ARMTargetLowering::LowerReturn(SDValue Chain,
1453 CallingConv::ID CallConv, bool isVarArg,
1454 const SmallVectorImpl<ISD::OutputArg> &Outs,
1455 DebugLoc dl, SelectionDAG &DAG) const {
1457 // CCValAssign - represent the assignment of the return value to a location.
1458 SmallVector<CCValAssign, 16> RVLocs;
1460 // CCState - Info about the registers and stack slots.
1461 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1464 // Analyze outgoing return values.
1465 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1468 // If this is the first return lowered for this function, add
1469 // the regs to the liveout set for the function.
1470 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1471 for (unsigned i = 0; i != RVLocs.size(); ++i)
1472 if (RVLocs[i].isRegLoc())
1473 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1478 // Copy the result values into the output registers.
1479 for (unsigned i = 0, realRVLocIdx = 0;
1481 ++i, ++realRVLocIdx) {
1482 CCValAssign &VA = RVLocs[i];
1483 assert(VA.isRegLoc() && "Can only return in registers!");
1485 SDValue Arg = Outs[realRVLocIdx].Val;
1487 switch (VA.getLocInfo()) {
1488 default: llvm_unreachable("Unknown loc info!");
1489 case CCValAssign::Full: break;
1490 case CCValAssign::BCvt:
1491 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1495 if (VA.needsCustom()) {
1496 if (VA.getLocVT() == MVT::v2f64) {
1497 // Extract the first half and return it in two registers.
1498 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1499 DAG.getConstant(0, MVT::i32));
1500 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1501 DAG.getVTList(MVT::i32, MVT::i32), Half);
1503 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1504 Flag = Chain.getValue(1);
1505 VA = RVLocs[++i]; // skip ahead to next loc
1506 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1507 HalfGPRs.getValue(1), Flag);
1508 Flag = Chain.getValue(1);
1509 VA = RVLocs[++i]; // skip ahead to next loc
1511 // Extract the 2nd half and fall through to handle it as an f64 value.
1512 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1513 DAG.getConstant(1, MVT::i32));
1515 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1517 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1518 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1519 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1520 Flag = Chain.getValue(1);
1521 VA = RVLocs[++i]; // skip ahead to next loc
1522 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1525 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1527 // Guarantee that all emitted copies are
1528 // stuck together, avoiding something bad.
1529 Flag = Chain.getValue(1);
1534 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1536 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1541 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1542 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1543 // one of the above mentioned nodes. It has to be wrapped because otherwise
1544 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1545 // be used to form addressing mode. These wrapped nodes will be selected
1547 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1548 EVT PtrVT = Op.getValueType();
1549 // FIXME there is no actual debug info here
1550 DebugLoc dl = Op.getDebugLoc();
1551 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1553 if (CP->isMachineConstantPoolEntry())
1554 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1555 CP->getAlignment());
1557 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1558 CP->getAlignment());
1559 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1562 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1563 SelectionDAG &DAG) const {
1564 MachineFunction &MF = DAG.getMachineFunction();
1565 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1566 unsigned ARMPCLabelIndex = 0;
1567 DebugLoc DL = Op.getDebugLoc();
1568 EVT PtrVT = getPointerTy();
1569 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1570 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1572 if (RelocM == Reloc::Static) {
1573 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1575 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1576 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1577 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1578 ARMCP::CPBlockAddress,
1580 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1582 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1583 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1584 PseudoSourceValue::getConstantPool(), 0,
1586 if (RelocM == Reloc::Static)
1588 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1589 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1592 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1594 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1595 SelectionDAG &DAG) const {
1596 DebugLoc dl = GA->getDebugLoc();
1597 EVT PtrVT = getPointerTy();
1598 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1599 MachineFunction &MF = DAG.getMachineFunction();
1600 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1601 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1602 ARMConstantPoolValue *CPV =
1603 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1604 ARMCP::CPValue, PCAdj, "tlsgd", true);
1605 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1606 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1607 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1608 PseudoSourceValue::getConstantPool(), 0,
1610 SDValue Chain = Argument.getValue(1);
1612 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1613 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1615 // call __tls_get_addr.
1618 Entry.Node = Argument;
1619 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1620 Args.push_back(Entry);
1621 // FIXME: is there useful debug info available here?
1622 std::pair<SDValue, SDValue> CallResult =
1623 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1624 false, false, false, false,
1625 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1626 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1627 return CallResult.first;
1630 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1631 // "local exec" model.
1633 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1634 SelectionDAG &DAG) const {
1635 const GlobalValue *GV = GA->getGlobal();
1636 DebugLoc dl = GA->getDebugLoc();
1638 SDValue Chain = DAG.getEntryNode();
1639 EVT PtrVT = getPointerTy();
1640 // Get the Thread Pointer
1641 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1643 if (GV->isDeclaration()) {
1644 MachineFunction &MF = DAG.getMachineFunction();
1645 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1646 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1647 // Initial exec model.
1648 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1649 ARMConstantPoolValue *CPV =
1650 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1651 ARMCP::CPValue, PCAdj, "gottpoff", true);
1652 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1653 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1654 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1655 PseudoSourceValue::getConstantPool(), 0,
1657 Chain = Offset.getValue(1);
1659 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1660 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1662 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1663 PseudoSourceValue::getConstantPool(), 0,
1667 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1668 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1669 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1670 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1671 PseudoSourceValue::getConstantPool(), 0,
1675 // The address of the thread local variable is the add of the thread
1676 // pointer with the offset of the variable.
1677 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1681 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1682 // TODO: implement the "local dynamic" model
1683 assert(Subtarget->isTargetELF() &&
1684 "TLS not implemented for non-ELF targets");
1685 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1686 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1687 // otherwise use the "Local Exec" TLS Model
1688 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1689 return LowerToTLSGeneralDynamicModel(GA, DAG);
1691 return LowerToTLSExecModels(GA, DAG);
1694 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1695 SelectionDAG &DAG) const {
1696 EVT PtrVT = getPointerTy();
1697 DebugLoc dl = Op.getDebugLoc();
1698 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1699 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1700 if (RelocM == Reloc::PIC_) {
1701 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1702 ARMConstantPoolValue *CPV =
1703 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1704 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1705 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1706 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1708 PseudoSourceValue::getConstantPool(), 0,
1710 SDValue Chain = Result.getValue(1);
1711 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1712 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1714 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1715 PseudoSourceValue::getGOT(), 0,
1719 // If we have T2 ops, we can materialize the address directly via movt/movw
1720 // pair. This is always cheaper.
1721 if (Subtarget->useMovt()) {
1722 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1723 DAG.getTargetGlobalAddress(GV, PtrVT));
1725 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1726 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1727 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1728 PseudoSourceValue::getConstantPool(), 0,
1734 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1735 SelectionDAG &DAG) const {
1736 MachineFunction &MF = DAG.getMachineFunction();
1737 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1738 unsigned ARMPCLabelIndex = 0;
1739 EVT PtrVT = getPointerTy();
1740 DebugLoc dl = Op.getDebugLoc();
1741 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1742 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1744 if (RelocM == Reloc::Static)
1745 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1747 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1748 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1749 ARMConstantPoolValue *CPV =
1750 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1751 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1753 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1755 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1756 PseudoSourceValue::getConstantPool(), 0,
1758 SDValue Chain = Result.getValue(1);
1760 if (RelocM == Reloc::PIC_) {
1761 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1762 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1765 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1766 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1767 PseudoSourceValue::getGOT(), 0,
1773 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1774 SelectionDAG &DAG) const {
1775 assert(Subtarget->isTargetELF() &&
1776 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1777 MachineFunction &MF = DAG.getMachineFunction();
1778 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1779 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1780 EVT PtrVT = getPointerTy();
1781 DebugLoc dl = Op.getDebugLoc();
1782 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1783 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1784 "_GLOBAL_OFFSET_TABLE_",
1785 ARMPCLabelIndex, PCAdj);
1786 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1787 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1788 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1789 PseudoSourceValue::getConstantPool(), 0,
1791 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1792 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1796 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1797 DebugLoc dl = Op.getDebugLoc();
1798 SDValue Val = DAG.getConstant(0, MVT::i32);
1799 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1800 Op.getOperand(1), Val);
1804 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1805 DebugLoc dl = Op.getDebugLoc();
1806 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1807 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1811 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1812 const ARMSubtarget *Subtarget)
1814 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1815 DebugLoc dl = Op.getDebugLoc();
1817 default: return SDValue(); // Don't custom lower most intrinsics.
1818 case Intrinsic::arm_thread_pointer: {
1819 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1820 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1822 case Intrinsic::eh_sjlj_lsda: {
1823 MachineFunction &MF = DAG.getMachineFunction();
1824 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1825 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1826 EVT PtrVT = getPointerTy();
1827 DebugLoc dl = Op.getDebugLoc();
1828 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1830 unsigned PCAdj = (RelocM != Reloc::PIC_)
1831 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1832 ARMConstantPoolValue *CPV =
1833 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1834 ARMCP::CPLSDA, PCAdj);
1835 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1836 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1838 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1839 PseudoSourceValue::getConstantPool(), 0,
1841 SDValue Chain = Result.getValue(1);
1843 if (RelocM == Reloc::PIC_) {
1844 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1845 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1852 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1853 const ARMSubtarget *Subtarget) {
1854 DebugLoc dl = Op.getDebugLoc();
1855 SDValue Op5 = Op.getOperand(5);
1857 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1858 if (isDeviceBarrier) {
1859 if (Subtarget->hasV7Ops())
1860 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0));
1862 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0),
1863 DAG.getConstant(0, MVT::i32));
1865 if (Subtarget->hasV7Ops())
1866 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
1868 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
1869 DAG.getConstant(0, MVT::i32));
1874 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
1875 MachineFunction &MF = DAG.getMachineFunction();
1876 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
1878 // vastart just stores the address of the VarArgsFrameIndex slot into the
1879 // memory location argument.
1880 DebugLoc dl = Op.getDebugLoc();
1881 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1882 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1883 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1884 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1889 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1890 SelectionDAG &DAG) const {
1891 SDNode *Node = Op.getNode();
1892 DebugLoc dl = Node->getDebugLoc();
1893 EVT VT = Node->getValueType(0);
1894 SDValue Chain = Op.getOperand(0);
1895 SDValue Size = Op.getOperand(1);
1896 SDValue Align = Op.getOperand(2);
1898 // Chain the dynamic stack allocation so that it doesn't modify the stack
1899 // pointer when other instructions are using the stack.
1900 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1902 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1903 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1904 if (AlignVal > StackAlign)
1905 // Do this now since selection pass cannot introduce new target
1906 // independent node.
1907 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1909 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1910 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1911 // do even more horrible hack later.
1912 MachineFunction &MF = DAG.getMachineFunction();
1913 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1914 if (AFI->isThumb1OnlyFunction()) {
1916 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1918 uint32_t Val = C->getZExtValue();
1919 if (Val <= 508 && ((Val & 3) == 0))
1923 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1926 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1927 SDValue Ops1[] = { Chain, Size, Align };
1928 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1929 Chain = Res.getValue(1);
1930 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1931 DAG.getIntPtrConstant(0, true), SDValue());
1932 SDValue Ops2[] = { Res, Chain };
1933 return DAG.getMergeValues(Ops2, 2, dl);
1937 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1938 SDValue &Root, SelectionDAG &DAG,
1939 DebugLoc dl) const {
1940 MachineFunction &MF = DAG.getMachineFunction();
1941 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1943 TargetRegisterClass *RC;
1944 if (AFI->isThumb1OnlyFunction())
1945 RC = ARM::tGPRRegisterClass;
1947 RC = ARM::GPRRegisterClass;
1949 // Transform the arguments stored in physical registers into virtual ones.
1950 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1951 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1954 if (NextVA.isMemLoc()) {
1955 MachineFrameInfo *MFI = MF.getFrameInfo();
1956 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true, false);
1958 // Create load node to retrieve arguments from the stack.
1959 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1960 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
1961 PseudoSourceValue::getFixedStack(FI), 0,
1964 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1965 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1968 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
1972 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1973 CallingConv::ID CallConv, bool isVarArg,
1974 const SmallVectorImpl<ISD::InputArg>
1976 DebugLoc dl, SelectionDAG &DAG,
1977 SmallVectorImpl<SDValue> &InVals)
1980 MachineFunction &MF = DAG.getMachineFunction();
1981 MachineFrameInfo *MFI = MF.getFrameInfo();
1983 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1985 // Assign locations to all of the incoming arguments.
1986 SmallVector<CCValAssign, 16> ArgLocs;
1987 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1989 CCInfo.AnalyzeFormalArguments(Ins,
1990 CCAssignFnForNode(CallConv, /* Return*/ false,
1993 SmallVector<SDValue, 16> ArgValues;
1995 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1996 CCValAssign &VA = ArgLocs[i];
1998 // Arguments stored in registers.
1999 if (VA.isRegLoc()) {
2000 EVT RegVT = VA.getLocVT();
2003 if (VA.needsCustom()) {
2004 // f64 and vector types are split up into multiple registers or
2005 // combinations of registers and stack slots.
2006 if (VA.getLocVT() == MVT::v2f64) {
2007 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2009 VA = ArgLocs[++i]; // skip ahead to next loc
2011 if (VA.isMemLoc()) {
2012 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(),
2014 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2015 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2016 PseudoSourceValue::getFixedStack(FI), 0,
2019 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2022 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2023 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2024 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2025 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2026 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2028 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2031 TargetRegisterClass *RC;
2033 if (RegVT == MVT::f32)
2034 RC = ARM::SPRRegisterClass;
2035 else if (RegVT == MVT::f64)
2036 RC = ARM::DPRRegisterClass;
2037 else if (RegVT == MVT::v2f64)
2038 RC = ARM::QPRRegisterClass;
2039 else if (RegVT == MVT::i32)
2040 RC = (AFI->isThumb1OnlyFunction() ?
2041 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2043 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2045 // Transform the arguments in physical registers into virtual ones.
2046 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2047 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2050 // If this is an 8 or 16-bit value, it is really passed promoted
2051 // to 32 bits. Insert an assert[sz]ext to capture this, then
2052 // truncate to the right size.
2053 switch (VA.getLocInfo()) {
2054 default: llvm_unreachable("Unknown loc info!");
2055 case CCValAssign::Full: break;
2056 case CCValAssign::BCvt:
2057 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2059 case CCValAssign::SExt:
2060 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2061 DAG.getValueType(VA.getValVT()));
2062 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2064 case CCValAssign::ZExt:
2065 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2066 DAG.getValueType(VA.getValVT()));
2067 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2071 InVals.push_back(ArgValue);
2073 } else { // VA.isRegLoc()
2076 assert(VA.isMemLoc());
2077 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2079 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2080 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2083 // Create load nodes to retrieve arguments from the stack.
2084 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2085 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2086 PseudoSourceValue::getFixedStack(FI), 0,
2093 static const unsigned GPRArgRegs[] = {
2094 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2097 unsigned NumGPRs = CCInfo.getFirstUnallocated
2098 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2100 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2101 unsigned VARegSize = (4 - NumGPRs) * 4;
2102 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2103 unsigned ArgOffset = CCInfo.getNextStackOffset();
2104 if (VARegSaveSize) {
2105 // If this function is vararg, store any remaining integer argument regs
2106 // to their spots on the stack so that they may be loaded by deferencing
2107 // the result of va_next.
2108 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2109 AFI->setVarArgsFrameIndex(
2110 MFI->CreateFixedObject(VARegSaveSize,
2111 ArgOffset + VARegSaveSize - VARegSize,
2113 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2116 SmallVector<SDValue, 4> MemOps;
2117 for (; NumGPRs < 4; ++NumGPRs) {
2118 TargetRegisterClass *RC;
2119 if (AFI->isThumb1OnlyFunction())
2120 RC = ARM::tGPRRegisterClass;
2122 RC = ARM::GPRRegisterClass;
2124 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2125 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2127 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2128 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()),
2129 0, false, false, 0);
2130 MemOps.push_back(Store);
2131 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2132 DAG.getConstant(4, getPointerTy()));
2134 if (!MemOps.empty())
2135 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2136 &MemOps[0], MemOps.size());
2138 // This will point to the next argument passed via stack.
2139 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset,
2146 /// isFloatingPointZero - Return true if this is +0.0.
2147 static bool isFloatingPointZero(SDValue Op) {
2148 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2149 return CFP->getValueAPF().isPosZero();
2150 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2151 // Maybe this has already been legalized into the constant pool?
2152 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2153 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2154 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2155 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2156 return CFP->getValueAPF().isPosZero();
2162 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2163 /// the given operands.
2165 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2166 SDValue &ARMCC, SelectionDAG &DAG,
2167 DebugLoc dl) const {
2168 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2169 unsigned C = RHSC->getZExtValue();
2170 if (!isLegalICmpImmediate(C)) {
2171 // Constant does not fit, try adjusting it by one?
2176 if (isLegalICmpImmediate(C-1)) {
2177 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2178 RHS = DAG.getConstant(C-1, MVT::i32);
2183 if (C > 0 && isLegalICmpImmediate(C-1)) {
2184 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2185 RHS = DAG.getConstant(C-1, MVT::i32);
2190 if (isLegalICmpImmediate(C+1)) {
2191 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2192 RHS = DAG.getConstant(C+1, MVT::i32);
2197 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
2198 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2199 RHS = DAG.getConstant(C+1, MVT::i32);
2206 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2207 ARMISD::NodeType CompareType;
2210 CompareType = ARMISD::CMP;
2215 CompareType = ARMISD::CMPZ;
2218 ARMCC = DAG.getConstant(CondCode, MVT::i32);
2219 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2222 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2223 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2226 if (!isFloatingPointZero(RHS))
2227 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2229 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2230 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2233 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2234 EVT VT = Op.getValueType();
2235 SDValue LHS = Op.getOperand(0);
2236 SDValue RHS = Op.getOperand(1);
2237 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2238 SDValue TrueVal = Op.getOperand(2);
2239 SDValue FalseVal = Op.getOperand(3);
2240 DebugLoc dl = Op.getDebugLoc();
2242 if (LHS.getValueType() == MVT::i32) {
2244 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2245 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2246 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
2249 ARMCC::CondCodes CondCode, CondCode2;
2250 FPCCToARMCC(CC, CondCode, CondCode2);
2252 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2253 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2254 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2255 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2257 if (CondCode2 != ARMCC::AL) {
2258 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
2259 // FIXME: Needs another CMP because flag can have but one use.
2260 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2261 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2262 Result, TrueVal, ARMCC2, CCR, Cmp2);
2267 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2268 SDValue Chain = Op.getOperand(0);
2269 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2270 SDValue LHS = Op.getOperand(2);
2271 SDValue RHS = Op.getOperand(3);
2272 SDValue Dest = Op.getOperand(4);
2273 DebugLoc dl = Op.getDebugLoc();
2275 if (LHS.getValueType() == MVT::i32) {
2277 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2278 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2279 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2280 Chain, Dest, ARMCC, CCR,Cmp);
2283 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2284 ARMCC::CondCodes CondCode, CondCode2;
2285 FPCCToARMCC(CC, CondCode, CondCode2);
2287 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2288 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2289 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2290 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2291 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
2292 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2293 if (CondCode2 != ARMCC::AL) {
2294 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
2295 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
2296 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2301 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2302 SDValue Chain = Op.getOperand(0);
2303 SDValue Table = Op.getOperand(1);
2304 SDValue Index = Op.getOperand(2);
2305 DebugLoc dl = Op.getDebugLoc();
2307 EVT PTy = getPointerTy();
2308 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2309 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2310 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2311 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2312 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2313 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2314 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2315 if (Subtarget->isThumb2()) {
2316 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2317 // which does another jump to the destination. This also makes it easier
2318 // to translate it to TBB / TBH later.
2319 // FIXME: This might not work if the function is extremely large.
2320 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2321 Addr, Op.getOperand(2), JTI, UId);
2323 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2324 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2325 PseudoSourceValue::getJumpTable(), 0,
2327 Chain = Addr.getValue(1);
2328 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2329 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2331 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2332 PseudoSourceValue::getJumpTable(), 0, false, false, 0);
2333 Chain = Addr.getValue(1);
2334 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2338 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2339 DebugLoc dl = Op.getDebugLoc();
2342 switch (Op.getOpcode()) {
2344 assert(0 && "Invalid opcode!");
2345 case ISD::FP_TO_SINT:
2346 Opc = ARMISD::FTOSI;
2348 case ISD::FP_TO_UINT:
2349 Opc = ARMISD::FTOUI;
2352 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2353 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2356 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2357 EVT VT = Op.getValueType();
2358 DebugLoc dl = Op.getDebugLoc();
2361 switch (Op.getOpcode()) {
2363 assert(0 && "Invalid opcode!");
2364 case ISD::SINT_TO_FP:
2365 Opc = ARMISD::SITOF;
2367 case ISD::UINT_TO_FP:
2368 Opc = ARMISD::UITOF;
2372 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2373 return DAG.getNode(Opc, dl, VT, Op);
2376 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
2377 // Implement fcopysign with a fabs and a conditional fneg.
2378 SDValue Tmp0 = Op.getOperand(0);
2379 SDValue Tmp1 = Op.getOperand(1);
2380 DebugLoc dl = Op.getDebugLoc();
2381 EVT VT = Op.getValueType();
2382 EVT SrcVT = Tmp1.getValueType();
2383 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2384 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
2385 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
2386 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2387 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
2390 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2391 MachineFunction &MF = DAG.getMachineFunction();
2392 MachineFrameInfo *MFI = MF.getFrameInfo();
2393 MFI->setReturnAddressIsTaken(true);
2395 EVT VT = Op.getValueType();
2396 DebugLoc dl = Op.getDebugLoc();
2397 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2399 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2400 SDValue Offset = DAG.getConstant(4, MVT::i32);
2401 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2402 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2403 NULL, 0, false, false, 0);
2406 // Return LR, which contains the return address. Mark it an implicit live-in.
2407 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
2408 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2411 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2412 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2413 MFI->setFrameAddressIsTaken(true);
2415 EVT VT = Op.getValueType();
2416 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2417 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2418 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2419 ? ARM::R7 : ARM::R11;
2420 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2422 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
2427 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2428 /// expand a bit convert where either the source or destination type is i64 to
2429 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2430 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2431 /// vectors), since the legalizer won't know what to do with that.
2432 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2433 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2434 DebugLoc dl = N->getDebugLoc();
2435 SDValue Op = N->getOperand(0);
2437 // This function is only supposed to be called for i64 types, either as the
2438 // source or destination of the bit convert.
2439 EVT SrcVT = Op.getValueType();
2440 EVT DstVT = N->getValueType(0);
2441 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2442 "ExpandBIT_CONVERT called for non-i64 type");
2444 // Turn i64->f64 into VMOVDRR.
2445 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2446 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2447 DAG.getConstant(0, MVT::i32));
2448 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2449 DAG.getConstant(1, MVT::i32));
2450 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2451 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2454 // Turn f64->i64 into VMOVRRD.
2455 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2456 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2457 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2458 // Merge the pieces into a single i64 value.
2459 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2465 /// getZeroVector - Returns a vector of specified type with all zero elements.
2467 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2468 assert(VT.isVector() && "Expected a vector type");
2470 // Zero vectors are used to represent vector negation and in those cases
2471 // will be implemented with the NEON VNEG instruction. However, VNEG does
2472 // not support i64 elements, so sometimes the zero vectors will need to be
2473 // explicitly constructed. For those cases, and potentially other uses in
2474 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
2475 // to their dest type. This ensures they get CSE'd.
2477 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2478 SmallVector<SDValue, 8> Ops;
2481 if (VT.getSizeInBits() == 64) {
2482 Ops.assign(8, Cst); TVT = MVT::v8i8;
2484 Ops.assign(16, Cst); TVT = MVT::v16i8;
2486 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2488 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2491 /// getOnesVector - Returns a vector of specified type with all bits set.
2493 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2494 assert(VT.isVector() && "Expected a vector type");
2496 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their
2497 // dest type. This ensures they get CSE'd.
2499 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2500 SmallVector<SDValue, 8> Ops;
2503 if (VT.getSizeInBits() == 64) {
2504 Ops.assign(8, Cst); TVT = MVT::v8i8;
2506 Ops.assign(16, Cst); TVT = MVT::v16i8;
2508 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2510 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2513 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2514 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2515 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2516 SelectionDAG &DAG) const {
2517 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2518 EVT VT = Op.getValueType();
2519 unsigned VTBits = VT.getSizeInBits();
2520 DebugLoc dl = Op.getDebugLoc();
2521 SDValue ShOpLo = Op.getOperand(0);
2522 SDValue ShOpHi = Op.getOperand(1);
2523 SDValue ShAmt = Op.getOperand(2);
2525 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2527 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2529 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2530 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2531 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2532 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2533 DAG.getConstant(VTBits, MVT::i32));
2534 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2535 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2536 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2538 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2539 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2541 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2542 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
2545 SDValue Ops[2] = { Lo, Hi };
2546 return DAG.getMergeValues(Ops, 2, dl);
2549 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2550 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2551 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2552 SelectionDAG &DAG) const {
2553 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2554 EVT VT = Op.getValueType();
2555 unsigned VTBits = VT.getSizeInBits();
2556 DebugLoc dl = Op.getDebugLoc();
2557 SDValue ShOpLo = Op.getOperand(0);
2558 SDValue ShOpHi = Op.getOperand(1);
2559 SDValue ShAmt = Op.getOperand(2);
2562 assert(Op.getOpcode() == ISD::SHL_PARTS);
2563 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2564 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2565 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2566 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2567 DAG.getConstant(VTBits, MVT::i32));
2568 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2569 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2571 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2572 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2573 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2575 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2576 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
2579 SDValue Ops[2] = { Lo, Hi };
2580 return DAG.getMergeValues(Ops, 2, dl);
2583 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2584 const ARMSubtarget *ST) {
2585 EVT VT = N->getValueType(0);
2586 DebugLoc dl = N->getDebugLoc();
2588 if (!ST->hasV6T2Ops())
2591 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2592 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2595 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2596 const ARMSubtarget *ST) {
2597 EVT VT = N->getValueType(0);
2598 DebugLoc dl = N->getDebugLoc();
2600 // Lower vector shifts on NEON to use VSHL.
2601 if (VT.isVector()) {
2602 assert(ST->hasNEON() && "unexpected vector shift");
2604 // Left shifts translate directly to the vshiftu intrinsic.
2605 if (N->getOpcode() == ISD::SHL)
2606 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2607 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2608 N->getOperand(0), N->getOperand(1));
2610 assert((N->getOpcode() == ISD::SRA ||
2611 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2613 // NEON uses the same intrinsics for both left and right shifts. For
2614 // right shifts, the shift amounts are negative, so negate the vector of
2616 EVT ShiftVT = N->getOperand(1).getValueType();
2617 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2618 getZeroVector(ShiftVT, DAG, dl),
2620 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2621 Intrinsic::arm_neon_vshifts :
2622 Intrinsic::arm_neon_vshiftu);
2623 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2624 DAG.getConstant(vshiftInt, MVT::i32),
2625 N->getOperand(0), NegatedCount);
2628 // We can get here for a node like i32 = ISD::SHL i32, i64
2632 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2633 "Unknown shift to lower!");
2635 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2636 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2637 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2640 // If we are in thumb mode, we don't have RRX.
2641 if (ST->isThumb1Only()) return SDValue();
2643 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2644 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2645 DAG.getConstant(0, MVT::i32));
2646 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2647 DAG.getConstant(1, MVT::i32));
2649 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2650 // captures the result into a carry flag.
2651 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2652 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2654 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2655 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2657 // Merge the pieces into a single i64 value.
2658 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2661 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2662 SDValue TmpOp0, TmpOp1;
2663 bool Invert = false;
2667 SDValue Op0 = Op.getOperand(0);
2668 SDValue Op1 = Op.getOperand(1);
2669 SDValue CC = Op.getOperand(2);
2670 EVT VT = Op.getValueType();
2671 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2672 DebugLoc dl = Op.getDebugLoc();
2674 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2675 switch (SetCCOpcode) {
2676 default: llvm_unreachable("Illegal FP comparison"); break;
2678 case ISD::SETNE: Invert = true; // Fallthrough
2680 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2682 case ISD::SETLT: Swap = true; // Fallthrough
2684 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2686 case ISD::SETLE: Swap = true; // Fallthrough
2688 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2689 case ISD::SETUGE: Swap = true; // Fallthrough
2690 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2691 case ISD::SETUGT: Swap = true; // Fallthrough
2692 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2693 case ISD::SETUEQ: Invert = true; // Fallthrough
2695 // Expand this to (OLT | OGT).
2699 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2700 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2702 case ISD::SETUO: Invert = true; // Fallthrough
2704 // Expand this to (OLT | OGE).
2708 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2709 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2713 // Integer comparisons.
2714 switch (SetCCOpcode) {
2715 default: llvm_unreachable("Illegal integer comparison"); break;
2716 case ISD::SETNE: Invert = true;
2717 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2718 case ISD::SETLT: Swap = true;
2719 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2720 case ISD::SETLE: Swap = true;
2721 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2722 case ISD::SETULT: Swap = true;
2723 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2724 case ISD::SETULE: Swap = true;
2725 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2728 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2729 if (Opc == ARMISD::VCEQ) {
2732 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2734 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2737 // Ignore bitconvert.
2738 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2739 AndOp = AndOp.getOperand(0);
2741 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2743 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2744 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2751 std::swap(Op0, Op1);
2753 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2756 Result = DAG.getNOT(dl, Result, VT);
2761 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2762 /// VMOV instruction. If so, return either the constant being splatted or the
2763 /// encoded value, depending on the DoEncode parameter. The format of the
2764 /// encoded value is: bit12=Op, bits11-8=Cmode, bits7-0=Immediate.
2765 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2766 unsigned SplatBitSize, SelectionDAG &DAG,
2768 unsigned Op, Cmode, Imm;
2772 switch (SplatBitSize) {
2774 // Any 1-byte value is OK. Op=0, Cmode=1110.
2775 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2782 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2784 if ((SplatBits & ~0xff) == 0) {
2785 // Value = 0x00nn: Op=x, Cmode=100x.
2790 if ((SplatBits & ~0xff00) == 0) {
2791 // Value = 0xnn00: Op=x, Cmode=101x.
2793 Imm = SplatBits >> 8;
2799 // NEON's 32-bit VMOV supports splat values where:
2800 // * only one byte is nonzero, or
2801 // * the least significant byte is 0xff and the second byte is nonzero, or
2802 // * the least significant 2 bytes are 0xff and the third is nonzero.
2804 if ((SplatBits & ~0xff) == 0) {
2805 // Value = 0x000000nn: Op=x, Cmode=000x.
2810 if ((SplatBits & ~0xff00) == 0) {
2811 // Value = 0x0000nn00: Op=x, Cmode=001x.
2813 Imm = SplatBits >> 8;
2816 if ((SplatBits & ~0xff0000) == 0) {
2817 // Value = 0x00nn0000: Op=x, Cmode=010x.
2819 Imm = SplatBits >> 16;
2822 if ((SplatBits & ~0xff000000) == 0) {
2823 // Value = 0xnn000000: Op=x, Cmode=011x.
2825 Imm = SplatBits >> 24;
2829 if ((SplatBits & ~0xffff) == 0 &&
2830 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
2831 // Value = 0x0000nnff: Op=x, Cmode=1100.
2833 Imm = SplatBits >> 8;
2838 if ((SplatBits & ~0xffffff) == 0 &&
2839 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
2840 // Value = 0x00nnffff: Op=x, Cmode=1101.
2842 Imm = SplatBits >> 16;
2843 SplatBits |= 0xffff;
2847 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2848 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2849 // VMOV.I32. A (very) minor optimization would be to replicate the value
2850 // and fall through here to test for a valid 64-bit splat. But, then the
2851 // caller would also need to check and handle the change in size.
2855 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2856 uint64_t BitMask = 0xff;
2858 unsigned ImmMask = 1;
2860 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2861 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
2864 } else if ((SplatBits & BitMask) != 0) {
2870 // Op=1, Cmode=1110.
2879 llvm_unreachable("unexpected size for EncodeNEONModImm");
2884 return DAG.getTargetConstant((Op << 12) | (Cmode << 8) | Imm, MVT::i32);
2885 return DAG.getTargetConstant(SplatBits, VT);
2888 /// getVMOVImm - If this is a build_vector of constants which can be
2889 /// formed by using a VMOV instruction of the specified element size,
2890 /// return the constant being splatted. The ByteSize field indicates the
2891 /// number of bytes of each element [1248].
2892 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2893 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2894 APInt SplatBits, SplatUndef;
2895 unsigned SplatBitSize;
2897 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2898 HasAnyUndefs, ByteSize * 8))
2901 if (SplatBitSize > ByteSize * 8)
2904 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2905 SplatBitSize, DAG, true);
2908 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2909 bool &ReverseVEXT, unsigned &Imm) {
2910 unsigned NumElts = VT.getVectorNumElements();
2911 ReverseVEXT = false;
2914 // If this is a VEXT shuffle, the immediate value is the index of the first
2915 // element. The other shuffle indices must be the successive elements after
2917 unsigned ExpectedElt = Imm;
2918 for (unsigned i = 1; i < NumElts; ++i) {
2919 // Increment the expected index. If it wraps around, it may still be
2920 // a VEXT but the source vectors must be swapped.
2922 if (ExpectedElt == NumElts * 2) {
2927 if (ExpectedElt != static_cast<unsigned>(M[i]))
2931 // Adjust the index value if the source operands will be swapped.
2938 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2939 /// instruction with the specified blocksize. (The order of the elements
2940 /// within each block of the vector is reversed.)
2941 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2942 unsigned BlockSize) {
2943 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2944 "Only possible block sizes for VREV are: 16, 32, 64");
2946 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2950 unsigned NumElts = VT.getVectorNumElements();
2951 unsigned BlockElts = M[0] + 1;
2953 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2956 for (unsigned i = 0; i < NumElts; ++i) {
2957 if ((unsigned) M[i] !=
2958 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2965 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
2966 unsigned &WhichResult) {
2967 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2971 unsigned NumElts = VT.getVectorNumElements();
2972 WhichResult = (M[0] == 0 ? 0 : 1);
2973 for (unsigned i = 0; i < NumElts; i += 2) {
2974 if ((unsigned) M[i] != i + WhichResult ||
2975 (unsigned) M[i+1] != i + NumElts + WhichResult)
2981 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
2982 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2983 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
2984 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2985 unsigned &WhichResult) {
2986 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2990 unsigned NumElts = VT.getVectorNumElements();
2991 WhichResult = (M[0] == 0 ? 0 : 1);
2992 for (unsigned i = 0; i < NumElts; i += 2) {
2993 if ((unsigned) M[i] != i + WhichResult ||
2994 (unsigned) M[i+1] != i + WhichResult)
3000 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3001 unsigned &WhichResult) {
3002 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3006 unsigned NumElts = VT.getVectorNumElements();
3007 WhichResult = (M[0] == 0 ? 0 : 1);
3008 for (unsigned i = 0; i != NumElts; ++i) {
3009 if ((unsigned) M[i] != 2 * i + WhichResult)
3013 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3014 if (VT.is64BitVector() && EltSz == 32)
3020 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3021 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3022 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3023 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3024 unsigned &WhichResult) {
3025 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3029 unsigned Half = VT.getVectorNumElements() / 2;
3030 WhichResult = (M[0] == 0 ? 0 : 1);
3031 for (unsigned j = 0; j != 2; ++j) {
3032 unsigned Idx = WhichResult;
3033 for (unsigned i = 0; i != Half; ++i) {
3034 if ((unsigned) M[i + j * Half] != Idx)
3040 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3041 if (VT.is64BitVector() && EltSz == 32)
3047 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3048 unsigned &WhichResult) {
3049 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3053 unsigned NumElts = VT.getVectorNumElements();
3054 WhichResult = (M[0] == 0 ? 0 : 1);
3055 unsigned Idx = WhichResult * NumElts / 2;
3056 for (unsigned i = 0; i != NumElts; i += 2) {
3057 if ((unsigned) M[i] != Idx ||
3058 (unsigned) M[i+1] != Idx + NumElts)
3063 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3064 if (VT.is64BitVector() && EltSz == 32)
3070 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3071 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3072 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3073 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3074 unsigned &WhichResult) {
3075 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3079 unsigned NumElts = VT.getVectorNumElements();
3080 WhichResult = (M[0] == 0 ? 0 : 1);
3081 unsigned Idx = WhichResult * NumElts / 2;
3082 for (unsigned i = 0; i != NumElts; i += 2) {
3083 if ((unsigned) M[i] != Idx ||
3084 (unsigned) M[i+1] != Idx)
3089 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3090 if (VT.is64BitVector() && EltSz == 32)
3097 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3098 // Canonicalize all-zeros and all-ones vectors.
3099 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
3100 if (ConstVal->isNullValue())
3101 return getZeroVector(VT, DAG, dl);
3102 if (ConstVal->isAllOnesValue())
3103 return getOnesVector(VT, DAG, dl);
3106 if (VT.is64BitVector()) {
3107 switch (Val.getValueType().getSizeInBits()) {
3108 case 8: CanonicalVT = MVT::v8i8; break;
3109 case 16: CanonicalVT = MVT::v4i16; break;
3110 case 32: CanonicalVT = MVT::v2i32; break;
3111 case 64: CanonicalVT = MVT::v1i64; break;
3112 default: llvm_unreachable("unexpected splat element type"); break;
3115 assert(VT.is128BitVector() && "unknown splat vector size");
3116 switch (Val.getValueType().getSizeInBits()) {
3117 case 8: CanonicalVT = MVT::v16i8; break;
3118 case 16: CanonicalVT = MVT::v8i16; break;
3119 case 32: CanonicalVT = MVT::v4i32; break;
3120 case 64: CanonicalVT = MVT::v2i64; break;
3121 default: llvm_unreachable("unexpected splat element type"); break;
3125 // Build a canonical splat for this value.
3126 SmallVector<SDValue, 8> Ops;
3127 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
3128 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
3130 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
3133 // If this is a case we can't handle, return null and let the default
3134 // expansion code take care of it.
3135 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3136 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3137 DebugLoc dl = Op.getDebugLoc();
3138 EVT VT = Op.getValueType();
3140 APInt SplatBits, SplatUndef;
3141 unsigned SplatBitSize;
3143 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3144 if (SplatBitSize <= 64) {
3145 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
3146 SplatUndef.getZExtValue(), SplatBitSize, DAG,
3149 return BuildSplat(Val, VT, DAG, dl);
3153 // Scan through the operands to see if only one value is used.
3154 unsigned NumElts = VT.getVectorNumElements();
3155 bool isOnlyLowElement = true;
3156 bool usesOnlyOneValue = true;
3157 bool isConstant = true;
3159 for (unsigned i = 0; i < NumElts; ++i) {
3160 SDValue V = Op.getOperand(i);
3161 if (V.getOpcode() == ISD::UNDEF)
3164 isOnlyLowElement = false;
3165 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3168 if (!Value.getNode())
3170 else if (V != Value)
3171 usesOnlyOneValue = false;
3174 if (!Value.getNode())
3175 return DAG.getUNDEF(VT);
3177 if (isOnlyLowElement)
3178 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3180 // If all elements are constants, fall back to the default expansion, which
3181 // will generate a load from the constant pool.
3185 // Use VDUP for non-constant splats.
3186 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3187 if (usesOnlyOneValue && EltSize <= 32)
3188 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3190 // Vectors with 32- or 64-bit elements can be built by directly assigning
3191 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3192 // will be legalized.
3193 if (EltSize >= 32) {
3194 // Do the expansion with floating-point types, since that is what the VFP
3195 // registers are defined to use, and since i64 is not legal.
3196 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3197 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3198 SmallVector<SDValue, 8> Ops;
3199 for (unsigned i = 0; i < NumElts; ++i)
3200 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3201 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3202 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3208 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3209 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3210 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3211 /// are assumed to be legal.
3213 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3215 if (VT.getVectorNumElements() == 4 &&
3216 (VT.is128BitVector() || VT.is64BitVector())) {
3217 unsigned PFIndexes[4];
3218 for (unsigned i = 0; i != 4; ++i) {
3222 PFIndexes[i] = M[i];
3225 // Compute the index in the perfect shuffle table.
3226 unsigned PFTableIndex =
3227 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3228 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3229 unsigned Cost = (PFEntry >> 30);
3236 unsigned Imm, WhichResult;
3238 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3239 return (EltSize >= 32 ||
3240 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3241 isVREVMask(M, VT, 64) ||
3242 isVREVMask(M, VT, 32) ||
3243 isVREVMask(M, VT, 16) ||
3244 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3245 isVTRNMask(M, VT, WhichResult) ||
3246 isVUZPMask(M, VT, WhichResult) ||
3247 isVZIPMask(M, VT, WhichResult) ||
3248 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3249 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3250 isVZIP_v_undef_Mask(M, VT, WhichResult));
3253 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3254 /// the specified operations to build the shuffle.
3255 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3256 SDValue RHS, SelectionDAG &DAG,
3258 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3259 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3260 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3263 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3272 OP_VUZPL, // VUZP, left result
3273 OP_VUZPR, // VUZP, right result
3274 OP_VZIPL, // VZIP, left result
3275 OP_VZIPR, // VZIP, right result
3276 OP_VTRNL, // VTRN, left result
3277 OP_VTRNR // VTRN, right result
3280 if (OpNum == OP_COPY) {
3281 if (LHSID == (1*9+2)*9+3) return LHS;
3282 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3286 SDValue OpLHS, OpRHS;
3287 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3288 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3289 EVT VT = OpLHS.getValueType();
3292 default: llvm_unreachable("Unknown shuffle opcode!");
3294 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3299 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3300 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3304 return DAG.getNode(ARMISD::VEXT, dl, VT,
3306 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3309 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3310 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3313 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3314 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3317 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3318 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3322 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3323 SDValue V1 = Op.getOperand(0);
3324 SDValue V2 = Op.getOperand(1);
3325 DebugLoc dl = Op.getDebugLoc();
3326 EVT VT = Op.getValueType();
3327 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3328 SmallVector<int, 8> ShuffleMask;
3330 // Convert shuffles that are directly supported on NEON to target-specific
3331 // DAG nodes, instead of keeping them as shuffles and matching them again
3332 // during code selection. This is more efficient and avoids the possibility
3333 // of inconsistencies between legalization and selection.
3334 // FIXME: floating-point vectors should be canonicalized to integer vectors
3335 // of the same time so that they get CSEd properly.
3336 SVN->getMask(ShuffleMask);
3338 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3339 if (EltSize <= 32) {
3340 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3341 int Lane = SVN->getSplatIndex();
3342 // If this is undef splat, generate it via "just" vdup, if possible.
3343 if (Lane == -1) Lane = 0;
3345 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3346 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3348 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3349 DAG.getConstant(Lane, MVT::i32));
3354 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3357 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3358 DAG.getConstant(Imm, MVT::i32));
3361 if (isVREVMask(ShuffleMask, VT, 64))
3362 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3363 if (isVREVMask(ShuffleMask, VT, 32))
3364 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3365 if (isVREVMask(ShuffleMask, VT, 16))
3366 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3368 // Check for Neon shuffles that modify both input vectors in place.
3369 // If both results are used, i.e., if there are two shuffles with the same
3370 // source operands and with masks corresponding to both results of one of
3371 // these operations, DAG memoization will ensure that a single node is
3372 // used for both shuffles.
3373 unsigned WhichResult;
3374 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3375 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3376 V1, V2).getValue(WhichResult);
3377 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3378 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3379 V1, V2).getValue(WhichResult);
3380 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3381 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3382 V1, V2).getValue(WhichResult);
3384 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3385 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3386 V1, V1).getValue(WhichResult);
3387 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3388 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3389 V1, V1).getValue(WhichResult);
3390 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3391 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3392 V1, V1).getValue(WhichResult);
3395 // If the shuffle is not directly supported and it has 4 elements, use
3396 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3397 unsigned NumElts = VT.getVectorNumElements();
3399 unsigned PFIndexes[4];
3400 for (unsigned i = 0; i != 4; ++i) {
3401 if (ShuffleMask[i] < 0)
3404 PFIndexes[i] = ShuffleMask[i];
3407 // Compute the index in the perfect shuffle table.
3408 unsigned PFTableIndex =
3409 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3410 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3411 unsigned Cost = (PFEntry >> 30);
3414 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3417 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3418 if (EltSize >= 32) {
3419 // Do the expansion with floating-point types, since that is what the VFP
3420 // registers are defined to use, and since i64 is not legal.
3421 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3422 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3423 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3424 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3425 SmallVector<SDValue, 8> Ops;
3426 for (unsigned i = 0; i < NumElts; ++i) {
3427 if (ShuffleMask[i] < 0)
3428 Ops.push_back(DAG.getUNDEF(EltVT));
3430 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3431 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3432 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3435 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3436 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3442 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3443 EVT VT = Op.getValueType();
3444 DebugLoc dl = Op.getDebugLoc();
3445 SDValue Vec = Op.getOperand(0);
3446 SDValue Lane = Op.getOperand(1);
3447 assert(VT == MVT::i32 &&
3448 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3449 "unexpected type for custom-lowering vector extract");
3450 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3453 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3454 // The only time a CONCAT_VECTORS operation can have legal types is when
3455 // two 64-bit vectors are concatenated to a 128-bit vector.
3456 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3457 "unexpected CONCAT_VECTORS");
3458 DebugLoc dl = Op.getDebugLoc();
3459 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3460 SDValue Op0 = Op.getOperand(0);
3461 SDValue Op1 = Op.getOperand(1);
3462 if (Op0.getOpcode() != ISD::UNDEF)
3463 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3464 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3465 DAG.getIntPtrConstant(0));
3466 if (Op1.getOpcode() != ISD::UNDEF)
3467 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3468 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3469 DAG.getIntPtrConstant(1));
3470 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3473 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3474 switch (Op.getOpcode()) {
3475 default: llvm_unreachable("Don't know how to custom lower this!");
3476 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3477 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3478 case ISD::GlobalAddress:
3479 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3480 LowerGlobalAddressELF(Op, DAG);
3481 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3482 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3483 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3484 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3485 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3486 case ISD::VASTART: return LowerVASTART(Op, DAG);
3487 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3488 case ISD::SINT_TO_FP:
3489 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3490 case ISD::FP_TO_SINT:
3491 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3492 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3493 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3494 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3495 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3496 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3497 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3498 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3500 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3503 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3504 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3505 case ISD::SRL_PARTS:
3506 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3507 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3508 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3509 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3510 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3511 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3512 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3517 /// ReplaceNodeResults - Replace the results of node with an illegal result
3518 /// type with new values built out of custom code.
3519 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3520 SmallVectorImpl<SDValue>&Results,
3521 SelectionDAG &DAG) const {
3523 switch (N->getOpcode()) {
3525 llvm_unreachable("Don't know how to custom expand this!");
3527 case ISD::BIT_CONVERT:
3528 Res = ExpandBIT_CONVERT(N, DAG);
3532 Res = LowerShift(N, DAG, Subtarget);
3536 Results.push_back(Res);
3539 //===----------------------------------------------------------------------===//
3540 // ARM Scheduler Hooks
3541 //===----------------------------------------------------------------------===//
3544 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3545 MachineBasicBlock *BB,
3546 unsigned Size) const {
3547 unsigned dest = MI->getOperand(0).getReg();
3548 unsigned ptr = MI->getOperand(1).getReg();
3549 unsigned oldval = MI->getOperand(2).getReg();
3550 unsigned newval = MI->getOperand(3).getReg();
3551 unsigned scratch = BB->getParent()->getRegInfo()
3552 .createVirtualRegister(ARM::GPRRegisterClass);
3553 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3554 DebugLoc dl = MI->getDebugLoc();
3555 bool isThumb2 = Subtarget->isThumb2();
3557 unsigned ldrOpc, strOpc;
3559 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3561 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3562 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3565 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3566 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3569 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3570 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3574 MachineFunction *MF = BB->getParent();
3575 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3576 MachineFunction::iterator It = BB;
3577 ++It; // insert the new blocks after the current block
3579 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3580 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3581 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3582 MF->insert(It, loop1MBB);
3583 MF->insert(It, loop2MBB);
3584 MF->insert(It, exitMBB);
3585 exitMBB->transferSuccessors(BB);
3589 // fallthrough --> loop1MBB
3590 BB->addSuccessor(loop1MBB);
3593 // ldrex dest, [ptr]
3597 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3598 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3599 .addReg(dest).addReg(oldval));
3600 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3601 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3602 BB->addSuccessor(loop2MBB);
3603 BB->addSuccessor(exitMBB);
3606 // strex scratch, newval, [ptr]
3610 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3612 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3613 .addReg(scratch).addImm(0));
3614 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3615 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3616 BB->addSuccessor(loop1MBB);
3617 BB->addSuccessor(exitMBB);
3623 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3629 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3630 unsigned Size, unsigned BinOpcode) const {
3631 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3632 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3634 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3635 MachineFunction *MF = BB->getParent();
3636 MachineFunction::iterator It = BB;
3639 unsigned dest = MI->getOperand(0).getReg();
3640 unsigned ptr = MI->getOperand(1).getReg();
3641 unsigned incr = MI->getOperand(2).getReg();
3642 DebugLoc dl = MI->getDebugLoc();
3644 bool isThumb2 = Subtarget->isThumb2();
3645 unsigned ldrOpc, strOpc;
3647 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3649 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3650 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3653 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3654 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3657 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3658 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3662 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3663 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3664 MF->insert(It, loopMBB);
3665 MF->insert(It, exitMBB);
3666 exitMBB->transferSuccessors(BB);
3668 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3669 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3670 unsigned scratch2 = (!BinOpcode) ? incr :
3671 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3675 // fallthrough --> loopMBB
3676 BB->addSuccessor(loopMBB);
3680 // <binop> scratch2, dest, incr
3681 // strex scratch, scratch2, ptr
3684 // fallthrough --> exitMBB
3686 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3688 // operand order needs to go the other way for NAND
3689 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3690 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3691 addReg(incr).addReg(dest)).addReg(0);
3693 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3694 addReg(dest).addReg(incr)).addReg(0);
3697 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3699 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3700 .addReg(scratch).addImm(0));
3701 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3702 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3704 BB->addSuccessor(loopMBB);
3705 BB->addSuccessor(exitMBB);
3711 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3717 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3718 MachineBasicBlock *BB) const {
3719 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3720 DebugLoc dl = MI->getDebugLoc();
3721 bool isThumb2 = Subtarget->isThumb2();
3722 switch (MI->getOpcode()) {
3725 llvm_unreachable("Unexpected instr type to insert");
3727 case ARM::ATOMIC_LOAD_ADD_I8:
3728 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3729 case ARM::ATOMIC_LOAD_ADD_I16:
3730 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3731 case ARM::ATOMIC_LOAD_ADD_I32:
3732 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3734 case ARM::ATOMIC_LOAD_AND_I8:
3735 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3736 case ARM::ATOMIC_LOAD_AND_I16:
3737 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3738 case ARM::ATOMIC_LOAD_AND_I32:
3739 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3741 case ARM::ATOMIC_LOAD_OR_I8:
3742 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3743 case ARM::ATOMIC_LOAD_OR_I16:
3744 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3745 case ARM::ATOMIC_LOAD_OR_I32:
3746 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3748 case ARM::ATOMIC_LOAD_XOR_I8:
3749 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3750 case ARM::ATOMIC_LOAD_XOR_I16:
3751 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3752 case ARM::ATOMIC_LOAD_XOR_I32:
3753 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3755 case ARM::ATOMIC_LOAD_NAND_I8:
3756 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3757 case ARM::ATOMIC_LOAD_NAND_I16:
3758 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3759 case ARM::ATOMIC_LOAD_NAND_I32:
3760 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3762 case ARM::ATOMIC_LOAD_SUB_I8:
3763 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3764 case ARM::ATOMIC_LOAD_SUB_I16:
3765 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3766 case ARM::ATOMIC_LOAD_SUB_I32:
3767 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3769 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3770 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3771 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3773 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3774 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3775 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3777 case ARM::tMOVCCr_pseudo: {
3778 // To "insert" a SELECT_CC instruction, we actually have to insert the
3779 // diamond control-flow pattern. The incoming instruction knows the
3780 // destination vreg to set, the condition code register to branch on, the
3781 // true/false values to select between, and a branch opcode to use.
3782 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3783 MachineFunction::iterator It = BB;
3789 // cmpTY ccX, r1, r2
3791 // fallthrough --> copy0MBB
3792 MachineBasicBlock *thisMBB = BB;
3793 MachineFunction *F = BB->getParent();
3794 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3795 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3796 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3797 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3798 F->insert(It, copy0MBB);
3799 F->insert(It, sinkMBB);
3800 // Update machine-CFG edges by first adding all successors of the current
3801 // block to the new block which will contain the Phi node for the select.
3802 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
3803 E = BB->succ_end(); I != E; ++I)
3804 sinkMBB->addSuccessor(*I);
3805 // Next, remove all successors of the current block, and add the true
3806 // and fallthrough blocks as its successors.
3807 while (!BB->succ_empty())
3808 BB->removeSuccessor(BB->succ_begin());
3809 BB->addSuccessor(copy0MBB);
3810 BB->addSuccessor(sinkMBB);
3813 // %FalseValue = ...
3814 // # fallthrough to sinkMBB
3817 // Update machine-CFG edges
3818 BB->addSuccessor(sinkMBB);
3821 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3824 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
3825 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3826 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3828 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3835 case ARM::t2SUBrSPi_:
3836 case ARM::t2SUBrSPi12_:
3837 case ARM::t2SUBrSPs_: {
3838 MachineFunction *MF = BB->getParent();
3839 unsigned DstReg = MI->getOperand(0).getReg();
3840 unsigned SrcReg = MI->getOperand(1).getReg();
3841 bool DstIsDead = MI->getOperand(0).isDead();
3842 bool SrcIsKill = MI->getOperand(1).isKill();
3844 if (SrcReg != ARM::SP) {
3845 // Copy the source to SP from virtual register.
3846 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
3847 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3848 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
3849 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
3850 .addReg(SrcReg, getKillRegState(SrcIsKill));
3854 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
3855 switch (MI->getOpcode()) {
3857 llvm_unreachable("Unexpected pseudo instruction!");
3863 OpOpc = ARM::tADDspr;
3866 OpOpc = ARM::tSUBspi;
3868 case ARM::t2SUBrSPi_:
3869 OpOpc = ARM::t2SUBrSPi;
3870 NeedPred = true; NeedCC = true;
3872 case ARM::t2SUBrSPi12_:
3873 OpOpc = ARM::t2SUBrSPi12;
3876 case ARM::t2SUBrSPs_:
3877 OpOpc = ARM::t2SUBrSPs;
3878 NeedPred = true; NeedCC = true; NeedOp3 = true;
3881 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
3882 if (OpOpc == ARM::tAND)
3883 AddDefaultT1CC(MIB);
3884 MIB.addReg(ARM::SP);
3885 MIB.addOperand(MI->getOperand(2));
3887 MIB.addOperand(MI->getOperand(3));
3889 AddDefaultPred(MIB);
3893 // Copy the result from SP to virtual register.
3894 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
3895 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3896 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
3897 BuildMI(BB, dl, TII->get(CopyOpc))
3898 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
3900 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3906 //===----------------------------------------------------------------------===//
3907 // ARM Optimization Hooks
3908 //===----------------------------------------------------------------------===//
3911 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
3912 TargetLowering::DAGCombinerInfo &DCI) {
3913 SelectionDAG &DAG = DCI.DAG;
3914 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3915 EVT VT = N->getValueType(0);
3916 unsigned Opc = N->getOpcode();
3917 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
3918 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
3919 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
3920 ISD::CondCode CC = ISD::SETCC_INVALID;
3923 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
3925 SDValue CCOp = Slct.getOperand(0);
3926 if (CCOp.getOpcode() == ISD::SETCC)
3927 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
3930 bool DoXform = false;
3932 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
3935 if (LHS.getOpcode() == ISD::Constant &&
3936 cast<ConstantSDNode>(LHS)->isNullValue()) {
3938 } else if (CC != ISD::SETCC_INVALID &&
3939 RHS.getOpcode() == ISD::Constant &&
3940 cast<ConstantSDNode>(RHS)->isNullValue()) {
3941 std::swap(LHS, RHS);
3942 SDValue Op0 = Slct.getOperand(0);
3943 EVT OpVT = isSlctCC ? Op0.getValueType() :
3944 Op0.getOperand(0).getValueType();
3945 bool isInt = OpVT.isInteger();
3946 CC = ISD::getSetCCInverse(CC, isInt);
3948 if (!TLI.isCondCodeLegal(CC, OpVT))
3949 return SDValue(); // Inverse operator isn't legal.
3956 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
3958 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
3959 Slct.getOperand(0), Slct.getOperand(1), CC);
3960 SDValue CCOp = Slct.getOperand(0);
3962 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
3963 CCOp.getOperand(0), CCOp.getOperand(1), CC);
3964 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3965 CCOp, OtherOp, Result);
3970 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3971 static SDValue PerformADDCombine(SDNode *N,
3972 TargetLowering::DAGCombinerInfo &DCI) {
3973 // added by evan in r37685 with no testcase.
3974 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3976 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
3977 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
3978 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
3979 if (Result.getNode()) return Result;
3981 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3982 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3983 if (Result.getNode()) return Result;
3989 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
3990 static SDValue PerformSUBCombine(SDNode *N,
3991 TargetLowering::DAGCombinerInfo &DCI) {
3992 // added by evan in r37685 with no testcase.
3993 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3995 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
3996 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3997 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3998 if (Result.getNode()) return Result;
4004 static SDValue PerformMULCombine(SDNode *N,
4005 TargetLowering::DAGCombinerInfo &DCI,
4006 const ARMSubtarget *Subtarget) {
4007 SelectionDAG &DAG = DCI.DAG;
4009 if (Subtarget->isThumb1Only())
4012 if (DAG.getMachineFunction().
4013 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
4016 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4019 EVT VT = N->getValueType(0);
4023 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4027 uint64_t MulAmt = C->getZExtValue();
4028 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4029 ShiftAmt = ShiftAmt & (32 - 1);
4030 SDValue V = N->getOperand(0);
4031 DebugLoc DL = N->getDebugLoc();
4034 MulAmt >>= ShiftAmt;
4035 if (isPowerOf2_32(MulAmt - 1)) {
4036 // (mul x, 2^N + 1) => (add (shl x, N), x)
4037 Res = DAG.getNode(ISD::ADD, DL, VT,
4038 V, DAG.getNode(ISD::SHL, DL, VT,
4039 V, DAG.getConstant(Log2_32(MulAmt-1),
4041 } else if (isPowerOf2_32(MulAmt + 1)) {
4042 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4043 Res = DAG.getNode(ISD::SUB, DL, VT,
4044 DAG.getNode(ISD::SHL, DL, VT,
4045 V, DAG.getConstant(Log2_32(MulAmt+1),
4052 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4053 DAG.getConstant(ShiftAmt, MVT::i32));
4055 // Do not add new nodes to DAG combiner worklist.
4056 DCI.CombineTo(N, Res, false);
4060 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4061 /// ARMISD::VMOVRRD.
4062 static SDValue PerformVMOVRRDCombine(SDNode *N,
4063 TargetLowering::DAGCombinerInfo &DCI) {
4064 // fmrrd(fmdrr x, y) -> x,y
4065 SDValue InDouble = N->getOperand(0);
4066 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4067 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4071 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4072 /// operand of a vector shift operation, where all the elements of the
4073 /// build_vector must have the same constant integer value.
4074 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4075 // Ignore bit_converts.
4076 while (Op.getOpcode() == ISD::BIT_CONVERT)
4077 Op = Op.getOperand(0);
4078 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4079 APInt SplatBits, SplatUndef;
4080 unsigned SplatBitSize;
4082 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4083 HasAnyUndefs, ElementBits) ||
4084 SplatBitSize > ElementBits)
4086 Cnt = SplatBits.getSExtValue();
4090 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4091 /// operand of a vector shift left operation. That value must be in the range:
4092 /// 0 <= Value < ElementBits for a left shift; or
4093 /// 0 <= Value <= ElementBits for a long left shift.
4094 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4095 assert(VT.isVector() && "vector shift count is not a vector type");
4096 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4097 if (! getVShiftImm(Op, ElementBits, Cnt))
4099 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4102 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4103 /// operand of a vector shift right operation. For a shift opcode, the value
4104 /// is positive, but for an intrinsic the value count must be negative. The
4105 /// absolute value must be in the range:
4106 /// 1 <= |Value| <= ElementBits for a right shift; or
4107 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4108 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4110 assert(VT.isVector() && "vector shift count is not a vector type");
4111 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4112 if (! getVShiftImm(Op, ElementBits, Cnt))
4116 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4119 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4120 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4121 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4124 // Don't do anything for most intrinsics.
4127 // Vector shifts: check for immediate versions and lower them.
4128 // Note: This is done during DAG combining instead of DAG legalizing because
4129 // the build_vectors for 64-bit vector element shift counts are generally
4130 // not legal, and it is hard to see their values after they get legalized to
4131 // loads from a constant pool.
4132 case Intrinsic::arm_neon_vshifts:
4133 case Intrinsic::arm_neon_vshiftu:
4134 case Intrinsic::arm_neon_vshiftls:
4135 case Intrinsic::arm_neon_vshiftlu:
4136 case Intrinsic::arm_neon_vshiftn:
4137 case Intrinsic::arm_neon_vrshifts:
4138 case Intrinsic::arm_neon_vrshiftu:
4139 case Intrinsic::arm_neon_vrshiftn:
4140 case Intrinsic::arm_neon_vqshifts:
4141 case Intrinsic::arm_neon_vqshiftu:
4142 case Intrinsic::arm_neon_vqshiftsu:
4143 case Intrinsic::arm_neon_vqshiftns:
4144 case Intrinsic::arm_neon_vqshiftnu:
4145 case Intrinsic::arm_neon_vqshiftnsu:
4146 case Intrinsic::arm_neon_vqrshiftns:
4147 case Intrinsic::arm_neon_vqrshiftnu:
4148 case Intrinsic::arm_neon_vqrshiftnsu: {
4149 EVT VT = N->getOperand(1).getValueType();
4151 unsigned VShiftOpc = 0;
4154 case Intrinsic::arm_neon_vshifts:
4155 case Intrinsic::arm_neon_vshiftu:
4156 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4157 VShiftOpc = ARMISD::VSHL;
4160 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4161 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4162 ARMISD::VSHRs : ARMISD::VSHRu);
4167 case Intrinsic::arm_neon_vshiftls:
4168 case Intrinsic::arm_neon_vshiftlu:
4169 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4171 llvm_unreachable("invalid shift count for vshll intrinsic");
4173 case Intrinsic::arm_neon_vrshifts:
4174 case Intrinsic::arm_neon_vrshiftu:
4175 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4179 case Intrinsic::arm_neon_vqshifts:
4180 case Intrinsic::arm_neon_vqshiftu:
4181 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4185 case Intrinsic::arm_neon_vqshiftsu:
4186 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4188 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4190 case Intrinsic::arm_neon_vshiftn:
4191 case Intrinsic::arm_neon_vrshiftn:
4192 case Intrinsic::arm_neon_vqshiftns:
4193 case Intrinsic::arm_neon_vqshiftnu:
4194 case Intrinsic::arm_neon_vqshiftnsu:
4195 case Intrinsic::arm_neon_vqrshiftns:
4196 case Intrinsic::arm_neon_vqrshiftnu:
4197 case Intrinsic::arm_neon_vqrshiftnsu:
4198 // Narrowing shifts require an immediate right shift.
4199 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4201 llvm_unreachable("invalid shift count for narrowing vector shift "
4205 llvm_unreachable("unhandled vector shift");
4209 case Intrinsic::arm_neon_vshifts:
4210 case Intrinsic::arm_neon_vshiftu:
4211 // Opcode already set above.
4213 case Intrinsic::arm_neon_vshiftls:
4214 case Intrinsic::arm_neon_vshiftlu:
4215 if (Cnt == VT.getVectorElementType().getSizeInBits())
4216 VShiftOpc = ARMISD::VSHLLi;
4218 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4219 ARMISD::VSHLLs : ARMISD::VSHLLu);
4221 case Intrinsic::arm_neon_vshiftn:
4222 VShiftOpc = ARMISD::VSHRN; break;
4223 case Intrinsic::arm_neon_vrshifts:
4224 VShiftOpc = ARMISD::VRSHRs; break;
4225 case Intrinsic::arm_neon_vrshiftu:
4226 VShiftOpc = ARMISD::VRSHRu; break;
4227 case Intrinsic::arm_neon_vrshiftn:
4228 VShiftOpc = ARMISD::VRSHRN; break;
4229 case Intrinsic::arm_neon_vqshifts:
4230 VShiftOpc = ARMISD::VQSHLs; break;
4231 case Intrinsic::arm_neon_vqshiftu:
4232 VShiftOpc = ARMISD::VQSHLu; break;
4233 case Intrinsic::arm_neon_vqshiftsu:
4234 VShiftOpc = ARMISD::VQSHLsu; break;
4235 case Intrinsic::arm_neon_vqshiftns:
4236 VShiftOpc = ARMISD::VQSHRNs; break;
4237 case Intrinsic::arm_neon_vqshiftnu:
4238 VShiftOpc = ARMISD::VQSHRNu; break;
4239 case Intrinsic::arm_neon_vqshiftnsu:
4240 VShiftOpc = ARMISD::VQSHRNsu; break;
4241 case Intrinsic::arm_neon_vqrshiftns:
4242 VShiftOpc = ARMISD::VQRSHRNs; break;
4243 case Intrinsic::arm_neon_vqrshiftnu:
4244 VShiftOpc = ARMISD::VQRSHRNu; break;
4245 case Intrinsic::arm_neon_vqrshiftnsu:
4246 VShiftOpc = ARMISD::VQRSHRNsu; break;
4249 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4250 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4253 case Intrinsic::arm_neon_vshiftins: {
4254 EVT VT = N->getOperand(1).getValueType();
4256 unsigned VShiftOpc = 0;
4258 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4259 VShiftOpc = ARMISD::VSLI;
4260 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4261 VShiftOpc = ARMISD::VSRI;
4263 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4266 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4267 N->getOperand(1), N->getOperand(2),
4268 DAG.getConstant(Cnt, MVT::i32));
4271 case Intrinsic::arm_neon_vqrshifts:
4272 case Intrinsic::arm_neon_vqrshiftu:
4273 // No immediate versions of these to check for.
4280 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4281 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4282 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4283 /// vector element shift counts are generally not legal, and it is hard to see
4284 /// their values after they get legalized to loads from a constant pool.
4285 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4286 const ARMSubtarget *ST) {
4287 EVT VT = N->getValueType(0);
4289 // Nothing to be done for scalar shifts.
4290 if (! VT.isVector())
4293 assert(ST->hasNEON() && "unexpected vector shift");
4296 switch (N->getOpcode()) {
4297 default: llvm_unreachable("unexpected shift opcode");
4300 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4301 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4302 DAG.getConstant(Cnt, MVT::i32));
4307 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4308 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4309 ARMISD::VSHRs : ARMISD::VSHRu);
4310 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4311 DAG.getConstant(Cnt, MVT::i32));
4317 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4318 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4319 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4320 const ARMSubtarget *ST) {
4321 SDValue N0 = N->getOperand(0);
4323 // Check for sign- and zero-extensions of vector extract operations of 8-
4324 // and 16-bit vector elements. NEON supports these directly. They are
4325 // handled during DAG combining because type legalization will promote them
4326 // to 32-bit types and it is messy to recognize the operations after that.
4327 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4328 SDValue Vec = N0.getOperand(0);
4329 SDValue Lane = N0.getOperand(1);
4330 EVT VT = N->getValueType(0);
4331 EVT EltVT = N0.getValueType();
4332 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4334 if (VT == MVT::i32 &&
4335 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4336 TLI.isTypeLegal(Vec.getValueType())) {
4339 switch (N->getOpcode()) {
4340 default: llvm_unreachable("unexpected opcode");
4341 case ISD::SIGN_EXTEND:
4342 Opc = ARMISD::VGETLANEs;
4344 case ISD::ZERO_EXTEND:
4345 case ISD::ANY_EXTEND:
4346 Opc = ARMISD::VGETLANEu;
4349 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4356 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4357 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4358 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4359 const ARMSubtarget *ST) {
4360 // If the target supports NEON, try to use vmax/vmin instructions for f32
4361 // selects like "x < y ? x : y". Unless the FiniteOnlyFPMath option is set,
4362 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4363 // a NaN; only do the transformation when it matches that behavior.
4365 // For now only do this when using NEON for FP operations; if using VFP, it
4366 // is not obvious that the benefit outweighs the cost of switching to the
4368 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4369 N->getValueType(0) != MVT::f32)
4372 SDValue CondLHS = N->getOperand(0);
4373 SDValue CondRHS = N->getOperand(1);
4374 SDValue LHS = N->getOperand(2);
4375 SDValue RHS = N->getOperand(3);
4376 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4378 unsigned Opcode = 0;
4380 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4381 IsReversed = false; // x CC y ? x : y
4382 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4383 IsReversed = true ; // x CC y ? y : x
4397 // If LHS is NaN, an ordered comparison will be false and the result will
4398 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4399 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4400 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4401 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4403 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4404 // will return -0, so vmin can only be used for unsafe math or if one of
4405 // the operands is known to be nonzero.
4406 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4408 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4410 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4419 // If LHS is NaN, an ordered comparison will be false and the result will
4420 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4421 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4422 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4423 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4425 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4426 // will return +0, so vmax can only be used for unsafe math or if one of
4427 // the operands is known to be nonzero.
4428 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4430 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4432 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4438 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4441 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4442 DAGCombinerInfo &DCI) const {
4443 switch (N->getOpcode()) {
4445 case ISD::ADD: return PerformADDCombine(N, DCI);
4446 case ISD::SUB: return PerformSUBCombine(N, DCI);
4447 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4448 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4449 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4452 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4453 case ISD::SIGN_EXTEND:
4454 case ISD::ZERO_EXTEND:
4455 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4456 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4461 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4462 if (!Subtarget->hasV6Ops())
4463 // Pre-v6 does not support unaligned mem access.
4466 // v6+ may or may not support unaligned mem access depending on the system
4468 // FIXME: This is pretty conservative. Should we provide cmdline option to
4469 // control the behaviour?
4470 if (!Subtarget->isTargetDarwin())
4474 switch (VT.getSimpleVT().SimpleTy) {
4481 // FIXME: VLD1 etc with standard alignment is legal.
4485 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4490 switch (VT.getSimpleVT().SimpleTy) {
4491 default: return false;
4506 if ((V & (Scale - 1)) != 0)
4509 return V == (V & ((1LL << 5) - 1));
4512 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4513 const ARMSubtarget *Subtarget) {
4520 switch (VT.getSimpleVT().SimpleTy) {
4521 default: return false;
4526 // + imm12 or - imm8
4528 return V == (V & ((1LL << 8) - 1));
4529 return V == (V & ((1LL << 12) - 1));
4532 // Same as ARM mode. FIXME: NEON?
4533 if (!Subtarget->hasVFP2())
4538 return V == (V & ((1LL << 8) - 1));
4542 /// isLegalAddressImmediate - Return true if the integer value can be used
4543 /// as the offset of the target addressing mode for load / store of the
4545 static bool isLegalAddressImmediate(int64_t V, EVT VT,
4546 const ARMSubtarget *Subtarget) {
4553 if (Subtarget->isThumb1Only())
4554 return isLegalT1AddressImmediate(V, VT);
4555 else if (Subtarget->isThumb2())
4556 return isLegalT2AddressImmediate(V, VT, Subtarget);
4561 switch (VT.getSimpleVT().SimpleTy) {
4562 default: return false;
4567 return V == (V & ((1LL << 12) - 1));
4570 return V == (V & ((1LL << 8) - 1));
4573 if (!Subtarget->hasVFP2()) // FIXME: NEON?
4578 return V == (V & ((1LL << 8) - 1));
4582 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
4584 int Scale = AM.Scale;
4588 switch (VT.getSimpleVT().SimpleTy) {
4589 default: return false;
4598 return Scale == 2 || Scale == 4 || Scale == 8;
4601 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4605 // Note, we allow "void" uses (basically, uses that aren't loads or
4606 // stores), because arm allows folding a scale into many arithmetic
4607 // operations. This should be made more precise and revisited later.
4609 // Allow r << imm, but the imm has to be a multiple of two.
4610 if (Scale & 1) return false;
4611 return isPowerOf2_32(Scale);
4615 /// isLegalAddressingMode - Return true if the addressing mode represented
4616 /// by AM is legal for this target, for a load/store of the specified type.
4617 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4618 const Type *Ty) const {
4619 EVT VT = getValueType(Ty, true);
4620 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4623 // Can never fold addr of global into load/store.
4628 case 0: // no scale reg, must be "r+i" or "r", or "i".
4631 if (Subtarget->isThumb1Only())
4635 // ARM doesn't support any R+R*scale+imm addr modes.
4642 if (Subtarget->isThumb2())
4643 return isLegalT2ScaledAddressingMode(AM, VT);
4645 int Scale = AM.Scale;
4646 switch (VT.getSimpleVT().SimpleTy) {
4647 default: return false;
4651 if (Scale < 0) Scale = -Scale;
4655 return isPowerOf2_32(Scale & ~1);
4659 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4664 // Note, we allow "void" uses (basically, uses that aren't loads or
4665 // stores), because arm allows folding a scale into many arithmetic
4666 // operations. This should be made more precise and revisited later.
4668 // Allow r << imm, but the imm has to be a multiple of two.
4669 if (Scale & 1) return false;
4670 return isPowerOf2_32(Scale);
4677 /// isLegalICmpImmediate - Return true if the specified immediate is legal
4678 /// icmp immediate, that is the target has icmp instructions which can compare
4679 /// a register against the immediate without having to materialize the
4680 /// immediate into a register.
4681 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4682 if (!Subtarget->isThumb())
4683 return ARM_AM::getSOImmVal(Imm) != -1;
4684 if (Subtarget->isThumb2())
4685 return ARM_AM::getT2SOImmVal(Imm) != -1;
4686 return Imm >= 0 && Imm <= 255;
4689 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
4690 bool isSEXTLoad, SDValue &Base,
4691 SDValue &Offset, bool &isInc,
4692 SelectionDAG &DAG) {
4693 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4696 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
4698 Base = Ptr->getOperand(0);
4699 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4700 int RHSC = (int)RHS->getZExtValue();
4701 if (RHSC < 0 && RHSC > -256) {
4702 assert(Ptr->getOpcode() == ISD::ADD);
4704 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4708 isInc = (Ptr->getOpcode() == ISD::ADD);
4709 Offset = Ptr->getOperand(1);
4711 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
4713 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4714 int RHSC = (int)RHS->getZExtValue();
4715 if (RHSC < 0 && RHSC > -0x1000) {
4716 assert(Ptr->getOpcode() == ISD::ADD);
4718 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4719 Base = Ptr->getOperand(0);
4724 if (Ptr->getOpcode() == ISD::ADD) {
4726 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4727 if (ShOpcVal != ARM_AM::no_shift) {
4728 Base = Ptr->getOperand(1);
4729 Offset = Ptr->getOperand(0);
4731 Base = Ptr->getOperand(0);
4732 Offset = Ptr->getOperand(1);
4737 isInc = (Ptr->getOpcode() == ISD::ADD);
4738 Base = Ptr->getOperand(0);
4739 Offset = Ptr->getOperand(1);
4743 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
4747 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
4748 bool isSEXTLoad, SDValue &Base,
4749 SDValue &Offset, bool &isInc,
4750 SelectionDAG &DAG) {
4751 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4754 Base = Ptr->getOperand(0);
4755 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4756 int RHSC = (int)RHS->getZExtValue();
4757 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
4758 assert(Ptr->getOpcode() == ISD::ADD);
4760 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4762 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
4763 isInc = Ptr->getOpcode() == ISD::ADD;
4764 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
4772 /// getPreIndexedAddressParts - returns true by value, base pointer and
4773 /// offset pointer and addressing mode by reference if the node's address
4774 /// can be legally represented as pre-indexed load / store address.
4776 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
4778 ISD::MemIndexedMode &AM,
4779 SelectionDAG &DAG) const {
4780 if (Subtarget->isThumb1Only())
4785 bool isSEXTLoad = false;
4786 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4787 Ptr = LD->getBasePtr();
4788 VT = LD->getMemoryVT();
4789 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4790 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4791 Ptr = ST->getBasePtr();
4792 VT = ST->getMemoryVT();
4797 bool isLegal = false;
4798 if (Subtarget->isThumb2())
4799 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4800 Offset, isInc, DAG);
4802 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4803 Offset, isInc, DAG);
4807 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
4811 /// getPostIndexedAddressParts - returns true by value, base pointer and
4812 /// offset pointer and addressing mode by reference if this node can be
4813 /// combined with a load / store to form a post-indexed load / store.
4814 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
4817 ISD::MemIndexedMode &AM,
4818 SelectionDAG &DAG) const {
4819 if (Subtarget->isThumb1Only())
4824 bool isSEXTLoad = false;
4825 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4826 VT = LD->getMemoryVT();
4827 Ptr = LD->getBasePtr();
4828 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4829 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4830 VT = ST->getMemoryVT();
4831 Ptr = ST->getBasePtr();
4836 bool isLegal = false;
4837 if (Subtarget->isThumb2())
4838 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4841 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4847 // Swap base ptr and offset to catch more post-index load / store when
4848 // it's legal. In Thumb2 mode, offset must be an immediate.
4849 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
4850 !Subtarget->isThumb2())
4851 std::swap(Base, Offset);
4853 // Post-indexed load / store update the base pointer.
4858 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
4862 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4866 const SelectionDAG &DAG,
4867 unsigned Depth) const {
4868 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4869 switch (Op.getOpcode()) {
4871 case ARMISD::CMOV: {
4872 // Bits are known zero/one if known on the LHS and RHS.
4873 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
4874 if (KnownZero == 0 && KnownOne == 0) return;
4876 APInt KnownZeroRHS, KnownOneRHS;
4877 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
4878 KnownZeroRHS, KnownOneRHS, Depth+1);
4879 KnownZero &= KnownZeroRHS;
4880 KnownOne &= KnownOneRHS;
4886 //===----------------------------------------------------------------------===//
4887 // ARM Inline Assembly Support
4888 //===----------------------------------------------------------------------===//
4890 /// getConstraintType - Given a constraint letter, return the type of
4891 /// constraint it is for this target.
4892 ARMTargetLowering::ConstraintType
4893 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
4894 if (Constraint.size() == 1) {
4895 switch (Constraint[0]) {
4897 case 'l': return C_RegisterClass;
4898 case 'w': return C_RegisterClass;
4901 return TargetLowering::getConstraintType(Constraint);
4904 std::pair<unsigned, const TargetRegisterClass*>
4905 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4907 if (Constraint.size() == 1) {
4908 // GCC ARM Constraint Letters
4909 switch (Constraint[0]) {
4911 if (Subtarget->isThumb())
4912 return std::make_pair(0U, ARM::tGPRRegisterClass);
4914 return std::make_pair(0U, ARM::GPRRegisterClass);
4916 return std::make_pair(0U, ARM::GPRRegisterClass);
4919 return std::make_pair(0U, ARM::SPRRegisterClass);
4920 if (VT.getSizeInBits() == 64)
4921 return std::make_pair(0U, ARM::DPRRegisterClass);
4922 if (VT.getSizeInBits() == 128)
4923 return std::make_pair(0U, ARM::QPRRegisterClass);
4927 if (StringRef("{cc}").equals_lower(Constraint))
4928 return std::make_pair(0U, ARM::CCRRegisterClass);
4930 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4933 std::vector<unsigned> ARMTargetLowering::
4934 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4936 if (Constraint.size() != 1)
4937 return std::vector<unsigned>();
4939 switch (Constraint[0]) { // GCC ARM Constraint Letters
4942 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4943 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4946 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4947 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4948 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
4949 ARM::R12, ARM::LR, 0);
4952 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
4953 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
4954 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
4955 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
4956 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
4957 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
4958 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
4959 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
4960 if (VT.getSizeInBits() == 64)
4961 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
4962 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
4963 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
4964 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
4965 if (VT.getSizeInBits() == 128)
4966 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
4967 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
4971 return std::vector<unsigned>();
4974 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4975 /// vector. If it is invalid, don't add anything to Ops.
4976 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4979 std::vector<SDValue>&Ops,
4980 SelectionDAG &DAG) const {
4981 SDValue Result(0, 0);
4983 switch (Constraint) {
4985 case 'I': case 'J': case 'K': case 'L':
4986 case 'M': case 'N': case 'O':
4987 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4991 int64_t CVal64 = C->getSExtValue();
4992 int CVal = (int) CVal64;
4993 // None of these constraints allow values larger than 32 bits. Check
4994 // that the value fits in an int.
4998 switch (Constraint) {
5000 if (Subtarget->isThumb1Only()) {
5001 // This must be a constant between 0 and 255, for ADD
5003 if (CVal >= 0 && CVal <= 255)
5005 } else if (Subtarget->isThumb2()) {
5006 // A constant that can be used as an immediate value in a
5007 // data-processing instruction.
5008 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5011 // A constant that can be used as an immediate value in a
5012 // data-processing instruction.
5013 if (ARM_AM::getSOImmVal(CVal) != -1)
5019 if (Subtarget->isThumb()) { // FIXME thumb2
5020 // This must be a constant between -255 and -1, for negated ADD
5021 // immediates. This can be used in GCC with an "n" modifier that
5022 // prints the negated value, for use with SUB instructions. It is
5023 // not useful otherwise but is implemented for compatibility.
5024 if (CVal >= -255 && CVal <= -1)
5027 // This must be a constant between -4095 and 4095. It is not clear
5028 // what this constraint is intended for. Implemented for
5029 // compatibility with GCC.
5030 if (CVal >= -4095 && CVal <= 4095)
5036 if (Subtarget->isThumb1Only()) {
5037 // A 32-bit value where only one byte has a nonzero value. Exclude
5038 // zero to match GCC. This constraint is used by GCC internally for
5039 // constants that can be loaded with a move/shift combination.
5040 // It is not useful otherwise but is implemented for compatibility.
5041 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5043 } else if (Subtarget->isThumb2()) {
5044 // A constant whose bitwise inverse can be used as an immediate
5045 // value in a data-processing instruction. This can be used in GCC
5046 // with a "B" modifier that prints the inverted value, for use with
5047 // BIC and MVN instructions. It is not useful otherwise but is
5048 // implemented for compatibility.
5049 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5052 // A constant whose bitwise inverse can be used as an immediate
5053 // value in a data-processing instruction. This can be used in GCC
5054 // with a "B" modifier that prints the inverted value, for use with
5055 // BIC and MVN instructions. It is not useful otherwise but is
5056 // implemented for compatibility.
5057 if (ARM_AM::getSOImmVal(~CVal) != -1)
5063 if (Subtarget->isThumb1Only()) {
5064 // This must be a constant between -7 and 7,
5065 // for 3-operand ADD/SUB immediate instructions.
5066 if (CVal >= -7 && CVal < 7)
5068 } else if (Subtarget->isThumb2()) {
5069 // A constant whose negation can be used as an immediate value in a
5070 // data-processing instruction. This can be used in GCC with an "n"
5071 // modifier that prints the negated value, for use with SUB
5072 // instructions. It is not useful otherwise but is implemented for
5074 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5077 // A constant whose negation can be used as an immediate value in a
5078 // data-processing instruction. This can be used in GCC with an "n"
5079 // modifier that prints the negated value, for use with SUB
5080 // instructions. It is not useful otherwise but is implemented for
5082 if (ARM_AM::getSOImmVal(-CVal) != -1)
5088 if (Subtarget->isThumb()) { // FIXME thumb2
5089 // This must be a multiple of 4 between 0 and 1020, for
5090 // ADD sp + immediate.
5091 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5094 // A power of two or a constant between 0 and 32. This is used in
5095 // GCC for the shift amount on shifted register operands, but it is
5096 // useful in general for any shift amounts.
5097 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5103 if (Subtarget->isThumb()) { // FIXME thumb2
5104 // This must be a constant between 0 and 31, for shift amounts.
5105 if (CVal >= 0 && CVal <= 31)
5111 if (Subtarget->isThumb()) { // FIXME thumb2
5112 // This must be a multiple of 4 between -508 and 508, for
5113 // ADD/SUB sp = sp + immediate.
5114 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5119 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5123 if (Result.getNode()) {
5124 Ops.push_back(Result);
5127 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
5132 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5133 // The ARM target isn't yet aware of offsets.
5137 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5138 APInt Imm = FPImm.bitcastToAPInt();
5139 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5140 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5141 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5143 // We can handle 4 bits of mantissa.
5144 // mantissa = (16+UInt(e:f:g:h))/16.
5145 if (Mantissa & 0x7ffff)
5148 if ((Mantissa & 0xf) != Mantissa)
5151 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5152 if (Exp < -3 || Exp > 4)
5154 Exp = ((Exp+3) & 0x7) ^ 4;
5156 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5159 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5160 APInt Imm = FPImm.bitcastToAPInt();
5161 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5162 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5163 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5165 // We can handle 4 bits of mantissa.
5166 // mantissa = (16+UInt(e:f:g:h))/16.
5167 if (Mantissa & 0xffffffffffffLL)
5170 if ((Mantissa & 0xf) != Mantissa)
5173 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5174 if (Exp < -3 || Exp > 4)
5176 Exp = ((Exp+3) & 0x7) ^ 4;
5178 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5181 /// isFPImmLegal - Returns true if the target can instruction select the
5182 /// specified FP immediate natively. If false, the legalizer will
5183 /// materialize the FP immediate as a load from a constant pool.
5184 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5185 if (!Subtarget->hasVFP3())
5188 return ARM::getVFPf32Imm(Imm) != -1;
5190 return ARM::getVFPf64Imm(Imm) != -1;