1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMTargetMachine.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
41 DisableShifterOp("disable-shifter-op", cl::Hidden,
42 cl::desc("Disable isel of shifter-op"),
46 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47 cl::desc("Check fp vmla / vmls hazard at isel time"),
50 //===--------------------------------------------------------------------===//
51 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
52 /// instructions for SelectionDAG operations.
57 AM2_BASE, // Simple AM2 (+-imm12)
58 AM2_SHOP // Shifter-op AM2
61 class ARMDAGToDAGISel : public SelectionDAGISel {
62 ARMBaseTargetMachine &TM;
63 const ARMBaseInstrInfo *TII;
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when generating code for different targets.
67 const ARMSubtarget *Subtarget;
70 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
71 CodeGenOpt::Level OptLevel)
72 : SelectionDAGISel(tm, OptLevel), TM(tm),
73 TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
74 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
77 virtual const char *getPassName() const {
78 return "ARM Instruction Selection";
81 /// getI32Imm - Return a target constant of type i32 with the specified
83 inline SDValue getI32Imm(unsigned Imm) {
84 return CurDAG->getTargetConstant(Imm, MVT::i32);
87 SDNode *Select(SDNode *N);
90 bool hasNoVMLxHazardUse(SDNode *N) const;
91 bool isShifterOpProfitable(const SDValue &Shift,
92 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
93 bool SelectRegShifterOperand(SDValue N, SDValue &A,
94 SDValue &B, SDValue &C,
95 bool CheckProfitability = true);
96 bool SelectImmShifterOperand(SDValue N, SDValue &A,
97 SDValue &B, bool CheckProfitability = true);
98 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
99 SDValue &B, SDValue &C) {
100 // Don't apply the profitability check
101 return SelectRegShifterOperand(N, A, B, C, false);
103 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
105 // Don't apply the profitability check
106 return SelectImmShifterOperand(N, A, B, false);
109 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
110 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
112 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
113 SDValue &Offset, SDValue &Opc);
114 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
116 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
119 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
121 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
124 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
126 SelectAddrMode2Worker(N, Base, Offset, Opc);
127 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
128 // This always matches one way or another.
132 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
133 SDValue &Offset, SDValue &Opc);
134 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
135 SDValue &Offset, SDValue &Opc);
136 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
137 SDValue &Offset, SDValue &Opc);
138 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
139 bool SelectAddrMode3(SDValue N, SDValue &Base,
140 SDValue &Offset, SDValue &Opc);
141 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
142 SDValue &Offset, SDValue &Opc);
143 bool SelectAddrMode5(SDValue N, SDValue &Base,
145 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
146 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
148 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
150 // Thumb Addressing Modes:
151 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
152 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
154 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
155 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
156 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
157 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
159 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
161 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
163 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
165 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
167 // Thumb 2 Addressing Modes:
168 bool SelectT2ShifterOperandReg(SDValue N,
169 SDValue &BaseReg, SDValue &Opc);
170 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
171 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
173 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
175 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
176 SDValue &OffReg, SDValue &ShImm);
178 inline bool is_so_imm(unsigned Imm) const {
179 return ARM_AM::getSOImmVal(Imm) != -1;
182 inline bool is_so_imm_not(unsigned Imm) const {
183 return ARM_AM::getSOImmVal(~Imm) != -1;
186 inline bool is_t2_so_imm(unsigned Imm) const {
187 return ARM_AM::getT2SOImmVal(Imm) != -1;
190 inline bool is_t2_so_imm_not(unsigned Imm) const {
191 return ARM_AM::getT2SOImmVal(~Imm) != -1;
194 // Include the pieces autogenerated from the target description.
195 #include "ARMGenDAGISel.inc"
198 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
200 SDNode *SelectARMIndexedLoad(SDNode *N);
201 SDNode *SelectT2IndexedLoad(SDNode *N);
203 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
204 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
205 /// loads of D registers and even subregs and odd subregs of Q registers.
206 /// For NumVecs <= 2, QOpcodes1 is not used.
207 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
208 const uint16_t *DOpcodes,
209 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
211 /// SelectVST - Select NEON store intrinsics. NumVecs should
212 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
213 /// stores of D registers and even subregs and odd subregs of Q registers.
214 /// For NumVecs <= 2, QOpcodes1 is not used.
215 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
216 const uint16_t *DOpcodes,
217 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
219 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
220 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
221 /// load/store of D registers and Q registers.
222 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
223 bool isUpdating, unsigned NumVecs,
224 const uint16_t *DOpcodes, const uint16_t *QOpcodes);
226 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
227 /// should be 2, 3 or 4. The opcode array specifies the instructions used
228 /// for loading D registers. (Q registers are not supported.)
229 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
230 const uint16_t *Opcodes);
232 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
233 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
234 /// generated to force the table registers to be consecutive.
235 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
237 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
238 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
240 /// SelectCMOVOp - Select CMOV instructions for ARM.
241 SDNode *SelectCMOVOp(SDNode *N);
242 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
243 ARMCC::CondCodes CCVal, SDValue CCR,
245 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
246 ARMCC::CondCodes CCVal, SDValue CCR,
248 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
249 ARMCC::CondCodes CCVal, SDValue CCR,
251 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
252 ARMCC::CondCodes CCVal, SDValue CCR,
255 // Select special operations if node forms integer ABS pattern
256 SDNode *SelectABSOp(SDNode *N);
258 SDNode *SelectConcatVector(SDNode *N);
260 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
262 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
263 /// inline asm expressions.
264 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
266 std::vector<SDValue> &OutOps);
268 // Form pairs of consecutive R, S, D, or Q registers.
269 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
270 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
271 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
272 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
274 // Form sequences of 4 consecutive S, D, or Q registers.
275 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
276 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
277 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
279 // Get the alignment operand for a NEON VLD or VST instruction.
280 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
284 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
285 /// operand. If so Imm will receive the 32-bit value.
286 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
287 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
288 Imm = cast<ConstantSDNode>(N)->getZExtValue();
294 // isInt32Immediate - This method tests to see if a constant operand.
295 // If so Imm will receive the 32 bit value.
296 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
297 return isInt32Immediate(N.getNode(), Imm);
300 // isOpcWithIntImmediate - This method tests to see if the node is a specific
301 // opcode and that it has a immediate integer right operand.
302 // If so Imm will receive the 32 bit value.
303 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
304 return N->getOpcode() == Opc &&
305 isInt32Immediate(N->getOperand(1).getNode(), Imm);
308 /// \brief Check whether a particular node is a constant value representable as
309 /// (N * Scale) where (N in [\p RangeMin, \p RangeMax).
311 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
312 static bool isScaledConstantInRange(SDValue Node, int Scale,
313 int RangeMin, int RangeMax,
314 int &ScaledConstant) {
315 assert(Scale > 0 && "Invalid scale!");
317 // Check that this is a constant.
318 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
322 ScaledConstant = (int) C->getZExtValue();
323 if ((ScaledConstant % Scale) != 0)
326 ScaledConstant /= Scale;
327 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
330 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
331 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
332 /// least on current ARM implementations) which should be avoidded.
333 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
334 if (OptLevel == CodeGenOpt::None)
337 if (!CheckVMLxHazard)
340 if (!Subtarget->isCortexA8() && !Subtarget->isLikeA9() &&
341 !Subtarget->isSwift())
347 SDNode *Use = *N->use_begin();
348 if (Use->getOpcode() == ISD::CopyToReg)
350 if (Use->isMachineOpcode()) {
351 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
354 unsigned Opcode = MCID.getOpcode();
355 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
357 // vmlx feeding into another vmlx. We actually want to unfold
358 // the use later in the MLxExpansion pass. e.g.
360 // vmla (stall 8 cycles)
365 // This adds up to about 18 - 19 cycles.
368 // vmul (stall 4 cycles)
369 // vadd adds up to about 14 cycles.
370 return TII->isFpMLxInstruction(Opcode);
376 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
377 ARM_AM::ShiftOpc ShOpcVal,
379 if (!Subtarget->isLikeA9() && !Subtarget->isSwift())
381 if (Shift.hasOneUse())
384 return ShOpcVal == ARM_AM::lsl &&
385 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
388 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
391 bool CheckProfitability) {
392 if (DisableShifterOp)
395 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
397 // Don't match base register only case. That is matched to a separate
398 // lower complexity pattern with explicit register operand.
399 if (ShOpcVal == ARM_AM::no_shift) return false;
401 BaseReg = N.getOperand(0);
402 unsigned ShImmVal = 0;
403 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
404 if (!RHS) return false;
405 ShImmVal = RHS->getZExtValue() & 31;
406 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
411 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
415 bool CheckProfitability) {
416 if (DisableShifterOp)
419 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
421 // Don't match base register only case. That is matched to a separate
422 // lower complexity pattern with explicit register operand.
423 if (ShOpcVal == ARM_AM::no_shift) return false;
425 BaseReg = N.getOperand(0);
426 unsigned ShImmVal = 0;
427 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
428 if (RHS) return false;
430 ShReg = N.getOperand(1);
431 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
433 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
439 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
442 // Match simple R + imm12 operands.
445 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
446 !CurDAG->isBaseWithConstantOffset(N)) {
447 if (N.getOpcode() == ISD::FrameIndex) {
448 // Match frame index.
449 int FI = cast<FrameIndexSDNode>(N)->getIndex();
450 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
451 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
455 if (N.getOpcode() == ARMISD::Wrapper &&
456 !(Subtarget->useMovt() &&
457 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
458 Base = N.getOperand(0);
461 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
465 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
466 int RHSC = (int)RHS->getZExtValue();
467 if (N.getOpcode() == ISD::SUB)
470 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
471 Base = N.getOperand(0);
472 if (Base.getOpcode() == ISD::FrameIndex) {
473 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
474 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
476 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
483 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
489 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
491 if (N.getOpcode() == ISD::MUL &&
492 ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.hasOneUse())) {
493 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
494 // X * [3,5,9] -> X + X * [2,4,8] etc.
495 int RHSC = (int)RHS->getZExtValue();
498 ARM_AM::AddrOpc AddSub = ARM_AM::add;
500 AddSub = ARM_AM::sub;
503 if (isPowerOf2_32(RHSC)) {
504 unsigned ShAmt = Log2_32(RHSC);
505 Base = Offset = N.getOperand(0);
506 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
515 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
516 // ISD::OR that is equivalent to an ISD::ADD.
517 !CurDAG->isBaseWithConstantOffset(N))
520 // Leave simple R +/- imm12 operands for LDRi12
521 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
523 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
524 -0x1000+1, 0x1000, RHSC)) // 12 bits.
528 // Otherwise this is R +/- [possibly shifted] R.
529 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
530 ARM_AM::ShiftOpc ShOpcVal =
531 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
534 Base = N.getOperand(0);
535 Offset = N.getOperand(1);
537 if (ShOpcVal != ARM_AM::no_shift) {
538 // Check to see if the RHS of the shift is a constant, if not, we can't fold
540 if (ConstantSDNode *Sh =
541 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
542 ShAmt = Sh->getZExtValue();
543 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
544 Offset = N.getOperand(1).getOperand(0);
547 ShOpcVal = ARM_AM::no_shift;
550 ShOpcVal = ARM_AM::no_shift;
554 // Try matching (R shl C) + (R).
555 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
556 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
557 N.getOperand(0).hasOneUse())) {
558 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
559 if (ShOpcVal != ARM_AM::no_shift) {
560 // Check to see if the RHS of the shift is a constant, if not, we can't
562 if (ConstantSDNode *Sh =
563 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
564 ShAmt = Sh->getZExtValue();
565 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
566 Offset = N.getOperand(0).getOperand(0);
567 Base = N.getOperand(1);
570 ShOpcVal = ARM_AM::no_shift;
573 ShOpcVal = ARM_AM::no_shift;
578 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
586 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
590 if (N.getOpcode() == ISD::MUL &&
591 (!(Subtarget->isLikeA9() || Subtarget->isSwift()) || N.hasOneUse())) {
592 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
593 // X * [3,5,9] -> X + X * [2,4,8] etc.
594 int RHSC = (int)RHS->getZExtValue();
597 ARM_AM::AddrOpc AddSub = ARM_AM::add;
599 AddSub = ARM_AM::sub;
602 if (isPowerOf2_32(RHSC)) {
603 unsigned ShAmt = Log2_32(RHSC);
604 Base = Offset = N.getOperand(0);
605 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
614 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
615 // ISD::OR that is equivalent to an ADD.
616 !CurDAG->isBaseWithConstantOffset(N)) {
618 if (N.getOpcode() == ISD::FrameIndex) {
619 int FI = cast<FrameIndexSDNode>(N)->getIndex();
620 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
621 } else if (N.getOpcode() == ARMISD::Wrapper &&
622 !(Subtarget->useMovt() &&
623 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
624 Base = N.getOperand(0);
626 Offset = CurDAG->getRegister(0, MVT::i32);
627 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
633 // Match simple R +/- imm12 operands.
634 if (N.getOpcode() != ISD::SUB) {
636 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
637 -0x1000+1, 0x1000, RHSC)) { // 12 bits.
638 Base = N.getOperand(0);
639 if (Base.getOpcode() == ISD::FrameIndex) {
640 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
641 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
643 Offset = CurDAG->getRegister(0, MVT::i32);
645 ARM_AM::AddrOpc AddSub = ARM_AM::add;
647 AddSub = ARM_AM::sub;
650 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
657 if ((Subtarget->isLikeA9() || Subtarget->isSwift()) && !N.hasOneUse()) {
658 // Compute R +/- (R << N) and reuse it.
660 Offset = CurDAG->getRegister(0, MVT::i32);
661 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
667 // Otherwise this is R +/- [possibly shifted] R.
668 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
669 ARM_AM::ShiftOpc ShOpcVal =
670 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
673 Base = N.getOperand(0);
674 Offset = N.getOperand(1);
676 if (ShOpcVal != ARM_AM::no_shift) {
677 // Check to see if the RHS of the shift is a constant, if not, we can't fold
679 if (ConstantSDNode *Sh =
680 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
681 ShAmt = Sh->getZExtValue();
682 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
683 Offset = N.getOperand(1).getOperand(0);
686 ShOpcVal = ARM_AM::no_shift;
689 ShOpcVal = ARM_AM::no_shift;
693 // Try matching (R shl C) + (R).
694 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
695 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
696 N.getOperand(0).hasOneUse())) {
697 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
698 if (ShOpcVal != ARM_AM::no_shift) {
699 // Check to see if the RHS of the shift is a constant, if not, we can't
701 if (ConstantSDNode *Sh =
702 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
703 ShAmt = Sh->getZExtValue();
704 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
705 Offset = N.getOperand(0).getOperand(0);
706 Base = N.getOperand(1);
709 ShOpcVal = ARM_AM::no_shift;
712 ShOpcVal = ARM_AM::no_shift;
717 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
722 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
723 SDValue &Offset, SDValue &Opc) {
724 unsigned Opcode = Op->getOpcode();
725 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
726 ? cast<LoadSDNode>(Op)->getAddressingMode()
727 : cast<StoreSDNode>(Op)->getAddressingMode();
728 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
729 ? ARM_AM::add : ARM_AM::sub;
731 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
735 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
737 if (ShOpcVal != ARM_AM::no_shift) {
738 // Check to see if the RHS of the shift is a constant, if not, we can't fold
740 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
741 ShAmt = Sh->getZExtValue();
742 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
743 Offset = N.getOperand(0);
746 ShOpcVal = ARM_AM::no_shift;
749 ShOpcVal = ARM_AM::no_shift;
753 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
758 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
759 SDValue &Offset, SDValue &Opc) {
760 unsigned Opcode = Op->getOpcode();
761 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
762 ? cast<LoadSDNode>(Op)->getAddressingMode()
763 : cast<StoreSDNode>(Op)->getAddressingMode();
764 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
765 ? ARM_AM::add : ARM_AM::sub;
767 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
768 if (AddSub == ARM_AM::sub) Val *= -1;
769 Offset = CurDAG->getRegister(0, MVT::i32);
770 Opc = CurDAG->getTargetConstant(Val, MVT::i32);
778 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
779 SDValue &Offset, SDValue &Opc) {
780 unsigned Opcode = Op->getOpcode();
781 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
782 ? cast<LoadSDNode>(Op)->getAddressingMode()
783 : cast<StoreSDNode>(Op)->getAddressingMode();
784 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
785 ? ARM_AM::add : ARM_AM::sub;
787 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
788 Offset = CurDAG->getRegister(0, MVT::i32);
789 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
798 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
803 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
804 SDValue &Base, SDValue &Offset,
806 if (N.getOpcode() == ISD::SUB) {
807 // X - C is canonicalize to X + -C, no need to handle it here.
808 Base = N.getOperand(0);
809 Offset = N.getOperand(1);
810 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
814 if (!CurDAG->isBaseWithConstantOffset(N)) {
816 if (N.getOpcode() == ISD::FrameIndex) {
817 int FI = cast<FrameIndexSDNode>(N)->getIndex();
818 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
820 Offset = CurDAG->getRegister(0, MVT::i32);
821 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
825 // If the RHS is +/- imm8, fold into addr mode.
827 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
828 -256 + 1, 256, RHSC)) { // 8 bits.
829 Base = N.getOperand(0);
830 if (Base.getOpcode() == ISD::FrameIndex) {
831 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
832 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
834 Offset = CurDAG->getRegister(0, MVT::i32);
836 ARM_AM::AddrOpc AddSub = ARM_AM::add;
838 AddSub = ARM_AM::sub;
841 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
845 Base = N.getOperand(0);
846 Offset = N.getOperand(1);
847 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
851 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
852 SDValue &Offset, SDValue &Opc) {
853 unsigned Opcode = Op->getOpcode();
854 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
855 ? cast<LoadSDNode>(Op)->getAddressingMode()
856 : cast<StoreSDNode>(Op)->getAddressingMode();
857 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
858 ? ARM_AM::add : ARM_AM::sub;
860 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
861 Offset = CurDAG->getRegister(0, MVT::i32);
862 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
867 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
871 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
872 SDValue &Base, SDValue &Offset) {
873 if (!CurDAG->isBaseWithConstantOffset(N)) {
875 if (N.getOpcode() == ISD::FrameIndex) {
876 int FI = cast<FrameIndexSDNode>(N)->getIndex();
877 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
878 } else if (N.getOpcode() == ARMISD::Wrapper &&
879 !(Subtarget->useMovt() &&
880 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
881 Base = N.getOperand(0);
883 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
888 // If the RHS is +/- imm8, fold into addr mode.
890 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
891 -256 + 1, 256, RHSC)) {
892 Base = N.getOperand(0);
893 if (Base.getOpcode() == ISD::FrameIndex) {
894 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
895 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
898 ARM_AM::AddrOpc AddSub = ARM_AM::add;
900 AddSub = ARM_AM::sub;
903 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
909 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
914 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
918 unsigned Alignment = 0;
919 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
920 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
921 // The maximum alignment is equal to the memory size being referenced.
922 unsigned LSNAlign = LSN->getAlignment();
923 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
924 if (LSNAlign >= MemSize && MemSize > 1)
927 // All other uses of addrmode6 are for intrinsics. For now just record
928 // the raw alignment value; it will be refined later based on the legal
929 // alignment operands for the intrinsic.
930 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
933 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
937 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
939 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
940 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
941 if (AM != ISD::POST_INC)
944 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
945 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
946 Offset = CurDAG->getRegister(0, MVT::i32);
951 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
952 SDValue &Offset, SDValue &Label) {
953 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
954 Offset = N.getOperand(0);
955 SDValue N1 = N.getOperand(1);
956 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
965 //===----------------------------------------------------------------------===//
966 // Thumb Addressing Modes
967 //===----------------------------------------------------------------------===//
969 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
970 SDValue &Base, SDValue &Offset){
971 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
972 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
973 if (!NC || !NC->isNullValue())
980 Base = N.getOperand(0);
981 Offset = N.getOperand(1);
986 ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
987 SDValue &Offset, unsigned Scale) {
989 SDValue TmpBase, TmpOffImm;
990 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
991 return false; // We want to select tLDRspi / tSTRspi instead.
993 if (N.getOpcode() == ARMISD::Wrapper &&
994 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
995 return false; // We want to select tLDRpci instead.
998 if (!CurDAG->isBaseWithConstantOffset(N))
1001 // Thumb does not have [sp, r] address mode.
1002 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1003 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1004 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1005 (RHSR && RHSR->getReg() == ARM::SP))
1008 // FIXME: Why do we explicitly check for a match here and then return false?
1009 // Presumably to allow something else to match, but shouldn't this be
1012 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1015 Base = N.getOperand(0);
1016 Offset = N.getOperand(1);
1021 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1024 return SelectThumbAddrModeRI(N, Base, Offset, 1);
1028 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1031 return SelectThumbAddrModeRI(N, Base, Offset, 2);
1035 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1038 return SelectThumbAddrModeRI(N, Base, Offset, 4);
1042 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1043 SDValue &Base, SDValue &OffImm) {
1045 SDValue TmpBase, TmpOffImm;
1046 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1047 return false; // We want to select tLDRspi / tSTRspi instead.
1049 if (N.getOpcode() == ARMISD::Wrapper &&
1050 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1051 return false; // We want to select tLDRpci instead.
1054 if (!CurDAG->isBaseWithConstantOffset(N)) {
1055 if (N.getOpcode() == ARMISD::Wrapper &&
1056 !(Subtarget->useMovt() &&
1057 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1058 Base = N.getOperand(0);
1063 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1067 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1068 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1069 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1070 (RHSR && RHSR->getReg() == ARM::SP)) {
1071 ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1072 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1073 unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1074 unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1076 // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1077 if (LHSC != 0 || RHSC != 0) return false;
1080 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1084 // If the RHS is + imm5 * scale, fold into addr mode.
1086 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1087 Base = N.getOperand(0);
1088 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1092 Base = N.getOperand(0);
1093 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1098 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1100 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1104 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1106 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1110 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1112 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1115 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1116 SDValue &Base, SDValue &OffImm) {
1117 if (N.getOpcode() == ISD::FrameIndex) {
1118 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1119 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1120 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1124 if (!CurDAG->isBaseWithConstantOffset(N))
1127 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1128 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1129 (LHSR && LHSR->getReg() == ARM::SP)) {
1130 // If the RHS is + imm8 * scale, fold into addr mode.
1132 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1133 Base = N.getOperand(0);
1134 if (Base.getOpcode() == ISD::FrameIndex) {
1135 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1136 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1138 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1147 //===----------------------------------------------------------------------===//
1148 // Thumb 2 Addressing Modes
1149 //===----------------------------------------------------------------------===//
1152 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1154 if (DisableShifterOp)
1157 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1159 // Don't match base register only case. That is matched to a separate
1160 // lower complexity pattern with explicit register operand.
1161 if (ShOpcVal == ARM_AM::no_shift) return false;
1163 BaseReg = N.getOperand(0);
1164 unsigned ShImmVal = 0;
1165 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1166 ShImmVal = RHS->getZExtValue() & 31;
1167 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1174 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1175 SDValue &Base, SDValue &OffImm) {
1176 // Match simple R + imm12 operands.
1179 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1180 !CurDAG->isBaseWithConstantOffset(N)) {
1181 if (N.getOpcode() == ISD::FrameIndex) {
1182 // Match frame index.
1183 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1184 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1185 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1189 if (N.getOpcode() == ARMISD::Wrapper &&
1190 !(Subtarget->useMovt() &&
1191 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1192 Base = N.getOperand(0);
1193 if (Base.getOpcode() == ISD::TargetConstantPool)
1194 return false; // We want to select t2LDRpci instead.
1197 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1201 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1202 if (SelectT2AddrModeImm8(N, Base, OffImm))
1203 // Let t2LDRi8 handle (R - imm8).
1206 int RHSC = (int)RHS->getZExtValue();
1207 if (N.getOpcode() == ISD::SUB)
1210 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1211 Base = N.getOperand(0);
1212 if (Base.getOpcode() == ISD::FrameIndex) {
1213 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1214 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1216 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1223 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1227 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1228 SDValue &Base, SDValue &OffImm) {
1229 // Match simple R - imm8 operands.
1230 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1231 !CurDAG->isBaseWithConstantOffset(N))
1234 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1235 int RHSC = (int)RHS->getSExtValue();
1236 if (N.getOpcode() == ISD::SUB)
1239 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1240 Base = N.getOperand(0);
1241 if (Base.getOpcode() == ISD::FrameIndex) {
1242 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1243 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1245 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1253 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1255 unsigned Opcode = Op->getOpcode();
1256 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1257 ? cast<LoadSDNode>(Op)->getAddressingMode()
1258 : cast<StoreSDNode>(Op)->getAddressingMode();
1260 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1261 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1262 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1263 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1270 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1272 SDValue &OffReg, SDValue &ShImm) {
1273 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1274 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1277 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1278 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1279 int RHSC = (int)RHS->getZExtValue();
1280 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1282 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1286 // Look for (R + R) or (R + (R << [1,2,3])).
1288 Base = N.getOperand(0);
1289 OffReg = N.getOperand(1);
1291 // Swap if it is ((R << c) + R).
1292 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1293 if (ShOpcVal != ARM_AM::lsl) {
1294 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1295 if (ShOpcVal == ARM_AM::lsl)
1296 std::swap(Base, OffReg);
1299 if (ShOpcVal == ARM_AM::lsl) {
1300 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1302 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1303 ShAmt = Sh->getZExtValue();
1304 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1305 OffReg = OffReg.getOperand(0);
1308 ShOpcVal = ARM_AM::no_shift;
1311 ShOpcVal = ARM_AM::no_shift;
1315 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1320 //===--------------------------------------------------------------------===//
1322 /// getAL - Returns a ARMCC::AL immediate node.
1323 static inline SDValue getAL(SelectionDAG *CurDAG) {
1324 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1327 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1328 LoadSDNode *LD = cast<LoadSDNode>(N);
1329 ISD::MemIndexedMode AM = LD->getAddressingMode();
1330 if (AM == ISD::UNINDEXED)
1333 EVT LoadedVT = LD->getMemoryVT();
1334 SDValue Offset, AMOpc;
1335 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1336 unsigned Opcode = 0;
1338 if (LoadedVT == MVT::i32 && isPre &&
1339 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1340 Opcode = ARM::LDR_PRE_IMM;
1342 } else if (LoadedVT == MVT::i32 && !isPre &&
1343 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1344 Opcode = ARM::LDR_POST_IMM;
1346 } else if (LoadedVT == MVT::i32 &&
1347 SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1348 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1351 } else if (LoadedVT == MVT::i16 &&
1352 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1354 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1355 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1356 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1357 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1358 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1359 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1361 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1365 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1367 Opcode = ARM::LDRB_PRE_IMM;
1368 } else if (!isPre &&
1369 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1371 Opcode = ARM::LDRB_POST_IMM;
1372 } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1374 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1380 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1381 SDValue Chain = LD->getChain();
1382 SDValue Base = LD->getBasePtr();
1383 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1384 CurDAG->getRegister(0, MVT::i32), Chain };
1385 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1386 MVT::i32, MVT::Other, Ops, 5);
1388 SDValue Chain = LD->getChain();
1389 SDValue Base = LD->getBasePtr();
1390 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1391 CurDAG->getRegister(0, MVT::i32), Chain };
1392 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1393 MVT::i32, MVT::Other, Ops, 6);
1400 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1401 LoadSDNode *LD = cast<LoadSDNode>(N);
1402 ISD::MemIndexedMode AM = LD->getAddressingMode();
1403 if (AM == ISD::UNINDEXED)
1406 EVT LoadedVT = LD->getMemoryVT();
1407 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1409 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1410 unsigned Opcode = 0;
1412 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1413 switch (LoadedVT.getSimpleVT().SimpleTy) {
1415 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1419 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1421 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1426 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1428 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1437 SDValue Chain = LD->getChain();
1438 SDValue Base = LD->getBasePtr();
1439 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1440 CurDAG->getRegister(0, MVT::i32), Chain };
1441 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1442 MVT::Other, Ops, 5);
1448 /// \brief Form a GPRPair pseudo register from a pair of GPR regs.
1449 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1450 DebugLoc dl = V0.getNode()->getDebugLoc();
1452 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);
1453 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
1454 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
1455 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1456 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1459 /// \brief Form a D register from a pair of S registers.
1460 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1461 DebugLoc dl = V0.getNode()->getDebugLoc();
1463 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1464 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1465 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1466 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1467 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1470 /// \brief Form a quad register from a pair of D registers.
1471 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1472 DebugLoc dl = V0.getNode()->getDebugLoc();
1473 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1474 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1475 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1476 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1477 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1480 /// \brief Form 4 consecutive D registers from a pair of Q registers.
1481 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1482 DebugLoc dl = V0.getNode()->getDebugLoc();
1483 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1484 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1485 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1486 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1487 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1490 /// \brief Form 4 consecutive S registers.
1491 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1492 SDValue V2, SDValue V3) {
1493 DebugLoc dl = V0.getNode()->getDebugLoc();
1495 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1496 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1497 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1498 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1499 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1500 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1501 V2, SubReg2, V3, SubReg3 };
1502 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1505 /// \brief Form 4 consecutive D registers.
1506 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1507 SDValue V2, SDValue V3) {
1508 DebugLoc dl = V0.getNode()->getDebugLoc();
1509 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1510 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1511 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1512 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1513 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1514 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1515 V2, SubReg2, V3, SubReg3 };
1516 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1519 /// \brief Form 4 consecutive Q registers.
1520 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1521 SDValue V2, SDValue V3) {
1522 DebugLoc dl = V0.getNode()->getDebugLoc();
1523 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1524 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1525 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1526 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1527 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1528 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1529 V2, SubReg2, V3, SubReg3 };
1530 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1533 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1534 /// of a NEON VLD or VST instruction. The supported values depend on the
1535 /// number of registers being loaded.
1536 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1537 bool is64BitVector) {
1538 unsigned NumRegs = NumVecs;
1539 if (!is64BitVector && NumVecs < 3)
1542 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1543 if (Alignment >= 32 && NumRegs == 4)
1545 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1547 else if (Alignment >= 8)
1552 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1555 // Get the register stride update opcode of a VLD/VST instruction that
1556 // is otherwise equivalent to the given fixed stride updating instruction.
1557 static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1560 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1561 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1562 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1563 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1564 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1565 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1566 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1567 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1569 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1570 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1571 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1572 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1573 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1574 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1575 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1576 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1577 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1578 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1580 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1581 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1582 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1583 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1584 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1585 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1587 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1588 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1589 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1590 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1591 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1592 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1594 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1595 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1596 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1598 return Opc; // If not one we handle, return it unchanged.
1601 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1602 const uint16_t *DOpcodes,
1603 const uint16_t *QOpcodes0,
1604 const uint16_t *QOpcodes1) {
1605 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1606 DebugLoc dl = N->getDebugLoc();
1608 SDValue MemAddr, Align;
1609 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1610 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1613 SDValue Chain = N->getOperand(0);
1614 EVT VT = N->getValueType(0);
1615 bool is64BitVector = VT.is64BitVector();
1616 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1618 unsigned OpcodeIndex;
1619 switch (VT.getSimpleVT().SimpleTy) {
1620 default: llvm_unreachable("unhandled vld type");
1621 // Double-register operations:
1622 case MVT::v8i8: OpcodeIndex = 0; break;
1623 case MVT::v4i16: OpcodeIndex = 1; break;
1625 case MVT::v2i32: OpcodeIndex = 2; break;
1626 case MVT::v1i64: OpcodeIndex = 3; break;
1627 // Quad-register operations:
1628 case MVT::v16i8: OpcodeIndex = 0; break;
1629 case MVT::v8i16: OpcodeIndex = 1; break;
1631 case MVT::v4i32: OpcodeIndex = 2; break;
1632 case MVT::v2i64: OpcodeIndex = 3;
1633 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1641 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1644 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1646 std::vector<EVT> ResTys;
1647 ResTys.push_back(ResTy);
1649 ResTys.push_back(MVT::i32);
1650 ResTys.push_back(MVT::Other);
1652 SDValue Pred = getAL(CurDAG);
1653 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1655 SmallVector<SDValue, 7> Ops;
1657 // Double registers and VLD1/VLD2 quad registers are directly supported.
1658 if (is64BitVector || NumVecs <= 2) {
1659 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1660 QOpcodes0[OpcodeIndex]);
1661 Ops.push_back(MemAddr);
1662 Ops.push_back(Align);
1664 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1665 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1666 // case entirely when the rest are updated to that form, too.
1667 if ((NumVecs == 1 || NumVecs == 2) && !isa<ConstantSDNode>(Inc.getNode()))
1668 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1669 // We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1670 // check for that explicitly too. Horribly hacky, but temporary.
1671 if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64wb_fixed) ||
1672 !isa<ConstantSDNode>(Inc.getNode()))
1673 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1675 Ops.push_back(Pred);
1676 Ops.push_back(Reg0);
1677 Ops.push_back(Chain);
1678 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1681 // Otherwise, quad registers are loaded with two separate instructions,
1682 // where one loads the even registers and the other loads the odd registers.
1683 EVT AddrTy = MemAddr.getValueType();
1685 // Load the even subregs. This is always an updating load, so that it
1686 // provides the address to the second load for the odd subregs.
1688 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1689 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1690 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1691 ResTy, AddrTy, MVT::Other, OpsA, 7);
1692 Chain = SDValue(VLdA, 2);
1694 // Load the odd subregs.
1695 Ops.push_back(SDValue(VLdA, 1));
1696 Ops.push_back(Align);
1698 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1699 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1700 "only constant post-increment update allowed for VLD3/4");
1702 Ops.push_back(Reg0);
1704 Ops.push_back(SDValue(VLdA, 0));
1705 Ops.push_back(Pred);
1706 Ops.push_back(Reg0);
1707 Ops.push_back(Chain);
1708 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1709 Ops.data(), Ops.size());
1712 // Transfer memoperands.
1713 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1714 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1715 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1720 // Extract out the subregisters.
1721 SDValue SuperReg = SDValue(VLd, 0);
1722 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1723 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1724 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1725 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1726 ReplaceUses(SDValue(N, Vec),
1727 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1728 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1730 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1734 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1735 const uint16_t *DOpcodes,
1736 const uint16_t *QOpcodes0,
1737 const uint16_t *QOpcodes1) {
1738 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1739 DebugLoc dl = N->getDebugLoc();
1741 SDValue MemAddr, Align;
1742 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1743 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1744 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1747 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1748 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1750 SDValue Chain = N->getOperand(0);
1751 EVT VT = N->getOperand(Vec0Idx).getValueType();
1752 bool is64BitVector = VT.is64BitVector();
1753 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1755 unsigned OpcodeIndex;
1756 switch (VT.getSimpleVT().SimpleTy) {
1757 default: llvm_unreachable("unhandled vst type");
1758 // Double-register operations:
1759 case MVT::v8i8: OpcodeIndex = 0; break;
1760 case MVT::v4i16: OpcodeIndex = 1; break;
1762 case MVT::v2i32: OpcodeIndex = 2; break;
1763 case MVT::v1i64: OpcodeIndex = 3; break;
1764 // Quad-register operations:
1765 case MVT::v16i8: OpcodeIndex = 0; break;
1766 case MVT::v8i16: OpcodeIndex = 1; break;
1768 case MVT::v4i32: OpcodeIndex = 2; break;
1769 case MVT::v2i64: OpcodeIndex = 3;
1770 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1774 std::vector<EVT> ResTys;
1776 ResTys.push_back(MVT::i32);
1777 ResTys.push_back(MVT::Other);
1779 SDValue Pred = getAL(CurDAG);
1780 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1781 SmallVector<SDValue, 7> Ops;
1783 // Double registers and VST1/VST2 quad registers are directly supported.
1784 if (is64BitVector || NumVecs <= 2) {
1787 SrcReg = N->getOperand(Vec0Idx);
1788 } else if (is64BitVector) {
1789 // Form a REG_SEQUENCE to force register allocation.
1790 SDValue V0 = N->getOperand(Vec0Idx + 0);
1791 SDValue V1 = N->getOperand(Vec0Idx + 1);
1793 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
1795 SDValue V2 = N->getOperand(Vec0Idx + 2);
1796 // If it's a vst3, form a quad D-register and leave the last part as
1798 SDValue V3 = (NumVecs == 3)
1799 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1800 : N->getOperand(Vec0Idx + 3);
1801 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
1804 // Form a QQ register.
1805 SDValue Q0 = N->getOperand(Vec0Idx);
1806 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1807 SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
1810 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1811 QOpcodes0[OpcodeIndex]);
1812 Ops.push_back(MemAddr);
1813 Ops.push_back(Align);
1815 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1816 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1817 // case entirely when the rest are updated to that form, too.
1818 if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1819 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1820 // We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
1821 // check for that explicitly too. Horribly hacky, but temporary.
1822 if ((NumVecs > 2 && Opc != ARM::VST1q64wb_fixed) ||
1823 !isa<ConstantSDNode>(Inc.getNode()))
1824 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1826 Ops.push_back(SrcReg);
1827 Ops.push_back(Pred);
1828 Ops.push_back(Reg0);
1829 Ops.push_back(Chain);
1831 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1833 // Transfer memoperands.
1834 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1839 // Otherwise, quad registers are stored with two separate instructions,
1840 // where one stores the even registers and the other stores the odd registers.
1842 // Form the QQQQ REG_SEQUENCE.
1843 SDValue V0 = N->getOperand(Vec0Idx + 0);
1844 SDValue V1 = N->getOperand(Vec0Idx + 1);
1845 SDValue V2 = N->getOperand(Vec0Idx + 2);
1846 SDValue V3 = (NumVecs == 3)
1847 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1848 : N->getOperand(Vec0Idx + 3);
1849 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
1851 // Store the even D registers. This is always an updating store, so that it
1852 // provides the address to the second store for the odd subregs.
1853 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1854 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1855 MemAddr.getValueType(),
1856 MVT::Other, OpsA, 7);
1857 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1858 Chain = SDValue(VStA, 1);
1860 // Store the odd D registers.
1861 Ops.push_back(SDValue(VStA, 0));
1862 Ops.push_back(Align);
1864 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1865 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1866 "only constant post-increment update allowed for VST3/4");
1868 Ops.push_back(Reg0);
1870 Ops.push_back(RegSeq);
1871 Ops.push_back(Pred);
1872 Ops.push_back(Reg0);
1873 Ops.push_back(Chain);
1874 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1875 Ops.data(), Ops.size());
1876 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1880 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1881 bool isUpdating, unsigned NumVecs,
1882 const uint16_t *DOpcodes,
1883 const uint16_t *QOpcodes) {
1884 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1885 DebugLoc dl = N->getDebugLoc();
1887 SDValue MemAddr, Align;
1888 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1889 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1890 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1893 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1894 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1896 SDValue Chain = N->getOperand(0);
1898 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1899 EVT VT = N->getOperand(Vec0Idx).getValueType();
1900 bool is64BitVector = VT.is64BitVector();
1902 unsigned Alignment = 0;
1904 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1905 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1906 if (Alignment > NumBytes)
1907 Alignment = NumBytes;
1908 if (Alignment < 8 && Alignment < NumBytes)
1910 // Alignment must be a power of two; make sure of that.
1911 Alignment = (Alignment & -Alignment);
1915 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1917 unsigned OpcodeIndex;
1918 switch (VT.getSimpleVT().SimpleTy) {
1919 default: llvm_unreachable("unhandled vld/vst lane type");
1920 // Double-register operations:
1921 case MVT::v8i8: OpcodeIndex = 0; break;
1922 case MVT::v4i16: OpcodeIndex = 1; break;
1924 case MVT::v2i32: OpcodeIndex = 2; break;
1925 // Quad-register operations:
1926 case MVT::v8i16: OpcodeIndex = 0; break;
1928 case MVT::v4i32: OpcodeIndex = 1; break;
1931 std::vector<EVT> ResTys;
1933 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1936 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1937 MVT::i64, ResTyElts));
1940 ResTys.push_back(MVT::i32);
1941 ResTys.push_back(MVT::Other);
1943 SDValue Pred = getAL(CurDAG);
1944 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1946 SmallVector<SDValue, 8> Ops;
1947 Ops.push_back(MemAddr);
1948 Ops.push_back(Align);
1950 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1951 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1955 SDValue V0 = N->getOperand(Vec0Idx + 0);
1956 SDValue V1 = N->getOperand(Vec0Idx + 1);
1959 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
1961 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
1963 SDValue V2 = N->getOperand(Vec0Idx + 2);
1964 SDValue V3 = (NumVecs == 3)
1965 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1966 : N->getOperand(Vec0Idx + 3);
1968 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
1970 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
1972 Ops.push_back(SuperReg);
1973 Ops.push_back(getI32Imm(Lane));
1974 Ops.push_back(Pred);
1975 Ops.push_back(Reg0);
1976 Ops.push_back(Chain);
1978 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1979 QOpcodes[OpcodeIndex]);
1980 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1981 Ops.data(), Ops.size());
1982 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
1986 // Extract the subregisters.
1987 SuperReg = SDValue(VLdLn, 0);
1988 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1989 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1990 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1991 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1992 ReplaceUses(SDValue(N, Vec),
1993 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1994 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1996 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2000 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
2002 const uint16_t *Opcodes) {
2003 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2004 DebugLoc dl = N->getDebugLoc();
2006 SDValue MemAddr, Align;
2007 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2010 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2011 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2013 SDValue Chain = N->getOperand(0);
2014 EVT VT = N->getValueType(0);
2016 unsigned Alignment = 0;
2018 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2019 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2020 if (Alignment > NumBytes)
2021 Alignment = NumBytes;
2022 if (Alignment < 8 && Alignment < NumBytes)
2024 // Alignment must be a power of two; make sure of that.
2025 Alignment = (Alignment & -Alignment);
2029 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2031 unsigned OpcodeIndex;
2032 switch (VT.getSimpleVT().SimpleTy) {
2033 default: llvm_unreachable("unhandled vld-dup type");
2034 case MVT::v8i8: OpcodeIndex = 0; break;
2035 case MVT::v4i16: OpcodeIndex = 1; break;
2037 case MVT::v2i32: OpcodeIndex = 2; break;
2040 SDValue Pred = getAL(CurDAG);
2041 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2043 unsigned Opc = Opcodes[OpcodeIndex];
2044 SmallVector<SDValue, 6> Ops;
2045 Ops.push_back(MemAddr);
2046 Ops.push_back(Align);
2048 // fixed-stride update instructions don't have an explicit writeback
2049 // operand. It's implicit in the opcode itself.
2050 SDValue Inc = N->getOperand(2);
2051 if (!isa<ConstantSDNode>(Inc.getNode()))
2053 // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2054 else if (NumVecs > 2)
2055 Ops.push_back(Reg0);
2057 Ops.push_back(Pred);
2058 Ops.push_back(Reg0);
2059 Ops.push_back(Chain);
2061 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2062 std::vector<EVT> ResTys;
2063 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2065 ResTys.push_back(MVT::i32);
2066 ResTys.push_back(MVT::Other);
2068 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
2069 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2070 SuperReg = SDValue(VLdDup, 0);
2072 // Extract the subregisters.
2073 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2074 unsigned SubIdx = ARM::dsub_0;
2075 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2076 ReplaceUses(SDValue(N, Vec),
2077 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2078 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2080 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2084 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2086 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2087 DebugLoc dl = N->getDebugLoc();
2088 EVT VT = N->getValueType(0);
2089 unsigned FirstTblReg = IsExt ? 2 : 1;
2091 // Form a REG_SEQUENCE to force register allocation.
2093 SDValue V0 = N->getOperand(FirstTblReg + 0);
2094 SDValue V1 = N->getOperand(FirstTblReg + 1);
2096 RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
2098 SDValue V2 = N->getOperand(FirstTblReg + 2);
2099 // If it's a vtbl3, form a quad D-register and leave the last part as
2101 SDValue V3 = (NumVecs == 3)
2102 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2103 : N->getOperand(FirstTblReg + 3);
2104 RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2107 SmallVector<SDValue, 6> Ops;
2109 Ops.push_back(N->getOperand(1));
2110 Ops.push_back(RegSeq);
2111 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2112 Ops.push_back(getAL(CurDAG)); // predicate
2113 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2114 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
2117 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2119 if (!Subtarget->hasV6T2Ops())
2122 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2123 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2126 // For unsigned extracts, check for a shift right and mask
2127 unsigned And_imm = 0;
2128 if (N->getOpcode() == ISD::AND) {
2129 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2131 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2132 if (And_imm & (And_imm + 1))
2135 unsigned Srl_imm = 0;
2136 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2138 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2140 // Note: The width operand is encoded as width-1.
2141 unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2142 unsigned LSB = Srl_imm;
2143 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2144 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2145 CurDAG->getTargetConstant(LSB, MVT::i32),
2146 CurDAG->getTargetConstant(Width, MVT::i32),
2147 getAL(CurDAG), Reg0 };
2148 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2154 // Otherwise, we're looking for a shift of a shift
2155 unsigned Shl_imm = 0;
2156 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2157 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2158 unsigned Srl_imm = 0;
2159 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2160 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2161 // Note: The width operand is encoded as width-1.
2162 unsigned Width = 32 - Srl_imm - 1;
2163 int LSB = Srl_imm - Shl_imm;
2166 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2167 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2168 CurDAG->getTargetConstant(LSB, MVT::i32),
2169 CurDAG->getTargetConstant(Width, MVT::i32),
2170 getAL(CurDAG), Reg0 };
2171 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2177 SDNode *ARMDAGToDAGISel::
2178 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2179 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2182 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2183 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
2184 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
2187 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
2188 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
2189 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
2190 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
2192 llvm_unreachable("Unknown so_reg opcode!");
2195 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
2196 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2197 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2198 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2203 SDNode *ARMDAGToDAGISel::
2204 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2205 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2209 if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
2210 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2211 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2212 return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
2215 if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2216 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2217 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2218 return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
2223 SDNode *ARMDAGToDAGISel::
2224 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2225 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2226 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2231 unsigned TrueImm = T->getZExtValue();
2232 if (is_t2_so_imm(TrueImm)) {
2233 Opc = ARM::t2MOVCCi;
2234 } else if (TrueImm <= 0xffff) {
2235 Opc = ARM::t2MOVCCi16;
2236 } else if (is_t2_so_imm_not(TrueImm)) {
2238 Opc = ARM::t2MVNCCi;
2239 } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2241 Opc = ARM::t2MOVCCi32imm;
2245 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2246 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2247 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2248 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2254 SDNode *ARMDAGToDAGISel::
2255 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2256 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2257 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2262 unsigned TrueImm = T->getZExtValue();
2263 bool isSoImm = is_so_imm(TrueImm);
2266 } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2267 Opc = ARM::MOVCCi16;
2268 } else if (is_so_imm_not(TrueImm)) {
2271 } else if (TrueVal.getNode()->hasOneUse() &&
2272 (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2274 Opc = ARM::MOVCCi32imm;
2278 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2279 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2280 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2281 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2287 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2288 EVT VT = N->getValueType(0);
2289 SDValue FalseVal = N->getOperand(0);
2290 SDValue TrueVal = N->getOperand(1);
2291 SDValue CC = N->getOperand(2);
2292 SDValue CCR = N->getOperand(3);
2293 SDValue InFlag = N->getOperand(4);
2294 assert(CC.getOpcode() == ISD::Constant);
2295 assert(CCR.getOpcode() == ISD::Register);
2296 ARMCC::CondCodes CCVal =
2297 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2299 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2300 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2301 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2302 // Pattern complexity = 18 cost = 1 size = 0
2303 if (Subtarget->isThumb()) {
2304 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2305 CCVal, CCR, InFlag);
2307 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2308 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2312 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2313 CCVal, CCR, InFlag);
2315 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2316 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2321 // Pattern: (ARMcmov:i32 GPR:i32:$false,
2322 // (imm:i32)<<P:Pred_so_imm>>:$true,
2324 // Emits: (MOVCCi:i32 GPR:i32:$false,
2325 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2326 // Pattern complexity = 10 cost = 1 size = 0
2327 if (Subtarget->isThumb()) {
2328 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2329 CCVal, CCR, InFlag);
2331 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2332 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2336 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2337 CCVal, CCR, InFlag);
2339 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2340 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2346 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2347 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2348 // Pattern complexity = 6 cost = 1 size = 0
2350 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2351 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2352 // Pattern complexity = 6 cost = 11 size = 0
2354 // Also VMOVScc and VMOVDcc.
2355 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2356 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2358 switch (VT.getSimpleVT().SimpleTy) {
2359 default: llvm_unreachable("Illegal conditional move type!");
2361 Opc = Subtarget->isThumb()
2362 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2372 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2375 /// Target-specific DAG combining for ISD::XOR.
2376 /// Target-independent combining lowers SELECT_CC nodes of the form
2377 /// select_cc setg[ge] X, 0, X, -X
2378 /// select_cc setgt X, -1, X, -X
2379 /// select_cc setl[te] X, 0, -X, X
2380 /// select_cc setlt X, 1, -X, X
2381 /// which represent Integer ABS into:
2382 /// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2383 /// ARM instruction selection detects the latter and matches it to
2384 /// ARM::ABS or ARM::t2ABS machine node.
2385 SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2386 SDValue XORSrc0 = N->getOperand(0);
2387 SDValue XORSrc1 = N->getOperand(1);
2388 EVT VT = N->getValueType(0);
2390 if (Subtarget->isThumb1Only())
2393 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2396 SDValue ADDSrc0 = XORSrc0.getOperand(0);
2397 SDValue ADDSrc1 = XORSrc0.getOperand(1);
2398 SDValue SRASrc0 = XORSrc1.getOperand(0);
2399 SDValue SRASrc1 = XORSrc1.getOperand(1);
2400 ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1);
2401 EVT XType = SRASrc0.getValueType();
2402 unsigned Size = XType.getSizeInBits() - 1;
2404 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2405 XType.isInteger() && SRAConstant != NULL &&
2406 Size == SRAConstant->getZExtValue()) {
2407 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2408 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2414 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2415 // The only time a CONCAT_VECTORS operation can have legal types is when
2416 // two 64-bit vectors are concatenated to a 128-bit vector.
2417 EVT VT = N->getValueType(0);
2418 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2419 llvm_unreachable("unexpected CONCAT_VECTORS");
2420 return createDRegPairNode(VT, N->getOperand(0), N->getOperand(1));
2423 SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
2424 SmallVector<SDValue, 6> Ops;
2425 Ops.push_back(Node->getOperand(1)); // Ptr
2426 Ops.push_back(Node->getOperand(2)); // Low part of Val1
2427 Ops.push_back(Node->getOperand(3)); // High part of Val1
2428 if (Opc == ARM::ATOMCMPXCHG6432) {
2429 Ops.push_back(Node->getOperand(4)); // Low part of Val2
2430 Ops.push_back(Node->getOperand(5)); // High part of Val2
2432 Ops.push_back(Node->getOperand(0)); // Chain
2433 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2434 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
2435 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
2436 MVT::i32, MVT::i32, MVT::Other,
2437 Ops.data() ,Ops.size());
2438 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
2442 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2443 DebugLoc dl = N->getDebugLoc();
2445 if (N->isMachineOpcode())
2446 return NULL; // Already selected.
2448 switch (N->getOpcode()) {
2451 // Select special operations if XOR node forms integer ABS pattern
2452 SDNode *ResNode = SelectABSOp(N);
2455 // Other cases are autogenerated.
2458 case ISD::Constant: {
2459 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2461 if (Subtarget->hasThumb2())
2462 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2463 // be done with MOV + MOVT, at worst.
2466 if (Subtarget->isThumb()) {
2467 UseCP = (Val > 255 && // MOV
2468 ~Val > 255 && // MOV + MVN
2469 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
2471 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2472 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2473 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
2478 CurDAG->getTargetConstantPool(ConstantInt::get(
2479 Type::getInt32Ty(*CurDAG->getContext()), Val),
2480 TLI.getPointerTy());
2483 if (Subtarget->isThumb1Only()) {
2484 SDValue Pred = getAL(CurDAG);
2485 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2486 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2487 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2492 CurDAG->getTargetConstant(0, MVT::i32),
2494 CurDAG->getRegister(0, MVT::i32),
2495 CurDAG->getEntryNode()
2497 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2500 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2504 // Other cases are autogenerated.
2507 case ISD::FrameIndex: {
2508 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2509 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2510 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2511 if (Subtarget->isThumb1Only()) {
2512 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2513 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2514 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2516 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2517 ARM::t2ADDri : ARM::ADDri);
2518 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2519 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2520 CurDAG->getRegister(0, MVT::i32) };
2521 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2525 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2529 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2533 if (Subtarget->isThumb1Only())
2535 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2536 unsigned RHSV = C->getZExtValue();
2538 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2539 unsigned ShImm = Log2_32(RHSV-1);
2542 SDValue V = N->getOperand(0);
2543 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2544 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2545 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2546 if (Subtarget->isThumb()) {
2547 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2548 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2550 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2551 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2554 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2555 unsigned ShImm = Log2_32(RHSV+1);
2558 SDValue V = N->getOperand(0);
2559 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2560 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2561 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2562 if (Subtarget->isThumb()) {
2563 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2564 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2566 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2567 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2573 // Check for unsigned bitfield extract
2574 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2577 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2578 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2579 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2580 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2581 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2582 EVT VT = N->getValueType(0);
2585 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2587 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2590 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2591 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2594 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2595 SDValue N2 = N0.getOperand(1);
2596 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2599 unsigned N1CVal = N1C->getZExtValue();
2600 unsigned N2CVal = N2C->getZExtValue();
2601 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2602 (N1CVal & 0xffffU) == 0xffffU &&
2603 (N2CVal & 0xffffU) == 0x0U) {
2604 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2606 SDValue Ops[] = { N0.getOperand(0), Imm16,
2607 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2608 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2613 case ARMISD::VMOVRRD:
2614 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2615 N->getOperand(0), getAL(CurDAG),
2616 CurDAG->getRegister(0, MVT::i32));
2617 case ISD::UMUL_LOHI: {
2618 if (Subtarget->isThumb1Only())
2620 if (Subtarget->isThumb()) {
2621 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2622 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2623 CurDAG->getRegister(0, MVT::i32) };
2624 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2626 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2627 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2628 CurDAG->getRegister(0, MVT::i32) };
2629 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2630 ARM::UMULL : ARM::UMULLv5,
2631 dl, MVT::i32, MVT::i32, Ops, 5);
2634 case ISD::SMUL_LOHI: {
2635 if (Subtarget->isThumb1Only())
2637 if (Subtarget->isThumb()) {
2638 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2639 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2640 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2642 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2643 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2644 CurDAG->getRegister(0, MVT::i32) };
2645 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2646 ARM::SMULL : ARM::SMULLv5,
2647 dl, MVT::i32, MVT::i32, Ops, 5);
2650 case ARMISD::UMLAL:{
2651 if (Subtarget->isThumb()) {
2652 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2653 N->getOperand(3), getAL(CurDAG),
2654 CurDAG->getRegister(0, MVT::i32)};
2655 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops, 6);
2657 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2658 N->getOperand(3), getAL(CurDAG),
2659 CurDAG->getRegister(0, MVT::i32),
2660 CurDAG->getRegister(0, MVT::i32) };
2661 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2662 ARM::UMLAL : ARM::UMLALv5,
2663 dl, MVT::i32, MVT::i32, Ops, 7);
2666 case ARMISD::SMLAL:{
2667 if (Subtarget->isThumb()) {
2668 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2669 N->getOperand(3), getAL(CurDAG),
2670 CurDAG->getRegister(0, MVT::i32)};
2671 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops, 6);
2673 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2674 N->getOperand(3), getAL(CurDAG),
2675 CurDAG->getRegister(0, MVT::i32),
2676 CurDAG->getRegister(0, MVT::i32) };
2677 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2678 ARM::SMLAL : ARM::SMLALv5,
2679 dl, MVT::i32, MVT::i32, Ops, 7);
2683 SDNode *ResNode = 0;
2684 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2685 ResNode = SelectT2IndexedLoad(N);
2687 ResNode = SelectARMIndexedLoad(N);
2690 // Other cases are autogenerated.
2693 case ARMISD::BRCOND: {
2694 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2695 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2696 // Pattern complexity = 6 cost = 1 size = 0
2698 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2699 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2700 // Pattern complexity = 6 cost = 1 size = 0
2702 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2703 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2704 // Pattern complexity = 6 cost = 1 size = 0
2706 unsigned Opc = Subtarget->isThumb() ?
2707 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2708 SDValue Chain = N->getOperand(0);
2709 SDValue N1 = N->getOperand(1);
2710 SDValue N2 = N->getOperand(2);
2711 SDValue N3 = N->getOperand(3);
2712 SDValue InFlag = N->getOperand(4);
2713 assert(N1.getOpcode() == ISD::BasicBlock);
2714 assert(N2.getOpcode() == ISD::Constant);
2715 assert(N3.getOpcode() == ISD::Register);
2717 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2718 cast<ConstantSDNode>(N2)->getZExtValue()),
2720 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2721 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2723 Chain = SDValue(ResNode, 0);
2724 if (N->getNumValues() == 2) {
2725 InFlag = SDValue(ResNode, 1);
2726 ReplaceUses(SDValue(N, 1), InFlag);
2728 ReplaceUses(SDValue(N, 0),
2729 SDValue(Chain.getNode(), Chain.getResNo()));
2733 return SelectCMOVOp(N);
2734 case ARMISD::VZIP: {
2736 EVT VT = N->getValueType(0);
2737 switch (VT.getSimpleVT().SimpleTy) {
2738 default: return NULL;
2739 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2740 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2742 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2743 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2744 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2745 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2747 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2749 SDValue Pred = getAL(CurDAG);
2750 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2751 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2752 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2754 case ARMISD::VUZP: {
2756 EVT VT = N->getValueType(0);
2757 switch (VT.getSimpleVT().SimpleTy) {
2758 default: return NULL;
2759 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2760 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2762 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2763 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2764 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2765 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2767 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2769 SDValue Pred = getAL(CurDAG);
2770 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2771 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2772 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2774 case ARMISD::VTRN: {
2776 EVT VT = N->getValueType(0);
2777 switch (VT.getSimpleVT().SimpleTy) {
2778 default: return NULL;
2779 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2780 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2782 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2783 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2784 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2786 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2788 SDValue Pred = getAL(CurDAG);
2789 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2790 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2791 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2793 case ARMISD::BUILD_VECTOR: {
2794 EVT VecVT = N->getValueType(0);
2795 EVT EltVT = VecVT.getVectorElementType();
2796 unsigned NumElts = VecVT.getVectorNumElements();
2797 if (EltVT == MVT::f64) {
2798 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2799 return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2801 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2803 return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2804 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2805 return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
2806 N->getOperand(2), N->getOperand(3));
2809 case ARMISD::VLD2DUP: {
2810 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2812 return SelectVLDDup(N, false, 2, Opcodes);
2815 case ARMISD::VLD3DUP: {
2816 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
2817 ARM::VLD3DUPd16Pseudo,
2818 ARM::VLD3DUPd32Pseudo };
2819 return SelectVLDDup(N, false, 3, Opcodes);
2822 case ARMISD::VLD4DUP: {
2823 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
2824 ARM::VLD4DUPd16Pseudo,
2825 ARM::VLD4DUPd32Pseudo };
2826 return SelectVLDDup(N, false, 4, Opcodes);
2829 case ARMISD::VLD2DUP_UPD: {
2830 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
2831 ARM::VLD2DUPd16wb_fixed,
2832 ARM::VLD2DUPd32wb_fixed };
2833 return SelectVLDDup(N, true, 2, Opcodes);
2836 case ARMISD::VLD3DUP_UPD: {
2837 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
2838 ARM::VLD3DUPd16Pseudo_UPD,
2839 ARM::VLD3DUPd32Pseudo_UPD };
2840 return SelectVLDDup(N, true, 3, Opcodes);
2843 case ARMISD::VLD4DUP_UPD: {
2844 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
2845 ARM::VLD4DUPd16Pseudo_UPD,
2846 ARM::VLD4DUPd32Pseudo_UPD };
2847 return SelectVLDDup(N, true, 4, Opcodes);
2850 case ARMISD::VLD1_UPD: {
2851 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
2852 ARM::VLD1d16wb_fixed,
2853 ARM::VLD1d32wb_fixed,
2854 ARM::VLD1d64wb_fixed };
2855 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
2856 ARM::VLD1q16wb_fixed,
2857 ARM::VLD1q32wb_fixed,
2858 ARM::VLD1q64wb_fixed };
2859 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2862 case ARMISD::VLD2_UPD: {
2863 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
2864 ARM::VLD2d16wb_fixed,
2865 ARM::VLD2d32wb_fixed,
2866 ARM::VLD1q64wb_fixed};
2867 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2868 ARM::VLD2q16PseudoWB_fixed,
2869 ARM::VLD2q32PseudoWB_fixed };
2870 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2873 case ARMISD::VLD3_UPD: {
2874 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
2875 ARM::VLD3d16Pseudo_UPD,
2876 ARM::VLD3d32Pseudo_UPD,
2877 ARM::VLD1q64wb_fixed};
2878 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2879 ARM::VLD3q16Pseudo_UPD,
2880 ARM::VLD3q32Pseudo_UPD };
2881 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2882 ARM::VLD3q16oddPseudo_UPD,
2883 ARM::VLD3q32oddPseudo_UPD };
2884 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2887 case ARMISD::VLD4_UPD: {
2888 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
2889 ARM::VLD4d16Pseudo_UPD,
2890 ARM::VLD4d32Pseudo_UPD,
2891 ARM::VLD1q64wb_fixed};
2892 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2893 ARM::VLD4q16Pseudo_UPD,
2894 ARM::VLD4q32Pseudo_UPD };
2895 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2896 ARM::VLD4q16oddPseudo_UPD,
2897 ARM::VLD4q32oddPseudo_UPD };
2898 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2901 case ARMISD::VLD2LN_UPD: {
2902 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
2903 ARM::VLD2LNd16Pseudo_UPD,
2904 ARM::VLD2LNd32Pseudo_UPD };
2905 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2906 ARM::VLD2LNq32Pseudo_UPD };
2907 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2910 case ARMISD::VLD3LN_UPD: {
2911 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
2912 ARM::VLD3LNd16Pseudo_UPD,
2913 ARM::VLD3LNd32Pseudo_UPD };
2914 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2915 ARM::VLD3LNq32Pseudo_UPD };
2916 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2919 case ARMISD::VLD4LN_UPD: {
2920 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
2921 ARM::VLD4LNd16Pseudo_UPD,
2922 ARM::VLD4LNd32Pseudo_UPD };
2923 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2924 ARM::VLD4LNq32Pseudo_UPD };
2925 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2928 case ARMISD::VST1_UPD: {
2929 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
2930 ARM::VST1d16wb_fixed,
2931 ARM::VST1d32wb_fixed,
2932 ARM::VST1d64wb_fixed };
2933 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
2934 ARM::VST1q16wb_fixed,
2935 ARM::VST1q32wb_fixed,
2936 ARM::VST1q64wb_fixed };
2937 return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2940 case ARMISD::VST2_UPD: {
2941 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
2942 ARM::VST2d16wb_fixed,
2943 ARM::VST2d32wb_fixed,
2944 ARM::VST1q64wb_fixed};
2945 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
2946 ARM::VST2q16PseudoWB_fixed,
2947 ARM::VST2q32PseudoWB_fixed };
2948 return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2951 case ARMISD::VST3_UPD: {
2952 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
2953 ARM::VST3d16Pseudo_UPD,
2954 ARM::VST3d32Pseudo_UPD,
2955 ARM::VST1d64TPseudoWB_fixed};
2956 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2957 ARM::VST3q16Pseudo_UPD,
2958 ARM::VST3q32Pseudo_UPD };
2959 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2960 ARM::VST3q16oddPseudo_UPD,
2961 ARM::VST3q32oddPseudo_UPD };
2962 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2965 case ARMISD::VST4_UPD: {
2966 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
2967 ARM::VST4d16Pseudo_UPD,
2968 ARM::VST4d32Pseudo_UPD,
2969 ARM::VST1d64QPseudoWB_fixed};
2970 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2971 ARM::VST4q16Pseudo_UPD,
2972 ARM::VST4q32Pseudo_UPD };
2973 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2974 ARM::VST4q16oddPseudo_UPD,
2975 ARM::VST4q32oddPseudo_UPD };
2976 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2979 case ARMISD::VST2LN_UPD: {
2980 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
2981 ARM::VST2LNd16Pseudo_UPD,
2982 ARM::VST2LNd32Pseudo_UPD };
2983 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2984 ARM::VST2LNq32Pseudo_UPD };
2985 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2988 case ARMISD::VST3LN_UPD: {
2989 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
2990 ARM::VST3LNd16Pseudo_UPD,
2991 ARM::VST3LNd32Pseudo_UPD };
2992 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2993 ARM::VST3LNq32Pseudo_UPD };
2994 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2997 case ARMISD::VST4LN_UPD: {
2998 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
2999 ARM::VST4LNd16Pseudo_UPD,
3000 ARM::VST4LNd32Pseudo_UPD };
3001 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
3002 ARM::VST4LNq32Pseudo_UPD };
3003 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
3006 case ISD::INTRINSIC_VOID:
3007 case ISD::INTRINSIC_W_CHAIN: {
3008 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
3013 case Intrinsic::arm_ldrexd: {
3014 SDValue MemAddr = N->getOperand(2);
3015 DebugLoc dl = N->getDebugLoc();
3016 SDValue Chain = N->getOperand(0);
3018 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3019 unsigned NewOpc = isThumb ? ARM::t2LDREXD :ARM::LDREXD;
3021 // arm_ldrexd returns a i64 value in {i32, i32}
3022 std::vector<EVT> ResTys;
3024 ResTys.push_back(MVT::i32);
3025 ResTys.push_back(MVT::i32);
3027 ResTys.push_back(MVT::Untyped);
3028 ResTys.push_back(MVT::Other);
3030 // Place arguments in the right order.
3031 SmallVector<SDValue, 7> Ops;
3032 Ops.push_back(MemAddr);
3033 Ops.push_back(getAL(CurDAG));
3034 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3035 Ops.push_back(Chain);
3036 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3038 // Transfer memoperands.
3039 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3040 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3041 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
3044 SDValue Glue = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
3045 if (!SDValue(N, 0).use_empty()) {
3048 Result = SDValue(Ld, 0);
3050 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
3051 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3052 dl, MVT::i32, MVT::Glue, SDValue(Ld, 0), SubRegIdx, Glue);
3053 Result = SDValue(ResNode,0);
3054 Glue = Result.getValue(1);
3056 ReplaceUses(SDValue(N, 0), Result);
3058 if (!SDValue(N, 1).use_empty()) {
3061 Result = SDValue(Ld, 1);
3063 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
3064 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3065 dl, MVT::i32, MVT::Glue, SDValue(Ld, 0), SubRegIdx, Glue);
3066 Result = SDValue(ResNode,0);
3067 Glue = Result.getValue(1);
3069 ReplaceUses(SDValue(N, 1), Result);
3071 ReplaceUses(SDValue(N, 2), Glue);
3075 case Intrinsic::arm_strexd: {
3076 DebugLoc dl = N->getDebugLoc();
3077 SDValue Chain = N->getOperand(0);
3078 SDValue Val0 = N->getOperand(2);
3079 SDValue Val1 = N->getOperand(3);
3080 SDValue MemAddr = N->getOperand(4);
3082 // Store exclusive double return a i32 value which is the return status
3083 // of the issued store.
3084 std::vector<EVT> ResTys;
3085 ResTys.push_back(MVT::i32);
3086 ResTys.push_back(MVT::Other);
3088 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3089 // Place arguments in the right order.
3090 SmallVector<SDValue, 7> Ops;
3092 Ops.push_back(Val0);
3093 Ops.push_back(Val1);
3095 // arm_strexd uses GPRPair.
3096 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
3097 Ops.push_back(MemAddr);
3098 Ops.push_back(getAL(CurDAG));
3099 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3100 Ops.push_back(Chain);
3102 unsigned NewOpc = isThumb ? ARM::t2STREXD : ARM::STREXD;
3104 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3106 // Transfer memoperands.
3107 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3108 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3109 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3114 case Intrinsic::arm_neon_vld1: {
3115 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3116 ARM::VLD1d32, ARM::VLD1d64 };
3117 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3118 ARM::VLD1q32, ARM::VLD1q64};
3119 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
3122 case Intrinsic::arm_neon_vld2: {
3123 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3124 ARM::VLD2d32, ARM::VLD1q64 };
3125 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3126 ARM::VLD2q32Pseudo };
3127 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
3130 case Intrinsic::arm_neon_vld3: {
3131 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
3134 ARM::VLD1d64TPseudo };
3135 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3136 ARM::VLD3q16Pseudo_UPD,
3137 ARM::VLD3q32Pseudo_UPD };
3138 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3139 ARM::VLD3q16oddPseudo,
3140 ARM::VLD3q32oddPseudo };
3141 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3144 case Intrinsic::arm_neon_vld4: {
3145 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
3148 ARM::VLD1d64QPseudo };
3149 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3150 ARM::VLD4q16Pseudo_UPD,
3151 ARM::VLD4q32Pseudo_UPD };
3152 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3153 ARM::VLD4q16oddPseudo,
3154 ARM::VLD4q32oddPseudo };
3155 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3158 case Intrinsic::arm_neon_vld2lane: {
3159 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
3160 ARM::VLD2LNd16Pseudo,
3161 ARM::VLD2LNd32Pseudo };
3162 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
3163 ARM::VLD2LNq32Pseudo };
3164 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3167 case Intrinsic::arm_neon_vld3lane: {
3168 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
3169 ARM::VLD3LNd16Pseudo,
3170 ARM::VLD3LNd32Pseudo };
3171 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
3172 ARM::VLD3LNq32Pseudo };
3173 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3176 case Intrinsic::arm_neon_vld4lane: {
3177 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
3178 ARM::VLD4LNd16Pseudo,
3179 ARM::VLD4LNd32Pseudo };
3180 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
3181 ARM::VLD4LNq32Pseudo };
3182 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3185 case Intrinsic::arm_neon_vst1: {
3186 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3187 ARM::VST1d32, ARM::VST1d64 };
3188 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3189 ARM::VST1q32, ARM::VST1q64 };
3190 return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3193 case Intrinsic::arm_neon_vst2: {
3194 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3195 ARM::VST2d32, ARM::VST1q64 };
3196 static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3197 ARM::VST2q32Pseudo };
3198 return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3201 case Intrinsic::arm_neon_vst3: {
3202 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
3205 ARM::VST1d64TPseudo };
3206 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3207 ARM::VST3q16Pseudo_UPD,
3208 ARM::VST3q32Pseudo_UPD };
3209 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
3210 ARM::VST3q16oddPseudo,
3211 ARM::VST3q32oddPseudo };
3212 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3215 case Intrinsic::arm_neon_vst4: {
3216 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
3219 ARM::VST1d64QPseudo };
3220 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3221 ARM::VST4q16Pseudo_UPD,
3222 ARM::VST4q32Pseudo_UPD };
3223 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
3224 ARM::VST4q16oddPseudo,
3225 ARM::VST4q32oddPseudo };
3226 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3229 case Intrinsic::arm_neon_vst2lane: {
3230 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
3231 ARM::VST2LNd16Pseudo,
3232 ARM::VST2LNd32Pseudo };
3233 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
3234 ARM::VST2LNq32Pseudo };
3235 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3238 case Intrinsic::arm_neon_vst3lane: {
3239 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
3240 ARM::VST3LNd16Pseudo,
3241 ARM::VST3LNd32Pseudo };
3242 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
3243 ARM::VST3LNq32Pseudo };
3244 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3247 case Intrinsic::arm_neon_vst4lane: {
3248 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
3249 ARM::VST4LNd16Pseudo,
3250 ARM::VST4LNd32Pseudo };
3251 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
3252 ARM::VST4LNq32Pseudo };
3253 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3259 case ISD::INTRINSIC_WO_CHAIN: {
3260 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3265 case Intrinsic::arm_neon_vtbl2:
3266 return SelectVTBL(N, false, 2, ARM::VTBL2);
3267 case Intrinsic::arm_neon_vtbl3:
3268 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3269 case Intrinsic::arm_neon_vtbl4:
3270 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3272 case Intrinsic::arm_neon_vtbx2:
3273 return SelectVTBL(N, true, 2, ARM::VTBX2);
3274 case Intrinsic::arm_neon_vtbx3:
3275 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3276 case Intrinsic::arm_neon_vtbx4:
3277 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3282 case ARMISD::VTBL1: {
3283 DebugLoc dl = N->getDebugLoc();
3284 EVT VT = N->getValueType(0);
3285 SmallVector<SDValue, 6> Ops;
3287 Ops.push_back(N->getOperand(0));
3288 Ops.push_back(N->getOperand(1));
3289 Ops.push_back(getAL(CurDAG)); // Predicate
3290 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3291 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
3293 case ARMISD::VTBL2: {
3294 DebugLoc dl = N->getDebugLoc();
3295 EVT VT = N->getValueType(0);
3297 // Form a REG_SEQUENCE to force register allocation.
3298 SDValue V0 = N->getOperand(0);
3299 SDValue V1 = N->getOperand(1);
3300 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
3302 SmallVector<SDValue, 6> Ops;
3303 Ops.push_back(RegSeq);
3304 Ops.push_back(N->getOperand(2));
3305 Ops.push_back(getAL(CurDAG)); // Predicate
3306 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3307 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT,
3308 Ops.data(), Ops.size());
3311 case ISD::CONCAT_VECTORS:
3312 return SelectConcatVector(N);
3314 case ARMISD::ATOMOR64_DAG:
3315 return SelectAtomic64(N, ARM::ATOMOR6432);
3316 case ARMISD::ATOMXOR64_DAG:
3317 return SelectAtomic64(N, ARM::ATOMXOR6432);
3318 case ARMISD::ATOMADD64_DAG:
3319 return SelectAtomic64(N, ARM::ATOMADD6432);
3320 case ARMISD::ATOMSUB64_DAG:
3321 return SelectAtomic64(N, ARM::ATOMSUB6432);
3322 case ARMISD::ATOMNAND64_DAG:
3323 return SelectAtomic64(N, ARM::ATOMNAND6432);
3324 case ARMISD::ATOMAND64_DAG:
3325 return SelectAtomic64(N, ARM::ATOMAND6432);
3326 case ARMISD::ATOMSWAP64_DAG:
3327 return SelectAtomic64(N, ARM::ATOMSWAP6432);
3328 case ARMISD::ATOMCMPXCHG64_DAG:
3329 return SelectAtomic64(N, ARM::ATOMCMPXCHG6432);
3331 case ARMISD::ATOMMIN64_DAG:
3332 return SelectAtomic64(N, ARM::ATOMMIN6432);
3333 case ARMISD::ATOMUMIN64_DAG:
3334 return SelectAtomic64(N, ARM::ATOMUMIN6432);
3335 case ARMISD::ATOMMAX64_DAG:
3336 return SelectAtomic64(N, ARM::ATOMMAX6432);
3337 case ARMISD::ATOMUMAX64_DAG:
3338 return SelectAtomic64(N, ARM::ATOMUMAX6432);
3341 return SelectCode(N);
3344 bool ARMDAGToDAGISel::
3345 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3346 std::vector<SDValue> &OutOps) {
3347 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3348 // Require the address to be in a register. That is safe for all ARM
3349 // variants and it is hard to do anything much smarter without knowing
3350 // how the operand is used.
3351 OutOps.push_back(Op);
3355 /// createARMISelDag - This pass converts a legalized DAG into a
3356 /// ARM-specific DAG, ready for instruction scheduling.
3358 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3359 CodeGenOpt::Level OptLevel) {
3360 return new ARMDAGToDAGISel(TM, OptLevel);