1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/CodeGen/SSARegMap.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Support/Debug.h"
33 //===--------------------------------------------------------------------===//
34 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
35 /// instructions for SelectionDAG operations.
38 class ARMDAGToDAGISel : public SelectionDAGISel {
39 ARMTargetLowering Lowering;
41 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
42 /// make the right decision when generating code for different targets.
43 const ARMSubtarget *Subtarget;
46 ARMDAGToDAGISel(ARMTargetMachine &TM)
47 : SelectionDAGISel(Lowering), Lowering(TM),
48 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
51 virtual const char *getPassName() const {
52 return "ARM Instruction Selection";
55 SDNode *Select(SDOperand Op);
56 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
57 bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Base,
58 SDOperand &Offset, SDOperand &Opc);
59 bool SelectAddrMode2Offset(SDOperand Op, SDOperand N,
60 SDOperand &Offset, SDOperand &Opc);
61 bool SelectAddrMode3(SDOperand Op, SDOperand N, SDOperand &Base,
62 SDOperand &Offset, SDOperand &Opc);
63 bool SelectAddrMode3Offset(SDOperand Op, SDOperand N,
64 SDOperand &Offset, SDOperand &Opc);
65 bool SelectAddrMode5(SDOperand Op, SDOperand N, SDOperand &Base,
68 bool SelectAddrModePC(SDOperand Op, SDOperand N, SDOperand &Offset,
71 bool SelectThumbAddrModeRR(SDOperand Op, SDOperand N, SDOperand &Base,
73 bool SelectThumbAddrModeRI5(SDOperand Op, SDOperand N, unsigned Scale,
74 SDOperand &Base, SDOperand &OffImm,
76 bool SelectThumbAddrModeS1(SDOperand Op, SDOperand N, SDOperand &Base,
77 SDOperand &OffImm, SDOperand &Offset);
78 bool SelectThumbAddrModeS2(SDOperand Op, SDOperand N, SDOperand &Base,
79 SDOperand &OffImm, SDOperand &Offset);
80 bool SelectThumbAddrModeS4(SDOperand Op, SDOperand N, SDOperand &Base,
81 SDOperand &OffImm, SDOperand &Offset);
82 bool SelectThumbAddrModeSP(SDOperand Op, SDOperand N, SDOperand &Base,
85 bool SelectShifterOperandReg(SDOperand Op, SDOperand N, SDOperand &A,
86 SDOperand &B, SDOperand &C);
88 // Include the pieces autogenerated from the target description.
89 #include "ARMGenDAGISel.inc"
93 void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
96 DAG.setRoot(SelectRoot(DAG.getRoot()));
97 DAG.RemoveDeadNodes();
99 ScheduleAndEmitDAG(DAG);
102 bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
103 SDOperand &Base, SDOperand &Offset,
105 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
107 if (N.getOpcode() == ISD::FrameIndex) {
108 int FI = cast<FrameIndexSDNode>(N)->getIndex();
109 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
110 } else if (N.getOpcode() == ARMISD::Wrapper) {
111 Base = N.getOperand(0);
113 Offset = CurDAG->getRegister(0, MVT::i32);
114 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
120 // Match simple R +/- imm12 operands.
121 if (N.getOpcode() == ISD::ADD)
122 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
123 int RHSC = (int)RHS->getValue();
124 if ((RHSC >= 0 && RHSC < 0x1000) ||
125 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
126 Base = N.getOperand(0);
127 if (Base.getOpcode() == ISD::FrameIndex) {
128 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
129 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
131 Offset = CurDAG->getRegister(0, MVT::i32);
133 ARM_AM::AddrOpc AddSub = ARM_AM::add;
135 AddSub = ARM_AM::sub;
138 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
145 // Otherwise this is R +/- [possibly shifted] R
146 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
147 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
150 Base = N.getOperand(0);
151 Offset = N.getOperand(1);
153 if (ShOpcVal != ARM_AM::no_shift) {
154 // Check to see if the RHS of the shift is a constant, if not, we can't fold
156 if (ConstantSDNode *Sh =
157 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
158 ShAmt = Sh->getValue();
159 Offset = N.getOperand(1).getOperand(0);
161 ShOpcVal = ARM_AM::no_shift;
165 // Try matching (R shl C) + (R).
166 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
167 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
168 if (ShOpcVal != ARM_AM::no_shift) {
169 // Check to see if the RHS of the shift is a constant, if not, we can't
171 if (ConstantSDNode *Sh =
172 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
173 ShAmt = Sh->getValue();
174 Offset = N.getOperand(0).getOperand(0);
175 Base = N.getOperand(1);
177 ShOpcVal = ARM_AM::no_shift;
182 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
187 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDOperand Op, SDOperand N,
188 SDOperand &Offset, SDOperand &Opc) {
189 unsigned Opcode = Op.getOpcode();
190 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
191 ? cast<LoadSDNode>(Op)->getAddressingMode()
192 : cast<StoreSDNode>(Op)->getAddressingMode();
193 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
194 ? ARM_AM::add : ARM_AM::sub;
195 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
196 int Val = (int)C->getValue();
197 if (Val >= 0 && Val < 0x1000) { // 12 bits.
198 Offset = CurDAG->getRegister(0, MVT::i32);
199 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
207 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
209 if (ShOpcVal != ARM_AM::no_shift) {
210 // Check to see if the RHS of the shift is a constant, if not, we can't fold
212 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
213 ShAmt = Sh->getValue();
214 Offset = N.getOperand(0);
216 ShOpcVal = ARM_AM::no_shift;
220 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
226 bool ARMDAGToDAGISel::SelectAddrMode3(SDOperand Op, SDOperand N,
227 SDOperand &Base, SDOperand &Offset,
229 if (N.getOpcode() == ISD::SUB) {
230 // X - C is canonicalize to X + -C, no need to handle it here.
231 Base = N.getOperand(0);
232 Offset = N.getOperand(1);
233 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
237 if (N.getOpcode() != ISD::ADD) {
239 if (N.getOpcode() == ISD::FrameIndex) {
240 int FI = cast<FrameIndexSDNode>(N)->getIndex();
241 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
243 Offset = CurDAG->getRegister(0, MVT::i32);
244 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
248 // If the RHS is +/- imm8, fold into addr mode.
249 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
250 int RHSC = (int)RHS->getValue();
251 if ((RHSC >= 0 && RHSC < 256) ||
252 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
253 Base = N.getOperand(0);
254 if (Base.getOpcode() == ISD::FrameIndex) {
255 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
256 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
258 Offset = CurDAG->getRegister(0, MVT::i32);
260 ARM_AM::AddrOpc AddSub = ARM_AM::add;
262 AddSub = ARM_AM::sub;
265 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
270 Base = N.getOperand(0);
271 Offset = N.getOperand(1);
272 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
276 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDOperand Op, SDOperand N,
277 SDOperand &Offset, SDOperand &Opc) {
278 unsigned Opcode = Op.getOpcode();
279 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
280 ? cast<LoadSDNode>(Op)->getAddressingMode()
281 : cast<StoreSDNode>(Op)->getAddressingMode();
282 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
283 ? ARM_AM::add : ARM_AM::sub;
284 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
285 int Val = (int)C->getValue();
286 if (Val >= 0 && Val < 256) {
287 Offset = CurDAG->getRegister(0, MVT::i32);
288 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
294 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
299 bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, SDOperand N,
300 SDOperand &Base, SDOperand &Offset) {
301 if (N.getOpcode() != ISD::ADD) {
303 if (N.getOpcode() == ISD::FrameIndex) {
304 int FI = cast<FrameIndexSDNode>(N)->getIndex();
305 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
306 } else if (N.getOpcode() == ARMISD::Wrapper) {
307 Base = N.getOperand(0);
309 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
314 // If the RHS is +/- imm8, fold into addr mode.
315 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
316 int RHSC = (int)RHS->getValue();
317 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
319 if ((RHSC >= 0 && RHSC < 256) ||
320 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
321 Base = N.getOperand(0);
322 if (Base.getOpcode() == ISD::FrameIndex) {
323 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
324 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
327 ARM_AM::AddrOpc AddSub = ARM_AM::add;
329 AddSub = ARM_AM::sub;
332 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
340 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
345 bool ARMDAGToDAGISel::SelectAddrModePC(SDOperand Op, SDOperand N,
346 SDOperand &Offset, SDOperand &Label) {
347 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
348 Offset = N.getOperand(0);
349 SDOperand N1 = N.getOperand(1);
350 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getValue(),
357 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N,
358 SDOperand &Base, SDOperand &Offset){
359 if (N.getOpcode() != ISD::ADD) {
361 // We must materialize a zero in a reg! Returning an constant here won't
362 // work since its node is -1 so it won't get added to the selection queue.
363 // Explicitly issue a tMOVri8 node!
364 Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVri8, MVT::i32,
365 CurDAG->getTargetConstant(0, MVT::i32)), 0);
369 Base = N.getOperand(0);
370 Offset = N.getOperand(1);
375 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N,
376 unsigned Scale, SDOperand &Base,
377 SDOperand &OffImm, SDOperand &Offset) {
379 SDOperand TmpBase, TmpOffImm;
380 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
381 return false; // We want to select tLDRspi / tSTRspi instead.
382 if (N.getOpcode() == ARMISD::Wrapper &&
383 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
384 return false; // We want to select tLDRpci instead.
387 if (N.getOpcode() != ISD::ADD) {
388 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
389 Offset = CurDAG->getRegister(0, MVT::i32);
390 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
394 // Thumb does not have [sp, r] address mode.
395 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
396 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
397 if ((LHSR && LHSR->getReg() == ARM::SP) ||
398 (RHSR && RHSR->getReg() == ARM::SP)) {
400 Offset = CurDAG->getRegister(0, MVT::i32);
401 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
405 // If the RHS is + imm5 * scale, fold into addr mode.
406 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
407 int RHSC = (int)RHS->getValue();
408 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
410 if (RHSC >= 0 && RHSC < 32) {
411 Base = N.getOperand(0);
412 Offset = CurDAG->getRegister(0, MVT::i32);
413 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
419 Base = N.getOperand(0);
420 Offset = N.getOperand(1);
421 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
425 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDOperand Op, SDOperand N,
426 SDOperand &Base, SDOperand &OffImm,
428 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
431 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDOperand Op, SDOperand N,
432 SDOperand &Base, SDOperand &OffImm,
434 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
437 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDOperand Op, SDOperand N,
438 SDOperand &Base, SDOperand &OffImm,
440 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
443 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N,
444 SDOperand &Base, SDOperand &OffImm) {
445 if (N.getOpcode() == ISD::FrameIndex) {
446 int FI = cast<FrameIndexSDNode>(N)->getIndex();
447 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
448 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
452 if (N.getOpcode() != ISD::ADD)
455 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
456 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
457 (LHSR && LHSR->getReg() == ARM::SP)) {
458 // If the RHS is + imm8 * scale, fold into addr mode.
459 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
460 int RHSC = (int)RHS->getValue();
461 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
463 if (RHSC >= 0 && RHSC < 256) {
464 Base = N.getOperand(0);
465 if (Base.getOpcode() == ISD::FrameIndex) {
466 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
467 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
469 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
479 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDOperand Op,
484 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
486 // Don't match base register only case. That is matched to a separate
487 // lower complexity pattern with explicit register operand.
488 if (ShOpcVal == ARM_AM::no_shift) return false;
490 BaseReg = N.getOperand(0);
491 unsigned ShImmVal = 0;
492 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
493 ShReg = CurDAG->getRegister(0, MVT::i32);
494 ShImmVal = RHS->getValue() & 31;
496 ShReg = N.getOperand(1);
498 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
504 SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
506 unsigned Opcode = N->getOpcode();
508 if (Opcode >= ISD::BUILTIN_OP_END && Opcode < ARMISD::FIRST_NUMBER)
509 return NULL; // Already selected.
511 switch (N->getOpcode()) {
513 case ISD::Constant: {
514 unsigned Val = cast<ConstantSDNode>(N)->getValue();
516 if (Subtarget->isThumb())
517 UseCP = (Val > 255 && // MOV
518 ~Val > 255 && // MOV + MVN
519 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
521 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
522 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
523 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
526 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
530 if (Subtarget->isThumb())
531 ResNode = CurDAG->getTargetNode(ARM::tLDRpci, MVT::i32, MVT::Other,
532 CPIdx, CurDAG->getEntryNode());
536 CurDAG->getRegister(0, MVT::i32),
537 CurDAG->getTargetConstant(0, MVT::i32),
538 CurDAG->getEntryNode()
540 ResNode = CurDAG->getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops, 4);
542 ReplaceUses(Op, SDOperand(ResNode, 0));
546 // Other cases are autogenerated.
549 case ISD::FrameIndex: {
550 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
551 int FI = cast<FrameIndexSDNode>(N)->getIndex();
552 unsigned Opc = Subtarget->isThumb() ? ARM::tADDrSPi : ARM::ADDri;
553 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
554 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, TFI,
555 CurDAG->getTargetConstant(0, MVT::i32));
558 // Select add sp, c to tADDhirr.
559 SDOperand N0 = Op.getOperand(0);
560 SDOperand N1 = Op.getOperand(1);
561 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
562 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
563 if (LHSR && LHSR->getReg() == ARM::SP) {
565 std::swap(LHSR, RHSR);
567 if (RHSR && RHSR->getReg() == ARM::SP) {
570 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), N0, N1);
575 if (Subtarget->isThumb())
577 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
578 unsigned RHSV = C->getValue();
580 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
581 SDOperand V = Op.getOperand(0);
583 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
584 SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
585 CurDAG->getTargetConstant(ShImm, MVT::i32)
587 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 4);
589 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
590 SDOperand V = Op.getOperand(0);
592 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
593 SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
594 CurDAG->getTargetConstant(ShImm, MVT::i32)
596 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 4);
601 AddToISelQueue(Op.getOperand(0));
602 return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32,
604 case ARMISD::MULHILOU:
605 AddToISelQueue(Op.getOperand(0));
606 AddToISelQueue(Op.getOperand(1));
607 return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32,
608 Op.getOperand(0), Op.getOperand(1));
609 case ARMISD::MULHILOS:
610 AddToISelQueue(Op.getOperand(0));
611 AddToISelQueue(Op.getOperand(1));
612 return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32,
613 Op.getOperand(0), Op.getOperand(1));
615 LoadSDNode *LD = cast<LoadSDNode>(Op);
616 ISD::MemIndexedMode AM = LD->getAddressingMode();
617 MVT::ValueType LoadedVT = LD->getLoadedVT();
618 if (AM != ISD::UNINDEXED) {
619 SDOperand Offset, AMOpc;
620 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
623 if (LoadedVT == MVT::i32 &&
624 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
625 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
627 } else if (LoadedVT == MVT::i16 &&
628 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
630 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
631 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
632 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
633 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
634 if (LD->getExtensionType() == ISD::SEXTLOAD) {
635 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
637 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
640 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
642 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
648 SDOperand Chain = LD->getChain();
649 SDOperand Base = LD->getBasePtr();
650 AddToISelQueue(Chain);
651 AddToISelQueue(Base);
652 AddToISelQueue(Offset);
653 SDOperand Ops[] = { Base, Offset, AMOpc, Chain };
654 return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
658 // Other cases are autogenerated.
663 return SelectCode(Op);
666 /// createARMISelDag - This pass converts a legalized DAG into a
667 /// ARM-specific DAG, ready for instruction scheduling.
669 FunctionPass *llvm::createARMISelDag(ARMTargetMachine &TM) {
670 return new ARMDAGToDAGISel(TM);