1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
41 DisableShifterOp("disable-shifter-op", cl::Hidden,
42 cl::desc("Disable isel of shifter-op"),
46 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47 cl::desc("Check fp vmla / vmls hazard at isel time"),
50 //===--------------------------------------------------------------------===//
51 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
52 /// instructions for SelectionDAG operations.
57 AM2_BASE, // Simple AM2 (+-imm12)
58 AM2_SHOP // Shifter-op AM2
61 class ARMDAGToDAGISel : public SelectionDAGISel {
62 ARMBaseTargetMachine &TM;
63 const ARMBaseInstrInfo *TII;
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when generating code for different targets.
67 const ARMSubtarget *Subtarget;
70 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
71 CodeGenOpt::Level OptLevel)
72 : SelectionDAGISel(tm, OptLevel), TM(tm),
73 TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
74 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
77 virtual const char *getPassName() const {
78 return "ARM Instruction Selection";
81 /// getI32Imm - Return a target constant of type i32 with the specified
83 inline SDValue getI32Imm(unsigned Imm) {
84 return CurDAG->getTargetConstant(Imm, MVT::i32);
87 SDNode *Select(SDNode *N);
90 bool hasNoVMLxHazardUse(SDNode *N) const;
91 bool isShifterOpProfitable(const SDValue &Shift,
92 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
93 bool SelectShifterOperandReg(SDValue N, SDValue &A,
94 SDValue &B, SDValue &C);
95 bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
96 SDValue &B, SDValue &C);
97 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
98 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
100 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
101 SDValue &Offset, SDValue &Opc);
102 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
104 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
107 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
109 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
112 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
114 SelectAddrMode2Worker(N, Base, Offset, Opc);
115 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
116 // This always matches one way or another.
120 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
121 SDValue &Offset, SDValue &Opc);
122 bool SelectAddrMode3(SDValue N, SDValue &Base,
123 SDValue &Offset, SDValue &Opc);
124 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
125 SDValue &Offset, SDValue &Opc);
126 bool SelectAddrMode5(SDValue N, SDValue &Base,
128 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
129 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
131 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
133 // Thumb Addressing Modes:
134 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
135 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
137 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
138 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
139 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
140 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
142 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
144 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
146 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
148 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
150 // Thumb 2 Addressing Modes:
151 bool SelectT2ShifterOperandReg(SDValue N,
152 SDValue &BaseReg, SDValue &Opc);
153 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
154 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
156 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
158 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
159 SDValue &OffReg, SDValue &ShImm);
161 inline bool is_so_imm(unsigned Imm) const {
162 return ARM_AM::getSOImmVal(Imm) != -1;
165 inline bool is_so_imm_not(unsigned Imm) const {
166 return ARM_AM::getSOImmVal(~Imm) != -1;
169 inline bool is_t2_so_imm(unsigned Imm) const {
170 return ARM_AM::getT2SOImmVal(Imm) != -1;
173 inline bool is_t2_so_imm_not(unsigned Imm) const {
174 return ARM_AM::getT2SOImmVal(~Imm) != -1;
177 inline bool Pred_so_imm(SDNode *inN) const {
178 ConstantSDNode *N = cast<ConstantSDNode>(inN);
179 return is_so_imm(N->getZExtValue());
182 inline bool Pred_t2_so_imm(SDNode *inN) const {
183 ConstantSDNode *N = cast<ConstantSDNode>(inN);
184 return is_t2_so_imm(N->getZExtValue());
187 // Include the pieces autogenerated from the target description.
188 #include "ARMGenDAGISel.inc"
191 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
193 SDNode *SelectARMIndexedLoad(SDNode *N);
194 SDNode *SelectT2IndexedLoad(SDNode *N);
196 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
197 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
198 /// loads of D registers and even subregs and odd subregs of Q registers.
199 /// For NumVecs <= 2, QOpcodes1 is not used.
200 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
202 unsigned *QOpcodes0, unsigned *QOpcodes1);
204 /// SelectVST - Select NEON store intrinsics. NumVecs should
205 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
206 /// stores of D registers and even subregs and odd subregs of Q registers.
207 /// For NumVecs <= 2, QOpcodes1 is not used.
208 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
210 unsigned *QOpcodes0, unsigned *QOpcodes1);
212 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
213 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
214 /// load/store of D registers and Q registers.
215 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
216 bool isUpdating, unsigned NumVecs,
217 unsigned *DOpcodes, unsigned *QOpcodes);
219 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
220 /// should be 2, 3 or 4. The opcode array specifies the instructions used
221 /// for loading D registers. (Q registers are not supported.)
222 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
225 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
226 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
227 /// generated to force the table registers to be consecutive.
228 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
230 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
231 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
233 /// SelectCMOVOp - Select CMOV instructions for ARM.
234 SDNode *SelectCMOVOp(SDNode *N);
235 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
236 ARMCC::CondCodes CCVal, SDValue CCR,
238 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
239 ARMCC::CondCodes CCVal, SDValue CCR,
241 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
242 ARMCC::CondCodes CCVal, SDValue CCR,
244 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
245 ARMCC::CondCodes CCVal, SDValue CCR,
248 SDNode *SelectConcatVector(SDNode *N);
250 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
251 /// inline asm expressions.
252 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
254 std::vector<SDValue> &OutOps);
256 // Form pairs of consecutive S, D, or Q registers.
257 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
258 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
259 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
261 // Form sequences of 4 consecutive S, D, or Q registers.
262 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
263 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
264 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
266 // Get the alignment operand for a NEON VLD or VST instruction.
267 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
271 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
272 /// operand. If so Imm will receive the 32-bit value.
273 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
274 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
275 Imm = cast<ConstantSDNode>(N)->getZExtValue();
281 // isInt32Immediate - This method tests to see if a constant operand.
282 // If so Imm will receive the 32 bit value.
283 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
284 return isInt32Immediate(N.getNode(), Imm);
287 // isOpcWithIntImmediate - This method tests to see if the node is a specific
288 // opcode and that it has a immediate integer right operand.
289 // If so Imm will receive the 32 bit value.
290 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
291 return N->getOpcode() == Opc &&
292 isInt32Immediate(N->getOperand(1).getNode(), Imm);
295 /// \brief Check whether a particular node is a constant value representable as
296 /// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
298 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
299 static bool isScaledConstantInRange(SDValue Node, unsigned Scale,
300 int RangeMin, int RangeMax,
301 int &ScaledConstant) {
302 assert(Scale && "Invalid scale!");
304 // Check that this is a constant.
305 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
309 ScaledConstant = (int) C->getZExtValue();
310 if ((ScaledConstant % Scale) != 0)
313 ScaledConstant /= Scale;
314 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
317 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
318 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
319 /// least on current ARM implementations) which should be avoidded.
320 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
321 if (OptLevel == CodeGenOpt::None)
324 if (!CheckVMLxHazard)
327 if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
333 SDNode *Use = *N->use_begin();
334 if (Use->getOpcode() == ISD::CopyToReg)
336 if (Use->isMachineOpcode()) {
337 const TargetInstrDesc &TID = TII->get(Use->getMachineOpcode());
340 unsigned Opcode = TID.getOpcode();
341 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
343 // vmlx feeding into another vmlx. We actually want to unfold
344 // the use later in the MLxExpansion pass. e.g.
346 // vmla (stall 8 cycles)
351 // This adds up to about 18 - 19 cycles.
354 // vmul (stall 4 cycles)
355 // vadd adds up to about 14 cycles.
356 return TII->isFpMLxInstruction(Opcode);
362 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
363 ARM_AM::ShiftOpc ShOpcVal,
365 if (!Subtarget->isCortexA9())
367 if (Shift.hasOneUse())
370 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
373 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
377 if (DisableShifterOp)
380 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
382 // Don't match base register only case. That is matched to a separate
383 // lower complexity pattern with explicit register operand.
384 if (ShOpcVal == ARM_AM::no_shift) return false;
386 BaseReg = N.getOperand(0);
387 unsigned ShImmVal = 0;
388 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
389 ShReg = CurDAG->getRegister(0, MVT::i32);
390 ShImmVal = RHS->getZExtValue() & 31;
392 ShReg = N.getOperand(1);
393 if (!isShifterOpProfitable(N, ShOpcVal, ShImmVal))
396 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
401 bool ARMDAGToDAGISel::SelectShiftShifterOperandReg(SDValue N,
405 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
407 // Don't match base register only case. That is matched to a separate
408 // lower complexity pattern with explicit register operand.
409 if (ShOpcVal == ARM_AM::no_shift) return false;
411 BaseReg = N.getOperand(0);
412 unsigned ShImmVal = 0;
413 // Do not check isShifterOpProfitable. This must return true.
414 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
415 ShReg = CurDAG->getRegister(0, MVT::i32);
416 ShImmVal = RHS->getZExtValue() & 31;
418 ShReg = N.getOperand(1);
420 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
425 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
428 // Match simple R + imm12 operands.
431 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
432 !CurDAG->isBaseWithConstantOffset(N)) {
433 if (N.getOpcode() == ISD::FrameIndex) {
434 // Match frame index.
435 int FI = cast<FrameIndexSDNode>(N)->getIndex();
436 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
437 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
441 if (N.getOpcode() == ARMISD::Wrapper &&
442 !(Subtarget->useMovt() &&
443 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
444 Base = N.getOperand(0);
447 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
451 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
452 int RHSC = (int)RHS->getZExtValue();
453 if (N.getOpcode() == ISD::SUB)
456 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
457 Base = N.getOperand(0);
458 if (Base.getOpcode() == ISD::FrameIndex) {
459 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
460 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
462 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
469 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
475 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
477 if (N.getOpcode() == ISD::MUL &&
478 (!Subtarget->isCortexA9() || N.hasOneUse())) {
479 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
480 // X * [3,5,9] -> X + X * [2,4,8] etc.
481 int RHSC = (int)RHS->getZExtValue();
484 ARM_AM::AddrOpc AddSub = ARM_AM::add;
486 AddSub = ARM_AM::sub;
489 if (isPowerOf2_32(RHSC)) {
490 unsigned ShAmt = Log2_32(RHSC);
491 Base = Offset = N.getOperand(0);
492 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
501 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
502 // ISD::OR that is equivalent to an ISD::ADD.
503 !CurDAG->isBaseWithConstantOffset(N))
506 // Leave simple R +/- imm12 operands for LDRi12
507 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
509 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
510 -0x1000+1, 0x1000, RHSC)) // 12 bits.
514 if (Subtarget->isCortexA9() && !N.hasOneUse())
515 // Compute R +/- (R << N) and reuse it.
518 // Otherwise this is R +/- [possibly shifted] R.
519 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
520 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
523 Base = N.getOperand(0);
524 Offset = N.getOperand(1);
526 if (ShOpcVal != ARM_AM::no_shift) {
527 // Check to see if the RHS of the shift is a constant, if not, we can't fold
529 if (ConstantSDNode *Sh =
530 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
531 ShAmt = Sh->getZExtValue();
532 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
533 Offset = N.getOperand(1).getOperand(0);
536 ShOpcVal = ARM_AM::no_shift;
539 ShOpcVal = ARM_AM::no_shift;
543 // Try matching (R shl C) + (R).
544 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
545 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
546 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
547 if (ShOpcVal != ARM_AM::no_shift) {
548 // Check to see if the RHS of the shift is a constant, if not, we can't
550 if (ConstantSDNode *Sh =
551 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
552 ShAmt = Sh->getZExtValue();
553 if (!Subtarget->isCortexA9() ||
555 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
556 Offset = N.getOperand(0).getOperand(0);
557 Base = N.getOperand(1);
560 ShOpcVal = ARM_AM::no_shift;
563 ShOpcVal = ARM_AM::no_shift;
568 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
578 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
582 if (N.getOpcode() == ISD::MUL &&
583 (!Subtarget->isCortexA9() || N.hasOneUse())) {
584 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
585 // X * [3,5,9] -> X + X * [2,4,8] etc.
586 int RHSC = (int)RHS->getZExtValue();
589 ARM_AM::AddrOpc AddSub = ARM_AM::add;
591 AddSub = ARM_AM::sub;
594 if (isPowerOf2_32(RHSC)) {
595 unsigned ShAmt = Log2_32(RHSC);
596 Base = Offset = N.getOperand(0);
597 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
606 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
607 // ISD::OR that is equivalent to an ADD.
608 !CurDAG->isBaseWithConstantOffset(N)) {
610 if (N.getOpcode() == ISD::FrameIndex) {
611 int FI = cast<FrameIndexSDNode>(N)->getIndex();
612 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
613 } else if (N.getOpcode() == ARMISD::Wrapper &&
614 !(Subtarget->useMovt() &&
615 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
616 Base = N.getOperand(0);
618 Offset = CurDAG->getRegister(0, MVT::i32);
619 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
625 // Match simple R +/- imm12 operands.
626 if (N.getOpcode() != ISD::SUB) {
628 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
629 -0x1000+1, 0x1000, RHSC)) { // 12 bits.
630 Base = N.getOperand(0);
631 if (Base.getOpcode() == ISD::FrameIndex) {
632 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
633 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
635 Offset = CurDAG->getRegister(0, MVT::i32);
637 ARM_AM::AddrOpc AddSub = ARM_AM::add;
639 AddSub = ARM_AM::sub;
642 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
649 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
650 // Compute R +/- (R << N) and reuse it.
652 Offset = CurDAG->getRegister(0, MVT::i32);
653 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
659 // Otherwise this is R +/- [possibly shifted] R.
660 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
661 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
664 Base = N.getOperand(0);
665 Offset = N.getOperand(1);
667 if (ShOpcVal != ARM_AM::no_shift) {
668 // Check to see if the RHS of the shift is a constant, if not, we can't fold
670 if (ConstantSDNode *Sh =
671 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
672 ShAmt = Sh->getZExtValue();
673 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
674 Offset = N.getOperand(1).getOperand(0);
677 ShOpcVal = ARM_AM::no_shift;
680 ShOpcVal = ARM_AM::no_shift;
684 // Try matching (R shl C) + (R).
685 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
686 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
687 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
688 if (ShOpcVal != ARM_AM::no_shift) {
689 // Check to see if the RHS of the shift is a constant, if not, we can't
691 if (ConstantSDNode *Sh =
692 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
693 ShAmt = Sh->getZExtValue();
694 if (!Subtarget->isCortexA9() ||
696 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
697 Offset = N.getOperand(0).getOperand(0);
698 Base = N.getOperand(1);
701 ShOpcVal = ARM_AM::no_shift;
704 ShOpcVal = ARM_AM::no_shift;
709 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
714 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
715 SDValue &Offset, SDValue &Opc) {
716 unsigned Opcode = Op->getOpcode();
717 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
718 ? cast<LoadSDNode>(Op)->getAddressingMode()
719 : cast<StoreSDNode>(Op)->getAddressingMode();
720 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
721 ? ARM_AM::add : ARM_AM::sub;
723 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
724 Offset = CurDAG->getRegister(0, MVT::i32);
725 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
732 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
734 if (ShOpcVal != ARM_AM::no_shift) {
735 // Check to see if the RHS of the shift is a constant, if not, we can't fold
737 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
738 ShAmt = Sh->getZExtValue();
739 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
740 Offset = N.getOperand(0);
743 ShOpcVal = ARM_AM::no_shift;
746 ShOpcVal = ARM_AM::no_shift;
750 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
756 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
757 SDValue &Base, SDValue &Offset,
759 if (N.getOpcode() == ISD::SUB) {
760 // X - C is canonicalize to X + -C, no need to handle it here.
761 Base = N.getOperand(0);
762 Offset = N.getOperand(1);
763 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
767 if (!CurDAG->isBaseWithConstantOffset(N)) {
769 if (N.getOpcode() == ISD::FrameIndex) {
770 int FI = cast<FrameIndexSDNode>(N)->getIndex();
771 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
773 Offset = CurDAG->getRegister(0, MVT::i32);
774 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
778 // If the RHS is +/- imm8, fold into addr mode.
780 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
781 -256 + 1, 256, RHSC)) { // 8 bits.
782 Base = N.getOperand(0);
783 if (Base.getOpcode() == ISD::FrameIndex) {
784 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
785 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
787 Offset = CurDAG->getRegister(0, MVT::i32);
789 ARM_AM::AddrOpc AddSub = ARM_AM::add;
791 AddSub = ARM_AM::sub;
794 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
798 Base = N.getOperand(0);
799 Offset = N.getOperand(1);
800 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
804 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
805 SDValue &Offset, SDValue &Opc) {
806 unsigned Opcode = Op->getOpcode();
807 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
808 ? cast<LoadSDNode>(Op)->getAddressingMode()
809 : cast<StoreSDNode>(Op)->getAddressingMode();
810 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
811 ? ARM_AM::add : ARM_AM::sub;
813 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
814 Offset = CurDAG->getRegister(0, MVT::i32);
815 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
820 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
824 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
825 SDValue &Base, SDValue &Offset) {
826 if (!CurDAG->isBaseWithConstantOffset(N)) {
828 if (N.getOpcode() == ISD::FrameIndex) {
829 int FI = cast<FrameIndexSDNode>(N)->getIndex();
830 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
831 } else if (N.getOpcode() == ARMISD::Wrapper &&
832 !(Subtarget->useMovt() &&
833 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
834 Base = N.getOperand(0);
836 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
841 // If the RHS is +/- imm8, fold into addr mode.
843 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
844 -256 + 1, 256, RHSC)) {
845 Base = N.getOperand(0);
846 if (Base.getOpcode() == ISD::FrameIndex) {
847 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
848 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
851 ARM_AM::AddrOpc AddSub = ARM_AM::add;
853 AddSub = ARM_AM::sub;
856 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
862 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
867 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
871 unsigned Alignment = 0;
872 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
873 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
874 // The maximum alignment is equal to the memory size being referenced.
875 unsigned LSNAlign = LSN->getAlignment();
876 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
877 if (LSNAlign > MemSize && MemSize > 1)
880 // All other uses of addrmode6 are for intrinsics. For now just record
881 // the raw alignment value; it will be refined later based on the legal
882 // alignment operands for the intrinsic.
883 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
886 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
890 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
892 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
893 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
894 if (AM != ISD::POST_INC)
897 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
898 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
899 Offset = CurDAG->getRegister(0, MVT::i32);
904 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
905 SDValue &Offset, SDValue &Label) {
906 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
907 Offset = N.getOperand(0);
908 SDValue N1 = N.getOperand(1);
909 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
918 //===----------------------------------------------------------------------===//
919 // Thumb Addressing Modes
920 //===----------------------------------------------------------------------===//
922 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
923 SDValue &Base, SDValue &Offset){
924 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
925 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
926 if (!NC || !NC->isNullValue())
933 Base = N.getOperand(0);
934 Offset = N.getOperand(1);
939 ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
940 SDValue &Offset, unsigned Scale) {
942 SDValue TmpBase, TmpOffImm;
943 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
944 return false; // We want to select tLDRspi / tSTRspi instead.
946 if (N.getOpcode() == ARMISD::Wrapper &&
947 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
948 return false; // We want to select tLDRpci instead.
951 if (!CurDAG->isBaseWithConstantOffset(N))
954 // Thumb does not have [sp, r] address mode.
955 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
956 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
957 if ((LHSR && LHSR->getReg() == ARM::SP) ||
958 (RHSR && RHSR->getReg() == ARM::SP))
961 // FIXME: Why do we explicitly check for a match here and then return false?
962 // Presumably to allow something else to match, but shouldn't this be
965 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
968 Base = N.getOperand(0);
969 Offset = N.getOperand(1);
974 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
977 return SelectThumbAddrModeRI(N, Base, Offset, 1);
981 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
984 return SelectThumbAddrModeRI(N, Base, Offset, 2);
988 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
991 return SelectThumbAddrModeRI(N, Base, Offset, 4);
995 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
996 SDValue &Base, SDValue &OffImm) {
998 SDValue TmpBase, TmpOffImm;
999 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1000 return false; // We want to select tLDRspi / tSTRspi instead.
1002 if (N.getOpcode() == ARMISD::Wrapper &&
1003 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1004 return false; // We want to select tLDRpci instead.
1007 if (!CurDAG->isBaseWithConstantOffset(N)) {
1008 if (N.getOpcode() == ARMISD::Wrapper &&
1009 !(Subtarget->useMovt() &&
1010 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1011 Base = N.getOperand(0);
1016 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1020 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1021 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1022 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1023 (RHSR && RHSR->getReg() == ARM::SP)) {
1024 ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1025 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1026 unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1027 unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1029 // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1030 if (LHSC != 0 || RHSC != 0) return false;
1033 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1037 // If the RHS is + imm5 * scale, fold into addr mode.
1039 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1040 Base = N.getOperand(0);
1041 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1045 Base = N.getOperand(0);
1046 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1051 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1053 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1057 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1059 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1063 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1065 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1068 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1069 SDValue &Base, SDValue &OffImm) {
1070 if (N.getOpcode() == ISD::FrameIndex) {
1071 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1072 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1073 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1077 if (!CurDAG->isBaseWithConstantOffset(N))
1080 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1081 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1082 (LHSR && LHSR->getReg() == ARM::SP)) {
1083 // If the RHS is + imm8 * scale, fold into addr mode.
1085 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1086 Base = N.getOperand(0);
1087 if (Base.getOpcode() == ISD::FrameIndex) {
1088 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1089 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1091 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1100 //===----------------------------------------------------------------------===//
1101 // Thumb 2 Addressing Modes
1102 //===----------------------------------------------------------------------===//
1105 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1107 if (DisableShifterOp)
1110 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
1112 // Don't match base register only case. That is matched to a separate
1113 // lower complexity pattern with explicit register operand.
1114 if (ShOpcVal == ARM_AM::no_shift) return false;
1116 BaseReg = N.getOperand(0);
1117 unsigned ShImmVal = 0;
1118 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1119 ShImmVal = RHS->getZExtValue() & 31;
1120 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1127 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1128 SDValue &Base, SDValue &OffImm) {
1129 // Match simple R + imm12 operands.
1132 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1133 !CurDAG->isBaseWithConstantOffset(N)) {
1134 if (N.getOpcode() == ISD::FrameIndex) {
1135 // Match frame index.
1136 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1137 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1138 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1142 if (N.getOpcode() == ARMISD::Wrapper &&
1143 !(Subtarget->useMovt() &&
1144 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1145 Base = N.getOperand(0);
1146 if (Base.getOpcode() == ISD::TargetConstantPool)
1147 return false; // We want to select t2LDRpci instead.
1150 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1154 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1155 if (SelectT2AddrModeImm8(N, Base, OffImm))
1156 // Let t2LDRi8 handle (R - imm8).
1159 int RHSC = (int)RHS->getZExtValue();
1160 if (N.getOpcode() == ISD::SUB)
1163 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1164 Base = N.getOperand(0);
1165 if (Base.getOpcode() == ISD::FrameIndex) {
1166 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1167 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1169 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1176 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1180 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1181 SDValue &Base, SDValue &OffImm) {
1182 // Match simple R - imm8 operands.
1183 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1184 !CurDAG->isBaseWithConstantOffset(N))
1187 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1188 int RHSC = (int)RHS->getSExtValue();
1189 if (N.getOpcode() == ISD::SUB)
1192 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1193 Base = N.getOperand(0);
1194 if (Base.getOpcode() == ISD::FrameIndex) {
1195 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1196 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1198 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1206 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1208 unsigned Opcode = Op->getOpcode();
1209 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1210 ? cast<LoadSDNode>(Op)->getAddressingMode()
1211 : cast<StoreSDNode>(Op)->getAddressingMode();
1213 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1214 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1215 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1216 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1223 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1225 SDValue &OffReg, SDValue &ShImm) {
1226 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1227 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1230 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1231 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1232 int RHSC = (int)RHS->getZExtValue();
1233 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1235 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1239 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1240 // Compute R + (R << [1,2,3]) and reuse it.
1245 // Look for (R + R) or (R + (R << [1,2,3])).
1247 Base = N.getOperand(0);
1248 OffReg = N.getOperand(1);
1250 // Swap if it is ((R << c) + R).
1251 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
1252 if (ShOpcVal != ARM_AM::lsl) {
1253 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
1254 if (ShOpcVal == ARM_AM::lsl)
1255 std::swap(Base, OffReg);
1258 if (ShOpcVal == ARM_AM::lsl) {
1259 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1261 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1262 ShAmt = Sh->getZExtValue();
1263 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1264 OffReg = OffReg.getOperand(0);
1267 ShOpcVal = ARM_AM::no_shift;
1270 ShOpcVal = ARM_AM::no_shift;
1274 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1279 //===--------------------------------------------------------------------===//
1281 /// getAL - Returns a ARMCC::AL immediate node.
1282 static inline SDValue getAL(SelectionDAG *CurDAG) {
1283 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1286 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1287 LoadSDNode *LD = cast<LoadSDNode>(N);
1288 ISD::MemIndexedMode AM = LD->getAddressingMode();
1289 if (AM == ISD::UNINDEXED)
1292 EVT LoadedVT = LD->getMemoryVT();
1293 SDValue Offset, AMOpc;
1294 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1295 unsigned Opcode = 0;
1297 if (LoadedVT == MVT::i32 &&
1298 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1299 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
1301 } else if (LoadedVT == MVT::i16 &&
1302 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1304 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1305 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1306 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1307 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1308 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1309 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1311 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1314 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1316 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
1322 SDValue Chain = LD->getChain();
1323 SDValue Base = LD->getBasePtr();
1324 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1325 CurDAG->getRegister(0, MVT::i32), Chain };
1326 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1327 MVT::Other, Ops, 6);
1333 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1334 LoadSDNode *LD = cast<LoadSDNode>(N);
1335 ISD::MemIndexedMode AM = LD->getAddressingMode();
1336 if (AM == ISD::UNINDEXED)
1339 EVT LoadedVT = LD->getMemoryVT();
1340 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1342 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1343 unsigned Opcode = 0;
1345 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1346 switch (LoadedVT.getSimpleVT().SimpleTy) {
1348 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1352 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1354 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1359 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1361 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1370 SDValue Chain = LD->getChain();
1371 SDValue Base = LD->getBasePtr();
1372 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1373 CurDAG->getRegister(0, MVT::i32), Chain };
1374 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1375 MVT::Other, Ops, 5);
1381 /// PairSRegs - Form a D register from a pair of S registers.
1383 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1384 DebugLoc dl = V0.getNode()->getDebugLoc();
1385 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1386 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1387 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1388 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1391 /// PairDRegs - Form a quad register from a pair of D registers.
1393 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1394 DebugLoc dl = V0.getNode()->getDebugLoc();
1395 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1396 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1397 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1398 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1401 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1403 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1404 DebugLoc dl = V0.getNode()->getDebugLoc();
1405 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1406 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1407 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1408 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1411 /// QuadSRegs - Form 4 consecutive S registers.
1413 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1414 SDValue V2, SDValue V3) {
1415 DebugLoc dl = V0.getNode()->getDebugLoc();
1416 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1417 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1418 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1419 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1420 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1421 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1424 /// QuadDRegs - Form 4 consecutive D registers.
1426 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1427 SDValue V2, SDValue V3) {
1428 DebugLoc dl = V0.getNode()->getDebugLoc();
1429 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1430 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1431 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1432 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1433 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1434 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1437 /// QuadQRegs - Form 4 consecutive Q registers.
1439 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1440 SDValue V2, SDValue V3) {
1441 DebugLoc dl = V0.getNode()->getDebugLoc();
1442 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1443 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1444 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1445 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1446 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1447 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1450 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1451 /// of a NEON VLD or VST instruction. The supported values depend on the
1452 /// number of registers being loaded.
1453 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1454 bool is64BitVector) {
1455 unsigned NumRegs = NumVecs;
1456 if (!is64BitVector && NumVecs < 3)
1459 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1460 if (Alignment >= 32 && NumRegs == 4)
1462 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1464 else if (Alignment >= 8)
1469 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1472 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1473 unsigned *DOpcodes, unsigned *QOpcodes0,
1474 unsigned *QOpcodes1) {
1475 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1476 DebugLoc dl = N->getDebugLoc();
1478 SDValue MemAddr, Align;
1479 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1480 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1483 SDValue Chain = N->getOperand(0);
1484 EVT VT = N->getValueType(0);
1485 bool is64BitVector = VT.is64BitVector();
1486 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1488 unsigned OpcodeIndex;
1489 switch (VT.getSimpleVT().SimpleTy) {
1490 default: llvm_unreachable("unhandled vld type");
1491 // Double-register operations:
1492 case MVT::v8i8: OpcodeIndex = 0; break;
1493 case MVT::v4i16: OpcodeIndex = 1; break;
1495 case MVT::v2i32: OpcodeIndex = 2; break;
1496 case MVT::v1i64: OpcodeIndex = 3; break;
1497 // Quad-register operations:
1498 case MVT::v16i8: OpcodeIndex = 0; break;
1499 case MVT::v8i16: OpcodeIndex = 1; break;
1501 case MVT::v4i32: OpcodeIndex = 2; break;
1502 case MVT::v2i64: OpcodeIndex = 3;
1503 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1511 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1514 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1516 std::vector<EVT> ResTys;
1517 ResTys.push_back(ResTy);
1519 ResTys.push_back(MVT::i32);
1520 ResTys.push_back(MVT::Other);
1522 SDValue Pred = getAL(CurDAG);
1523 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1525 SmallVector<SDValue, 7> Ops;
1527 // Double registers and VLD1/VLD2 quad registers are directly supported.
1528 if (is64BitVector || NumVecs <= 2) {
1529 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1530 QOpcodes0[OpcodeIndex]);
1531 Ops.push_back(MemAddr);
1532 Ops.push_back(Align);
1534 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1535 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1537 Ops.push_back(Pred);
1538 Ops.push_back(Reg0);
1539 Ops.push_back(Chain);
1540 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1543 // Otherwise, quad registers are loaded with two separate instructions,
1544 // where one loads the even registers and the other loads the odd registers.
1545 EVT AddrTy = MemAddr.getValueType();
1547 // Load the even subregs. This is always an updating load, so that it
1548 // provides the address to the second load for the odd subregs.
1550 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1551 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1552 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1553 ResTy, AddrTy, MVT::Other, OpsA, 7);
1554 Chain = SDValue(VLdA, 2);
1556 // Load the odd subregs.
1557 Ops.push_back(SDValue(VLdA, 1));
1558 Ops.push_back(Align);
1560 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1561 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1562 "only constant post-increment update allowed for VLD3/4");
1564 Ops.push_back(Reg0);
1566 Ops.push_back(SDValue(VLdA, 0));
1567 Ops.push_back(Pred);
1568 Ops.push_back(Reg0);
1569 Ops.push_back(Chain);
1570 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1571 Ops.data(), Ops.size());
1577 // Extract out the subregisters.
1578 SDValue SuperReg = SDValue(VLd, 0);
1579 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1580 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1581 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1582 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1583 ReplaceUses(SDValue(N, Vec),
1584 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1585 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1587 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1591 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1592 unsigned *DOpcodes, unsigned *QOpcodes0,
1593 unsigned *QOpcodes1) {
1594 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1595 DebugLoc dl = N->getDebugLoc();
1597 SDValue MemAddr, Align;
1598 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1599 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1600 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1603 SDValue Chain = N->getOperand(0);
1604 EVT VT = N->getOperand(Vec0Idx).getValueType();
1605 bool is64BitVector = VT.is64BitVector();
1606 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1608 unsigned OpcodeIndex;
1609 switch (VT.getSimpleVT().SimpleTy) {
1610 default: llvm_unreachable("unhandled vst type");
1611 // Double-register operations:
1612 case MVT::v8i8: OpcodeIndex = 0; break;
1613 case MVT::v4i16: OpcodeIndex = 1; break;
1615 case MVT::v2i32: OpcodeIndex = 2; break;
1616 case MVT::v1i64: OpcodeIndex = 3; break;
1617 // Quad-register operations:
1618 case MVT::v16i8: OpcodeIndex = 0; break;
1619 case MVT::v8i16: OpcodeIndex = 1; break;
1621 case MVT::v4i32: OpcodeIndex = 2; break;
1622 case MVT::v2i64: OpcodeIndex = 3;
1623 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1627 std::vector<EVT> ResTys;
1629 ResTys.push_back(MVT::i32);
1630 ResTys.push_back(MVT::Other);
1632 SDValue Pred = getAL(CurDAG);
1633 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1634 SmallVector<SDValue, 7> Ops;
1636 // Double registers and VST1/VST2 quad registers are directly supported.
1637 if (is64BitVector || NumVecs <= 2) {
1640 SrcReg = N->getOperand(Vec0Idx);
1641 } else if (is64BitVector) {
1642 // Form a REG_SEQUENCE to force register allocation.
1643 SDValue V0 = N->getOperand(Vec0Idx + 0);
1644 SDValue V1 = N->getOperand(Vec0Idx + 1);
1646 SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1648 SDValue V2 = N->getOperand(Vec0Idx + 2);
1649 // If it's a vst3, form a quad D-register and leave the last part as
1651 SDValue V3 = (NumVecs == 3)
1652 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1653 : N->getOperand(Vec0Idx + 3);
1654 SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1657 // Form a QQ register.
1658 SDValue Q0 = N->getOperand(Vec0Idx);
1659 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1660 SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1663 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1664 QOpcodes0[OpcodeIndex]);
1665 Ops.push_back(MemAddr);
1666 Ops.push_back(Align);
1668 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1669 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1671 Ops.push_back(SrcReg);
1672 Ops.push_back(Pred);
1673 Ops.push_back(Reg0);
1674 Ops.push_back(Chain);
1675 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1678 // Otherwise, quad registers are stored with two separate instructions,
1679 // where one stores the even registers and the other stores the odd registers.
1681 // Form the QQQQ REG_SEQUENCE.
1682 SDValue V0 = N->getOperand(Vec0Idx + 0);
1683 SDValue V1 = N->getOperand(Vec0Idx + 1);
1684 SDValue V2 = N->getOperand(Vec0Idx + 2);
1685 SDValue V3 = (NumVecs == 3)
1686 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1687 : N->getOperand(Vec0Idx + 3);
1688 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1690 // Store the even D registers. This is always an updating store, so that it
1691 // provides the address to the second store for the odd subregs.
1692 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1693 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1694 MemAddr.getValueType(),
1695 MVT::Other, OpsA, 7);
1696 Chain = SDValue(VStA, 1);
1698 // Store the odd D registers.
1699 Ops.push_back(SDValue(VStA, 0));
1700 Ops.push_back(Align);
1702 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1703 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1704 "only constant post-increment update allowed for VST3/4");
1706 Ops.push_back(Reg0);
1708 Ops.push_back(RegSeq);
1709 Ops.push_back(Pred);
1710 Ops.push_back(Reg0);
1711 Ops.push_back(Chain);
1712 return CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1713 Ops.data(), Ops.size());
1716 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1717 bool isUpdating, unsigned NumVecs,
1719 unsigned *QOpcodes) {
1720 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1721 DebugLoc dl = N->getDebugLoc();
1723 SDValue MemAddr, Align;
1724 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1725 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1726 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1729 SDValue Chain = N->getOperand(0);
1731 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1732 EVT VT = N->getOperand(Vec0Idx).getValueType();
1733 bool is64BitVector = VT.is64BitVector();
1735 unsigned Alignment = 0;
1737 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1738 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1739 if (Alignment > NumBytes)
1740 Alignment = NumBytes;
1741 if (Alignment < 8 && Alignment < NumBytes)
1743 // Alignment must be a power of two; make sure of that.
1744 Alignment = (Alignment & -Alignment);
1748 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1750 unsigned OpcodeIndex;
1751 switch (VT.getSimpleVT().SimpleTy) {
1752 default: llvm_unreachable("unhandled vld/vst lane type");
1753 // Double-register operations:
1754 case MVT::v8i8: OpcodeIndex = 0; break;
1755 case MVT::v4i16: OpcodeIndex = 1; break;
1757 case MVT::v2i32: OpcodeIndex = 2; break;
1758 // Quad-register operations:
1759 case MVT::v8i16: OpcodeIndex = 0; break;
1761 case MVT::v4i32: OpcodeIndex = 1; break;
1764 std::vector<EVT> ResTys;
1766 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1769 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1770 MVT::i64, ResTyElts));
1773 ResTys.push_back(MVT::i32);
1774 ResTys.push_back(MVT::Other);
1776 SDValue Pred = getAL(CurDAG);
1777 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1779 SmallVector<SDValue, 8> Ops;
1780 Ops.push_back(MemAddr);
1781 Ops.push_back(Align);
1783 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1784 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1788 SDValue V0 = N->getOperand(Vec0Idx + 0);
1789 SDValue V1 = N->getOperand(Vec0Idx + 1);
1792 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1794 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1796 SDValue V2 = N->getOperand(Vec0Idx + 2);
1797 SDValue V3 = (NumVecs == 3)
1798 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1799 : N->getOperand(Vec0Idx + 3);
1801 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1803 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1805 Ops.push_back(SuperReg);
1806 Ops.push_back(getI32Imm(Lane));
1807 Ops.push_back(Pred);
1808 Ops.push_back(Reg0);
1809 Ops.push_back(Chain);
1811 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1812 QOpcodes[OpcodeIndex]);
1813 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1814 Ops.data(), Ops.size());
1818 // Extract the subregisters.
1819 SuperReg = SDValue(VLdLn, 0);
1820 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1821 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1822 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1823 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1824 ReplaceUses(SDValue(N, Vec),
1825 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1826 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1828 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1832 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
1833 unsigned NumVecs, unsigned *Opcodes) {
1834 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1835 DebugLoc dl = N->getDebugLoc();
1837 SDValue MemAddr, Align;
1838 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
1841 SDValue Chain = N->getOperand(0);
1842 EVT VT = N->getValueType(0);
1844 unsigned Alignment = 0;
1846 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1847 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1848 if (Alignment > NumBytes)
1849 Alignment = NumBytes;
1850 if (Alignment < 8 && Alignment < NumBytes)
1852 // Alignment must be a power of two; make sure of that.
1853 Alignment = (Alignment & -Alignment);
1857 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1859 unsigned OpcodeIndex;
1860 switch (VT.getSimpleVT().SimpleTy) {
1861 default: llvm_unreachable("unhandled vld-dup type");
1862 case MVT::v8i8: OpcodeIndex = 0; break;
1863 case MVT::v4i16: OpcodeIndex = 1; break;
1865 case MVT::v2i32: OpcodeIndex = 2; break;
1868 SDValue Pred = getAL(CurDAG);
1869 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1871 unsigned Opc = Opcodes[OpcodeIndex];
1872 SmallVector<SDValue, 6> Ops;
1873 Ops.push_back(MemAddr);
1874 Ops.push_back(Align);
1876 SDValue Inc = N->getOperand(2);
1877 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1879 Ops.push_back(Pred);
1880 Ops.push_back(Reg0);
1881 Ops.push_back(Chain);
1883 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1884 std::vector<EVT> ResTys;
1885 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts));
1887 ResTys.push_back(MVT::i32);
1888 ResTys.push_back(MVT::Other);
1890 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1891 SuperReg = SDValue(VLdDup, 0);
1893 // Extract the subregisters.
1894 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1895 unsigned SubIdx = ARM::dsub_0;
1896 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1897 ReplaceUses(SDValue(N, Vec),
1898 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1899 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
1901 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
1905 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1907 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1908 DebugLoc dl = N->getDebugLoc();
1909 EVT VT = N->getValueType(0);
1910 unsigned FirstTblReg = IsExt ? 2 : 1;
1912 // Form a REG_SEQUENCE to force register allocation.
1914 SDValue V0 = N->getOperand(FirstTblReg + 0);
1915 SDValue V1 = N->getOperand(FirstTblReg + 1);
1917 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1919 SDValue V2 = N->getOperand(FirstTblReg + 2);
1920 // If it's a vtbl3, form a quad D-register and leave the last part as
1922 SDValue V3 = (NumVecs == 3)
1923 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1924 : N->getOperand(FirstTblReg + 3);
1925 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1928 SmallVector<SDValue, 6> Ops;
1930 Ops.push_back(N->getOperand(1));
1931 Ops.push_back(RegSeq);
1932 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1933 Ops.push_back(getAL(CurDAG)); // predicate
1934 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1935 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1938 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1940 if (!Subtarget->hasV6T2Ops())
1943 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1944 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1947 // For unsigned extracts, check for a shift right and mask
1948 unsigned And_imm = 0;
1949 if (N->getOpcode() == ISD::AND) {
1950 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1952 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1953 if (And_imm & (And_imm + 1))
1956 unsigned Srl_imm = 0;
1957 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1959 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1961 unsigned Width = CountTrailingOnes_32(And_imm);
1962 unsigned LSB = Srl_imm;
1963 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1964 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1965 CurDAG->getTargetConstant(LSB, MVT::i32),
1966 CurDAG->getTargetConstant(Width, MVT::i32),
1967 getAL(CurDAG), Reg0 };
1968 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1974 // Otherwise, we're looking for a shift of a shift
1975 unsigned Shl_imm = 0;
1976 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1977 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1978 unsigned Srl_imm = 0;
1979 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1980 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1981 unsigned Width = 32 - Srl_imm;
1982 int LSB = Srl_imm - Shl_imm;
1985 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1986 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1987 CurDAG->getTargetConstant(LSB, MVT::i32),
1988 CurDAG->getTargetConstant(Width, MVT::i32),
1989 getAL(CurDAG), Reg0 };
1990 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1996 SDNode *ARMDAGToDAGISel::
1997 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1998 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2001 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2002 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
2003 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
2006 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
2007 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
2008 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
2009 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
2011 llvm_unreachable("Unknown so_reg opcode!");
2015 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
2016 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2017 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2018 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2023 SDNode *ARMDAGToDAGISel::
2024 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2025 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2029 if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2030 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2031 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2032 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
2037 SDNode *ARMDAGToDAGISel::
2038 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2039 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2040 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2045 unsigned TrueImm = T->getZExtValue();
2046 if (is_t2_so_imm(TrueImm)) {
2047 Opc = ARM::t2MOVCCi;
2048 } else if (TrueImm <= 0xffff) {
2049 Opc = ARM::t2MOVCCi16;
2050 } else if (is_t2_so_imm_not(TrueImm)) {
2052 Opc = ARM::t2MVNCCi;
2053 } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2055 Opc = ARM::t2MOVCCi32imm;
2059 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2060 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2061 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2062 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2068 SDNode *ARMDAGToDAGISel::
2069 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2070 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2071 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2076 unsigned TrueImm = T->getZExtValue();
2077 bool isSoImm = is_so_imm(TrueImm);
2080 } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2081 Opc = ARM::MOVCCi16;
2082 } else if (is_so_imm_not(TrueImm)) {
2085 } else if (TrueVal.getNode()->hasOneUse() &&
2086 (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2088 Opc = ARM::MOVCCi32imm;
2092 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2093 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2094 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2095 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2101 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2102 EVT VT = N->getValueType(0);
2103 SDValue FalseVal = N->getOperand(0);
2104 SDValue TrueVal = N->getOperand(1);
2105 SDValue CC = N->getOperand(2);
2106 SDValue CCR = N->getOperand(3);
2107 SDValue InFlag = N->getOperand(4);
2108 assert(CC.getOpcode() == ISD::Constant);
2109 assert(CCR.getOpcode() == ISD::Register);
2110 ARMCC::CondCodes CCVal =
2111 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2113 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2114 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2115 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2116 // Pattern complexity = 18 cost = 1 size = 0
2120 if (Subtarget->isThumb()) {
2121 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2122 CCVal, CCR, InFlag);
2124 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2125 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2129 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2130 CCVal, CCR, InFlag);
2132 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2133 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2138 // Pattern: (ARMcmov:i32 GPR:i32:$false,
2139 // (imm:i32)<<P:Pred_so_imm>>:$true,
2141 // Emits: (MOVCCi:i32 GPR:i32:$false,
2142 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2143 // Pattern complexity = 10 cost = 1 size = 0
2144 if (Subtarget->isThumb()) {
2145 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2146 CCVal, CCR, InFlag);
2148 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2149 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2153 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2154 CCVal, CCR, InFlag);
2156 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2157 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2163 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2164 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2165 // Pattern complexity = 6 cost = 1 size = 0
2167 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2168 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2169 // Pattern complexity = 6 cost = 11 size = 0
2171 // Also VMOVScc and VMOVDcc.
2172 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2173 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2175 switch (VT.getSimpleVT().SimpleTy) {
2176 default: assert(false && "Illegal conditional move type!");
2179 Opc = Subtarget->isThumb()
2180 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2190 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2193 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2194 // The only time a CONCAT_VECTORS operation can have legal types is when
2195 // two 64-bit vectors are concatenated to a 128-bit vector.
2196 EVT VT = N->getValueType(0);
2197 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2198 llvm_unreachable("unexpected CONCAT_VECTORS");
2199 return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2202 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2203 DebugLoc dl = N->getDebugLoc();
2205 if (N->isMachineOpcode())
2206 return NULL; // Already selected.
2208 switch (N->getOpcode()) {
2210 case ISD::Constant: {
2211 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2213 if (Subtarget->hasThumb2())
2214 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2215 // be done with MOV + MOVT, at worst.
2218 if (Subtarget->isThumb()) {
2219 UseCP = (Val > 255 && // MOV
2220 ~Val > 255 && // MOV + MVN
2221 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
2223 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2224 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2225 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
2230 CurDAG->getTargetConstantPool(ConstantInt::get(
2231 Type::getInt32Ty(*CurDAG->getContext()), Val),
2232 TLI.getPointerTy());
2235 if (Subtarget->isThumb1Only()) {
2236 SDValue Pred = getAL(CurDAG);
2237 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2238 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2239 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2244 CurDAG->getTargetConstant(0, MVT::i32),
2246 CurDAG->getRegister(0, MVT::i32),
2247 CurDAG->getEntryNode()
2249 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2252 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2256 // Other cases are autogenerated.
2259 case ISD::FrameIndex: {
2260 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2261 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2262 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2263 if (Subtarget->isThumb1Only()) {
2264 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
2265 CurDAG->getTargetConstant(0, MVT::i32));
2267 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2268 ARM::t2ADDri : ARM::ADDri);
2269 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2270 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2271 CurDAG->getRegister(0, MVT::i32) };
2272 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2276 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2280 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2284 if (Subtarget->isThumb1Only())
2286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2287 unsigned RHSV = C->getZExtValue();
2289 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2290 unsigned ShImm = Log2_32(RHSV-1);
2293 SDValue V = N->getOperand(0);
2294 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2295 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2296 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2297 if (Subtarget->isThumb()) {
2298 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2299 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2301 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2302 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
2305 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2306 unsigned ShImm = Log2_32(RHSV+1);
2309 SDValue V = N->getOperand(0);
2310 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2311 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2312 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2313 if (Subtarget->isThumb()) {
2314 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2315 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2317 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2318 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
2324 // Check for unsigned bitfield extract
2325 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2328 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2329 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2330 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2331 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2332 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2333 EVT VT = N->getValueType(0);
2336 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2338 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2341 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2342 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2345 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2346 SDValue N2 = N0.getOperand(1);
2347 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2350 unsigned N1CVal = N1C->getZExtValue();
2351 unsigned N2CVal = N2C->getZExtValue();
2352 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2353 (N1CVal & 0xffffU) == 0xffffU &&
2354 (N2CVal & 0xffffU) == 0x0U) {
2355 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2357 SDValue Ops[] = { N0.getOperand(0), Imm16,
2358 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2359 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2364 case ARMISD::VMOVRRD:
2365 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2366 N->getOperand(0), getAL(CurDAG),
2367 CurDAG->getRegister(0, MVT::i32));
2368 case ISD::UMUL_LOHI: {
2369 if (Subtarget->isThumb1Only())
2371 if (Subtarget->isThumb()) {
2372 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2373 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2374 CurDAG->getRegister(0, MVT::i32) };
2375 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2377 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2378 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2379 CurDAG->getRegister(0, MVT::i32) };
2380 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2381 ARM::UMULL : ARM::UMULLv5,
2382 dl, MVT::i32, MVT::i32, Ops, 5);
2385 case ISD::SMUL_LOHI: {
2386 if (Subtarget->isThumb1Only())
2388 if (Subtarget->isThumb()) {
2389 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2390 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2391 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2393 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2394 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2395 CurDAG->getRegister(0, MVT::i32) };
2396 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2397 ARM::SMULL : ARM::SMULLv5,
2398 dl, MVT::i32, MVT::i32, Ops, 5);
2402 SDNode *ResNode = 0;
2403 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2404 ResNode = SelectT2IndexedLoad(N);
2406 ResNode = SelectARMIndexedLoad(N);
2409 // Other cases are autogenerated.
2412 case ARMISD::BRCOND: {
2413 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2414 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2415 // Pattern complexity = 6 cost = 1 size = 0
2417 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2418 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2419 // Pattern complexity = 6 cost = 1 size = 0
2421 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2422 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2423 // Pattern complexity = 6 cost = 1 size = 0
2425 unsigned Opc = Subtarget->isThumb() ?
2426 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2427 SDValue Chain = N->getOperand(0);
2428 SDValue N1 = N->getOperand(1);
2429 SDValue N2 = N->getOperand(2);
2430 SDValue N3 = N->getOperand(3);
2431 SDValue InFlag = N->getOperand(4);
2432 assert(N1.getOpcode() == ISD::BasicBlock);
2433 assert(N2.getOpcode() == ISD::Constant);
2434 assert(N3.getOpcode() == ISD::Register);
2436 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2437 cast<ConstantSDNode>(N2)->getZExtValue()),
2439 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2440 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2442 Chain = SDValue(ResNode, 0);
2443 if (N->getNumValues() == 2) {
2444 InFlag = SDValue(ResNode, 1);
2445 ReplaceUses(SDValue(N, 1), InFlag);
2447 ReplaceUses(SDValue(N, 0),
2448 SDValue(Chain.getNode(), Chain.getResNo()));
2452 return SelectCMOVOp(N);
2453 case ARMISD::VZIP: {
2455 EVT VT = N->getValueType(0);
2456 switch (VT.getSimpleVT().SimpleTy) {
2457 default: return NULL;
2458 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2459 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2461 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2462 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2463 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2465 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2467 SDValue Pred = getAL(CurDAG);
2468 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2469 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2470 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2472 case ARMISD::VUZP: {
2474 EVT VT = N->getValueType(0);
2475 switch (VT.getSimpleVT().SimpleTy) {
2476 default: return NULL;
2477 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2478 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2480 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2481 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2482 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2484 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2486 SDValue Pred = getAL(CurDAG);
2487 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2488 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2489 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2491 case ARMISD::VTRN: {
2493 EVT VT = N->getValueType(0);
2494 switch (VT.getSimpleVT().SimpleTy) {
2495 default: return NULL;
2496 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2497 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2499 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2500 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2501 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2503 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2505 SDValue Pred = getAL(CurDAG);
2506 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2507 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2508 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2510 case ARMISD::BUILD_VECTOR: {
2511 EVT VecVT = N->getValueType(0);
2512 EVT EltVT = VecVT.getVectorElementType();
2513 unsigned NumElts = VecVT.getVectorNumElements();
2514 if (EltVT == MVT::f64) {
2515 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2516 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2518 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2520 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2521 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2522 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2523 N->getOperand(2), N->getOperand(3));
2526 case ARMISD::VLD2DUP: {
2527 unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2528 ARM::VLD2DUPd32Pseudo };
2529 return SelectVLDDup(N, false, 2, Opcodes);
2532 case ARMISD::VLD3DUP: {
2533 unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2534 ARM::VLD3DUPd32Pseudo };
2535 return SelectVLDDup(N, false, 3, Opcodes);
2538 case ARMISD::VLD4DUP: {
2539 unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2540 ARM::VLD4DUPd32Pseudo };
2541 return SelectVLDDup(N, false, 4, Opcodes);
2544 case ARMISD::VLD2DUP_UPD: {
2545 unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd16Pseudo_UPD,
2546 ARM::VLD2DUPd32Pseudo_UPD };
2547 return SelectVLDDup(N, true, 2, Opcodes);
2550 case ARMISD::VLD3DUP_UPD: {
2551 unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2552 ARM::VLD3DUPd32Pseudo_UPD };
2553 return SelectVLDDup(N, true, 3, Opcodes);
2556 case ARMISD::VLD4DUP_UPD: {
2557 unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2558 ARM::VLD4DUPd32Pseudo_UPD };
2559 return SelectVLDDup(N, true, 4, Opcodes);
2562 case ARMISD::VLD1_UPD: {
2563 unsigned DOpcodes[] = { ARM::VLD1d8_UPD, ARM::VLD1d16_UPD,
2564 ARM::VLD1d32_UPD, ARM::VLD1d64_UPD };
2565 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q16Pseudo_UPD,
2566 ARM::VLD1q32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2567 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2570 case ARMISD::VLD2_UPD: {
2571 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d16Pseudo_UPD,
2572 ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2573 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q16Pseudo_UPD,
2574 ARM::VLD2q32Pseudo_UPD };
2575 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2578 case ARMISD::VLD3_UPD: {
2579 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2580 ARM::VLD3d32Pseudo_UPD, ARM::VLD1d64TPseudo_UPD };
2581 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2582 ARM::VLD3q16Pseudo_UPD,
2583 ARM::VLD3q32Pseudo_UPD };
2584 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2585 ARM::VLD3q16oddPseudo_UPD,
2586 ARM::VLD3q32oddPseudo_UPD };
2587 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2590 case ARMISD::VLD4_UPD: {
2591 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2592 ARM::VLD4d32Pseudo_UPD, ARM::VLD1d64QPseudo_UPD };
2593 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2594 ARM::VLD4q16Pseudo_UPD,
2595 ARM::VLD4q32Pseudo_UPD };
2596 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2597 ARM::VLD4q16oddPseudo_UPD,
2598 ARM::VLD4q32oddPseudo_UPD };
2599 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2602 case ARMISD::VLD2LN_UPD: {
2603 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2604 ARM::VLD2LNd32Pseudo_UPD };
2605 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2606 ARM::VLD2LNq32Pseudo_UPD };
2607 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2610 case ARMISD::VLD3LN_UPD: {
2611 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2612 ARM::VLD3LNd32Pseudo_UPD };
2613 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2614 ARM::VLD3LNq32Pseudo_UPD };
2615 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2618 case ARMISD::VLD4LN_UPD: {
2619 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
2620 ARM::VLD4LNd32Pseudo_UPD };
2621 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2622 ARM::VLD4LNq32Pseudo_UPD };
2623 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2626 case ARMISD::VST1_UPD: {
2627 unsigned DOpcodes[] = { ARM::VST1d8_UPD, ARM::VST1d16_UPD,
2628 ARM::VST1d32_UPD, ARM::VST1d64_UPD };
2629 unsigned QOpcodes[] = { ARM::VST1q8Pseudo_UPD, ARM::VST1q16Pseudo_UPD,
2630 ARM::VST1q32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2631 return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2634 case ARMISD::VST2_UPD: {
2635 unsigned DOpcodes[] = { ARM::VST2d8Pseudo_UPD, ARM::VST2d16Pseudo_UPD,
2636 ARM::VST2d32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2637 unsigned QOpcodes[] = { ARM::VST2q8Pseudo_UPD, ARM::VST2q16Pseudo_UPD,
2638 ARM::VST2q32Pseudo_UPD };
2639 return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2642 case ARMISD::VST3_UPD: {
2643 unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
2644 ARM::VST3d32Pseudo_UPD, ARM::VST1d64TPseudo_UPD };
2645 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2646 ARM::VST3q16Pseudo_UPD,
2647 ARM::VST3q32Pseudo_UPD };
2648 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2649 ARM::VST3q16oddPseudo_UPD,
2650 ARM::VST3q32oddPseudo_UPD };
2651 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2654 case ARMISD::VST4_UPD: {
2655 unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
2656 ARM::VST4d32Pseudo_UPD, ARM::VST1d64QPseudo_UPD };
2657 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2658 ARM::VST4q16Pseudo_UPD,
2659 ARM::VST4q32Pseudo_UPD };
2660 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2661 ARM::VST4q16oddPseudo_UPD,
2662 ARM::VST4q32oddPseudo_UPD };
2663 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2666 case ARMISD::VST2LN_UPD: {
2667 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
2668 ARM::VST2LNd32Pseudo_UPD };
2669 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2670 ARM::VST2LNq32Pseudo_UPD };
2671 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2674 case ARMISD::VST3LN_UPD: {
2675 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
2676 ARM::VST3LNd32Pseudo_UPD };
2677 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2678 ARM::VST3LNq32Pseudo_UPD };
2679 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2682 case ARMISD::VST4LN_UPD: {
2683 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
2684 ARM::VST4LNd32Pseudo_UPD };
2685 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2686 ARM::VST4LNq32Pseudo_UPD };
2687 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2690 case ISD::INTRINSIC_VOID:
2691 case ISD::INTRINSIC_W_CHAIN: {
2692 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2697 case Intrinsic::arm_neon_vld1: {
2698 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2699 ARM::VLD1d32, ARM::VLD1d64 };
2700 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2701 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2702 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
2705 case Intrinsic::arm_neon_vld2: {
2706 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2707 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2708 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2709 ARM::VLD2q32Pseudo };
2710 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
2713 case Intrinsic::arm_neon_vld3: {
2714 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2715 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2716 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2717 ARM::VLD3q16Pseudo_UPD,
2718 ARM::VLD3q32Pseudo_UPD };
2719 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
2720 ARM::VLD3q16oddPseudo,
2721 ARM::VLD3q32oddPseudo };
2722 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2725 case Intrinsic::arm_neon_vld4: {
2726 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2727 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2728 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2729 ARM::VLD4q16Pseudo_UPD,
2730 ARM::VLD4q32Pseudo_UPD };
2731 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
2732 ARM::VLD4q16oddPseudo,
2733 ARM::VLD4q32oddPseudo };
2734 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2737 case Intrinsic::arm_neon_vld2lane: {
2738 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2739 ARM::VLD2LNd32Pseudo };
2740 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2741 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
2744 case Intrinsic::arm_neon_vld3lane: {
2745 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2746 ARM::VLD3LNd32Pseudo };
2747 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2748 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
2751 case Intrinsic::arm_neon_vld4lane: {
2752 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2753 ARM::VLD4LNd32Pseudo };
2754 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2755 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
2758 case Intrinsic::arm_neon_vst1: {
2759 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2760 ARM::VST1d32, ARM::VST1d64 };
2761 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2762 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2763 return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
2766 case Intrinsic::arm_neon_vst2: {
2767 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2768 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2769 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2770 ARM::VST2q32Pseudo };
2771 return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
2774 case Intrinsic::arm_neon_vst3: {
2775 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2776 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2777 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2778 ARM::VST3q16Pseudo_UPD,
2779 ARM::VST3q32Pseudo_UPD };
2780 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
2781 ARM::VST3q16oddPseudo,
2782 ARM::VST3q32oddPseudo };
2783 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2786 case Intrinsic::arm_neon_vst4: {
2787 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2788 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2789 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2790 ARM::VST4q16Pseudo_UPD,
2791 ARM::VST4q32Pseudo_UPD };
2792 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
2793 ARM::VST4q16oddPseudo,
2794 ARM::VST4q32oddPseudo };
2795 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2798 case Intrinsic::arm_neon_vst2lane: {
2799 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
2800 ARM::VST2LNd32Pseudo };
2801 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
2802 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
2805 case Intrinsic::arm_neon_vst3lane: {
2806 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
2807 ARM::VST3LNd32Pseudo };
2808 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
2809 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
2812 case Intrinsic::arm_neon_vst4lane: {
2813 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
2814 ARM::VST4LNd32Pseudo };
2815 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
2816 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
2822 case ISD::INTRINSIC_WO_CHAIN: {
2823 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2828 case Intrinsic::arm_neon_vtbl2:
2829 return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
2830 case Intrinsic::arm_neon_vtbl3:
2831 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
2832 case Intrinsic::arm_neon_vtbl4:
2833 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
2835 case Intrinsic::arm_neon_vtbx2:
2836 return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
2837 case Intrinsic::arm_neon_vtbx3:
2838 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
2839 case Intrinsic::arm_neon_vtbx4:
2840 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
2845 case ARMISD::VTBL1: {
2846 DebugLoc dl = N->getDebugLoc();
2847 EVT VT = N->getValueType(0);
2848 SmallVector<SDValue, 6> Ops;
2850 Ops.push_back(N->getOperand(0));
2851 Ops.push_back(N->getOperand(1));
2852 Ops.push_back(getAL(CurDAG)); // Predicate
2853 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
2854 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
2856 case ARMISD::VTBL2: {
2857 DebugLoc dl = N->getDebugLoc();
2858 EVT VT = N->getValueType(0);
2860 // Form a REG_SEQUENCE to force register allocation.
2861 SDValue V0 = N->getOperand(0);
2862 SDValue V1 = N->getOperand(1);
2863 SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2865 SmallVector<SDValue, 6> Ops;
2866 Ops.push_back(RegSeq);
2867 Ops.push_back(N->getOperand(2));
2868 Ops.push_back(getAL(CurDAG)); // Predicate
2869 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
2870 return CurDAG->getMachineNode(ARM::VTBL2Pseudo, dl, VT,
2871 Ops.data(), Ops.size());
2874 case ISD::CONCAT_VECTORS:
2875 return SelectConcatVector(N);
2878 return SelectCode(N);
2881 bool ARMDAGToDAGISel::
2882 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2883 std::vector<SDValue> &OutOps) {
2884 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2885 // Require the address to be in a register. That is safe for all ARM
2886 // variants and it is hard to do anything much smarter without knowing
2887 // how the operand is used.
2888 OutOps.push_back(Op);
2892 /// createARMISelDag - This pass converts a legalized DAG into a
2893 /// ARM-specific DAG, ready for instruction scheduling.
2895 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2896 CodeGenOpt::Level OptLevel) {
2897 return new ARMDAGToDAGISel(TM, OptLevel);