1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMTargetMachine.h"
16 #include "llvm/CallingConv.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Intrinsics.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/Debug.h"
35 class ARMTargetLowering : public TargetLowering {
36 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
38 ARMTargetLowering(TargetMachine &TM);
39 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
40 virtual const char *getTargetNodeName(unsigned Opcode) const;
45 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
46 : TargetLowering(TM) {
47 addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass);
49 //LLVM requires that a register class supports MVT::f64!
50 addRegisterClass(MVT::f64, ARM::IntRegsRegisterClass);
52 setOperationAction(ISD::RET, MVT::Other, Custom);
53 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
54 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
56 setOperationAction(ISD::SETCC, MVT::i32, Expand);
57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
58 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
60 setOperationAction(ISD::VASTART, MVT::Other, Custom);
61 setOperationAction(ISD::VAEND, MVT::Other, Expand);
63 setSchedulingPreference(SchedulingForRegPressure);
64 computeRegisterProperties();
70 // Start the numbering where the builting ops and target ops leave off.
71 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
72 /// CALL - A direct function call.
75 /// Return with a flag operand.
87 /// DAGCCToARMCC - Convert a DAG integer condition code to an ARM CC
88 static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) {
91 std::cerr << "CC = " << CC << "\n";
92 assert(0 && "Unknown condition code!");
93 case ISD::SETUGT: return ARMCC::HI;
94 case ISD::SETULE: return ARMCC::LS;
95 case ISD::SETLE: return ARMCC::LE;
96 case ISD::SETLT: return ARMCC::LT;
97 case ISD::SETGT: return ARMCC::GT;
98 case ISD::SETNE: return ARMCC::NE;
99 case ISD::SETEQ: return ARMCC::EQ;
100 case ISD::SETGE: return ARMCC::GE;
101 case ISD::SETUGE: return ARMCC::CS;
102 case ISD::SETULT: return ARMCC::CC;
106 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
109 case ARMISD::CALL: return "ARMISD::CALL";
110 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
111 case ARMISD::SELECT: return "ARMISD::SELECT";
112 case ARMISD::CMP: return "ARMISD::CMP";
113 case ARMISD::BR: return "ARMISD::BR";
117 // This transforms a ISD::CALL node into a
118 // callseq_star <- ARMISD:CALL <- callseq_end
120 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
121 SDOperand Chain = Op.getOperand(0);
122 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
123 assert(CallConv == CallingConv::C && "unknown calling convention");
124 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
125 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
126 assert(isTailCall == false && "tail call not supported");
127 SDOperand Callee = Op.getOperand(4);
128 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
130 // Count how many bytes are to be pushed on the stack.
131 unsigned NumBytes = 0;
133 // Add up all the space actually used.
134 for (unsigned i = 4; i < NumOps; ++i)
135 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
137 // Adjust the stack pointer for the new arguments...
138 // These operations are automatically eliminated by the prolog/epilog pass
139 Chain = DAG.getCALLSEQ_START(Chain,
140 DAG.getConstant(NumBytes, MVT::i32));
142 SDOperand StackPtr = DAG.getRegister(ARM::R13, MVT::i32);
144 static const unsigned int num_regs = 4;
145 static const unsigned regs[num_regs] = {
146 ARM::R0, ARM::R1, ARM::R2, ARM::R3
149 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
150 std::vector<SDOperand> MemOpChains;
152 for (unsigned i = 0; i != NumOps; ++i) {
153 SDOperand Arg = Op.getOperand(5+2*i);
154 assert(Arg.getValueType() == MVT::i32);
156 RegsToPass.push_back(std::make_pair(regs[i], Arg));
158 unsigned ArgOffset = (i - num_regs) * 4;
159 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
160 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
161 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
162 Arg, PtrOff, DAG.getSrcValue(NULL)));
165 if (!MemOpChains.empty())
166 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
167 &MemOpChains[0], MemOpChains.size());
169 // Build a sequence of copy-to-reg nodes chained together with token chain
170 // and flag operands which copy the outgoing args into the appropriate regs.
172 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
173 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
175 InFlag = Chain.getValue(1);
178 std::vector<MVT::ValueType> NodeTys;
179 NodeTys.push_back(MVT::Other); // Returns a chain
180 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
182 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
183 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
184 // node so that legalize doesn't hack it.
185 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
186 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
188 // If this is a direct call, pass the chain and the callee.
190 std::vector<SDOperand> Ops;
191 Ops.push_back(Chain);
192 Ops.push_back(Callee);
194 // Add argument registers to the end of the list so that they are known live
196 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
197 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
198 RegsToPass[i].second.getValueType()));
200 unsigned CallOpc = ARMISD::CALL;
202 Ops.push_back(InFlag);
203 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
204 InFlag = Chain.getValue(1);
206 std::vector<SDOperand> ResultVals;
209 // If the call has results, copy the values out of the ret val registers.
210 switch (Op.Val->getValueType(0)) {
211 default: assert(0 && "Unexpected ret value!");
215 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
216 ResultVals.push_back(Chain.getValue(0));
217 NodeTys.push_back(MVT::i32);
220 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
221 DAG.getConstant(NumBytes, MVT::i32));
222 NodeTys.push_back(MVT::Other);
224 if (ResultVals.empty())
227 ResultVals.push_back(Chain);
228 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
230 return Res.getValue(Op.ResNo);
233 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
235 SDOperand Chain = Op.getOperand(0);
236 switch(Op.getNumOperands()) {
238 assert(0 && "Do not know how to return this many arguments!");
241 SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
242 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
245 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op.getOperand(1), SDOperand());
246 if (DAG.getMachineFunction().liveout_empty())
247 DAG.getMachineFunction().addLiveOut(ARM::R0);
250 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
251 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
252 // If we haven't noted the R0+R1 are live out, do so now.
253 if (DAG.getMachineFunction().liveout_empty()) {
254 DAG.getMachineFunction().addLiveOut(ARM::R0);
255 DAG.getMachineFunction().addLiveOut(ARM::R1);
260 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
261 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
264 static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
267 MachineFunction &MF = DAG.getMachineFunction();
268 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
269 assert (ObjectVT == MVT::i32);
270 SDOperand Root = Op.getOperand(0);
271 SSARegMap *RegMap = MF.getSSARegMap();
273 unsigned num_regs = 4;
274 static const unsigned REGS[] = {
275 ARM::R0, ARM::R1, ARM::R2, ARM::R3
278 if(ArgNo < num_regs) {
279 unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
280 MF.addLiveIn(REGS[ArgNo], VReg);
282 return DAG.getCopyFromReg(Root, VReg, MVT::i32);
284 // If the argument is actually used, emit a load from the right stack
286 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
287 unsigned ArgOffset = (ArgNo - num_regs) * 4;
289 MachineFrameInfo *MFI = MF.getFrameInfo();
290 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
291 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
292 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
293 return DAG.getLoad(ObjectVT, Root, FIN,
294 DAG.getSrcValue(NULL));
296 // Don't emit a dead load.
297 return DAG.getNode(ISD::UNDEF, ObjectVT);
302 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
303 MVT::ValueType PtrVT = Op.getValueType();
304 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
305 Constant *C = CP->getConstVal();
306 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
311 static SDOperand LowerGlobalAddress(SDOperand Op,
313 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
315 SDOperand CPAddr = DAG.getConstantPool(GV, MVT::i32, alignment);
316 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr,
317 DAG.getSrcValue(NULL));
320 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
321 unsigned VarArgsFrameIndex) {
322 // vastart just stores the address of the VarArgsFrameIndex slot into the
323 // memory location argument.
324 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
325 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
326 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
327 Op.getOperand(1), Op.getOperand(2));
330 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
331 int &VarArgsFrameIndex) {
332 std::vector<SDOperand> ArgValues;
333 SDOperand Root = Op.getOperand(0);
336 unsigned NumArgs = Op.Val->getNumValues()-1;
337 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) {
338 SDOperand ArgVal = LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo);
340 ArgValues.push_back(ArgVal);
343 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
345 MachineFunction &MF = DAG.getMachineFunction();
346 SSARegMap *RegMap = MF.getSSARegMap();
347 MachineFrameInfo *MFI = MF.getFrameInfo();
348 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
352 static const unsigned REGS[] = {
353 ARM::R0, ARM::R1, ARM::R2, ARM::R3
355 // If this function is vararg, store r0-r3 to their spots on the stack
356 // so that they may be loaded by deferencing the result of va_next.
357 SmallVector<SDOperand, 4> MemOps;
358 for (unsigned ArgNo = 0; ArgNo < 4; ++ArgNo) {
359 int ArgOffset = - (4 - ArgNo) * 4;
360 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
362 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
368 VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
369 if (ArgNo >= NumArgs)
370 MF.addLiveIn(REGS[ArgNo], VReg);
372 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
373 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
374 Val, FIN, DAG.getSrcValue(NULL));
375 MemOps.push_back(Store);
377 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
380 ArgValues.push_back(Root);
382 // Return the new list of results.
383 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
384 Op.Val->value_end());
385 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
388 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
389 SDOperand LHS = Op.getOperand(0);
390 SDOperand RHS = Op.getOperand(1);
391 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
392 SDOperand TrueVal = Op.getOperand(2);
393 SDOperand FalseVal = Op.getOperand(3);
394 SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
396 SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
397 return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp);
400 static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
401 SDOperand Chain = Op.getOperand(0);
402 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
403 SDOperand LHS = Op.getOperand(2);
404 SDOperand RHS = Op.getOperand(3);
405 SDOperand Dest = Op.getOperand(4);
406 SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
408 SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
409 return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
412 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
413 switch (Op.getOpcode()) {
415 assert(0 && "Should not custom lower this!");
417 case ISD::ConstantPool:
418 return LowerConstantPool(Op, DAG);
419 case ISD::GlobalAddress:
420 return LowerGlobalAddress(Op, DAG);
421 case ISD::FORMAL_ARGUMENTS:
422 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
424 return LowerCALL(Op, DAG);
426 return LowerRET(Op, DAG);
428 return LowerSELECT_CC(Op, DAG);
430 return LowerBR_CC(Op, DAG);
432 return LowerVASTART(Op, DAG, VarArgsFrameIndex);
436 //===----------------------------------------------------------------------===//
437 // Instruction Selector Implementation
438 //===----------------------------------------------------------------------===//
440 //===--------------------------------------------------------------------===//
441 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
442 /// instructions for SelectionDAG operations.
445 class ARMDAGToDAGISel : public SelectionDAGISel {
446 ARMTargetLowering Lowering;
449 ARMDAGToDAGISel(TargetMachine &TM)
450 : SelectionDAGISel(Lowering), Lowering(TM) {
453 SDNode *Select(SDOperand Op);
454 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
455 bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
456 bool SelectAddrMode1(SDOperand N, SDOperand &Arg, SDOperand &Shift,
457 SDOperand &ShiftType);
459 // Include the pieces autogenerated from the target description.
460 #include "ARMGenDAGISel.inc"
463 void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
466 DAG.setRoot(SelectRoot(DAG.getRoot()));
467 DAG.RemoveDeadNodes();
469 ScheduleAndEmitDAG(DAG);
472 static bool isInt12Immediate(SDNode *N, short &Imm) {
473 if (N->getOpcode() != ISD::Constant)
476 int32_t t = cast<ConstantSDNode>(N)->getValue();
479 if (t > min && t < max) {
487 static bool isInt12Immediate(SDOperand Op, short &Imm) {
488 return isInt12Immediate(Op.Val, Imm);
491 static uint32_t rotateL(uint32_t x) {
492 uint32_t bit31 = (x & (1 << 31)) >> 31;
497 static bool isUInt8Immediate(uint32_t x) {
501 static bool isRotInt8Immediate(uint32_t x) {
503 for (r = 0; r < 16; r++) {
504 if (isUInt8Immediate(x))
506 x = rotateL(rotateL(x));
511 bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
514 SDOperand &ShiftType) {
515 switch(N.getOpcode()) {
516 case ISD::Constant: {
517 uint32_t val = cast<ConstantSDNode>(N)->getValue();
518 if(!isRotInt8Immediate(val)) {
519 const Type *t = MVT::getTypeForValueType(MVT::i32);
520 Constant *C = ConstantUInt::get(t, val);
522 SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment);
523 SDOperand Z = CurDAG->getTargetConstant(0, MVT::i32);
524 SDNode *n = CurDAG->getTargetNode(ARM::ldr, MVT::i32, Z, Addr);
525 Arg = SDOperand(n, 0);
527 Arg = CurDAG->getTargetConstant(val, MVT::i32);
529 Shift = CurDAG->getTargetConstant(0, MVT::i32);
530 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
534 Arg = N.getOperand(0);
535 Shift = N.getOperand(1);
536 ShiftType = CurDAG->getTargetConstant(ARMShift::ASR, MVT::i32);
539 Arg = N.getOperand(0);
540 Shift = N.getOperand(1);
541 ShiftType = CurDAG->getTargetConstant(ARMShift::LSR, MVT::i32);
544 Arg = N.getOperand(0);
545 Shift = N.getOperand(1);
546 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
551 Shift = CurDAG->getTargetConstant(0, MVT::i32);
552 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
556 //register plus/minus 12 bit offset
557 bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
559 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
560 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
561 Offset = CurDAG->getTargetConstant(0, MVT::i32);
564 if (N.getOpcode() == ISD::ADD) {
566 if (isInt12Immediate(N.getOperand(1), imm)) {
567 Offset = CurDAG->getTargetConstant(imm, MVT::i32);
568 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
569 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
571 Base = N.getOperand(0);
573 return true; // [r+i]
577 Offset = CurDAG->getTargetConstant(0, MVT::i32);
578 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
579 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
583 return true; //any address fits in a register
586 SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
589 switch (N->getOpcode()) {
591 return SelectCode(Op);
597 } // end anonymous namespace
599 /// createARMISelDag - This pass converts a legalized DAG into a
600 /// ARM-specific DAG, ready for instruction scheduling.
602 FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
603 return new ARMDAGToDAGISel(TM);