1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 static const unsigned arm_dsubreg_0 = 5;
39 static const unsigned arm_dsubreg_1 = 6;
41 //===--------------------------------------------------------------------===//
42 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
43 /// instructions for SelectionDAG operations.
46 class ARMDAGToDAGISel : public SelectionDAGISel {
47 ARMBaseTargetMachine &TM;
49 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
50 /// make the right decision when generating code for different targets.
51 const ARMSubtarget *Subtarget;
54 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm)
55 : SelectionDAGISel(tm), TM(tm),
56 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
59 virtual const char *getPassName() const {
60 return "ARM Instruction Selection";
63 /// getI32Imm - Return a target constant with the specified value, of type i32.
64 inline SDValue getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 SDNode *Select(SDValue Op);
69 virtual void InstructionSelect();
70 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
71 SDValue &B, SDValue &C);
72 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
73 SDValue &Offset, SDValue &Opc);
74 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
75 SDValue &Offset, SDValue &Opc);
76 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
77 SDValue &Offset, SDValue &Opc);
78 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
79 SDValue &Offset, SDValue &Opc);
80 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
82 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
85 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
88 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
90 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
91 SDValue &Base, SDValue &OffImm,
93 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
94 SDValue &OffImm, SDValue &Offset);
95 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
96 SDValue &OffImm, SDValue &Offset);
97 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
98 SDValue &OffImm, SDValue &Offset);
99 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
102 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
103 SDValue &BaseReg, SDValue &Opc);
104 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
106 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
108 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
110 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
112 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
113 SDValue &OffReg, SDValue &ShImm);
115 // Include the pieces autogenerated from the target description.
116 #include "ARMGenDAGISel.inc"
119 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
121 SDNode *SelectARMIndexedLoad(SDValue Op);
122 SDNode *SelectT2IndexedLoad(SDValue Op);
125 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
126 /// inline asm expressions.
127 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
129 std::vector<SDValue> &OutOps);
133 void ARMDAGToDAGISel::InstructionSelect() {
137 CurDAG->RemoveDeadNodes();
140 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
145 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
147 // Don't match base register only case. That is matched to a separate
148 // lower complexity pattern with explicit register operand.
149 if (ShOpcVal == ARM_AM::no_shift) return false;
151 BaseReg = N.getOperand(0);
152 unsigned ShImmVal = 0;
153 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
154 ShReg = CurDAG->getRegister(0, MVT::i32);
155 ShImmVal = RHS->getZExtValue() & 31;
157 ShReg = N.getOperand(1);
159 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
164 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
165 SDValue &Base, SDValue &Offset,
167 if (N.getOpcode() == ISD::MUL) {
168 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
169 // X * [3,5,9] -> X + X * [2,4,8] etc.
170 int RHSC = (int)RHS->getZExtValue();
173 ARM_AM::AddrOpc AddSub = ARM_AM::add;
175 AddSub = ARM_AM::sub;
178 if (isPowerOf2_32(RHSC)) {
179 unsigned ShAmt = Log2_32(RHSC);
180 Base = Offset = N.getOperand(0);
181 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
190 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
192 if (N.getOpcode() == ISD::FrameIndex) {
193 int FI = cast<FrameIndexSDNode>(N)->getIndex();
194 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
195 } else if (N.getOpcode() == ARMISD::Wrapper) {
196 Base = N.getOperand(0);
198 Offset = CurDAG->getRegister(0, MVT::i32);
199 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
205 // Match simple R +/- imm12 operands.
206 if (N.getOpcode() == ISD::ADD)
207 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
208 int RHSC = (int)RHS->getZExtValue();
209 if ((RHSC >= 0 && RHSC < 0x1000) ||
210 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
211 Base = N.getOperand(0);
212 if (Base.getOpcode() == ISD::FrameIndex) {
213 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
214 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
216 Offset = CurDAG->getRegister(0, MVT::i32);
218 ARM_AM::AddrOpc AddSub = ARM_AM::add;
220 AddSub = ARM_AM::sub;
223 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
230 // Otherwise this is R +/- [possibly shifted] R
231 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
232 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
235 Base = N.getOperand(0);
236 Offset = N.getOperand(1);
238 if (ShOpcVal != ARM_AM::no_shift) {
239 // Check to see if the RHS of the shift is a constant, if not, we can't fold
241 if (ConstantSDNode *Sh =
242 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
243 ShAmt = Sh->getZExtValue();
244 Offset = N.getOperand(1).getOperand(0);
246 ShOpcVal = ARM_AM::no_shift;
250 // Try matching (R shl C) + (R).
251 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
252 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
253 if (ShOpcVal != ARM_AM::no_shift) {
254 // Check to see if the RHS of the shift is a constant, if not, we can't
256 if (ConstantSDNode *Sh =
257 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
258 ShAmt = Sh->getZExtValue();
259 Offset = N.getOperand(0).getOperand(0);
260 Base = N.getOperand(1);
262 ShOpcVal = ARM_AM::no_shift;
267 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
272 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
273 SDValue &Offset, SDValue &Opc) {
274 unsigned Opcode = Op.getOpcode();
275 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
276 ? cast<LoadSDNode>(Op)->getAddressingMode()
277 : cast<StoreSDNode>(Op)->getAddressingMode();
278 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
279 ? ARM_AM::add : ARM_AM::sub;
280 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
281 int Val = (int)C->getZExtValue();
282 if (Val >= 0 && Val < 0x1000) { // 12 bits.
283 Offset = CurDAG->getRegister(0, MVT::i32);
284 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
292 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
294 if (ShOpcVal != ARM_AM::no_shift) {
295 // Check to see if the RHS of the shift is a constant, if not, we can't fold
297 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
298 ShAmt = Sh->getZExtValue();
299 Offset = N.getOperand(0);
301 ShOpcVal = ARM_AM::no_shift;
305 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
311 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
312 SDValue &Base, SDValue &Offset,
314 if (N.getOpcode() == ISD::SUB) {
315 // X - C is canonicalize to X + -C, no need to handle it here.
316 Base = N.getOperand(0);
317 Offset = N.getOperand(1);
318 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
322 if (N.getOpcode() != ISD::ADD) {
324 if (N.getOpcode() == ISD::FrameIndex) {
325 int FI = cast<FrameIndexSDNode>(N)->getIndex();
326 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
328 Offset = CurDAG->getRegister(0, MVT::i32);
329 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
333 // If the RHS is +/- imm8, fold into addr mode.
334 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
335 int RHSC = (int)RHS->getZExtValue();
336 if ((RHSC >= 0 && RHSC < 256) ||
337 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
338 Base = N.getOperand(0);
339 if (Base.getOpcode() == ISD::FrameIndex) {
340 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
341 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
343 Offset = CurDAG->getRegister(0, MVT::i32);
345 ARM_AM::AddrOpc AddSub = ARM_AM::add;
347 AddSub = ARM_AM::sub;
350 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
355 Base = N.getOperand(0);
356 Offset = N.getOperand(1);
357 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
361 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
362 SDValue &Offset, SDValue &Opc) {
363 unsigned Opcode = Op.getOpcode();
364 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
365 ? cast<LoadSDNode>(Op)->getAddressingMode()
366 : cast<StoreSDNode>(Op)->getAddressingMode();
367 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
368 ? ARM_AM::add : ARM_AM::sub;
369 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
370 int Val = (int)C->getZExtValue();
371 if (Val >= 0 && Val < 256) {
372 Offset = CurDAG->getRegister(0, MVT::i32);
373 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
379 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
384 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
385 SDValue &Base, SDValue &Offset) {
386 if (N.getOpcode() != ISD::ADD) {
388 if (N.getOpcode() == ISD::FrameIndex) {
389 int FI = cast<FrameIndexSDNode>(N)->getIndex();
390 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
391 } else if (N.getOpcode() == ARMISD::Wrapper) {
392 Base = N.getOperand(0);
394 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
399 // If the RHS is +/- imm8, fold into addr mode.
400 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
401 int RHSC = (int)RHS->getZExtValue();
402 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
404 if ((RHSC >= 0 && RHSC < 256) ||
405 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
406 Base = N.getOperand(0);
407 if (Base.getOpcode() == ISD::FrameIndex) {
408 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
409 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
412 ARM_AM::AddrOpc AddSub = ARM_AM::add;
414 AddSub = ARM_AM::sub;
417 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
425 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
430 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
431 SDValue &Addr, SDValue &Update,
434 // The optional writeback is handled in ARMLoadStoreOpt.
435 Update = CurDAG->getRegister(0, MVT::i32);
436 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
440 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
441 SDValue &Offset, SDValue &Label) {
442 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
443 Offset = N.getOperand(0);
444 SDValue N1 = N.getOperand(1);
445 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
452 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
453 SDValue &Base, SDValue &Offset){
454 // FIXME dl should come from the parent load or store, not the address
455 DebugLoc dl = Op.getDebugLoc();
456 if (N.getOpcode() != ISD::ADD) {
457 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
458 if (!NC || NC->getZExtValue() != 0)
465 Base = N.getOperand(0);
466 Offset = N.getOperand(1);
471 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
472 unsigned Scale, SDValue &Base,
473 SDValue &OffImm, SDValue &Offset) {
475 SDValue TmpBase, TmpOffImm;
476 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
477 return false; // We want to select tLDRspi / tSTRspi instead.
478 if (N.getOpcode() == ARMISD::Wrapper &&
479 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
480 return false; // We want to select tLDRpci instead.
483 if (N.getOpcode() != ISD::ADD) {
484 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
485 Offset = CurDAG->getRegister(0, MVT::i32);
486 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
490 // Thumb does not have [sp, r] address mode.
491 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
492 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
493 if ((LHSR && LHSR->getReg() == ARM::SP) ||
494 (RHSR && RHSR->getReg() == ARM::SP)) {
496 Offset = CurDAG->getRegister(0, MVT::i32);
497 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
501 // If the RHS is + imm5 * scale, fold into addr mode.
502 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
503 int RHSC = (int)RHS->getZExtValue();
504 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
506 if (RHSC >= 0 && RHSC < 32) {
507 Base = N.getOperand(0);
508 Offset = CurDAG->getRegister(0, MVT::i32);
509 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
515 Base = N.getOperand(0);
516 Offset = N.getOperand(1);
517 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
521 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
522 SDValue &Base, SDValue &OffImm,
524 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
527 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
528 SDValue &Base, SDValue &OffImm,
530 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
533 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
534 SDValue &Base, SDValue &OffImm,
536 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
539 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
540 SDValue &Base, SDValue &OffImm) {
541 if (N.getOpcode() == ISD::FrameIndex) {
542 int FI = cast<FrameIndexSDNode>(N)->getIndex();
543 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
544 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
548 if (N.getOpcode() != ISD::ADD)
551 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
552 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
553 (LHSR && LHSR->getReg() == ARM::SP)) {
554 // If the RHS is + imm8 * scale, fold into addr mode.
555 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
556 int RHSC = (int)RHS->getZExtValue();
557 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
559 if (RHSC >= 0 && RHSC < 256) {
560 Base = N.getOperand(0);
561 if (Base.getOpcode() == ISD::FrameIndex) {
562 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
563 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
565 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
575 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
578 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
580 // Don't match base register only case. That is matched to a separate
581 // lower complexity pattern with explicit register operand.
582 if (ShOpcVal == ARM_AM::no_shift) return false;
584 BaseReg = N.getOperand(0);
585 unsigned ShImmVal = 0;
586 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
587 ShImmVal = RHS->getZExtValue() & 31;
588 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
595 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
596 SDValue &Base, SDValue &OffImm) {
597 // Match simple R + imm12 operands.
598 if (N.getOpcode() != ISD::ADD)
601 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
602 int RHSC = (int)RHS->getZExtValue();
603 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits.
604 Base = N.getOperand(0);
605 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
613 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
614 SDValue &Base, SDValue &OffImm) {
615 if (N.getOpcode() == ISD::ADD) {
616 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
617 int RHSC = (int)RHS->getZExtValue();
618 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
619 Base = N.getOperand(0);
620 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
624 } else if (N.getOpcode() == ISD::SUB) {
625 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
626 int RHSC = (int)RHS->getZExtValue();
627 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
628 Base = N.getOperand(0);
629 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
638 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
640 unsigned Opcode = Op.getOpcode();
641 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
642 ? cast<LoadSDNode>(Op)->getAddressingMode()
643 : cast<StoreSDNode>(Op)->getAddressingMode();
644 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
645 int RHSC = (int)RHS->getZExtValue();
646 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
647 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
648 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
649 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
657 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
658 SDValue &Base, SDValue &OffImm) {
659 if (N.getOpcode() == ISD::ADD) {
660 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
661 int RHSC = (int)RHS->getZExtValue();
662 if (((RHSC & 0x3) == 0) &&
663 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
664 Base = N.getOperand(0);
665 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
669 } else if (N.getOpcode() == ISD::SUB) {
670 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
671 int RHSC = (int)RHS->getZExtValue();
672 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
673 Base = N.getOperand(0);
674 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
683 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
685 SDValue &OffReg, SDValue &ShImm) {
687 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
689 if (N.getOpcode() == ISD::FrameIndex) {
690 int FI = cast<FrameIndexSDNode>(N)->getIndex();
691 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
692 } else if (N.getOpcode() == ARMISD::Wrapper) {
693 Base = N.getOperand(0);
694 if (Base.getOpcode() == ISD::TargetConstantPool)
695 return false; // We want to select t2LDRpci instead.
697 OffReg = CurDAG->getRegister(0, MVT::i32);
698 ShImm = CurDAG->getTargetConstant(0, MVT::i32);
702 // Look for (R + R) or (R + (R << [1,2,3])).
704 Base = N.getOperand(0);
705 OffReg = N.getOperand(1);
707 // Swap if it is ((R << c) + R).
708 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
709 if (ShOpcVal != ARM_AM::lsl) {
710 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
711 if (ShOpcVal == ARM_AM::lsl)
712 std::swap(Base, OffReg);
715 if (ShOpcVal == ARM_AM::lsl) {
716 // Check to see if the RHS of the shift is a constant, if not, we can't fold
718 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
719 ShAmt = Sh->getZExtValue();
722 ShOpcVal = ARM_AM::no_shift;
724 OffReg = OffReg.getOperand(0);
726 ShOpcVal = ARM_AM::no_shift;
728 } else if (SelectT2AddrModeImm12(Op, N, Base, ShImm) ||
729 SelectT2AddrModeImm8 (Op, N, Base, ShImm))
730 // Don't match if it's possible to match to one of the r +/- imm cases.
733 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
738 //===--------------------------------------------------------------------===//
740 /// getAL - Returns a ARMCC::AL immediate node.
741 static inline SDValue getAL(SelectionDAG *CurDAG) {
742 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
745 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
746 LoadSDNode *LD = cast<LoadSDNode>(Op);
747 ISD::MemIndexedMode AM = LD->getAddressingMode();
748 if (AM == ISD::UNINDEXED)
751 MVT LoadedVT = LD->getMemoryVT();
752 SDValue Offset, AMOpc;
753 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
756 if (LoadedVT == MVT::i32 &&
757 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
758 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
760 } else if (LoadedVT == MVT::i16 &&
761 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
763 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
764 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
765 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
766 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
767 if (LD->getExtensionType() == ISD::SEXTLOAD) {
768 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
770 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
773 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
775 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
781 SDValue Chain = LD->getChain();
782 SDValue Base = LD->getBasePtr();
783 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
784 CurDAG->getRegister(0, MVT::i32), Chain };
785 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
792 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
793 LoadSDNode *LD = cast<LoadSDNode>(Op);
794 ISD::MemIndexedMode AM = LD->getAddressingMode();
795 if (AM == ISD::UNINDEXED)
798 MVT LoadedVT = LD->getMemoryVT();
799 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
801 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
804 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
805 switch (LoadedVT.getSimpleVT()) {
807 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
811 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
813 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
818 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
820 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
829 SDValue Chain = LD->getChain();
830 SDValue Base = LD->getBasePtr();
831 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
832 CurDAG->getRegister(0, MVT::i32), Chain };
833 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
841 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
842 SDNode *N = Op.getNode();
843 DebugLoc dl = N->getDebugLoc();
845 if (N->isMachineOpcode())
846 return NULL; // Already selected.
848 switch (N->getOpcode()) {
850 case ISD::Constant: {
851 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
853 if (Subtarget->isThumb()) {
854 if (Subtarget->hasThumb2())
855 // Thumb2 has the MOVT instruction, so all immediates can
856 // be done with MOV + MOVT, at worst.
859 UseCP = (Val > 255 && // MOV
860 ~Val > 255 && // MOV + MVN
861 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
863 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
864 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
865 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
868 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
872 if (Subtarget->isThumb1Only()) {
873 SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
874 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
875 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
876 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
881 CurDAG->getRegister(0, MVT::i32),
882 CurDAG->getTargetConstant(0, MVT::i32),
884 CurDAG->getRegister(0, MVT::i32),
885 CurDAG->getEntryNode()
887 ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
890 ReplaceUses(Op, SDValue(ResNode, 0));
894 // Other cases are autogenerated.
897 case ISD::FrameIndex: {
898 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
899 int FI = cast<FrameIndexSDNode>(N)->getIndex();
900 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
901 if (Subtarget->isThumb1Only()) {
902 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
903 CurDAG->getTargetConstant(0, MVT::i32));
905 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
906 ARM::t2ADDri : ARM::ADDri);
907 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
908 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
909 CurDAG->getRegister(0, MVT::i32) };
910 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
914 if (!Subtarget->isThumb1Only())
916 // Select add sp, c to tADDhirr.
917 SDValue N0 = Op.getOperand(0);
918 SDValue N1 = Op.getOperand(1);
919 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
920 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
921 if (LHSR && LHSR->getReg() == ARM::SP) {
923 std::swap(LHSR, RHSR);
925 if (RHSR && RHSR->getReg() == ARM::SP) {
926 SDValue Val = SDValue(CurDAG->getTargetNode(ARM::tMOVlor2hir, dl,
927 Op.getValueType(), N0, N0),0);
928 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), Val, N1);
933 if (Subtarget->isThumb1Only())
935 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
936 unsigned RHSV = C->getZExtValue();
938 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
939 SDValue V = Op.getOperand(0);
940 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
941 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
942 CurDAG->getTargetConstant(ShImm, MVT::i32),
943 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
944 CurDAG->getRegister(0, MVT::i32) };
945 return CurDAG->SelectNodeTo(N, (Subtarget->isThumb() &&
946 Subtarget->hasThumb2()) ?
947 ARM::t2ADDrs : ARM::ADDrs, MVT::i32, Ops, 7);
949 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
950 SDValue V = Op.getOperand(0);
951 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
952 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
953 CurDAG->getTargetConstant(ShImm, MVT::i32),
954 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
955 CurDAG->getRegister(0, MVT::i32) };
956 return CurDAG->SelectNodeTo(N, (Subtarget->isThumb() &&
957 Subtarget->hasThumb2()) ?
958 ARM::t2RSBrs : ARM::RSBrs, MVT::i32, Ops, 7);
963 return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
964 Op.getOperand(0), getAL(CurDAG),
965 CurDAG->getRegister(0, MVT::i32));
966 case ISD::UMUL_LOHI: {
967 if (Subtarget->isThumb1Only())
969 if (Subtarget->isThumb()) {
970 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
971 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
972 CurDAG->getRegister(0, MVT::i32) };
973 return CurDAG->getTargetNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
975 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
976 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
977 CurDAG->getRegister(0, MVT::i32) };
978 return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
981 case ISD::SMUL_LOHI: {
982 if (Subtarget->isThumb1Only())
984 if (Subtarget->isThumb()) {
985 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
986 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
987 return CurDAG->getTargetNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
989 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
990 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
991 CurDAG->getRegister(0, MVT::i32) };
992 return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
997 if (Subtarget->isThumb() && Subtarget->hasThumb2())
998 ResNode = SelectT2IndexedLoad(Op);
1000 ResNode = SelectARMIndexedLoad(Op);
1003 // Other cases are autogenerated.
1006 case ARMISD::BRCOND: {
1007 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1008 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1009 // Pattern complexity = 6 cost = 1 size = 0
1011 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1012 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1013 // Pattern complexity = 6 cost = 1 size = 0
1015 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1016 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1017 // Pattern complexity = 6 cost = 1 size = 0
1019 unsigned Opc = Subtarget->isThumb() ?
1020 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1021 SDValue Chain = Op.getOperand(0);
1022 SDValue N1 = Op.getOperand(1);
1023 SDValue N2 = Op.getOperand(2);
1024 SDValue N3 = Op.getOperand(3);
1025 SDValue InFlag = Op.getOperand(4);
1026 assert(N1.getOpcode() == ISD::BasicBlock);
1027 assert(N2.getOpcode() == ISD::Constant);
1028 assert(N3.getOpcode() == ISD::Register);
1030 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1031 cast<ConstantSDNode>(N2)->getZExtValue()),
1033 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1034 SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
1036 Chain = SDValue(ResNode, 0);
1037 if (Op.getNode()->getNumValues() == 2) {
1038 InFlag = SDValue(ResNode, 1);
1039 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1041 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
1044 case ARMISD::CMOV: {
1045 MVT VT = Op.getValueType();
1046 SDValue N0 = Op.getOperand(0);
1047 SDValue N1 = Op.getOperand(1);
1048 SDValue N2 = Op.getOperand(2);
1049 SDValue N3 = Op.getOperand(3);
1050 SDValue InFlag = Op.getOperand(4);
1051 assert(N2.getOpcode() == ISD::Constant);
1052 assert(N3.getOpcode() == ISD::Register);
1054 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1055 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1056 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1057 // Pattern complexity = 18 cost = 1 size = 0
1061 if (Subtarget->isThumb()) {
1062 if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1063 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1064 cast<ConstantSDNode>(N2)->getZExtValue()),
1066 SDValue Ops[] = { N0, CPTmp0, CPTmp1, Tmp2, N3, InFlag };
1067 return CurDAG->SelectNodeTo(Op.getNode(),
1068 ARM::t2MOVCCs, MVT::i32,Ops, 6);
1071 if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1072 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1073 cast<ConstantSDNode>(N2)->getZExtValue()),
1075 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1076 return CurDAG->SelectNodeTo(Op.getNode(),
1077 ARM::MOVCCs, MVT::i32, Ops, 7);
1081 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1082 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1084 // Emits: (MOVCCi:i32 GPR:i32:$false,
1085 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1086 // Pattern complexity = 10 cost = 1 size = 0
1087 if (N3.getOpcode() == ISD::Constant) {
1088 if (Subtarget->isThumb()) {
1089 if (Predicate_t2_so_imm(N3.getNode())) {
1090 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1091 cast<ConstantSDNode>(N1)->getZExtValue()),
1093 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1094 cast<ConstantSDNode>(N2)->getZExtValue()),
1096 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1097 return CurDAG->SelectNodeTo(Op.getNode(),
1098 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1101 if (Predicate_so_imm(N3.getNode())) {
1102 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1103 cast<ConstantSDNode>(N1)->getZExtValue()),
1105 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1106 cast<ConstantSDNode>(N2)->getZExtValue()),
1108 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1109 return CurDAG->SelectNodeTo(Op.getNode(),
1110 ARM::MOVCCi, MVT::i32, Ops, 5);
1116 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1117 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1118 // Pattern complexity = 6 cost = 1 size = 0
1120 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1121 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1122 // Pattern complexity = 6 cost = 11 size = 0
1124 // Also FCPYScc and FCPYDcc.
1125 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1126 cast<ConstantSDNode>(N2)->getZExtValue()),
1128 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1130 switch (VT.getSimpleVT()) {
1131 default: assert(false && "Illegal conditional move type!");
1134 Opc = Subtarget->isThumb()
1135 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr)
1145 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1147 case ARMISD::CNEG: {
1148 MVT VT = Op.getValueType();
1149 SDValue N0 = Op.getOperand(0);
1150 SDValue N1 = Op.getOperand(1);
1151 SDValue N2 = Op.getOperand(2);
1152 SDValue N3 = Op.getOperand(3);
1153 SDValue InFlag = Op.getOperand(4);
1154 assert(N2.getOpcode() == ISD::Constant);
1155 assert(N3.getOpcode() == ISD::Register);
1157 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1158 cast<ConstantSDNode>(N2)->getZExtValue()),
1160 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1162 switch (VT.getSimpleVT()) {
1163 default: assert(false && "Illegal conditional move type!");
1172 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1175 case ISD::DECLARE: {
1176 SDValue Chain = Op.getOperand(0);
1177 SDValue N1 = Op.getOperand(1);
1178 SDValue N2 = Op.getOperand(2);
1179 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
1180 // FIXME: handle VLAs.
1182 ReplaceUses(Op.getValue(0), Chain);
1185 if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0)))
1186 N2 = N2.getOperand(0);
1187 LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2);
1189 ReplaceUses(Op.getValue(0), Chain);
1192 SDValue BasePtr = Ld->getBasePtr();
1193 assert(BasePtr.getOpcode() == ARMISD::Wrapper &&
1194 isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) &&
1195 "llvm.dbg.variable should be a constantpool node");
1196 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0));
1197 GlobalValue *GV = 0;
1198 if (CP->isMachineConstantPoolEntry()) {
1199 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal();
1202 GV = dyn_cast<GlobalValue>(CP->getConstVal());
1204 ReplaceUses(Op.getValue(0), Chain);
1208 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
1209 TLI.getPointerTy());
1210 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
1211 SDValue Ops[] = { Tmp1, Tmp2, Chain };
1212 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
1213 MVT::Other, Ops, 3);
1216 case ISD::CONCAT_VECTORS: {
1217 MVT VT = Op.getValueType();
1218 assert(VT.is128BitVector() && Op.getNumOperands() == 2 &&
1219 "unexpected CONCAT_VECTORS");
1220 SDValue N0 = Op.getOperand(0);
1221 SDValue N1 = Op.getOperand(1);
1223 CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT);
1224 if (N0.getOpcode() != ISD::UNDEF)
1225 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1226 SDValue(Result, 0), N0,
1227 CurDAG->getTargetConstant(arm_dsubreg_0,
1229 if (N1.getOpcode() != ISD::UNDEF)
1230 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1231 SDValue(Result, 0), N1,
1232 CurDAG->getTargetConstant(arm_dsubreg_1,
1237 case ISD::VECTOR_SHUFFLE: {
1238 MVT VT = Op.getValueType();
1240 // Match 128-bit splat to VDUPLANEQ. (This could be done with a Pat in
1241 // ARMInstrNEON.td but it is awkward because the shuffle mask needs to be
1242 // transformed first into a lane number and then to both a subregister
1243 // index and an adjusted lane number.) If the source operand is a
1244 // SCALAR_TO_VECTOR, leave it so it will be matched later as a VDUP.
1245 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1246 if (VT.is128BitVector() && SVOp->isSplat() &&
1247 Op.getOperand(0).getOpcode() != ISD::SCALAR_TO_VECTOR &&
1248 Op.getOperand(1).getOpcode() == ISD::UNDEF) {
1249 unsigned LaneVal = SVOp->getSplatIndex();
1253 switch (VT.getVectorElementType().getSimpleVT()) {
1254 default: assert(false && "unhandled VDUP splat type");
1255 case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
1256 case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
1257 case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
1258 case MVT::f32: Opc = ARM::VDUPLNfq; HalfVT = MVT::v2f32; break;
1261 // The source operand needs to be changed to a subreg of the original
1262 // 128-bit operand, and the lane number needs to be adjusted accordingly.
1263 unsigned NumElts = VT.getVectorNumElements() / 2;
1264 unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
1265 SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32);
1266 SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32);
1267 SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
1268 dl, HalfVT, N->getOperand(0), SR);
1269 return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
1276 return SelectCode(Op);
1279 bool ARMDAGToDAGISel::
1280 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1281 std::vector<SDValue> &OutOps) {
1282 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1284 SDValue Base, Offset, Opc;
1285 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
1288 OutOps.push_back(Base);
1289 OutOps.push_back(Offset);
1290 OutOps.push_back(Opc);
1294 /// createARMISelDag - This pass converts a legalized DAG into a
1295 /// ARM-specific DAG, ready for instruction scheduling.
1297 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM) {
1298 return new ARMDAGToDAGISel(TM);