1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMTargetMachine.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/IR/CallingConv.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetOptions.h"
41 DisableShifterOp("disable-shifter-op", cl::Hidden,
42 cl::desc("Disable isel of shifter-op"),
46 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47 cl::desc("Check fp vmla / vmls hazard at isel time"),
50 //===--------------------------------------------------------------------===//
51 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
52 /// instructions for SelectionDAG operations.
57 AM2_BASE, // Simple AM2 (+-imm12)
58 AM2_SHOP // Shifter-op AM2
61 class ARMDAGToDAGISel : public SelectionDAGISel {
62 ARMBaseTargetMachine &TM;
64 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
65 /// make the right decision when generating code for different targets.
66 const ARMSubtarget *Subtarget;
69 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
70 CodeGenOpt::Level OptLevel)
71 : SelectionDAGISel(tm, OptLevel), TM(tm),
72 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
75 const char *getPassName() const override {
76 return "ARM Instruction Selection";
79 void PreprocessISelDAG() override;
81 /// getI32Imm - Return a target constant of type i32 with the specified
83 inline SDValue getI32Imm(unsigned Imm) {
84 return CurDAG->getTargetConstant(Imm, MVT::i32);
87 SDNode *Select(SDNode *N) override;
90 bool hasNoVMLxHazardUse(SDNode *N) const;
91 bool isShifterOpProfitable(const SDValue &Shift,
92 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
93 bool SelectRegShifterOperand(SDValue N, SDValue &A,
94 SDValue &B, SDValue &C,
95 bool CheckProfitability = true);
96 bool SelectImmShifterOperand(SDValue N, SDValue &A,
97 SDValue &B, bool CheckProfitability = true);
98 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
99 SDValue &B, SDValue &C) {
100 // Don't apply the profitability check
101 return SelectRegShifterOperand(N, A, B, C, false);
103 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
105 // Don't apply the profitability check
106 return SelectImmShifterOperand(N, A, B, false);
109 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
110 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
112 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
113 SDValue &Offset, SDValue &Opc);
114 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
116 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
119 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
121 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
124 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
126 SelectAddrMode2Worker(N, Base, Offset, Opc);
127 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
128 // This always matches one way or another.
132 bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
133 const ConstantSDNode *CN = cast<ConstantSDNode>(N);
134 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
135 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
139 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
140 SDValue &Offset, SDValue &Opc);
141 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
142 SDValue &Offset, SDValue &Opc);
143 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
144 SDValue &Offset, SDValue &Opc);
145 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
146 bool SelectAddrMode3(SDValue N, SDValue &Base,
147 SDValue &Offset, SDValue &Opc);
148 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
149 SDValue &Offset, SDValue &Opc);
150 bool SelectAddrMode5(SDValue N, SDValue &Base,
152 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
153 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
155 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
157 // Thumb Addressing Modes:
158 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
159 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
161 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
162 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
163 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
164 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
166 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
168 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
170 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
172 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
174 // Thumb 2 Addressing Modes:
175 bool SelectT2ShifterOperandReg(SDValue N,
176 SDValue &BaseReg, SDValue &Opc);
177 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
178 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
180 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
182 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
183 SDValue &OffReg, SDValue &ShImm);
184 bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
186 inline bool is_so_imm(unsigned Imm) const {
187 return ARM_AM::getSOImmVal(Imm) != -1;
190 inline bool is_so_imm_not(unsigned Imm) const {
191 return ARM_AM::getSOImmVal(~Imm) != -1;
194 inline bool is_t2_so_imm(unsigned Imm) const {
195 return ARM_AM::getT2SOImmVal(Imm) != -1;
198 inline bool is_t2_so_imm_not(unsigned Imm) const {
199 return ARM_AM::getT2SOImmVal(~Imm) != -1;
202 // Include the pieces autogenerated from the target description.
203 #include "ARMGenDAGISel.inc"
206 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
208 SDNode *SelectARMIndexedLoad(SDNode *N);
209 SDNode *SelectT2IndexedLoad(SDNode *N);
211 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
212 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
213 /// loads of D registers and even subregs and odd subregs of Q registers.
214 /// For NumVecs <= 2, QOpcodes1 is not used.
215 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
216 const uint16_t *DOpcodes,
217 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
219 /// SelectVST - Select NEON store intrinsics. NumVecs should
220 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
221 /// stores of D registers and even subregs and odd subregs of Q registers.
222 /// For NumVecs <= 2, QOpcodes1 is not used.
223 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
224 const uint16_t *DOpcodes,
225 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
227 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
228 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
229 /// load/store of D registers and Q registers.
230 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
231 bool isUpdating, unsigned NumVecs,
232 const uint16_t *DOpcodes, const uint16_t *QOpcodes);
234 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
235 /// should be 2, 3 or 4. The opcode array specifies the instructions used
236 /// for loading D registers. (Q registers are not supported.)
237 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
238 const uint16_t *Opcodes);
240 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
241 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
242 /// generated to force the table registers to be consecutive.
243 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
245 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
246 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
248 // Select special operations if node forms integer ABS pattern
249 SDNode *SelectABSOp(SDNode *N);
251 SDNode *SelectInlineAsm(SDNode *N);
253 SDNode *SelectConcatVector(SDNode *N);
255 SDNode *SelectAtomic(SDNode *N, unsigned Op8, unsigned Op16, unsigned Op32, unsigned Op64);
257 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
258 /// inline asm expressions.
259 bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
260 std::vector<SDValue> &OutOps) override;
262 // Form pairs of consecutive R, S, D, or Q registers.
263 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
264 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
265 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
266 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
268 // Form sequences of 4 consecutive S, D, or Q registers.
269 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
270 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
271 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
273 // Get the alignment operand for a NEON VLD or VST instruction.
274 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
278 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
279 /// operand. If so Imm will receive the 32-bit value.
280 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
281 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
282 Imm = cast<ConstantSDNode>(N)->getZExtValue();
288 // isInt32Immediate - This method tests to see if a constant operand.
289 // If so Imm will receive the 32 bit value.
290 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
291 return isInt32Immediate(N.getNode(), Imm);
294 // isOpcWithIntImmediate - This method tests to see if the node is a specific
295 // opcode and that it has a immediate integer right operand.
296 // If so Imm will receive the 32 bit value.
297 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
298 return N->getOpcode() == Opc &&
299 isInt32Immediate(N->getOperand(1).getNode(), Imm);
302 /// \brief Check whether a particular node is a constant value representable as
303 /// (N * Scale) where (N in [\p RangeMin, \p RangeMax).
305 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
306 static bool isScaledConstantInRange(SDValue Node, int Scale,
307 int RangeMin, int RangeMax,
308 int &ScaledConstant) {
309 assert(Scale > 0 && "Invalid scale!");
311 // Check that this is a constant.
312 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
316 ScaledConstant = (int) C->getZExtValue();
317 if ((ScaledConstant % Scale) != 0)
320 ScaledConstant /= Scale;
321 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
324 void ARMDAGToDAGISel::PreprocessISelDAG() {
325 if (!Subtarget->hasV6T2Ops())
328 bool isThumb2 = Subtarget->isThumb();
329 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
330 E = CurDAG->allnodes_end(); I != E; ) {
331 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
333 if (N->getOpcode() != ISD::ADD)
336 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
337 // leading zeros, followed by consecutive set bits, followed by 1 or 2
338 // trailing zeros, e.g. 1020.
339 // Transform the expression to
340 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
341 // of trailing zeros of c2. The left shift would be folded as an shifter
342 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
345 SDValue N0 = N->getOperand(0);
346 SDValue N1 = N->getOperand(1);
347 unsigned And_imm = 0;
348 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
349 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
355 // Check if the AND mask is an immediate of the form: 000.....1111111100
356 unsigned TZ = countTrailingZeros(And_imm);
357 if (TZ != 1 && TZ != 2)
358 // Be conservative here. Shifter operands aren't always free. e.g. On
359 // Swift, left shifter operand of 1 / 2 for free but others are not.
361 // ubfx r3, r1, #16, #8
362 // ldr.w r3, [r0, r3, lsl #2]
365 // and.w r2, r9, r1, lsr #14
369 if (And_imm & (And_imm + 1))
372 // Look for (and (srl X, c1), c2).
373 SDValue Srl = N1.getOperand(0);
374 unsigned Srl_imm = 0;
375 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
379 // Make sure first operand is not a shifter operand which would prevent
380 // folding of the left shift.
385 if (SelectT2ShifterOperandReg(N0, CPTmp0, CPTmp1))
388 if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1) ||
389 SelectRegShifterOperand(N0, CPTmp0, CPTmp1, CPTmp2))
393 // Now make the transformation.
394 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
396 CurDAG->getConstant(Srl_imm+TZ, MVT::i32));
397 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
398 Srl, CurDAG->getConstant(And_imm, MVT::i32));
399 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
400 N1, CurDAG->getConstant(TZ, MVT::i32));
401 CurDAG->UpdateNodeOperands(N, N0, N1);
405 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
406 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
407 /// least on current ARM implementations) which should be avoidded.
408 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
409 if (OptLevel == CodeGenOpt::None)
412 if (!CheckVMLxHazard)
415 if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9() &&
416 !Subtarget->isSwift())
422 SDNode *Use = *N->use_begin();
423 if (Use->getOpcode() == ISD::CopyToReg)
425 if (Use->isMachineOpcode()) {
426 const ARMBaseInstrInfo *TII =
427 static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
429 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
432 unsigned Opcode = MCID.getOpcode();
433 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
435 // vmlx feeding into another vmlx. We actually want to unfold
436 // the use later in the MLxExpansion pass. e.g.
438 // vmla (stall 8 cycles)
443 // This adds up to about 18 - 19 cycles.
446 // vmul (stall 4 cycles)
447 // vadd adds up to about 14 cycles.
448 return TII->isFpMLxInstruction(Opcode);
454 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
455 ARM_AM::ShiftOpc ShOpcVal,
457 if (!Subtarget->isLikeA9() && !Subtarget->isSwift())
459 if (Shift.hasOneUse())
462 return ShOpcVal == ARM_AM::lsl &&
463 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
466 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
469 bool CheckProfitability) {
470 if (DisableShifterOp)
473 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
475 // Don't match base register only case. That is matched to a separate
476 // lower complexity pattern with explicit register operand.
477 if (ShOpcVal == ARM_AM::no_shift) return false;
479 BaseReg = N.getOperand(0);
480 unsigned ShImmVal = 0;
481 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
482 if (!RHS) return false;
483 ShImmVal = RHS->getZExtValue() & 31;
484 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
489 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
493 bool CheckProfitability) {
494 if (DisableShifterOp)
497 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
499 // Don't match base register only case. That is matched to a separate
500 // lower complexity pattern with explicit register operand.
501 if (ShOpcVal == ARM_AM::no_shift) return false;
503 BaseReg = N.getOperand(0);
504 unsigned ShImmVal = 0;
505 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
506 if (RHS) return false;
508 ShReg = N.getOperand(1);
509 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
511 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
517 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
520 // Match simple R + imm12 operands.
523 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
524 !CurDAG->isBaseWithConstantOffset(N)) {
525 if (N.getOpcode() == ISD::FrameIndex) {
526 // Match frame index.
527 int FI = cast<FrameIndexSDNode>(N)->getIndex();
528 Base = CurDAG->getTargetFrameIndex(FI,
529 getTargetLowering()->getPointerTy());
530 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
534 if (N.getOpcode() == ARMISD::Wrapper &&
535 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
536 Base = N.getOperand(0);
539 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
543 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
544 int RHSC = (int)RHS->getZExtValue();
545 if (N.getOpcode() == ISD::SUB)
548 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
549 Base = N.getOperand(0);
550 if (Base.getOpcode() == ISD::FrameIndex) {
551 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
552 Base = CurDAG->getTargetFrameIndex(FI,
553 getTargetLowering()->getPointerTy());
555 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
562 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
568 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
570 if (N.getOpcode() == ISD::MUL &&
571 ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.hasOneUse())) {
572 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
573 // X * [3,5,9] -> X + X * [2,4,8] etc.
574 int RHSC = (int)RHS->getZExtValue();
577 ARM_AM::AddrOpc AddSub = ARM_AM::add;
579 AddSub = ARM_AM::sub;
582 if (isPowerOf2_32(RHSC)) {
583 unsigned ShAmt = Log2_32(RHSC);
584 Base = Offset = N.getOperand(0);
585 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
594 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
595 // ISD::OR that is equivalent to an ISD::ADD.
596 !CurDAG->isBaseWithConstantOffset(N))
599 // Leave simple R +/- imm12 operands for LDRi12
600 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
602 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
603 -0x1000+1, 0x1000, RHSC)) // 12 bits.
607 // Otherwise this is R +/- [possibly shifted] R.
608 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
609 ARM_AM::ShiftOpc ShOpcVal =
610 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
613 Base = N.getOperand(0);
614 Offset = N.getOperand(1);
616 if (ShOpcVal != ARM_AM::no_shift) {
617 // Check to see if the RHS of the shift is a constant, if not, we can't fold
619 if (ConstantSDNode *Sh =
620 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
621 ShAmt = Sh->getZExtValue();
622 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
623 Offset = N.getOperand(1).getOperand(0);
626 ShOpcVal = ARM_AM::no_shift;
629 ShOpcVal = ARM_AM::no_shift;
633 // Try matching (R shl C) + (R).
634 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
635 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
636 N.getOperand(0).hasOneUse())) {
637 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
638 if (ShOpcVal != ARM_AM::no_shift) {
639 // Check to see if the RHS of the shift is a constant, if not, we can't
641 if (ConstantSDNode *Sh =
642 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
643 ShAmt = Sh->getZExtValue();
644 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
645 Offset = N.getOperand(0).getOperand(0);
646 Base = N.getOperand(1);
649 ShOpcVal = ARM_AM::no_shift;
652 ShOpcVal = ARM_AM::no_shift;
657 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
665 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
669 if (N.getOpcode() == ISD::MUL &&
670 (!(Subtarget->isLikeA9() || Subtarget->isSwift()) || N.hasOneUse())) {
671 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
672 // X * [3,5,9] -> X + X * [2,4,8] etc.
673 int RHSC = (int)RHS->getZExtValue();
676 ARM_AM::AddrOpc AddSub = ARM_AM::add;
678 AddSub = ARM_AM::sub;
681 if (isPowerOf2_32(RHSC)) {
682 unsigned ShAmt = Log2_32(RHSC);
683 Base = Offset = N.getOperand(0);
684 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
693 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
694 // ISD::OR that is equivalent to an ADD.
695 !CurDAG->isBaseWithConstantOffset(N)) {
697 if (N.getOpcode() == ISD::FrameIndex) {
698 int FI = cast<FrameIndexSDNode>(N)->getIndex();
699 Base = CurDAG->getTargetFrameIndex(FI,
700 getTargetLowering()->getPointerTy());
701 } else if (N.getOpcode() == ARMISD::Wrapper &&
702 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
703 Base = N.getOperand(0);
705 Offset = CurDAG->getRegister(0, MVT::i32);
706 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
712 // Match simple R +/- imm12 operands.
713 if (N.getOpcode() != ISD::SUB) {
715 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
716 -0x1000+1, 0x1000, RHSC)) { // 12 bits.
717 Base = N.getOperand(0);
718 if (Base.getOpcode() == ISD::FrameIndex) {
719 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
720 Base = CurDAG->getTargetFrameIndex(FI,
721 getTargetLowering()->getPointerTy());
723 Offset = CurDAG->getRegister(0, MVT::i32);
725 ARM_AM::AddrOpc AddSub = ARM_AM::add;
727 AddSub = ARM_AM::sub;
730 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
737 if ((Subtarget->isLikeA9() || Subtarget->isSwift()) && !N.hasOneUse()) {
738 // Compute R +/- (R << N) and reuse it.
740 Offset = CurDAG->getRegister(0, MVT::i32);
741 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
747 // Otherwise this is R +/- [possibly shifted] R.
748 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
749 ARM_AM::ShiftOpc ShOpcVal =
750 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
753 Base = N.getOperand(0);
754 Offset = N.getOperand(1);
756 if (ShOpcVal != ARM_AM::no_shift) {
757 // Check to see if the RHS of the shift is a constant, if not, we can't fold
759 if (ConstantSDNode *Sh =
760 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
761 ShAmt = Sh->getZExtValue();
762 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
763 Offset = N.getOperand(1).getOperand(0);
766 ShOpcVal = ARM_AM::no_shift;
769 ShOpcVal = ARM_AM::no_shift;
773 // Try matching (R shl C) + (R).
774 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
775 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
776 N.getOperand(0).hasOneUse())) {
777 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
778 if (ShOpcVal != ARM_AM::no_shift) {
779 // Check to see if the RHS of the shift is a constant, if not, we can't
781 if (ConstantSDNode *Sh =
782 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
783 ShAmt = Sh->getZExtValue();
784 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
785 Offset = N.getOperand(0).getOperand(0);
786 Base = N.getOperand(1);
789 ShOpcVal = ARM_AM::no_shift;
792 ShOpcVal = ARM_AM::no_shift;
797 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
802 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
803 SDValue &Offset, SDValue &Opc) {
804 unsigned Opcode = Op->getOpcode();
805 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
806 ? cast<LoadSDNode>(Op)->getAddressingMode()
807 : cast<StoreSDNode>(Op)->getAddressingMode();
808 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
809 ? ARM_AM::add : ARM_AM::sub;
811 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
815 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
817 if (ShOpcVal != ARM_AM::no_shift) {
818 // Check to see if the RHS of the shift is a constant, if not, we can't fold
820 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
821 ShAmt = Sh->getZExtValue();
822 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
823 Offset = N.getOperand(0);
826 ShOpcVal = ARM_AM::no_shift;
829 ShOpcVal = ARM_AM::no_shift;
833 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
838 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
839 SDValue &Offset, SDValue &Opc) {
840 unsigned Opcode = Op->getOpcode();
841 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
842 ? cast<LoadSDNode>(Op)->getAddressingMode()
843 : cast<StoreSDNode>(Op)->getAddressingMode();
844 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
845 ? ARM_AM::add : ARM_AM::sub;
847 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
848 if (AddSub == ARM_AM::sub) Val *= -1;
849 Offset = CurDAG->getRegister(0, MVT::i32);
850 Opc = CurDAG->getTargetConstant(Val, MVT::i32);
858 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
859 SDValue &Offset, SDValue &Opc) {
860 unsigned Opcode = Op->getOpcode();
861 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
862 ? cast<LoadSDNode>(Op)->getAddressingMode()
863 : cast<StoreSDNode>(Op)->getAddressingMode();
864 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
865 ? ARM_AM::add : ARM_AM::sub;
867 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
868 Offset = CurDAG->getRegister(0, MVT::i32);
869 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
878 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
883 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
884 SDValue &Base, SDValue &Offset,
886 if (N.getOpcode() == ISD::SUB) {
887 // X - C is canonicalize to X + -C, no need to handle it here.
888 Base = N.getOperand(0);
889 Offset = N.getOperand(1);
890 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
894 if (!CurDAG->isBaseWithConstantOffset(N)) {
896 if (N.getOpcode() == ISD::FrameIndex) {
897 int FI = cast<FrameIndexSDNode>(N)->getIndex();
898 Base = CurDAG->getTargetFrameIndex(FI,
899 getTargetLowering()->getPointerTy());
901 Offset = CurDAG->getRegister(0, MVT::i32);
902 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
906 // If the RHS is +/- imm8, fold into addr mode.
908 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
909 -256 + 1, 256, RHSC)) { // 8 bits.
910 Base = N.getOperand(0);
911 if (Base.getOpcode() == ISD::FrameIndex) {
912 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
913 Base = CurDAG->getTargetFrameIndex(FI,
914 getTargetLowering()->getPointerTy());
916 Offset = CurDAG->getRegister(0, MVT::i32);
918 ARM_AM::AddrOpc AddSub = ARM_AM::add;
920 AddSub = ARM_AM::sub;
923 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
927 Base = N.getOperand(0);
928 Offset = N.getOperand(1);
929 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
933 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
934 SDValue &Offset, SDValue &Opc) {
935 unsigned Opcode = Op->getOpcode();
936 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
937 ? cast<LoadSDNode>(Op)->getAddressingMode()
938 : cast<StoreSDNode>(Op)->getAddressingMode();
939 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
940 ? ARM_AM::add : ARM_AM::sub;
942 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
943 Offset = CurDAG->getRegister(0, MVT::i32);
944 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
949 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
953 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
954 SDValue &Base, SDValue &Offset) {
955 if (!CurDAG->isBaseWithConstantOffset(N)) {
957 if (N.getOpcode() == ISD::FrameIndex) {
958 int FI = cast<FrameIndexSDNode>(N)->getIndex();
959 Base = CurDAG->getTargetFrameIndex(FI,
960 getTargetLowering()->getPointerTy());
961 } else if (N.getOpcode() == ARMISD::Wrapper &&
962 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
963 Base = N.getOperand(0);
965 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
970 // If the RHS is +/- imm8, fold into addr mode.
972 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
973 -256 + 1, 256, RHSC)) {
974 Base = N.getOperand(0);
975 if (Base.getOpcode() == ISD::FrameIndex) {
976 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
977 Base = CurDAG->getTargetFrameIndex(FI,
978 getTargetLowering()->getPointerTy());
981 ARM_AM::AddrOpc AddSub = ARM_AM::add;
983 AddSub = ARM_AM::sub;
986 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
992 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
997 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
1001 unsigned Alignment = 0;
1002 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
1003 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
1004 // The maximum alignment is equal to the memory size being referenced.
1005 unsigned LSNAlign = LSN->getAlignment();
1006 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
1007 if (LSNAlign >= MemSize && MemSize > 1)
1008 Alignment = MemSize;
1010 // All other uses of addrmode6 are for intrinsics. For now just record
1011 // the raw alignment value; it will be refined later based on the legal
1012 // alignment operands for the intrinsic.
1013 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
1016 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1020 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
1022 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
1023 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1024 if (AM != ISD::POST_INC)
1027 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
1028 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
1029 Offset = CurDAG->getRegister(0, MVT::i32);
1034 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
1035 SDValue &Offset, SDValue &Label) {
1036 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
1037 Offset = N.getOperand(0);
1038 SDValue N1 = N.getOperand(1);
1039 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
1048 //===----------------------------------------------------------------------===//
1049 // Thumb Addressing Modes
1050 //===----------------------------------------------------------------------===//
1052 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
1053 SDValue &Base, SDValue &Offset){
1054 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1055 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
1056 if (!NC || !NC->isNullValue())
1063 Base = N.getOperand(0);
1064 Offset = N.getOperand(1);
1069 ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
1070 SDValue &Offset, unsigned Scale) {
1072 SDValue TmpBase, TmpOffImm;
1073 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1074 return false; // We want to select tLDRspi / tSTRspi instead.
1076 if (N.getOpcode() == ARMISD::Wrapper &&
1077 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1078 return false; // We want to select tLDRpci instead.
1081 if (!CurDAG->isBaseWithConstantOffset(N))
1084 // Thumb does not have [sp, r] address mode.
1085 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1086 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1087 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1088 (RHSR && RHSR->getReg() == ARM::SP))
1091 // FIXME: Why do we explicitly check for a match here and then return false?
1092 // Presumably to allow something else to match, but shouldn't this be
1095 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1098 Base = N.getOperand(0);
1099 Offset = N.getOperand(1);
1104 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1107 return SelectThumbAddrModeRI(N, Base, Offset, 1);
1111 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1114 return SelectThumbAddrModeRI(N, Base, Offset, 2);
1118 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1121 return SelectThumbAddrModeRI(N, Base, Offset, 4);
1125 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1126 SDValue &Base, SDValue &OffImm) {
1128 SDValue TmpBase, TmpOffImm;
1129 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1130 return false; // We want to select tLDRspi / tSTRspi instead.
1132 if (N.getOpcode() == ARMISD::Wrapper &&
1133 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1134 return false; // We want to select tLDRpci instead.
1137 if (!CurDAG->isBaseWithConstantOffset(N)) {
1138 if (N.getOpcode() == ARMISD::Wrapper &&
1139 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1140 Base = N.getOperand(0);
1145 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1149 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1150 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1151 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1152 (RHSR && RHSR->getReg() == ARM::SP)) {
1153 ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1154 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1155 unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1156 unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1158 // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1159 if (LHSC != 0 || RHSC != 0) return false;
1162 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1166 // If the RHS is + imm5 * scale, fold into addr mode.
1168 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1169 Base = N.getOperand(0);
1170 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1174 Base = N.getOperand(0);
1175 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1180 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1182 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1186 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1188 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1192 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1194 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1197 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1198 SDValue &Base, SDValue &OffImm) {
1199 if (N.getOpcode() == ISD::FrameIndex) {
1200 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1201 Base = CurDAG->getTargetFrameIndex(FI,
1202 getTargetLowering()->getPointerTy());
1203 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1207 if (!CurDAG->isBaseWithConstantOffset(N))
1210 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1211 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1212 (LHSR && LHSR->getReg() == ARM::SP)) {
1213 // If the RHS is + imm8 * scale, fold into addr mode.
1215 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1216 Base = N.getOperand(0);
1217 if (Base.getOpcode() == ISD::FrameIndex) {
1218 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1219 Base = CurDAG->getTargetFrameIndex(FI,
1220 getTargetLowering()->getPointerTy());
1222 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1231 //===----------------------------------------------------------------------===//
1232 // Thumb 2 Addressing Modes
1233 //===----------------------------------------------------------------------===//
1236 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1238 if (DisableShifterOp)
1241 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1243 // Don't match base register only case. That is matched to a separate
1244 // lower complexity pattern with explicit register operand.
1245 if (ShOpcVal == ARM_AM::no_shift) return false;
1247 BaseReg = N.getOperand(0);
1248 unsigned ShImmVal = 0;
1249 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1250 ShImmVal = RHS->getZExtValue() & 31;
1251 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1258 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1259 SDValue &Base, SDValue &OffImm) {
1260 // Match simple R + imm12 operands.
1263 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1264 !CurDAG->isBaseWithConstantOffset(N)) {
1265 if (N.getOpcode() == ISD::FrameIndex) {
1266 // Match frame index.
1267 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1268 Base = CurDAG->getTargetFrameIndex(FI,
1269 getTargetLowering()->getPointerTy());
1270 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1274 if (N.getOpcode() == ARMISD::Wrapper &&
1275 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1276 Base = N.getOperand(0);
1277 if (Base.getOpcode() == ISD::TargetConstantPool)
1278 return false; // We want to select t2LDRpci instead.
1281 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1285 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1286 if (SelectT2AddrModeImm8(N, Base, OffImm))
1287 // Let t2LDRi8 handle (R - imm8).
1290 int RHSC = (int)RHS->getZExtValue();
1291 if (N.getOpcode() == ISD::SUB)
1294 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1295 Base = N.getOperand(0);
1296 if (Base.getOpcode() == ISD::FrameIndex) {
1297 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1298 Base = CurDAG->getTargetFrameIndex(FI,
1299 getTargetLowering()->getPointerTy());
1301 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1308 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1312 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1313 SDValue &Base, SDValue &OffImm) {
1314 // Match simple R - imm8 operands.
1315 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1316 !CurDAG->isBaseWithConstantOffset(N))
1319 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1320 int RHSC = (int)RHS->getSExtValue();
1321 if (N.getOpcode() == ISD::SUB)
1324 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1325 Base = N.getOperand(0);
1326 if (Base.getOpcode() == ISD::FrameIndex) {
1327 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1328 Base = CurDAG->getTargetFrameIndex(FI,
1329 getTargetLowering()->getPointerTy());
1331 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1339 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1341 unsigned Opcode = Op->getOpcode();
1342 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1343 ? cast<LoadSDNode>(Op)->getAddressingMode()
1344 : cast<StoreSDNode>(Op)->getAddressingMode();
1346 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1347 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1348 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1349 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1356 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1358 SDValue &OffReg, SDValue &ShImm) {
1359 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1360 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1363 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1364 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1365 int RHSC = (int)RHS->getZExtValue();
1366 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1368 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1372 // Look for (R + R) or (R + (R << [1,2,3])).
1374 Base = N.getOperand(0);
1375 OffReg = N.getOperand(1);
1377 // Swap if it is ((R << c) + R).
1378 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1379 if (ShOpcVal != ARM_AM::lsl) {
1380 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1381 if (ShOpcVal == ARM_AM::lsl)
1382 std::swap(Base, OffReg);
1385 if (ShOpcVal == ARM_AM::lsl) {
1386 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1388 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1389 ShAmt = Sh->getZExtValue();
1390 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1391 OffReg = OffReg.getOperand(0);
1394 ShOpcVal = ARM_AM::no_shift;
1397 ShOpcVal = ARM_AM::no_shift;
1401 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1406 bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
1408 // This *must* succeed since it's used for the irreplaceable ldrex and strex
1411 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1413 if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
1416 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1420 uint32_t RHSC = (int)RHS->getZExtValue();
1421 if (RHSC > 1020 || RHSC % 4 != 0)
1424 Base = N.getOperand(0);
1425 if (Base.getOpcode() == ISD::FrameIndex) {
1426 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1427 Base = CurDAG->getTargetFrameIndex(FI, getTargetLowering()->getPointerTy());
1430 OffImm = CurDAG->getTargetConstant(RHSC / 4, MVT::i32);
1434 //===--------------------------------------------------------------------===//
1436 /// getAL - Returns a ARMCC::AL immediate node.
1437 static inline SDValue getAL(SelectionDAG *CurDAG) {
1438 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1441 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1442 LoadSDNode *LD = cast<LoadSDNode>(N);
1443 ISD::MemIndexedMode AM = LD->getAddressingMode();
1444 if (AM == ISD::UNINDEXED)
1447 EVT LoadedVT = LD->getMemoryVT();
1448 SDValue Offset, AMOpc;
1449 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1450 unsigned Opcode = 0;
1452 if (LoadedVT == MVT::i32 && isPre &&
1453 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1454 Opcode = ARM::LDR_PRE_IMM;
1456 } else if (LoadedVT == MVT::i32 && !isPre &&
1457 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1458 Opcode = ARM::LDR_POST_IMM;
1460 } else if (LoadedVT == MVT::i32 &&
1461 SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1462 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1465 } else if (LoadedVT == MVT::i16 &&
1466 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1468 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1469 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1470 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1471 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1472 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1473 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1475 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1479 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1481 Opcode = ARM::LDRB_PRE_IMM;
1482 } else if (!isPre &&
1483 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1485 Opcode = ARM::LDRB_POST_IMM;
1486 } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1488 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1494 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1495 SDValue Chain = LD->getChain();
1496 SDValue Base = LD->getBasePtr();
1497 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1498 CurDAG->getRegister(0, MVT::i32), Chain };
1499 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1500 MVT::i32, MVT::Other, Ops);
1502 SDValue Chain = LD->getChain();
1503 SDValue Base = LD->getBasePtr();
1504 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1505 CurDAG->getRegister(0, MVT::i32), Chain };
1506 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1507 MVT::i32, MVT::Other, Ops);
1514 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1515 LoadSDNode *LD = cast<LoadSDNode>(N);
1516 ISD::MemIndexedMode AM = LD->getAddressingMode();
1517 if (AM == ISD::UNINDEXED)
1520 EVT LoadedVT = LD->getMemoryVT();
1521 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1523 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1524 unsigned Opcode = 0;
1526 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1527 switch (LoadedVT.getSimpleVT().SimpleTy) {
1529 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1533 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1535 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1540 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1542 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1551 SDValue Chain = LD->getChain();
1552 SDValue Base = LD->getBasePtr();
1553 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1554 CurDAG->getRegister(0, MVT::i32), Chain };
1555 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
1562 /// \brief Form a GPRPair pseudo register from a pair of GPR regs.
1563 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1564 SDLoc dl(V0.getNode());
1566 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);
1567 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
1568 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
1569 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1570 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1573 /// \brief Form a D register from a pair of S registers.
1574 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1575 SDLoc dl(V0.getNode());
1577 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1578 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1579 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1580 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1581 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1584 /// \brief Form a quad register from a pair of D registers.
1585 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1586 SDLoc dl(V0.getNode());
1587 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1588 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1589 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1590 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1591 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1594 /// \brief Form 4 consecutive D registers from a pair of Q registers.
1595 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1596 SDLoc dl(V0.getNode());
1597 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1598 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1599 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1600 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1601 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1604 /// \brief Form 4 consecutive S registers.
1605 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1606 SDValue V2, SDValue V3) {
1607 SDLoc dl(V0.getNode());
1609 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1610 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1611 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1612 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1613 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1614 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1615 V2, SubReg2, V3, SubReg3 };
1616 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1619 /// \brief Form 4 consecutive D registers.
1620 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1621 SDValue V2, SDValue V3) {
1622 SDLoc dl(V0.getNode());
1623 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1624 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1625 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1626 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1627 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1628 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1629 V2, SubReg2, V3, SubReg3 };
1630 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1633 /// \brief Form 4 consecutive Q registers.
1634 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1635 SDValue V2, SDValue V3) {
1636 SDLoc dl(V0.getNode());
1637 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1638 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1639 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1640 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1641 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1642 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1643 V2, SubReg2, V3, SubReg3 };
1644 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1647 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1648 /// of a NEON VLD or VST instruction. The supported values depend on the
1649 /// number of registers being loaded.
1650 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1651 bool is64BitVector) {
1652 unsigned NumRegs = NumVecs;
1653 if (!is64BitVector && NumVecs < 3)
1656 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1657 if (Alignment >= 32 && NumRegs == 4)
1659 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1661 else if (Alignment >= 8)
1666 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1669 static bool isVLDfixed(unsigned Opc)
1672 default: return false;
1673 case ARM::VLD1d8wb_fixed : return true;
1674 case ARM::VLD1d16wb_fixed : return true;
1675 case ARM::VLD1d64Qwb_fixed : return true;
1676 case ARM::VLD1d32wb_fixed : return true;
1677 case ARM::VLD1d64wb_fixed : return true;
1678 case ARM::VLD1d64TPseudoWB_fixed : return true;
1679 case ARM::VLD1d64QPseudoWB_fixed : return true;
1680 case ARM::VLD1q8wb_fixed : return true;
1681 case ARM::VLD1q16wb_fixed : return true;
1682 case ARM::VLD1q32wb_fixed : return true;
1683 case ARM::VLD1q64wb_fixed : return true;
1684 case ARM::VLD2d8wb_fixed : return true;
1685 case ARM::VLD2d16wb_fixed : return true;
1686 case ARM::VLD2d32wb_fixed : return true;
1687 case ARM::VLD2q8PseudoWB_fixed : return true;
1688 case ARM::VLD2q16PseudoWB_fixed : return true;
1689 case ARM::VLD2q32PseudoWB_fixed : return true;
1690 case ARM::VLD2DUPd8wb_fixed : return true;
1691 case ARM::VLD2DUPd16wb_fixed : return true;
1692 case ARM::VLD2DUPd32wb_fixed : return true;
1696 static bool isVSTfixed(unsigned Opc)
1699 default: return false;
1700 case ARM::VST1d8wb_fixed : return true;
1701 case ARM::VST1d16wb_fixed : return true;
1702 case ARM::VST1d32wb_fixed : return true;
1703 case ARM::VST1d64wb_fixed : return true;
1704 case ARM::VST1q8wb_fixed : return true;
1705 case ARM::VST1q16wb_fixed : return true;
1706 case ARM::VST1q32wb_fixed : return true;
1707 case ARM::VST1q64wb_fixed : return true;
1708 case ARM::VST1d64TPseudoWB_fixed : return true;
1709 case ARM::VST1d64QPseudoWB_fixed : return true;
1710 case ARM::VST2d8wb_fixed : return true;
1711 case ARM::VST2d16wb_fixed : return true;
1712 case ARM::VST2d32wb_fixed : return true;
1713 case ARM::VST2q8PseudoWB_fixed : return true;
1714 case ARM::VST2q16PseudoWB_fixed : return true;
1715 case ARM::VST2q32PseudoWB_fixed : return true;
1719 // Get the register stride update opcode of a VLD/VST instruction that
1720 // is otherwise equivalent to the given fixed stride updating instruction.
1721 static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1722 assert((isVLDfixed(Opc) || isVSTfixed(Opc))
1723 && "Incorrect fixed stride updating instruction.");
1726 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1727 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1728 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1729 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1730 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1731 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1732 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1733 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1734 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register;
1735 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register;
1736 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register;
1737 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register;
1739 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1740 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1741 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1742 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1743 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1744 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1745 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1746 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1747 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1748 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1750 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1751 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1752 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1753 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1754 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1755 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1757 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1758 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1759 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1760 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1761 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1762 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1764 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1765 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1766 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1768 return Opc; // If not one we handle, return it unchanged.
1771 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1772 const uint16_t *DOpcodes,
1773 const uint16_t *QOpcodes0,
1774 const uint16_t *QOpcodes1) {
1775 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1778 SDValue MemAddr, Align;
1779 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1780 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1783 SDValue Chain = N->getOperand(0);
1784 EVT VT = N->getValueType(0);
1785 bool is64BitVector = VT.is64BitVector();
1786 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1788 unsigned OpcodeIndex;
1789 switch (VT.getSimpleVT().SimpleTy) {
1790 default: llvm_unreachable("unhandled vld type");
1791 // Double-register operations:
1792 case MVT::v8i8: OpcodeIndex = 0; break;
1793 case MVT::v4i16: OpcodeIndex = 1; break;
1795 case MVT::v2i32: OpcodeIndex = 2; break;
1796 case MVT::v1i64: OpcodeIndex = 3; break;
1797 // Quad-register operations:
1798 case MVT::v16i8: OpcodeIndex = 0; break;
1799 case MVT::v8i16: OpcodeIndex = 1; break;
1801 case MVT::v4i32: OpcodeIndex = 2; break;
1802 case MVT::v2i64: OpcodeIndex = 3;
1803 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1811 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1814 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1816 std::vector<EVT> ResTys;
1817 ResTys.push_back(ResTy);
1819 ResTys.push_back(MVT::i32);
1820 ResTys.push_back(MVT::Other);
1822 SDValue Pred = getAL(CurDAG);
1823 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1825 SmallVector<SDValue, 7> Ops;
1827 // Double registers and VLD1/VLD2 quad registers are directly supported.
1828 if (is64BitVector || NumVecs <= 2) {
1829 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1830 QOpcodes0[OpcodeIndex]);
1831 Ops.push_back(MemAddr);
1832 Ops.push_back(Align);
1834 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1835 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1836 // case entirely when the rest are updated to that form, too.
1837 if ((NumVecs <= 2) && !isa<ConstantSDNode>(Inc.getNode()))
1838 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1839 // FIXME: We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1840 // check for that explicitly too. Horribly hacky, but temporary.
1841 if ((NumVecs > 2 && !isVLDfixed(Opc)) ||
1842 !isa<ConstantSDNode>(Inc.getNode()))
1843 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1845 Ops.push_back(Pred);
1846 Ops.push_back(Reg0);
1847 Ops.push_back(Chain);
1848 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1851 // Otherwise, quad registers are loaded with two separate instructions,
1852 // where one loads the even registers and the other loads the odd registers.
1853 EVT AddrTy = MemAddr.getValueType();
1855 // Load the even subregs. This is always an updating load, so that it
1856 // provides the address to the second load for the odd subregs.
1858 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1859 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1860 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1861 ResTy, AddrTy, MVT::Other, OpsA);
1862 Chain = SDValue(VLdA, 2);
1864 // Load the odd subregs.
1865 Ops.push_back(SDValue(VLdA, 1));
1866 Ops.push_back(Align);
1868 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1869 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1870 "only constant post-increment update allowed for VLD3/4");
1872 Ops.push_back(Reg0);
1874 Ops.push_back(SDValue(VLdA, 0));
1875 Ops.push_back(Pred);
1876 Ops.push_back(Reg0);
1877 Ops.push_back(Chain);
1878 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
1881 // Transfer memoperands.
1882 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1883 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1884 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1889 // Extract out the subregisters.
1890 SDValue SuperReg = SDValue(VLd, 0);
1891 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1892 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1893 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1894 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1895 ReplaceUses(SDValue(N, Vec),
1896 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1897 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1899 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1903 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1904 const uint16_t *DOpcodes,
1905 const uint16_t *QOpcodes0,
1906 const uint16_t *QOpcodes1) {
1907 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1910 SDValue MemAddr, Align;
1911 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1912 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1913 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1916 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1917 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1919 SDValue Chain = N->getOperand(0);
1920 EVT VT = N->getOperand(Vec0Idx).getValueType();
1921 bool is64BitVector = VT.is64BitVector();
1922 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1924 unsigned OpcodeIndex;
1925 switch (VT.getSimpleVT().SimpleTy) {
1926 default: llvm_unreachable("unhandled vst type");
1927 // Double-register operations:
1928 case MVT::v8i8: OpcodeIndex = 0; break;
1929 case MVT::v4i16: OpcodeIndex = 1; break;
1931 case MVT::v2i32: OpcodeIndex = 2; break;
1932 case MVT::v1i64: OpcodeIndex = 3; break;
1933 // Quad-register operations:
1934 case MVT::v16i8: OpcodeIndex = 0; break;
1935 case MVT::v8i16: OpcodeIndex = 1; break;
1937 case MVT::v4i32: OpcodeIndex = 2; break;
1938 case MVT::v2i64: OpcodeIndex = 3;
1939 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1943 std::vector<EVT> ResTys;
1945 ResTys.push_back(MVT::i32);
1946 ResTys.push_back(MVT::Other);
1948 SDValue Pred = getAL(CurDAG);
1949 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1950 SmallVector<SDValue, 7> Ops;
1952 // Double registers and VST1/VST2 quad registers are directly supported.
1953 if (is64BitVector || NumVecs <= 2) {
1956 SrcReg = N->getOperand(Vec0Idx);
1957 } else if (is64BitVector) {
1958 // Form a REG_SEQUENCE to force register allocation.
1959 SDValue V0 = N->getOperand(Vec0Idx + 0);
1960 SDValue V1 = N->getOperand(Vec0Idx + 1);
1962 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
1964 SDValue V2 = N->getOperand(Vec0Idx + 2);
1965 // If it's a vst3, form a quad D-register and leave the last part as
1967 SDValue V3 = (NumVecs == 3)
1968 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1969 : N->getOperand(Vec0Idx + 3);
1970 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
1973 // Form a QQ register.
1974 SDValue Q0 = N->getOperand(Vec0Idx);
1975 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1976 SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
1979 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1980 QOpcodes0[OpcodeIndex]);
1981 Ops.push_back(MemAddr);
1982 Ops.push_back(Align);
1984 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1985 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1986 // case entirely when the rest are updated to that form, too.
1987 if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1988 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1989 // FIXME: We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
1990 // check for that explicitly too. Horribly hacky, but temporary.
1991 if (!isa<ConstantSDNode>(Inc.getNode()))
1993 else if (NumVecs > 2 && !isVSTfixed(Opc))
1994 Ops.push_back(Reg0);
1996 Ops.push_back(SrcReg);
1997 Ops.push_back(Pred);
1998 Ops.push_back(Reg0);
1999 Ops.push_back(Chain);
2000 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2002 // Transfer memoperands.
2003 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
2008 // Otherwise, quad registers are stored with two separate instructions,
2009 // where one stores the even registers and the other stores the odd registers.
2011 // Form the QQQQ REG_SEQUENCE.
2012 SDValue V0 = N->getOperand(Vec0Idx + 0);
2013 SDValue V1 = N->getOperand(Vec0Idx + 1);
2014 SDValue V2 = N->getOperand(Vec0Idx + 2);
2015 SDValue V3 = (NumVecs == 3)
2016 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2017 : N->getOperand(Vec0Idx + 3);
2018 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2020 // Store the even D registers. This is always an updating store, so that it
2021 // provides the address to the second store for the odd subregs.
2022 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
2023 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
2024 MemAddr.getValueType(),
2026 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
2027 Chain = SDValue(VStA, 1);
2029 // Store the odd D registers.
2030 Ops.push_back(SDValue(VStA, 0));
2031 Ops.push_back(Align);
2033 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2034 assert(isa<ConstantSDNode>(Inc.getNode()) &&
2035 "only constant post-increment update allowed for VST3/4");
2037 Ops.push_back(Reg0);
2039 Ops.push_back(RegSeq);
2040 Ops.push_back(Pred);
2041 Ops.push_back(Reg0);
2042 Ops.push_back(Chain);
2043 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
2045 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
2049 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
2050 bool isUpdating, unsigned NumVecs,
2051 const uint16_t *DOpcodes,
2052 const uint16_t *QOpcodes) {
2053 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2056 SDValue MemAddr, Align;
2057 unsigned AddrOpIdx = isUpdating ? 1 : 2;
2058 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
2059 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
2062 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2063 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2065 SDValue Chain = N->getOperand(0);
2067 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
2068 EVT VT = N->getOperand(Vec0Idx).getValueType();
2069 bool is64BitVector = VT.is64BitVector();
2071 unsigned Alignment = 0;
2073 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2074 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2075 if (Alignment > NumBytes)
2076 Alignment = NumBytes;
2077 if (Alignment < 8 && Alignment < NumBytes)
2079 // Alignment must be a power of two; make sure of that.
2080 Alignment = (Alignment & -Alignment);
2084 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2086 unsigned OpcodeIndex;
2087 switch (VT.getSimpleVT().SimpleTy) {
2088 default: llvm_unreachable("unhandled vld/vst lane type");
2089 // Double-register operations:
2090 case MVT::v8i8: OpcodeIndex = 0; break;
2091 case MVT::v4i16: OpcodeIndex = 1; break;
2093 case MVT::v2i32: OpcodeIndex = 2; break;
2094 // Quad-register operations:
2095 case MVT::v8i16: OpcodeIndex = 0; break;
2097 case MVT::v4i32: OpcodeIndex = 1; break;
2100 std::vector<EVT> ResTys;
2102 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2105 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
2106 MVT::i64, ResTyElts));
2109 ResTys.push_back(MVT::i32);
2110 ResTys.push_back(MVT::Other);
2112 SDValue Pred = getAL(CurDAG);
2113 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2115 SmallVector<SDValue, 8> Ops;
2116 Ops.push_back(MemAddr);
2117 Ops.push_back(Align);
2119 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2120 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2124 SDValue V0 = N->getOperand(Vec0Idx + 0);
2125 SDValue V1 = N->getOperand(Vec0Idx + 1);
2128 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2130 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2132 SDValue V2 = N->getOperand(Vec0Idx + 2);
2133 SDValue V3 = (NumVecs == 3)
2134 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2135 : N->getOperand(Vec0Idx + 3);
2137 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2139 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2141 Ops.push_back(SuperReg);
2142 Ops.push_back(getI32Imm(Lane));
2143 Ops.push_back(Pred);
2144 Ops.push_back(Reg0);
2145 Ops.push_back(Chain);
2147 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
2148 QOpcodes[OpcodeIndex]);
2149 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2150 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
2154 // Extract the subregisters.
2155 SuperReg = SDValue(VLdLn, 0);
2156 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
2157 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
2158 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2159 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2160 ReplaceUses(SDValue(N, Vec),
2161 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2162 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2164 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2168 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
2170 const uint16_t *Opcodes) {
2171 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2174 SDValue MemAddr, Align;
2175 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2178 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2179 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2181 SDValue Chain = N->getOperand(0);
2182 EVT VT = N->getValueType(0);
2184 unsigned Alignment = 0;
2186 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2187 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2188 if (Alignment > NumBytes)
2189 Alignment = NumBytes;
2190 if (Alignment < 8 && Alignment < NumBytes)
2192 // Alignment must be a power of two; make sure of that.
2193 Alignment = (Alignment & -Alignment);
2197 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2199 unsigned OpcodeIndex;
2200 switch (VT.getSimpleVT().SimpleTy) {
2201 default: llvm_unreachable("unhandled vld-dup type");
2202 case MVT::v8i8: OpcodeIndex = 0; break;
2203 case MVT::v4i16: OpcodeIndex = 1; break;
2205 case MVT::v2i32: OpcodeIndex = 2; break;
2208 SDValue Pred = getAL(CurDAG);
2209 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2211 unsigned Opc = Opcodes[OpcodeIndex];
2212 SmallVector<SDValue, 6> Ops;
2213 Ops.push_back(MemAddr);
2214 Ops.push_back(Align);
2216 // fixed-stride update instructions don't have an explicit writeback
2217 // operand. It's implicit in the opcode itself.
2218 SDValue Inc = N->getOperand(2);
2219 if (!isa<ConstantSDNode>(Inc.getNode()))
2221 // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2222 else if (NumVecs > 2)
2223 Ops.push_back(Reg0);
2225 Ops.push_back(Pred);
2226 Ops.push_back(Reg0);
2227 Ops.push_back(Chain);
2229 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2230 std::vector<EVT> ResTys;
2231 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2233 ResTys.push_back(MVT::i32);
2234 ResTys.push_back(MVT::Other);
2235 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2236 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2237 SuperReg = SDValue(VLdDup, 0);
2239 // Extract the subregisters.
2240 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2241 unsigned SubIdx = ARM::dsub_0;
2242 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2243 ReplaceUses(SDValue(N, Vec),
2244 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2245 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2247 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2251 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2253 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2255 EVT VT = N->getValueType(0);
2256 unsigned FirstTblReg = IsExt ? 2 : 1;
2258 // Form a REG_SEQUENCE to force register allocation.
2260 SDValue V0 = N->getOperand(FirstTblReg + 0);
2261 SDValue V1 = N->getOperand(FirstTblReg + 1);
2263 RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
2265 SDValue V2 = N->getOperand(FirstTblReg + 2);
2266 // If it's a vtbl3, form a quad D-register and leave the last part as
2268 SDValue V3 = (NumVecs == 3)
2269 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2270 : N->getOperand(FirstTblReg + 3);
2271 RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2274 SmallVector<SDValue, 6> Ops;
2276 Ops.push_back(N->getOperand(1));
2277 Ops.push_back(RegSeq);
2278 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2279 Ops.push_back(getAL(CurDAG)); // predicate
2280 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2281 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2284 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2286 if (!Subtarget->hasV6T2Ops())
2289 unsigned Opc = isSigned
2290 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2291 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2293 // For unsigned extracts, check for a shift right and mask
2294 unsigned And_imm = 0;
2295 if (N->getOpcode() == ISD::AND) {
2296 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2298 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2299 if (And_imm & (And_imm + 1))
2302 unsigned Srl_imm = 0;
2303 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2305 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2307 // Note: The width operand is encoded as width-1.
2308 unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2309 unsigned LSB = Srl_imm;
2311 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2313 if ((LSB + Width + 1) == N->getValueType(0).getSizeInBits()) {
2314 // It's cheaper to use a right shift to extract the top bits.
2315 if (Subtarget->isThumb()) {
2316 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
2317 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2318 CurDAG->getTargetConstant(LSB, MVT::i32),
2319 getAL(CurDAG), Reg0, Reg0 };
2320 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2323 // ARM models shift instructions as MOVsi with shifter operand.
2324 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
2326 CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, LSB),
2328 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
2329 getAL(CurDAG), Reg0, Reg0 };
2330 return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops, 5);
2333 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2334 CurDAG->getTargetConstant(LSB, MVT::i32),
2335 CurDAG->getTargetConstant(Width, MVT::i32),
2336 getAL(CurDAG), Reg0 };
2337 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2343 // Otherwise, we're looking for a shift of a shift
2344 unsigned Shl_imm = 0;
2345 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2346 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2347 unsigned Srl_imm = 0;
2348 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2349 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2350 // Note: The width operand is encoded as width-1.
2351 unsigned Width = 32 - Srl_imm - 1;
2352 int LSB = Srl_imm - Shl_imm;
2355 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2356 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2357 CurDAG->getTargetConstant(LSB, MVT::i32),
2358 CurDAG->getTargetConstant(Width, MVT::i32),
2359 getAL(CurDAG), Reg0 };
2360 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2366 /// Target-specific DAG combining for ISD::XOR.
2367 /// Target-independent combining lowers SELECT_CC nodes of the form
2368 /// select_cc setg[ge] X, 0, X, -X
2369 /// select_cc setgt X, -1, X, -X
2370 /// select_cc setl[te] X, 0, -X, X
2371 /// select_cc setlt X, 1, -X, X
2372 /// which represent Integer ABS into:
2373 /// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2374 /// ARM instruction selection detects the latter and matches it to
2375 /// ARM::ABS or ARM::t2ABS machine node.
2376 SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2377 SDValue XORSrc0 = N->getOperand(0);
2378 SDValue XORSrc1 = N->getOperand(1);
2379 EVT VT = N->getValueType(0);
2381 if (Subtarget->isThumb1Only())
2384 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2387 SDValue ADDSrc0 = XORSrc0.getOperand(0);
2388 SDValue ADDSrc1 = XORSrc0.getOperand(1);
2389 SDValue SRASrc0 = XORSrc1.getOperand(0);
2390 SDValue SRASrc1 = XORSrc1.getOperand(1);
2391 ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1);
2392 EVT XType = SRASrc0.getValueType();
2393 unsigned Size = XType.getSizeInBits() - 1;
2395 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2396 XType.isInteger() && SRAConstant != NULL &&
2397 Size == SRAConstant->getZExtValue()) {
2398 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2399 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2405 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2406 // The only time a CONCAT_VECTORS operation can have legal types is when
2407 // two 64-bit vectors are concatenated to a 128-bit vector.
2408 EVT VT = N->getValueType(0);
2409 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2410 llvm_unreachable("unexpected CONCAT_VECTORS");
2411 return createDRegPairNode(VT, N->getOperand(0), N->getOperand(1));
2414 SDNode *ARMDAGToDAGISel::SelectAtomic(SDNode *Node, unsigned Op8,
2415 unsigned Op16,unsigned Op32,
2417 // Mostly direct translation to the given operations, except that we preserve
2418 // the AtomicOrdering for use later on.
2419 AtomicSDNode *AN = cast<AtomicSDNode>(Node);
2420 EVT VT = AN->getMemoryVT();
2423 SDVTList VTs = CurDAG->getVTList(AN->getValueType(0), MVT::Other);
2426 else if (VT == MVT::i16)
2428 else if (VT == MVT::i32)
2430 else if (VT == MVT::i64) {
2432 VTs = CurDAG->getVTList(MVT::i32, MVT::i32, MVT::Other);
2434 llvm_unreachable("Unexpected atomic operation");
2436 SmallVector<SDValue, 6> Ops;
2437 for (unsigned i = 1; i < AN->getNumOperands(); ++i)
2438 Ops.push_back(AN->getOperand(i));
2440 Ops.push_back(CurDAG->getTargetConstant(AN->getOrdering(), MVT::i32));
2441 Ops.push_back(AN->getOperand(0)); // Chain moves to the end
2443 return CurDAG->SelectNodeTo(Node, Op, VTs, &Ops[0], Ops.size());
2446 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2449 if (N->isMachineOpcode()) {
2451 return NULL; // Already selected.
2454 switch (N->getOpcode()) {
2456 case ISD::INLINEASM: {
2457 SDNode *ResNode = SelectInlineAsm(N);
2463 // Select special operations if XOR node forms integer ABS pattern
2464 SDNode *ResNode = SelectABSOp(N);
2467 // Other cases are autogenerated.
2470 case ISD::Constant: {
2471 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2473 if (Subtarget->useMovt())
2474 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2475 // be done with MOV + MOVT, at worst.
2478 if (Subtarget->isThumb()) {
2479 UseCP = (Val > 255 && // MOV
2480 ~Val > 255 && // MOV + MVN
2481 !ARM_AM::isThumbImmShiftedVal(Val) && // MOV + LSL
2482 !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW
2484 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2485 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2486 !ARM_AM::isSOImmTwoPartVal(Val) && // two instrs.
2487 !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW
2492 CurDAG->getTargetConstantPool(ConstantInt::get(
2493 Type::getInt32Ty(*CurDAG->getContext()), Val),
2494 getTargetLowering()->getPointerTy());
2497 if (Subtarget->isThumb()) {
2498 SDValue Pred = getAL(CurDAG);
2499 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2500 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2501 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2506 CurDAG->getTargetConstant(0, MVT::i32),
2508 CurDAG->getRegister(0, MVT::i32),
2509 CurDAG->getEntryNode()
2511 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2514 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2518 // Other cases are autogenerated.
2521 case ISD::FrameIndex: {
2522 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2523 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2524 SDValue TFI = CurDAG->getTargetFrameIndex(FI,
2525 getTargetLowering()->getPointerTy());
2526 if (Subtarget->isThumb1Only()) {
2527 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2528 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2529 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2531 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2532 ARM::t2ADDri : ARM::ADDri);
2533 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2534 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2535 CurDAG->getRegister(0, MVT::i32) };
2536 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2540 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2544 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2548 if (Subtarget->isThumb1Only())
2550 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2551 unsigned RHSV = C->getZExtValue();
2553 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2554 unsigned ShImm = Log2_32(RHSV-1);
2557 SDValue V = N->getOperand(0);
2558 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2559 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2560 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2561 if (Subtarget->isThumb()) {
2562 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2563 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2565 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2566 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2569 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2570 unsigned ShImm = Log2_32(RHSV+1);
2573 SDValue V = N->getOperand(0);
2574 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2575 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2576 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2577 if (Subtarget->isThumb()) {
2578 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2579 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2581 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2582 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2588 // Check for unsigned bitfield extract
2589 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2592 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2593 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2594 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2595 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2596 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2597 EVT VT = N->getValueType(0);
2600 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2602 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2605 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2606 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2609 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2610 SDValue N2 = N0.getOperand(1);
2611 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2614 unsigned N1CVal = N1C->getZExtValue();
2615 unsigned N2CVal = N2C->getZExtValue();
2616 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2617 (N1CVal & 0xffffU) == 0xffffU &&
2618 (N2CVal & 0xffffU) == 0x0U) {
2619 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2621 SDValue Ops[] = { N0.getOperand(0), Imm16,
2622 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2623 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2628 case ARMISD::VMOVRRD:
2629 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2630 N->getOperand(0), getAL(CurDAG),
2631 CurDAG->getRegister(0, MVT::i32));
2632 case ISD::UMUL_LOHI: {
2633 if (Subtarget->isThumb1Only())
2635 if (Subtarget->isThumb()) {
2636 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2637 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2638 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
2640 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2641 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2642 CurDAG->getRegister(0, MVT::i32) };
2643 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2644 ARM::UMULL : ARM::UMULLv5,
2645 dl, MVT::i32, MVT::i32, Ops);
2648 case ISD::SMUL_LOHI: {
2649 if (Subtarget->isThumb1Only())
2651 if (Subtarget->isThumb()) {
2652 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2653 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2654 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
2656 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2657 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2658 CurDAG->getRegister(0, MVT::i32) };
2659 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2660 ARM::SMULL : ARM::SMULLv5,
2661 dl, MVT::i32, MVT::i32, Ops);
2664 case ARMISD::UMLAL:{
2665 if (Subtarget->isThumb()) {
2666 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2667 N->getOperand(3), getAL(CurDAG),
2668 CurDAG->getRegister(0, MVT::i32)};
2669 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
2671 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2672 N->getOperand(3), getAL(CurDAG),
2673 CurDAG->getRegister(0, MVT::i32),
2674 CurDAG->getRegister(0, MVT::i32) };
2675 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2676 ARM::UMLAL : ARM::UMLALv5,
2677 dl, MVT::i32, MVT::i32, Ops);
2680 case ARMISD::SMLAL:{
2681 if (Subtarget->isThumb()) {
2682 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2683 N->getOperand(3), getAL(CurDAG),
2684 CurDAG->getRegister(0, MVT::i32)};
2685 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
2687 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2688 N->getOperand(3), getAL(CurDAG),
2689 CurDAG->getRegister(0, MVT::i32),
2690 CurDAG->getRegister(0, MVT::i32) };
2691 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2692 ARM::SMLAL : ARM::SMLALv5,
2693 dl, MVT::i32, MVT::i32, Ops);
2697 SDNode *ResNode = 0;
2698 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2699 ResNode = SelectT2IndexedLoad(N);
2701 ResNode = SelectARMIndexedLoad(N);
2704 // Other cases are autogenerated.
2707 case ARMISD::BRCOND: {
2708 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2709 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2710 // Pattern complexity = 6 cost = 1 size = 0
2712 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2713 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2714 // Pattern complexity = 6 cost = 1 size = 0
2716 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2717 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2718 // Pattern complexity = 6 cost = 1 size = 0
2720 unsigned Opc = Subtarget->isThumb() ?
2721 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2722 SDValue Chain = N->getOperand(0);
2723 SDValue N1 = N->getOperand(1);
2724 SDValue N2 = N->getOperand(2);
2725 SDValue N3 = N->getOperand(3);
2726 SDValue InFlag = N->getOperand(4);
2727 assert(N1.getOpcode() == ISD::BasicBlock);
2728 assert(N2.getOpcode() == ISD::Constant);
2729 assert(N3.getOpcode() == ISD::Register);
2731 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2732 cast<ConstantSDNode>(N2)->getZExtValue()),
2734 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2735 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2737 Chain = SDValue(ResNode, 0);
2738 if (N->getNumValues() == 2) {
2739 InFlag = SDValue(ResNode, 1);
2740 ReplaceUses(SDValue(N, 1), InFlag);
2742 ReplaceUses(SDValue(N, 0),
2743 SDValue(Chain.getNode(), Chain.getResNo()));
2746 case ARMISD::VZIP: {
2748 EVT VT = N->getValueType(0);
2749 switch (VT.getSimpleVT().SimpleTy) {
2750 default: return NULL;
2751 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2752 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2754 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2755 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2756 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2757 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2759 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2761 SDValue Pred = getAL(CurDAG);
2762 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2763 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2764 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2766 case ARMISD::VUZP: {
2768 EVT VT = N->getValueType(0);
2769 switch (VT.getSimpleVT().SimpleTy) {
2770 default: return NULL;
2771 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2772 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2774 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2775 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2776 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2777 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2779 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2781 SDValue Pred = getAL(CurDAG);
2782 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2783 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2784 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2786 case ARMISD::VTRN: {
2788 EVT VT = N->getValueType(0);
2789 switch (VT.getSimpleVT().SimpleTy) {
2790 default: return NULL;
2791 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2792 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2794 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2795 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2796 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2798 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2800 SDValue Pred = getAL(CurDAG);
2801 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2802 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2803 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2805 case ARMISD::BUILD_VECTOR: {
2806 EVT VecVT = N->getValueType(0);
2807 EVT EltVT = VecVT.getVectorElementType();
2808 unsigned NumElts = VecVT.getVectorNumElements();
2809 if (EltVT == MVT::f64) {
2810 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2811 return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2813 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2815 return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2816 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2817 return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
2818 N->getOperand(2), N->getOperand(3));
2821 case ARMISD::VLD2DUP: {
2822 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2824 return SelectVLDDup(N, false, 2, Opcodes);
2827 case ARMISD::VLD3DUP: {
2828 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
2829 ARM::VLD3DUPd16Pseudo,
2830 ARM::VLD3DUPd32Pseudo };
2831 return SelectVLDDup(N, false, 3, Opcodes);
2834 case ARMISD::VLD4DUP: {
2835 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
2836 ARM::VLD4DUPd16Pseudo,
2837 ARM::VLD4DUPd32Pseudo };
2838 return SelectVLDDup(N, false, 4, Opcodes);
2841 case ARMISD::VLD2DUP_UPD: {
2842 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
2843 ARM::VLD2DUPd16wb_fixed,
2844 ARM::VLD2DUPd32wb_fixed };
2845 return SelectVLDDup(N, true, 2, Opcodes);
2848 case ARMISD::VLD3DUP_UPD: {
2849 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
2850 ARM::VLD3DUPd16Pseudo_UPD,
2851 ARM::VLD3DUPd32Pseudo_UPD };
2852 return SelectVLDDup(N, true, 3, Opcodes);
2855 case ARMISD::VLD4DUP_UPD: {
2856 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
2857 ARM::VLD4DUPd16Pseudo_UPD,
2858 ARM::VLD4DUPd32Pseudo_UPD };
2859 return SelectVLDDup(N, true, 4, Opcodes);
2862 case ARMISD::VLD1_UPD: {
2863 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
2864 ARM::VLD1d16wb_fixed,
2865 ARM::VLD1d32wb_fixed,
2866 ARM::VLD1d64wb_fixed };
2867 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
2868 ARM::VLD1q16wb_fixed,
2869 ARM::VLD1q32wb_fixed,
2870 ARM::VLD1q64wb_fixed };
2871 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2874 case ARMISD::VLD2_UPD: {
2875 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
2876 ARM::VLD2d16wb_fixed,
2877 ARM::VLD2d32wb_fixed,
2878 ARM::VLD1q64wb_fixed};
2879 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2880 ARM::VLD2q16PseudoWB_fixed,
2881 ARM::VLD2q32PseudoWB_fixed };
2882 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2885 case ARMISD::VLD3_UPD: {
2886 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
2887 ARM::VLD3d16Pseudo_UPD,
2888 ARM::VLD3d32Pseudo_UPD,
2889 ARM::VLD1d64TPseudoWB_fixed};
2890 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2891 ARM::VLD3q16Pseudo_UPD,
2892 ARM::VLD3q32Pseudo_UPD };
2893 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2894 ARM::VLD3q16oddPseudo_UPD,
2895 ARM::VLD3q32oddPseudo_UPD };
2896 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2899 case ARMISD::VLD4_UPD: {
2900 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
2901 ARM::VLD4d16Pseudo_UPD,
2902 ARM::VLD4d32Pseudo_UPD,
2903 ARM::VLD1d64QPseudoWB_fixed};
2904 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2905 ARM::VLD4q16Pseudo_UPD,
2906 ARM::VLD4q32Pseudo_UPD };
2907 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2908 ARM::VLD4q16oddPseudo_UPD,
2909 ARM::VLD4q32oddPseudo_UPD };
2910 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2913 case ARMISD::VLD2LN_UPD: {
2914 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
2915 ARM::VLD2LNd16Pseudo_UPD,
2916 ARM::VLD2LNd32Pseudo_UPD };
2917 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2918 ARM::VLD2LNq32Pseudo_UPD };
2919 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2922 case ARMISD::VLD3LN_UPD: {
2923 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
2924 ARM::VLD3LNd16Pseudo_UPD,
2925 ARM::VLD3LNd32Pseudo_UPD };
2926 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2927 ARM::VLD3LNq32Pseudo_UPD };
2928 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2931 case ARMISD::VLD4LN_UPD: {
2932 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
2933 ARM::VLD4LNd16Pseudo_UPD,
2934 ARM::VLD4LNd32Pseudo_UPD };
2935 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2936 ARM::VLD4LNq32Pseudo_UPD };
2937 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2940 case ARMISD::VST1_UPD: {
2941 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
2942 ARM::VST1d16wb_fixed,
2943 ARM::VST1d32wb_fixed,
2944 ARM::VST1d64wb_fixed };
2945 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
2946 ARM::VST1q16wb_fixed,
2947 ARM::VST1q32wb_fixed,
2948 ARM::VST1q64wb_fixed };
2949 return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2952 case ARMISD::VST2_UPD: {
2953 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
2954 ARM::VST2d16wb_fixed,
2955 ARM::VST2d32wb_fixed,
2956 ARM::VST1q64wb_fixed};
2957 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
2958 ARM::VST2q16PseudoWB_fixed,
2959 ARM::VST2q32PseudoWB_fixed };
2960 return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2963 case ARMISD::VST3_UPD: {
2964 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
2965 ARM::VST3d16Pseudo_UPD,
2966 ARM::VST3d32Pseudo_UPD,
2967 ARM::VST1d64TPseudoWB_fixed};
2968 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2969 ARM::VST3q16Pseudo_UPD,
2970 ARM::VST3q32Pseudo_UPD };
2971 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2972 ARM::VST3q16oddPseudo_UPD,
2973 ARM::VST3q32oddPseudo_UPD };
2974 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2977 case ARMISD::VST4_UPD: {
2978 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
2979 ARM::VST4d16Pseudo_UPD,
2980 ARM::VST4d32Pseudo_UPD,
2981 ARM::VST1d64QPseudoWB_fixed};
2982 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2983 ARM::VST4q16Pseudo_UPD,
2984 ARM::VST4q32Pseudo_UPD };
2985 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2986 ARM::VST4q16oddPseudo_UPD,
2987 ARM::VST4q32oddPseudo_UPD };
2988 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2991 case ARMISD::VST2LN_UPD: {
2992 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
2993 ARM::VST2LNd16Pseudo_UPD,
2994 ARM::VST2LNd32Pseudo_UPD };
2995 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2996 ARM::VST2LNq32Pseudo_UPD };
2997 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
3000 case ARMISD::VST3LN_UPD: {
3001 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
3002 ARM::VST3LNd16Pseudo_UPD,
3003 ARM::VST3LNd32Pseudo_UPD };
3004 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
3005 ARM::VST3LNq32Pseudo_UPD };
3006 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
3009 case ARMISD::VST4LN_UPD: {
3010 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
3011 ARM::VST4LNd16Pseudo_UPD,
3012 ARM::VST4LNd32Pseudo_UPD };
3013 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
3014 ARM::VST4LNq32Pseudo_UPD };
3015 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
3018 case ISD::INTRINSIC_VOID:
3019 case ISD::INTRINSIC_W_CHAIN: {
3020 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
3025 case Intrinsic::arm_ldrexd: {
3026 SDValue MemAddr = N->getOperand(2);
3028 SDValue Chain = N->getOperand(0);
3030 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3031 unsigned NewOpc = isThumb ? ARM::t2LDREXD :ARM::LDREXD;
3033 // arm_ldrexd returns a i64 value in {i32, i32}
3034 std::vector<EVT> ResTys;
3036 ResTys.push_back(MVT::i32);
3037 ResTys.push_back(MVT::i32);
3039 ResTys.push_back(MVT::Untyped);
3040 ResTys.push_back(MVT::Other);
3042 // Place arguments in the right order.
3043 SmallVector<SDValue, 7> Ops;
3044 Ops.push_back(MemAddr);
3045 Ops.push_back(getAL(CurDAG));
3046 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3047 Ops.push_back(Chain);
3048 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3049 // Transfer memoperands.
3050 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3051 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3052 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
3055 SDValue OutChain = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
3056 if (!SDValue(N, 0).use_empty()) {
3059 Result = SDValue(Ld, 0);
3061 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
3062 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3063 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3064 Result = SDValue(ResNode,0);
3066 ReplaceUses(SDValue(N, 0), Result);
3068 if (!SDValue(N, 1).use_empty()) {
3071 Result = SDValue(Ld, 1);
3073 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
3074 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3075 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3076 Result = SDValue(ResNode,0);
3078 ReplaceUses(SDValue(N, 1), Result);
3080 ReplaceUses(SDValue(N, 2), OutChain);
3084 case Intrinsic::arm_strexd: {
3086 SDValue Chain = N->getOperand(0);
3087 SDValue Val0 = N->getOperand(2);
3088 SDValue Val1 = N->getOperand(3);
3089 SDValue MemAddr = N->getOperand(4);
3091 // Store exclusive double return a i32 value which is the return status
3092 // of the issued store.
3093 EVT ResTys[] = { MVT::i32, MVT::Other };
3095 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3096 // Place arguments in the right order.
3097 SmallVector<SDValue, 7> Ops;
3099 Ops.push_back(Val0);
3100 Ops.push_back(Val1);
3102 // arm_strexd uses GPRPair.
3103 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
3104 Ops.push_back(MemAddr);
3105 Ops.push_back(getAL(CurDAG));
3106 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3107 Ops.push_back(Chain);
3109 unsigned NewOpc = isThumb ? ARM::t2STREXD : ARM::STREXD;
3111 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3112 // Transfer memoperands.
3113 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3114 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3115 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3120 case Intrinsic::arm_neon_vld1: {
3121 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3122 ARM::VLD1d32, ARM::VLD1d64 };
3123 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3124 ARM::VLD1q32, ARM::VLD1q64};
3125 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
3128 case Intrinsic::arm_neon_vld2: {
3129 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3130 ARM::VLD2d32, ARM::VLD1q64 };
3131 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3132 ARM::VLD2q32Pseudo };
3133 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
3136 case Intrinsic::arm_neon_vld3: {
3137 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
3140 ARM::VLD1d64TPseudo };
3141 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3142 ARM::VLD3q16Pseudo_UPD,
3143 ARM::VLD3q32Pseudo_UPD };
3144 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3145 ARM::VLD3q16oddPseudo,
3146 ARM::VLD3q32oddPseudo };
3147 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3150 case Intrinsic::arm_neon_vld4: {
3151 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
3154 ARM::VLD1d64QPseudo };
3155 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3156 ARM::VLD4q16Pseudo_UPD,
3157 ARM::VLD4q32Pseudo_UPD };
3158 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3159 ARM::VLD4q16oddPseudo,
3160 ARM::VLD4q32oddPseudo };
3161 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3164 case Intrinsic::arm_neon_vld2lane: {
3165 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
3166 ARM::VLD2LNd16Pseudo,
3167 ARM::VLD2LNd32Pseudo };
3168 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
3169 ARM::VLD2LNq32Pseudo };
3170 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3173 case Intrinsic::arm_neon_vld3lane: {
3174 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
3175 ARM::VLD3LNd16Pseudo,
3176 ARM::VLD3LNd32Pseudo };
3177 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
3178 ARM::VLD3LNq32Pseudo };
3179 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3182 case Intrinsic::arm_neon_vld4lane: {
3183 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
3184 ARM::VLD4LNd16Pseudo,
3185 ARM::VLD4LNd32Pseudo };
3186 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
3187 ARM::VLD4LNq32Pseudo };
3188 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3191 case Intrinsic::arm_neon_vst1: {
3192 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3193 ARM::VST1d32, ARM::VST1d64 };
3194 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3195 ARM::VST1q32, ARM::VST1q64 };
3196 return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3199 case Intrinsic::arm_neon_vst2: {
3200 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3201 ARM::VST2d32, ARM::VST1q64 };
3202 static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3203 ARM::VST2q32Pseudo };
3204 return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3207 case Intrinsic::arm_neon_vst3: {
3208 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
3211 ARM::VST1d64TPseudo };
3212 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3213 ARM::VST3q16Pseudo_UPD,
3214 ARM::VST3q32Pseudo_UPD };
3215 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
3216 ARM::VST3q16oddPseudo,
3217 ARM::VST3q32oddPseudo };
3218 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3221 case Intrinsic::arm_neon_vst4: {
3222 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
3225 ARM::VST1d64QPseudo };
3226 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3227 ARM::VST4q16Pseudo_UPD,
3228 ARM::VST4q32Pseudo_UPD };
3229 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
3230 ARM::VST4q16oddPseudo,
3231 ARM::VST4q32oddPseudo };
3232 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3235 case Intrinsic::arm_neon_vst2lane: {
3236 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
3237 ARM::VST2LNd16Pseudo,
3238 ARM::VST2LNd32Pseudo };
3239 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
3240 ARM::VST2LNq32Pseudo };
3241 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3244 case Intrinsic::arm_neon_vst3lane: {
3245 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
3246 ARM::VST3LNd16Pseudo,
3247 ARM::VST3LNd32Pseudo };
3248 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
3249 ARM::VST3LNq32Pseudo };
3250 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3253 case Intrinsic::arm_neon_vst4lane: {
3254 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
3255 ARM::VST4LNd16Pseudo,
3256 ARM::VST4LNd32Pseudo };
3257 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
3258 ARM::VST4LNq32Pseudo };
3259 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3265 case ISD::INTRINSIC_WO_CHAIN: {
3266 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3271 case Intrinsic::arm_neon_vtbl2:
3272 return SelectVTBL(N, false, 2, ARM::VTBL2);
3273 case Intrinsic::arm_neon_vtbl3:
3274 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3275 case Intrinsic::arm_neon_vtbl4:
3276 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3278 case Intrinsic::arm_neon_vtbx2:
3279 return SelectVTBL(N, true, 2, ARM::VTBX2);
3280 case Intrinsic::arm_neon_vtbx3:
3281 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3282 case Intrinsic::arm_neon_vtbx4:
3283 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3288 case ARMISD::VTBL1: {
3290 EVT VT = N->getValueType(0);
3291 SmallVector<SDValue, 6> Ops;
3293 Ops.push_back(N->getOperand(0));
3294 Ops.push_back(N->getOperand(1));
3295 Ops.push_back(getAL(CurDAG)); // Predicate
3296 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3297 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
3299 case ARMISD::VTBL2: {
3301 EVT VT = N->getValueType(0);
3303 // Form a REG_SEQUENCE to force register allocation.
3304 SDValue V0 = N->getOperand(0);
3305 SDValue V1 = N->getOperand(1);
3306 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
3308 SmallVector<SDValue, 6> Ops;
3309 Ops.push_back(RegSeq);
3310 Ops.push_back(N->getOperand(2));
3311 Ops.push_back(getAL(CurDAG)); // Predicate
3312 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3313 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
3316 case ISD::CONCAT_VECTORS:
3317 return SelectConcatVector(N);
3319 case ISD::ATOMIC_LOAD:
3320 if (cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64)
3321 return SelectAtomic(N, 0, 0, 0, ARM::ATOMIC_LOAD_I64);
3325 case ISD::ATOMIC_LOAD_ADD:
3326 return SelectAtomic(N,
3327 ARM::ATOMIC_LOAD_ADD_I8,
3328 ARM::ATOMIC_LOAD_ADD_I16,
3329 ARM::ATOMIC_LOAD_ADD_I32,
3330 ARM::ATOMIC_LOAD_ADD_I64);
3331 case ISD::ATOMIC_LOAD_SUB:
3332 return SelectAtomic(N,
3333 ARM::ATOMIC_LOAD_SUB_I8,
3334 ARM::ATOMIC_LOAD_SUB_I16,
3335 ARM::ATOMIC_LOAD_SUB_I32,
3336 ARM::ATOMIC_LOAD_SUB_I64);
3337 case ISD::ATOMIC_LOAD_AND:
3338 return SelectAtomic(N,
3339 ARM::ATOMIC_LOAD_AND_I8,
3340 ARM::ATOMIC_LOAD_AND_I16,
3341 ARM::ATOMIC_LOAD_AND_I32,
3342 ARM::ATOMIC_LOAD_AND_I64);
3343 case ISD::ATOMIC_LOAD_OR:
3344 return SelectAtomic(N,
3345 ARM::ATOMIC_LOAD_OR_I8,
3346 ARM::ATOMIC_LOAD_OR_I16,
3347 ARM::ATOMIC_LOAD_OR_I32,
3348 ARM::ATOMIC_LOAD_OR_I64);
3349 case ISD::ATOMIC_LOAD_XOR:
3350 return SelectAtomic(N,
3351 ARM::ATOMIC_LOAD_XOR_I8,
3352 ARM::ATOMIC_LOAD_XOR_I16,
3353 ARM::ATOMIC_LOAD_XOR_I32,
3354 ARM::ATOMIC_LOAD_XOR_I64);
3355 case ISD::ATOMIC_LOAD_NAND:
3356 return SelectAtomic(N,
3357 ARM::ATOMIC_LOAD_NAND_I8,
3358 ARM::ATOMIC_LOAD_NAND_I16,
3359 ARM::ATOMIC_LOAD_NAND_I32,
3360 ARM::ATOMIC_LOAD_NAND_I64);
3361 case ISD::ATOMIC_LOAD_MIN:
3362 return SelectAtomic(N,
3363 ARM::ATOMIC_LOAD_MIN_I8,
3364 ARM::ATOMIC_LOAD_MIN_I16,
3365 ARM::ATOMIC_LOAD_MIN_I32,
3366 ARM::ATOMIC_LOAD_MIN_I64);
3367 case ISD::ATOMIC_LOAD_MAX:
3368 return SelectAtomic(N,
3369 ARM::ATOMIC_LOAD_MAX_I8,
3370 ARM::ATOMIC_LOAD_MAX_I16,
3371 ARM::ATOMIC_LOAD_MAX_I32,
3372 ARM::ATOMIC_LOAD_MAX_I64);
3373 case ISD::ATOMIC_LOAD_UMIN:
3374 return SelectAtomic(N,
3375 ARM::ATOMIC_LOAD_UMIN_I8,
3376 ARM::ATOMIC_LOAD_UMIN_I16,
3377 ARM::ATOMIC_LOAD_UMIN_I32,
3378 ARM::ATOMIC_LOAD_UMIN_I64);
3379 case ISD::ATOMIC_LOAD_UMAX:
3380 return SelectAtomic(N,
3381 ARM::ATOMIC_LOAD_UMAX_I8,
3382 ARM::ATOMIC_LOAD_UMAX_I16,
3383 ARM::ATOMIC_LOAD_UMAX_I32,
3384 ARM::ATOMIC_LOAD_UMAX_I64);
3385 case ISD::ATOMIC_SWAP:
3386 return SelectAtomic(N,
3387 ARM::ATOMIC_SWAP_I8,
3388 ARM::ATOMIC_SWAP_I16,
3389 ARM::ATOMIC_SWAP_I32,
3390 ARM::ATOMIC_SWAP_I64);
3391 case ISD::ATOMIC_CMP_SWAP:
3392 return SelectAtomic(N,
3393 ARM::ATOMIC_CMP_SWAP_I8,
3394 ARM::ATOMIC_CMP_SWAP_I16,
3395 ARM::ATOMIC_CMP_SWAP_I32,
3396 ARM::ATOMIC_CMP_SWAP_I64);
3399 return SelectCode(N);
3402 SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
3403 std::vector<SDValue> AsmNodeOperands;
3404 unsigned Flag, Kind;
3405 bool Changed = false;
3406 unsigned NumOps = N->getNumOperands();
3408 // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
3409 // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
3410 // (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
3411 // respectively. Since there is no constraint to explicitly specify a
3412 // reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
3413 // the 64-bit data may be referred by H, Q, R modifiers, so we still pack
3414 // them into a GPRPair.
3417 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1) : SDValue(0,0);
3419 SmallVector<bool, 8> OpChanged;
3420 // Glue node will be appended late.
3421 for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
3422 SDValue op = N->getOperand(i);
3423 AsmNodeOperands.push_back(op);
3425 if (i < InlineAsm::Op_FirstOperand)
3428 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
3429 Flag = C->getZExtValue();
3430 Kind = InlineAsm::getKind(Flag);
3435 // Immediate operands to inline asm in the SelectionDAG are modeled with
3436 // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
3437 // the second is a constant with the value of the immediate. If we get here
3438 // and we have a Kind_Imm, skip the next operand, and continue.
3439 if (Kind == InlineAsm::Kind_Imm) {
3440 SDValue op = N->getOperand(++i);
3441 AsmNodeOperands.push_back(op);
3445 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
3447 OpChanged.push_back(false);
3449 unsigned DefIdx = 0;
3450 bool IsTiedToChangedOp = false;
3451 // If it's a use that is tied with a previous def, it has no
3452 // reg class constraint.
3453 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
3454 IsTiedToChangedOp = OpChanged[DefIdx];
3456 if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
3457 && Kind != InlineAsm::Kind_RegDefEarlyClobber)
3461 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
3462 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
3466 assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
3467 SDValue V0 = N->getOperand(i+1);
3468 SDValue V1 = N->getOperand(i+2);
3469 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
3470 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
3472 MachineRegisterInfo &MRI = MF->getRegInfo();
3474 if (Kind == InlineAsm::Kind_RegDef ||
3475 Kind == InlineAsm::Kind_RegDefEarlyClobber) {
3476 // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
3477 // the original GPRs.
3479 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3480 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3481 SDValue Chain = SDValue(N,0);
3483 SDNode *GU = N->getGluedUser();
3484 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
3487 // Extract values from a GPRPair reg and copy to the original GPR reg.
3488 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
3490 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
3492 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
3493 RegCopy.getValue(1));
3494 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
3496 // Update the original glue user.
3497 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
3498 Ops.push_back(T1.getValue(1));
3499 CurDAG->UpdateNodeOperands(GU, &Ops[0], Ops.size());
3503 // For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
3504 // GPRPair and then pass the GPRPair to the inline asm.
3505 SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
3507 // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
3508 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
3510 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
3512 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
3514 // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
3515 // i32 VRs of inline asm with it.
3516 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3517 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3518 Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
3520 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
3521 Glue = Chain.getValue(1);
3526 if(PairedReg.getNode()) {
3527 OpChanged[OpChanged.size() -1 ] = true;
3528 Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
3529 if (IsTiedToChangedOp)
3530 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
3532 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
3533 // Replace the current flag.
3534 AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
3536 // Add the new register node and skip the original two GPRs.
3537 AsmNodeOperands.push_back(PairedReg);
3538 // Skip the next two GPRs.
3544 AsmNodeOperands.push_back(Glue);
3548 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
3549 CurDAG->getVTList(MVT::Other, MVT::Glue), &AsmNodeOperands[0],
3550 AsmNodeOperands.size());
3552 return New.getNode();
3556 bool ARMDAGToDAGISel::
3557 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3558 std::vector<SDValue> &OutOps) {
3559 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3560 // Require the address to be in a register. That is safe for all ARM
3561 // variants and it is hard to do anything much smarter without knowing
3562 // how the operand is used.
3563 OutOps.push_back(Op);
3567 /// createARMISelDag - This pass converts a legalized DAG into a
3568 /// ARM-specific DAG, ready for instruction scheduling.
3570 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3571 CodeGenOpt::Level OptLevel) {
3572 return new ARMDAGToDAGISel(TM, OptLevel);