1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 static const unsigned arm_dsubreg_0 = 5;
40 static const unsigned arm_dsubreg_1 = 6;
42 //===--------------------------------------------------------------------===//
43 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
44 /// instructions for SelectionDAG operations.
47 class ARMDAGToDAGISel : public SelectionDAGISel {
48 ARMBaseTargetMachine &TM;
50 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
51 /// make the right decision when generating code for different targets.
52 const ARMSubtarget *Subtarget;
55 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm)
56 : SelectionDAGISel(tm), TM(tm),
57 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
60 virtual const char *getPassName() const {
61 return "ARM Instruction Selection";
64 /// getI32Imm - Return a target constant with the specified value, of type i32.
65 inline SDValue getI32Imm(unsigned Imm) {
66 return CurDAG->getTargetConstant(Imm, EVT::i32);
69 SDNode *Select(SDValue Op);
70 virtual void InstructionSelect();
71 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
72 SDValue &B, SDValue &C);
73 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
76 SDValue &Offset, SDValue &Opc);
77 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
80 SDValue &Offset, SDValue &Opc);
81 bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
83 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
85 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
88 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
91 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
93 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
94 SDValue &Base, SDValue &OffImm,
96 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
99 SDValue &OffImm, SDValue &Offset);
100 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
101 SDValue &OffImm, SDValue &Offset);
102 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
105 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
106 SDValue &BaseReg, SDValue &Opc);
107 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
109 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
111 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
113 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
115 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
116 SDValue &OffReg, SDValue &ShImm);
118 // Include the pieces autogenerated from the target description.
119 #include "ARMGenDAGISel.inc"
122 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
124 SDNode *SelectARMIndexedLoad(SDValue Op);
125 SDNode *SelectT2IndexedLoad(SDValue Op);
127 /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
128 SDNode *SelectDYN_ALLOC(SDValue Op);
130 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
131 /// inline asm expressions.
132 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
134 std::vector<SDValue> &OutOps);
138 void ARMDAGToDAGISel::InstructionSelect() {
142 CurDAG->RemoveDeadNodes();
145 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
150 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
152 // Don't match base register only case. That is matched to a separate
153 // lower complexity pattern with explicit register operand.
154 if (ShOpcVal == ARM_AM::no_shift) return false;
156 BaseReg = N.getOperand(0);
157 unsigned ShImmVal = 0;
158 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
159 ShReg = CurDAG->getRegister(0, EVT::i32);
160 ShImmVal = RHS->getZExtValue() & 31;
162 ShReg = N.getOperand(1);
164 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
169 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
170 SDValue &Base, SDValue &Offset,
172 if (N.getOpcode() == ISD::MUL) {
173 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
174 // X * [3,5,9] -> X + X * [2,4,8] etc.
175 int RHSC = (int)RHS->getZExtValue();
178 ARM_AM::AddrOpc AddSub = ARM_AM::add;
180 AddSub = ARM_AM::sub;
183 if (isPowerOf2_32(RHSC)) {
184 unsigned ShAmt = Log2_32(RHSC);
185 Base = Offset = N.getOperand(0);
186 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
195 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
197 if (N.getOpcode() == ISD::FrameIndex) {
198 int FI = cast<FrameIndexSDNode>(N)->getIndex();
199 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
200 } else if (N.getOpcode() == ARMISD::Wrapper) {
201 Base = N.getOperand(0);
203 Offset = CurDAG->getRegister(0, EVT::i32);
204 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
210 // Match simple R +/- imm12 operands.
211 if (N.getOpcode() == ISD::ADD)
212 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
213 int RHSC = (int)RHS->getZExtValue();
214 if ((RHSC >= 0 && RHSC < 0x1000) ||
215 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
216 Base = N.getOperand(0);
217 if (Base.getOpcode() == ISD::FrameIndex) {
218 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
219 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
221 Offset = CurDAG->getRegister(0, EVT::i32);
223 ARM_AM::AddrOpc AddSub = ARM_AM::add;
225 AddSub = ARM_AM::sub;
228 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
235 // Otherwise this is R +/- [possibly shifted] R
236 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
237 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
240 Base = N.getOperand(0);
241 Offset = N.getOperand(1);
243 if (ShOpcVal != ARM_AM::no_shift) {
244 // Check to see if the RHS of the shift is a constant, if not, we can't fold
246 if (ConstantSDNode *Sh =
247 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
248 ShAmt = Sh->getZExtValue();
249 Offset = N.getOperand(1).getOperand(0);
251 ShOpcVal = ARM_AM::no_shift;
255 // Try matching (R shl C) + (R).
256 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
257 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
258 if (ShOpcVal != ARM_AM::no_shift) {
259 // Check to see if the RHS of the shift is a constant, if not, we can't
261 if (ConstantSDNode *Sh =
262 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
263 ShAmt = Sh->getZExtValue();
264 Offset = N.getOperand(0).getOperand(0);
265 Base = N.getOperand(1);
267 ShOpcVal = ARM_AM::no_shift;
272 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
277 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
278 SDValue &Offset, SDValue &Opc) {
279 unsigned Opcode = Op.getOpcode();
280 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
281 ? cast<LoadSDNode>(Op)->getAddressingMode()
282 : cast<StoreSDNode>(Op)->getAddressingMode();
283 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
284 ? ARM_AM::add : ARM_AM::sub;
285 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
286 int Val = (int)C->getZExtValue();
287 if (Val >= 0 && Val < 0x1000) { // 12 bits.
288 Offset = CurDAG->getRegister(0, EVT::i32);
289 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
297 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
299 if (ShOpcVal != ARM_AM::no_shift) {
300 // Check to see if the RHS of the shift is a constant, if not, we can't fold
302 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
303 ShAmt = Sh->getZExtValue();
304 Offset = N.getOperand(0);
306 ShOpcVal = ARM_AM::no_shift;
310 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
316 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
317 SDValue &Base, SDValue &Offset,
319 if (N.getOpcode() == ISD::SUB) {
320 // X - C is canonicalize to X + -C, no need to handle it here.
321 Base = N.getOperand(0);
322 Offset = N.getOperand(1);
323 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),EVT::i32);
327 if (N.getOpcode() != ISD::ADD) {
329 if (N.getOpcode() == ISD::FrameIndex) {
330 int FI = cast<FrameIndexSDNode>(N)->getIndex();
331 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
333 Offset = CurDAG->getRegister(0, EVT::i32);
334 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),EVT::i32);
338 // If the RHS is +/- imm8, fold into addr mode.
339 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
340 int RHSC = (int)RHS->getZExtValue();
341 if ((RHSC >= 0 && RHSC < 256) ||
342 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
343 Base = N.getOperand(0);
344 if (Base.getOpcode() == ISD::FrameIndex) {
345 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
346 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
348 Offset = CurDAG->getRegister(0, EVT::i32);
350 ARM_AM::AddrOpc AddSub = ARM_AM::add;
352 AddSub = ARM_AM::sub;
355 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),EVT::i32);
360 Base = N.getOperand(0);
361 Offset = N.getOperand(1);
362 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), EVT::i32);
366 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
367 SDValue &Offset, SDValue &Opc) {
368 unsigned Opcode = Op.getOpcode();
369 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
370 ? cast<LoadSDNode>(Op)->getAddressingMode()
371 : cast<StoreSDNode>(Op)->getAddressingMode();
372 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
373 ? ARM_AM::add : ARM_AM::sub;
374 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
375 int Val = (int)C->getZExtValue();
376 if (Val >= 0 && Val < 256) {
377 Offset = CurDAG->getRegister(0, EVT::i32);
378 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), EVT::i32);
384 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), EVT::i32);
388 bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
389 SDValue &Addr, SDValue &Mode) {
391 Mode = CurDAG->getTargetConstant(0, EVT::i32);
395 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
396 SDValue &Base, SDValue &Offset) {
397 if (N.getOpcode() != ISD::ADD) {
399 if (N.getOpcode() == ISD::FrameIndex) {
400 int FI = cast<FrameIndexSDNode>(N)->getIndex();
401 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
402 } else if (N.getOpcode() == ARMISD::Wrapper) {
403 Base = N.getOperand(0);
405 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
410 // If the RHS is +/- imm8, fold into addr mode.
411 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
412 int RHSC = (int)RHS->getZExtValue();
413 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
415 if ((RHSC >= 0 && RHSC < 256) ||
416 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
417 Base = N.getOperand(0);
418 if (Base.getOpcode() == ISD::FrameIndex) {
419 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
420 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
423 ARM_AM::AddrOpc AddSub = ARM_AM::add;
425 AddSub = ARM_AM::sub;
428 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
436 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
441 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
442 SDValue &Addr, SDValue &Update,
445 // The optional writeback is handled in ARMLoadStoreOpt.
446 Update = CurDAG->getRegister(0, EVT::i32);
447 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), EVT::i32);
451 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
452 SDValue &Offset, SDValue &Label) {
453 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
454 Offset = N.getOperand(0);
455 SDValue N1 = N.getOperand(1);
456 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
463 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
464 SDValue &Base, SDValue &Offset){
465 // FIXME dl should come from the parent load or store, not the address
466 DebugLoc dl = Op.getDebugLoc();
467 if (N.getOpcode() != ISD::ADD) {
468 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
469 if (!NC || NC->getZExtValue() != 0)
476 Base = N.getOperand(0);
477 Offset = N.getOperand(1);
482 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
483 unsigned Scale, SDValue &Base,
484 SDValue &OffImm, SDValue &Offset) {
486 SDValue TmpBase, TmpOffImm;
487 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
488 return false; // We want to select tLDRspi / tSTRspi instead.
489 if (N.getOpcode() == ARMISD::Wrapper &&
490 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
491 return false; // We want to select tLDRpci instead.
494 if (N.getOpcode() != ISD::ADD) {
495 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
496 Offset = CurDAG->getRegister(0, EVT::i32);
497 OffImm = CurDAG->getTargetConstant(0, EVT::i32);
501 // Thumb does not have [sp, r] address mode.
502 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
503 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
504 if ((LHSR && LHSR->getReg() == ARM::SP) ||
505 (RHSR && RHSR->getReg() == ARM::SP)) {
507 Offset = CurDAG->getRegister(0, EVT::i32);
508 OffImm = CurDAG->getTargetConstant(0, EVT::i32);
512 // If the RHS is + imm5 * scale, fold into addr mode.
513 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
514 int RHSC = (int)RHS->getZExtValue();
515 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
517 if (RHSC >= 0 && RHSC < 32) {
518 Base = N.getOperand(0);
519 Offset = CurDAG->getRegister(0, EVT::i32);
520 OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
526 Base = N.getOperand(0);
527 Offset = N.getOperand(1);
528 OffImm = CurDAG->getTargetConstant(0, EVT::i32);
532 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
533 SDValue &Base, SDValue &OffImm,
535 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
538 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
539 SDValue &Base, SDValue &OffImm,
541 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
544 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
545 SDValue &Base, SDValue &OffImm,
547 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
550 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
551 SDValue &Base, SDValue &OffImm) {
552 if (N.getOpcode() == ISD::FrameIndex) {
553 int FI = cast<FrameIndexSDNode>(N)->getIndex();
554 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
555 OffImm = CurDAG->getTargetConstant(0, EVT::i32);
559 if (N.getOpcode() != ISD::ADD)
562 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
563 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
564 (LHSR && LHSR->getReg() == ARM::SP)) {
565 // If the RHS is + imm8 * scale, fold into addr mode.
566 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
567 int RHSC = (int)RHS->getZExtValue();
568 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
570 if (RHSC >= 0 && RHSC < 256) {
571 Base = N.getOperand(0);
572 if (Base.getOpcode() == ISD::FrameIndex) {
573 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
574 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
576 OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
586 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
589 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
591 // Don't match base register only case. That is matched to a separate
592 // lower complexity pattern with explicit register operand.
593 if (ShOpcVal == ARM_AM::no_shift) return false;
595 BaseReg = N.getOperand(0);
596 unsigned ShImmVal = 0;
597 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
598 ShImmVal = RHS->getZExtValue() & 31;
599 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
606 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
607 SDValue &Base, SDValue &OffImm) {
608 // Match simple R + imm12 operands.
610 // Match frame index...
611 if ((N.getOpcode() != ISD::ADD) && (N.getOpcode() != ISD::SUB)) {
612 if (N.getOpcode() == ISD::FrameIndex) {
613 int FI = cast<FrameIndexSDNode>(N)->getIndex();
614 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
615 OffImm = CurDAG->getTargetConstant(0, EVT::i32);
621 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
622 int RHSC = (int)RHS->getZExtValue();
623 if (N.getOpcode() == ISD::SUB)
626 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
627 Base = N.getOperand(0);
628 if (Base.getOpcode() == ISD::FrameIndex) {
629 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
630 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
632 OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
640 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
641 SDValue &Base, SDValue &OffImm) {
642 // Match simple R - imm8 operands.
643 if ((N.getOpcode() == ISD::ADD) || (N.getOpcode() == ISD::SUB)) {
644 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
645 int RHSC = (int)RHS->getSExtValue();
646 if (N.getOpcode() == ISD::SUB)
649 if ((RHSC >= -255) && (RHSC <= 0)) { // 8 bits (always negative)
650 Base = N.getOperand(0);
651 if (Base.getOpcode() == ISD::FrameIndex) {
652 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
653 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
655 OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
664 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
666 unsigned Opcode = Op.getOpcode();
667 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
668 ? cast<LoadSDNode>(Op)->getAddressingMode()
669 : cast<StoreSDNode>(Op)->getAddressingMode();
670 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
671 int RHSC = (int)RHS->getZExtValue();
672 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
673 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
674 ? CurDAG->getTargetConstant(RHSC, EVT::i32)
675 : CurDAG->getTargetConstant(-RHSC, EVT::i32);
683 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
684 SDValue &Base, SDValue &OffImm) {
685 if (N.getOpcode() == ISD::ADD) {
686 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
687 int RHSC = (int)RHS->getZExtValue();
688 if (((RHSC & 0x3) == 0) &&
689 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
690 Base = N.getOperand(0);
691 OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
695 } else if (N.getOpcode() == ISD::SUB) {
696 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
697 int RHSC = (int)RHS->getZExtValue();
698 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
699 Base = N.getOperand(0);
700 OffImm = CurDAG->getTargetConstant(-RHSC, EVT::i32);
709 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
711 SDValue &OffReg, SDValue &ShImm) {
713 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
715 if (N.getOpcode() == ISD::FrameIndex) {
716 return false; // we want to select t2LDRri12 instead
717 } else if (N.getOpcode() == ARMISD::Wrapper) {
718 Base = N.getOperand(0);
719 if (Base.getOpcode() == ISD::TargetConstantPool)
720 return false; // We want to select t2LDRpci instead.
722 OffReg = CurDAG->getRegister(0, EVT::i32);
723 ShImm = CurDAG->getTargetConstant(0, EVT::i32);
727 // Leave (R +/- imm) for other address modes... unless they can't
729 if (dyn_cast<ConstantSDNode>(N.getOperand(1)) != NULL) {
731 if (SelectT2AddrModeImm12(Op, N, Base, OffImm) ||
732 SelectT2AddrModeImm8 (Op, N, Base, OffImm))
736 // Thumb2 does not support (R - R) or (R - (R << [1,2,3])).
737 if (N.getOpcode() == ISD::SUB) {
739 OffReg = CurDAG->getRegister(0, EVT::i32);
740 ShImm = CurDAG->getTargetConstant(0, EVT::i32);
744 assert(N.getOpcode() == ISD::ADD);
746 // Look for (R + R) or (R + (R << [1,2,3])).
748 Base = N.getOperand(0);
749 OffReg = N.getOperand(1);
751 // Swap if it is ((R << c) + R).
752 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
753 if (ShOpcVal != ARM_AM::lsl) {
754 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
755 if (ShOpcVal == ARM_AM::lsl)
756 std::swap(Base, OffReg);
759 if (ShOpcVal == ARM_AM::lsl) {
760 // Check to see if the RHS of the shift is a constant, if not, we can't fold
762 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
763 ShAmt = Sh->getZExtValue();
766 ShOpcVal = ARM_AM::no_shift;
768 OffReg = OffReg.getOperand(0);
770 ShOpcVal = ARM_AM::no_shift;
774 ShImm = CurDAG->getTargetConstant(ShAmt, EVT::i32);
779 //===--------------------------------------------------------------------===//
781 /// getAL - Returns a ARMCC::AL immediate node.
782 static inline SDValue getAL(SelectionDAG *CurDAG) {
783 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, EVT::i32);
786 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
787 LoadSDNode *LD = cast<LoadSDNode>(Op);
788 ISD::MemIndexedMode AM = LD->getAddressingMode();
789 if (AM == ISD::UNINDEXED)
792 EVT LoadedVT = LD->getMemoryVT();
793 SDValue Offset, AMOpc;
794 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
797 if (LoadedVT == EVT::i32 &&
798 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
799 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
801 } else if (LoadedVT == EVT::i16 &&
802 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
804 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
805 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
806 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
807 } else if (LoadedVT == EVT::i8 || LoadedVT == EVT::i1) {
808 if (LD->getExtensionType() == ISD::SEXTLOAD) {
809 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
811 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
814 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
816 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
822 SDValue Chain = LD->getChain();
823 SDValue Base = LD->getBasePtr();
824 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
825 CurDAG->getRegister(0, EVT::i32), Chain };
826 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), EVT::i32, EVT::i32,
833 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
834 LoadSDNode *LD = cast<LoadSDNode>(Op);
835 ISD::MemIndexedMode AM = LD->getAddressingMode();
836 if (AM == ISD::UNINDEXED)
839 EVT LoadedVT = LD->getMemoryVT();
840 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
842 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
845 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
846 switch (LoadedVT.getSimpleVT()) {
848 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
852 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
854 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
859 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
861 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
870 SDValue Chain = LD->getChain();
871 SDValue Base = LD->getBasePtr();
872 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
873 CurDAG->getRegister(0, EVT::i32), Chain };
874 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), EVT::i32, EVT::i32,
881 SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
882 SDNode *N = Op.getNode();
883 DebugLoc dl = N->getDebugLoc();
884 EVT VT = Op.getValueType();
885 SDValue Chain = Op.getOperand(0);
886 SDValue Size = Op.getOperand(1);
887 SDValue Align = Op.getOperand(2);
888 SDValue SP = CurDAG->getRegister(ARM::SP, EVT::i32);
889 int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
891 // We need to align the stack. Use Thumb1 tAND which is the only thumb
892 // instruction that can read and write SP. This matches to a pseudo
893 // instruction that has a chain to ensure the result is written back to
894 // the stack pointer.
895 SP = SDValue(CurDAG->getTargetNode(ARM::tANDsp, dl, VT, SP, Align), 0);
897 bool isC = isa<ConstantSDNode>(Size);
898 uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
899 // Handle the most common case for both Thumb1 and Thumb2:
900 // tSUBspi - immediate is between 0 ... 508 inclusive.
901 if (C <= 508 && ((C & 3) == 0))
902 // FIXME: tSUBspi encode scale 4 implicitly.
903 return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, EVT::Other, SP,
904 CurDAG->getTargetConstant(C/4, EVT::i32),
907 if (Subtarget->isThumb1Only()) {
908 // Use tADDrSPr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
909 // should have negated the size operand already. FIXME: We can't insert
910 // new target independent node at this stage so we are forced to negate
911 // it earlier. Is there a better solution?
912 return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, EVT::Other, SP, Size,
914 } else if (Subtarget->isThumb2()) {
915 if (isC && Predicate_t2_so_imm(Size.getNode())) {
917 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, EVT::i32), Chain };
918 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, EVT::Other, Ops, 3);
919 } else if (isC && Predicate_imm0_4095(Size.getNode())) {
921 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, EVT::i32), Chain };
922 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, EVT::Other, Ops, 3);
925 SDValue Ops[] = { SP, Size,
926 getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
927 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, EVT::Other, Ops, 4);
931 // FIXME: Add ADD / SUB sp instructions for ARM.
935 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
936 SDNode *N = Op.getNode();
937 DebugLoc dl = N->getDebugLoc();
939 if (N->isMachineOpcode())
940 return NULL; // Already selected.
942 switch (N->getOpcode()) {
944 case ISD::Constant: {
945 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
947 if (Subtarget->isThumb()) {
948 if (Subtarget->hasThumb2())
949 // Thumb2 has the MOVT instruction, so all immediates can
950 // be done with MOV + MOVT, at worst.
953 UseCP = (Val > 255 && // MOV
954 ~Val > 255 && // MOV + MVN
955 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
957 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
958 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
959 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
962 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
966 if (Subtarget->isThumb1Only()) {
967 SDValue Pred = CurDAG->getTargetConstant(0xEULL, EVT::i32);
968 SDValue PredReg = CurDAG->getRegister(0, EVT::i32);
969 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
970 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, EVT::i32, EVT::Other,
975 CurDAG->getRegister(0, EVT::i32),
976 CurDAG->getTargetConstant(0, EVT::i32),
978 CurDAG->getRegister(0, EVT::i32),
979 CurDAG->getEntryNode()
981 ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, EVT::i32, EVT::Other,
984 ReplaceUses(Op, SDValue(ResNode, 0));
988 // Other cases are autogenerated.
991 case ISD::FrameIndex: {
992 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
993 int FI = cast<FrameIndexSDNode>(N)->getIndex();
994 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
995 if (Subtarget->isThumb1Only()) {
996 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, EVT::i32, TFI,
997 CurDAG->getTargetConstant(0, EVT::i32));
999 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1000 ARM::t2ADDri : ARM::ADDri);
1001 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, EVT::i32),
1002 getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
1003 CurDAG->getRegister(0, EVT::i32) };
1004 return CurDAG->SelectNodeTo(N, Opc, EVT::i32, Ops, 5);
1007 case ARMISD::DYN_ALLOC:
1008 return SelectDYN_ALLOC(Op);
1010 if (Subtarget->isThumb1Only())
1012 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1013 unsigned RHSV = C->getZExtValue();
1015 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1016 unsigned ShImm = Log2_32(RHSV-1);
1019 SDValue V = Op.getOperand(0);
1020 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1021 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, EVT::i32);
1022 SDValue Reg0 = CurDAG->getRegister(0, EVT::i32);
1023 if (Subtarget->isThumb()) {
1024 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1025 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, EVT::i32, Ops, 6);
1027 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1028 return CurDAG->SelectNodeTo(N, ARM::ADDrs, EVT::i32, Ops, 7);
1031 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1032 unsigned ShImm = Log2_32(RHSV+1);
1035 SDValue V = Op.getOperand(0);
1036 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1037 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, EVT::i32);
1038 SDValue Reg0 = CurDAG->getRegister(0, EVT::i32);
1039 if (Subtarget->isThumb()) {
1040 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1041 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, EVT::i32, Ops, 5);
1043 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1044 return CurDAG->SelectNodeTo(N, ARM::RSBrs, EVT::i32, Ops, 7);
1050 return CurDAG->getTargetNode(ARM::FMRRD, dl, EVT::i32, EVT::i32,
1051 Op.getOperand(0), getAL(CurDAG),
1052 CurDAG->getRegister(0, EVT::i32));
1053 case ISD::UMUL_LOHI: {
1054 if (Subtarget->isThumb1Only())
1056 if (Subtarget->isThumb()) {
1057 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1058 getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
1059 CurDAG->getRegister(0, EVT::i32) };
1060 return CurDAG->getTargetNode(ARM::t2UMULL, dl, EVT::i32, EVT::i32, Ops,4);
1062 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1063 getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
1064 CurDAG->getRegister(0, EVT::i32) };
1065 return CurDAG->getTargetNode(ARM::UMULL, dl, EVT::i32, EVT::i32, Ops, 5);
1068 case ISD::SMUL_LOHI: {
1069 if (Subtarget->isThumb1Only())
1071 if (Subtarget->isThumb()) {
1072 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1073 getAL(CurDAG), CurDAG->getRegister(0, EVT::i32) };
1074 return CurDAG->getTargetNode(ARM::t2SMULL, dl, EVT::i32, EVT::i32, Ops,4);
1076 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1077 getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
1078 CurDAG->getRegister(0, EVT::i32) };
1079 return CurDAG->getTargetNode(ARM::SMULL, dl, EVT::i32, EVT::i32, Ops, 5);
1083 SDNode *ResNode = 0;
1084 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1085 ResNode = SelectT2IndexedLoad(Op);
1087 ResNode = SelectARMIndexedLoad(Op);
1090 // Other cases are autogenerated.
1093 case ARMISD::BRCOND: {
1094 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1095 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1096 // Pattern complexity = 6 cost = 1 size = 0
1098 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1099 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1100 // Pattern complexity = 6 cost = 1 size = 0
1102 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1103 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1104 // Pattern complexity = 6 cost = 1 size = 0
1106 unsigned Opc = Subtarget->isThumb() ?
1107 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1108 SDValue Chain = Op.getOperand(0);
1109 SDValue N1 = Op.getOperand(1);
1110 SDValue N2 = Op.getOperand(2);
1111 SDValue N3 = Op.getOperand(3);
1112 SDValue InFlag = Op.getOperand(4);
1113 assert(N1.getOpcode() == ISD::BasicBlock);
1114 assert(N2.getOpcode() == ISD::Constant);
1115 assert(N3.getOpcode() == ISD::Register);
1117 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1118 cast<ConstantSDNode>(N2)->getZExtValue()),
1120 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1121 SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, EVT::Other,
1123 Chain = SDValue(ResNode, 0);
1124 if (Op.getNode()->getNumValues() == 2) {
1125 InFlag = SDValue(ResNode, 1);
1126 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1128 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
1131 case ARMISD::CMOV: {
1132 EVT VT = Op.getValueType();
1133 SDValue N0 = Op.getOperand(0);
1134 SDValue N1 = Op.getOperand(1);
1135 SDValue N2 = Op.getOperand(2);
1136 SDValue N3 = Op.getOperand(3);
1137 SDValue InFlag = Op.getOperand(4);
1138 assert(N2.getOpcode() == ISD::Constant);
1139 assert(N3.getOpcode() == ISD::Register);
1141 if (!Subtarget->isThumb1Only() && VT == EVT::i32) {
1142 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1143 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1144 // Pattern complexity = 18 cost = 1 size = 0
1148 if (Subtarget->isThumb()) {
1149 if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1150 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1151 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1154 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1155 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1156 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1157 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1159 llvm_unreachable("Unknown so_reg opcode!");
1163 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), EVT::i32);
1164 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1165 cast<ConstantSDNode>(N2)->getZExtValue()),
1167 SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
1168 return CurDAG->SelectNodeTo(Op.getNode(), Opc, EVT::i32,Ops, 6);
1171 if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1172 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1173 cast<ConstantSDNode>(N2)->getZExtValue()),
1175 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1176 return CurDAG->SelectNodeTo(Op.getNode(),
1177 ARM::MOVCCs, EVT::i32, Ops, 7);
1181 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1182 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1184 // Emits: (MOVCCi:i32 GPR:i32:$false,
1185 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1186 // Pattern complexity = 10 cost = 1 size = 0
1187 if (N3.getOpcode() == ISD::Constant) {
1188 if (Subtarget->isThumb()) {
1189 if (Predicate_t2_so_imm(N3.getNode())) {
1190 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1191 cast<ConstantSDNode>(N1)->getZExtValue()),
1193 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1194 cast<ConstantSDNode>(N2)->getZExtValue()),
1196 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1197 return CurDAG->SelectNodeTo(Op.getNode(),
1198 ARM::t2MOVCCi, EVT::i32, Ops, 5);
1201 if (Predicate_so_imm(N3.getNode())) {
1202 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1203 cast<ConstantSDNode>(N1)->getZExtValue()),
1205 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1206 cast<ConstantSDNode>(N2)->getZExtValue()),
1208 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1209 return CurDAG->SelectNodeTo(Op.getNode(),
1210 ARM::MOVCCi, EVT::i32, Ops, 5);
1216 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1217 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1218 // Pattern complexity = 6 cost = 1 size = 0
1220 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1221 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1222 // Pattern complexity = 6 cost = 11 size = 0
1224 // Also FCPYScc and FCPYDcc.
1225 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1226 cast<ConstantSDNode>(N2)->getZExtValue()),
1228 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1230 switch (VT.getSimpleVT()) {
1231 default: assert(false && "Illegal conditional move type!");
1234 Opc = Subtarget->isThumb()
1235 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr)
1245 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1247 case ARMISD::CNEG: {
1248 EVT VT = Op.getValueType();
1249 SDValue N0 = Op.getOperand(0);
1250 SDValue N1 = Op.getOperand(1);
1251 SDValue N2 = Op.getOperand(2);
1252 SDValue N3 = Op.getOperand(3);
1253 SDValue InFlag = Op.getOperand(4);
1254 assert(N2.getOpcode() == ISD::Constant);
1255 assert(N3.getOpcode() == ISD::Register);
1257 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1258 cast<ConstantSDNode>(N2)->getZExtValue()),
1260 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1262 switch (VT.getSimpleVT()) {
1263 default: assert(false && "Illegal conditional move type!");
1272 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1275 case ISD::DECLARE: {
1276 SDValue Chain = Op.getOperand(0);
1277 SDValue N1 = Op.getOperand(1);
1278 SDValue N2 = Op.getOperand(2);
1279 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
1280 // FIXME: handle VLAs.
1282 ReplaceUses(Op.getValue(0), Chain);
1285 if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0)))
1286 N2 = N2.getOperand(0);
1287 LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2);
1289 ReplaceUses(Op.getValue(0), Chain);
1292 SDValue BasePtr = Ld->getBasePtr();
1293 assert(BasePtr.getOpcode() == ARMISD::Wrapper &&
1294 isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) &&
1295 "llvm.dbg.variable should be a constantpool node");
1296 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0));
1297 GlobalValue *GV = 0;
1298 if (CP->isMachineConstantPoolEntry()) {
1299 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal();
1302 GV = dyn_cast<GlobalValue>(CP->getConstVal());
1304 ReplaceUses(Op.getValue(0), Chain);
1308 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
1309 TLI.getPointerTy());
1310 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
1311 SDValue Ops[] = { Tmp1, Tmp2, Chain };
1312 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
1313 EVT::Other, Ops, 3);
1316 case ISD::VECTOR_SHUFFLE: {
1317 EVT VT = Op.getValueType();
1319 // Match 128-bit splat to VDUPLANEQ. (This could be done with a Pat in
1320 // ARMInstrNEON.td but it is awkward because the shuffle mask needs to be
1321 // transformed first into a lane number and then to both a subregister
1322 // index and an adjusted lane number.) If the source operand is a
1323 // SCALAR_TO_VECTOR, leave it so it will be matched later as a VDUP.
1324 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1325 if (VT.is128BitVector() && SVOp->isSplat() &&
1326 Op.getOperand(0).getOpcode() != ISD::SCALAR_TO_VECTOR &&
1327 Op.getOperand(1).getOpcode() == ISD::UNDEF) {
1328 unsigned LaneVal = SVOp->getSplatIndex();
1332 switch (VT.getVectorElementType().getSimpleVT()) {
1333 default: llvm_unreachable("unhandled VDUP splat type");
1334 case EVT::i8: Opc = ARM::VDUPLN8q; HalfVT = EVT::v8i8; break;
1335 case EVT::i16: Opc = ARM::VDUPLN16q; HalfVT = EVT::v4i16; break;
1336 case EVT::i32: Opc = ARM::VDUPLN32q; HalfVT = EVT::v2i32; break;
1337 case EVT::f32: Opc = ARM::VDUPLNfq; HalfVT = EVT::v2f32; break;
1340 // The source operand needs to be changed to a subreg of the original
1341 // 128-bit operand, and the lane number needs to be adjusted accordingly.
1342 unsigned NumElts = VT.getVectorNumElements() / 2;
1343 unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
1344 SDValue SR = CurDAG->getTargetConstant(SRVal, EVT::i32);
1345 SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, EVT::i32);
1346 SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
1347 dl, HalfVT, N->getOperand(0), SR);
1348 return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
1354 case ARMISD::VLD2D: {
1355 SDValue MemAddr, MemUpdate, MemOpc;
1356 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1359 EVT VT = Op.getValueType();
1360 switch (VT.getSimpleVT()) {
1361 default: llvm_unreachable("unhandled VLD2D type");
1362 case EVT::v8i8: Opc = ARM::VLD2d8; break;
1363 case EVT::v4i16: Opc = ARM::VLD2d16; break;
1365 case EVT::v2i32: Opc = ARM::VLD2d32; break;
1367 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
1368 return CurDAG->getTargetNode(Opc, dl, VT, VT, EVT::Other, Ops, 3);
1371 case ARMISD::VLD3D: {
1372 SDValue MemAddr, MemUpdate, MemOpc;
1373 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1376 EVT VT = Op.getValueType();
1377 switch (VT.getSimpleVT()) {
1378 default: llvm_unreachable("unhandled VLD3D type");
1379 case EVT::v8i8: Opc = ARM::VLD3d8; break;
1380 case EVT::v4i16: Opc = ARM::VLD3d16; break;
1382 case EVT::v2i32: Opc = ARM::VLD3d32; break;
1384 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
1385 return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, EVT::Other, Ops, 3);
1388 case ARMISD::VLD4D: {
1389 SDValue MemAddr, MemUpdate, MemOpc;
1390 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1393 EVT VT = Op.getValueType();
1394 switch (VT.getSimpleVT()) {
1395 default: llvm_unreachable("unhandled VLD4D type");
1396 case EVT::v8i8: Opc = ARM::VLD4d8; break;
1397 case EVT::v4i16: Opc = ARM::VLD4d16; break;
1399 case EVT::v2i32: Opc = ARM::VLD4d32; break;
1401 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
1402 std::vector<EVT> ResTys(4, VT);
1403 ResTys.push_back(EVT::Other);
1404 return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3);
1407 case ARMISD::VST2D: {
1408 SDValue MemAddr, MemUpdate, MemOpc;
1409 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1412 switch (N->getOperand(2).getValueType().getSimpleVT()) {
1413 default: llvm_unreachable("unhandled VST2D type");
1414 case EVT::v8i8: Opc = ARM::VST2d8; break;
1415 case EVT::v4i16: Opc = ARM::VST2d16; break;
1417 case EVT::v2i32: Opc = ARM::VST2d32; break;
1419 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1420 N->getOperand(2), N->getOperand(3) };
1421 return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 5);
1424 case ARMISD::VST3D: {
1425 SDValue MemAddr, MemUpdate, MemOpc;
1426 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1429 switch (N->getOperand(2).getValueType().getSimpleVT()) {
1430 default: llvm_unreachable("unhandled VST3D type");
1431 case EVT::v8i8: Opc = ARM::VST3d8; break;
1432 case EVT::v4i16: Opc = ARM::VST3d16; break;
1434 case EVT::v2i32: Opc = ARM::VST3d32; break;
1436 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1437 N->getOperand(2), N->getOperand(3),
1439 return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 6);
1442 case ARMISD::VST4D: {
1443 SDValue MemAddr, MemUpdate, MemOpc;
1444 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1447 switch (N->getOperand(2).getValueType().getSimpleVT()) {
1448 default: llvm_unreachable("unhandled VST4D type");
1449 case EVT::v8i8: Opc = ARM::VST4d8; break;
1450 case EVT::v4i16: Opc = ARM::VST4d16; break;
1452 case EVT::v2i32: Opc = ARM::VST4d32; break;
1454 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1455 N->getOperand(2), N->getOperand(3),
1456 N->getOperand(4), N->getOperand(5) };
1457 return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 7);
1460 case ISD::INTRINSIC_WO_CHAIN: {
1461 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
1462 EVT VT = N->getValueType(0);
1465 // Match intrinsics that return multiple values.
1469 case Intrinsic::arm_neon_vtrni:
1470 case Intrinsic::arm_neon_vtrnf:
1471 switch (VT.getSimpleVT()) {
1472 default: return NULL;
1473 case EVT::v8i8: Opc = ARM::VTRNd8; break;
1474 case EVT::v4i16: Opc = ARM::VTRNd16; break;
1476 case EVT::v2i32: Opc = ARM::VTRNd32; break;
1477 case EVT::v16i8: Opc = ARM::VTRNq8; break;
1478 case EVT::v8i16: Opc = ARM::VTRNq16; break;
1480 case EVT::v4i32: Opc = ARM::VTRNq32; break;
1482 return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
1485 case Intrinsic::arm_neon_vuzpi:
1486 case Intrinsic::arm_neon_vuzpf:
1487 switch (VT.getSimpleVT()) {
1488 default: return NULL;
1489 case EVT::v8i8: Opc = ARM::VUZPd8; break;
1490 case EVT::v4i16: Opc = ARM::VUZPd16; break;
1492 case EVT::v2i32: Opc = ARM::VUZPd32; break;
1493 case EVT::v16i8: Opc = ARM::VUZPq8; break;
1494 case EVT::v8i16: Opc = ARM::VUZPq16; break;
1496 case EVT::v4i32: Opc = ARM::VUZPq32; break;
1498 return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
1501 case Intrinsic::arm_neon_vzipi:
1502 case Intrinsic::arm_neon_vzipf:
1503 switch (VT.getSimpleVT()) {
1504 default: return NULL;
1505 case EVT::v8i8: Opc = ARM::VZIPd8; break;
1506 case EVT::v4i16: Opc = ARM::VZIPd16; break;
1508 case EVT::v2i32: Opc = ARM::VZIPd32; break;
1509 case EVT::v16i8: Opc = ARM::VZIPq8; break;
1510 case EVT::v8i16: Opc = ARM::VZIPq16; break;
1512 case EVT::v4i32: Opc = ARM::VZIPq32; break;
1514 return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
1521 return SelectCode(Op);
1524 bool ARMDAGToDAGISel::
1525 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1526 std::vector<SDValue> &OutOps) {
1527 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1529 SDValue Base, Offset, Opc;
1530 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
1533 OutOps.push_back(Base);
1534 OutOps.push_back(Offset);
1535 OutOps.push_back(Opc);
1539 /// createARMISelDag - This pass converts a legalized DAG into a
1540 /// ARM-specific DAG, ready for instruction scheduling.
1542 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM) {
1543 return new ARMDAGToDAGISel(TM);