1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMTargetMachine.h"
16 #include "llvm/CallingConv.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Intrinsics.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/Debug.h"
34 class ARMTargetLowering : public TargetLowering {
35 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
37 ARMTargetLowering(TargetMachine &TM);
38 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
39 virtual const char *getTargetNodeName(unsigned Opcode) const;
44 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
45 : TargetLowering(TM) {
46 addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass);
47 addRegisterClass(MVT::f32, ARM::FPRegsRegisterClass);
48 addRegisterClass(MVT::f64, ARM::DFPRegsRegisterClass);
50 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
52 setOperationAction(ISD::RET, MVT::Other, Custom);
53 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
54 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
56 setOperationAction(ISD::SETCC, MVT::i32, Expand);
57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
58 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
60 setOperationAction(ISD::VASTART, MVT::Other, Custom);
61 setOperationAction(ISD::VAEND, MVT::Other, Expand);
63 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
64 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
66 setSchedulingPreference(SchedulingForRegPressure);
67 computeRegisterProperties();
73 // Start the numbering where the builting ops and target ops leave off.
74 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
75 /// CALL - A direct function call.
78 /// Return with a flag operand.
98 /// DAGCCToARMCC - Convert a DAG integer condition code to an ARM CC
99 static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) {
102 std::cerr << "CC = " << CC << "\n";
103 assert(0 && "Unknown condition code!");
104 case ISD::SETUGT: return ARMCC::HI;
105 case ISD::SETULE: return ARMCC::LS;
106 case ISD::SETLE: return ARMCC::LE;
107 case ISD::SETLT: return ARMCC::LT;
108 case ISD::SETGT: return ARMCC::GT;
109 case ISD::SETNE: return ARMCC::NE;
110 case ISD::SETEQ: return ARMCC::EQ;
111 case ISD::SETGE: return ARMCC::GE;
112 case ISD::SETUGE: return ARMCC::CS;
113 case ISD::SETULT: return ARMCC::CC;
117 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
120 case ARMISD::CALL: return "ARMISD::CALL";
121 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
122 case ARMISD::SELECT: return "ARMISD::SELECT";
123 case ARMISD::CMP: return "ARMISD::CMP";
124 case ARMISD::BR: return "ARMISD::BR";
125 case ARMISD::FSITOS: return "ARMISD::FSITOS";
126 case ARMISD::FSITOD: return "ARMISD::FSITOD";
127 case ARMISD::FMRRD: return "ARMISD::FMRRD";
128 case ARMISD::FMDRR: return "ARMISD::FMDRR";
132 class ArgumentLayout {
133 std::vector<bool> is_reg;
134 std::vector<unsigned> pos;
135 std::vector<MVT::ValueType> types;
137 ArgumentLayout(const std::vector<MVT::ValueType> &Types) {
141 unsigned StackOffset = 0;
142 for(std::vector<MVT::ValueType>::const_iterator I = Types.begin();
145 MVT::ValueType VT = *I;
146 assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
147 unsigned size = MVT::getSizeInBits(VT)/32;
149 RegNum = ((RegNum + size - 1) / size) * size;
151 pos.push_back(RegNum);
152 is_reg.push_back(true);
155 unsigned bytes = size * 32/8;
156 StackOffset = ((StackOffset + bytes - 1) / bytes) * bytes;
157 pos.push_back(StackOffset);
158 is_reg.push_back(false);
159 StackOffset += bytes;
163 unsigned getRegisterNum(unsigned argNum) {
164 assert(isRegister(argNum));
167 unsigned getOffset(unsigned argNum) {
168 assert(isOffset(argNum));
171 unsigned isRegister(unsigned argNum) {
172 assert(argNum < is_reg.size());
173 return is_reg[argNum];
175 unsigned isOffset(unsigned argNum) {
176 return !isRegister(argNum);
178 MVT::ValueType getType(unsigned argNum) {
179 assert(argNum < types.size());
180 return types[argNum];
182 unsigned getStackSize(void) {
183 int last = is_reg.size() - 1;
184 if (isRegister(last))
186 return getOffset(last) + MVT::getSizeInBits(getType(last))/8;
188 int lastRegArg(void) {
189 int size = is_reg.size();
191 while(last < size && isRegister(last))
196 unsigned lastRegNum(void) {
197 int l = lastRegArg();
200 unsigned r = getRegisterNum(l);
201 MVT::ValueType t = getType(l);
202 assert(t == MVT::i32 || t == MVT::f32 || t == MVT::f64);
209 // This transforms a ISD::CALL node into a
210 // callseq_star <- ARMISD:CALL <- callseq_end
212 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
213 SDOperand Chain = Op.getOperand(0);
214 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
215 assert(CallConv == CallingConv::C && "unknown calling convention");
216 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
217 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
218 assert(isTailCall == false && "tail call not supported");
219 SDOperand Callee = Op.getOperand(4);
220 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
221 SDOperand StackPtr = DAG.getRegister(ARM::R13, MVT::i32);
222 static const unsigned regs[] = {
223 ARM::R0, ARM::R1, ARM::R2, ARM::R3
226 std::vector<MVT::ValueType> Types;
227 for (unsigned i = 0; i < NumOps; ++i) {
228 MVT::ValueType VT = Op.getOperand(5+2*i).getValueType();
231 ArgumentLayout Layout(Types);
233 unsigned NumBytes = Layout.getStackSize();
235 Chain = DAG.getCALLSEQ_START(Chain,
236 DAG.getConstant(NumBytes, MVT::i32));
238 //Build a sequence of stores
239 std::vector<SDOperand> MemOpChains;
240 for (unsigned i = Layout.lastRegArg() + 1; i < NumOps; ++i) {
241 SDOperand Arg = Op.getOperand(5+2*i);
242 unsigned ArgOffset = Layout.getOffset(i);
243 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
244 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
245 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
246 DAG.getSrcValue(NULL)));
248 if (!MemOpChains.empty())
249 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
250 &MemOpChains[0], MemOpChains.size());
252 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
253 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
254 // node so that legalize doesn't hack it.
255 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
256 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
258 // If this is a direct call, pass the chain and the callee.
260 std::vector<SDOperand> Ops;
261 Ops.push_back(Chain);
262 Ops.push_back(Callee);
264 // Build a sequence of copy-to-reg nodes chained together with token chain
265 // and flag operands which copy the outgoing args into the appropriate regs.
267 for (unsigned i = 0, e = Layout.lastRegArg(); i <= e; ++i) {
268 SDOperand Arg = Op.getOperand(5+2*i);
269 unsigned RegNum = Layout.getRegisterNum(i);
270 unsigned Reg1 = regs[RegNum];
271 MVT::ValueType VT = Layout.getType(i);
272 assert(VT == Arg.getValueType());
273 assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
275 // Add argument register to the end of the list so that it is known live
277 Ops.push_back(DAG.getRegister(Reg1, MVT::i32));
278 if (VT == MVT::f64) {
279 unsigned Reg2 = regs[RegNum + 1];
280 SDOperand SDReg1 = DAG.getRegister(Reg1, MVT::i32);
281 SDOperand SDReg2 = DAG.getRegister(Reg2, MVT::i32);
283 Ops.push_back(DAG.getRegister(Reg2, MVT::i32));
284 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
285 SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg}; //missing flag
286 Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4);
289 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg);
290 Chain = DAG.getCopyToReg(Chain, Reg1, Arg, InFlag);
292 InFlag = Chain.getValue(1);
295 std::vector<MVT::ValueType> NodeTys;
296 NodeTys.push_back(MVT::Other); // Returns a chain
297 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
299 unsigned CallOpc = ARMISD::CALL;
301 Ops.push_back(InFlag);
302 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
303 InFlag = Chain.getValue(1);
305 std::vector<SDOperand> ResultVals;
308 // If the call has results, copy the values out of the ret val registers.
309 switch (Op.Val->getValueType(0)) {
310 default: assert(0 && "Unexpected ret value!");
314 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
315 ResultVals.push_back(Chain.getValue(0));
316 NodeTys.push_back(MVT::i32);
319 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
320 DAG.getConstant(NumBytes, MVT::i32));
321 NodeTys.push_back(MVT::Other);
323 if (ResultVals.empty())
326 ResultVals.push_back(Chain);
327 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
329 return Res.getValue(Op.ResNo);
332 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
334 SDOperand Chain = Op.getOperand(0);
335 SDOperand R0 = DAG.getRegister(ARM::R0, MVT::i32);
336 SDOperand R1 = DAG.getRegister(ARM::R1, MVT::i32);
338 switch(Op.getNumOperands()) {
340 assert(0 && "Do not know how to return this many arguments!");
343 SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
344 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
347 SDOperand Val = Op.getOperand(1);
348 assert(Val.getValueType() == MVT::i32 ||
349 Val.getValueType() == MVT::f32 ||
350 Val.getValueType() == MVT::f64);
352 if (Val.getValueType() == MVT::f64) {
353 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
354 SDOperand Ops[] = {Chain, R0, R1, Val};
355 Copy = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4);
357 if (Val.getValueType() == MVT::f32)
358 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
359 Copy = DAG.getCopyToReg(Chain, R0, Val, SDOperand());
362 if (DAG.getMachineFunction().liveout_empty()) {
363 DAG.getMachineFunction().addLiveOut(ARM::R0);
364 if (Val.getValueType() == MVT::f64)
365 DAG.getMachineFunction().addLiveOut(ARM::R1);
370 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
371 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
372 // If we haven't noted the R0+R1 are live out, do so now.
373 if (DAG.getMachineFunction().liveout_empty()) {
374 DAG.getMachineFunction().addLiveOut(ARM::R0);
375 DAG.getMachineFunction().addLiveOut(ARM::R1);
380 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
381 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
384 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
385 MVT::ValueType PtrVT = Op.getValueType();
386 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
387 Constant *C = CP->getConstVal();
388 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
393 static SDOperand LowerGlobalAddress(SDOperand Op,
395 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
397 SDOperand CPAddr = DAG.getConstantPool(GV, MVT::i32, alignment);
398 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr,
399 DAG.getSrcValue(NULL));
402 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
403 unsigned VarArgsFrameIndex) {
404 // vastart just stores the address of the VarArgsFrameIndex slot into the
405 // memory location argument.
406 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
407 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
408 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), Op.getOperand(2));
411 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
412 int &VarArgsFrameIndex) {
413 MachineFunction &MF = DAG.getMachineFunction();
414 MachineFrameInfo *MFI = MF.getFrameInfo();
415 SSARegMap *RegMap = MF.getSSARegMap();
416 unsigned NumArgs = Op.Val->getNumValues()-1;
417 SDOperand Root = Op.getOperand(0);
418 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
419 static const unsigned REGS[] = {
420 ARM::R0, ARM::R1, ARM::R2, ARM::R3
423 std::vector<MVT::ValueType> Types(Op.Val->value_begin(), Op.Val->value_end() - 1);
424 ArgumentLayout Layout(Types);
426 std::vector<SDOperand> ArgValues;
427 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) {
428 MVT::ValueType VT = Types[ArgNo];
431 if (Layout.isRegister(ArgNo)) {
432 assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
433 unsigned RegNum = Layout.getRegisterNum(ArgNo);
434 unsigned Reg1 = REGS[RegNum];
435 unsigned VReg1 = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
436 SDOperand Value1 = DAG.getCopyFromReg(Root, VReg1, MVT::i32);
437 MF.addLiveIn(Reg1, VReg1);
438 if (VT == MVT::f64) {
439 unsigned Reg2 = REGS[RegNum + 1];
440 unsigned VReg2 = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
441 SDOperand Value2 = DAG.getCopyFromReg(Root, VReg2, MVT::i32);
442 MF.addLiveIn(Reg2, VReg2);
443 Value = DAG.getNode(ARMISD::FMDRR, MVT::f64, Value1, Value2);
447 Value = DAG.getNode(ISD::BIT_CONVERT, VT, Value);
450 // If the argument is actually used, emit a load from the right stack
452 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
453 unsigned Offset = Layout.getOffset(ArgNo);
454 unsigned Size = MVT::getSizeInBits(VT)/8;
455 int FI = MFI->CreateFixedObject(Size, Offset);
456 SDOperand FIN = DAG.getFrameIndex(FI, VT);
457 Value = DAG.getLoad(VT, Root, FIN, DAG.getSrcValue(NULL));
459 Value = DAG.getNode(ISD::UNDEF, VT);
462 ArgValues.push_back(Value);
465 unsigned NextRegNum = Layout.lastRegNum() + 1;
468 //If this function is vararg we must store the remaing
469 //registers so that they can be acessed with va_start
470 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
471 -16 + NextRegNum * 4);
473 SmallVector<SDOperand, 4> MemOps;
474 for (unsigned RegNo = NextRegNum; RegNo < 4; ++RegNo) {
475 int RegOffset = - (4 - RegNo) * 4;
476 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
478 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
480 unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
481 MF.addLiveIn(REGS[RegNo], VReg);
483 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
484 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
485 DAG.getSrcValue(NULL));
486 MemOps.push_back(Store);
488 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
491 ArgValues.push_back(Root);
493 // Return the new list of results.
494 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
495 Op.Val->value_end());
496 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
499 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
500 SDOperand LHS = Op.getOperand(0);
501 SDOperand RHS = Op.getOperand(1);
502 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
503 SDOperand TrueVal = Op.getOperand(2);
504 SDOperand FalseVal = Op.getOperand(3);
505 SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
507 SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
508 return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp);
511 static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
512 SDOperand Chain = Op.getOperand(0);
513 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
514 SDOperand LHS = Op.getOperand(2);
515 SDOperand RHS = Op.getOperand(3);
516 SDOperand Dest = Op.getOperand(4);
517 SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
519 SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
520 return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
523 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
524 SDOperand IntVal = Op.getOperand(0);
525 assert(IntVal.getValueType() == MVT::i32);
526 MVT::ValueType vt = Op.getValueType();
527 assert(vt == MVT::f32 ||
530 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal);
531 ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FSITOS : ARMISD::FSITOD;
532 return DAG.getNode(op, vt, Tmp);
535 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
536 switch (Op.getOpcode()) {
538 assert(0 && "Should not custom lower this!");
540 case ISD::ConstantPool:
541 return LowerConstantPool(Op, DAG);
542 case ISD::GlobalAddress:
543 return LowerGlobalAddress(Op, DAG);
544 case ISD::SINT_TO_FP:
545 return LowerSINT_TO_FP(Op, DAG);
546 case ISD::FORMAL_ARGUMENTS:
547 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
549 return LowerCALL(Op, DAG);
551 return LowerRET(Op, DAG);
553 return LowerSELECT_CC(Op, DAG);
555 return LowerBR_CC(Op, DAG);
557 return LowerVASTART(Op, DAG, VarArgsFrameIndex);
561 //===----------------------------------------------------------------------===//
562 // Instruction Selector Implementation
563 //===----------------------------------------------------------------------===//
565 //===--------------------------------------------------------------------===//
566 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
567 /// instructions for SelectionDAG operations.
570 class ARMDAGToDAGISel : public SelectionDAGISel {
571 ARMTargetLowering Lowering;
574 ARMDAGToDAGISel(TargetMachine &TM)
575 : SelectionDAGISel(Lowering), Lowering(TM) {
578 SDNode *Select(SDOperand Op);
579 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
580 bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
581 bool SelectAddrMode1(SDOperand N, SDOperand &Arg, SDOperand &Shift,
582 SDOperand &ShiftType);
584 // Include the pieces autogenerated from the target description.
585 #include "ARMGenDAGISel.inc"
588 void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
591 DAG.setRoot(SelectRoot(DAG.getRoot()));
592 DAG.RemoveDeadNodes();
594 ScheduleAndEmitDAG(DAG);
597 static bool isInt12Immediate(SDNode *N, short &Imm) {
598 if (N->getOpcode() != ISD::Constant)
601 int32_t t = cast<ConstantSDNode>(N)->getValue();
604 if (t > min && t < max) {
612 static bool isInt12Immediate(SDOperand Op, short &Imm) {
613 return isInt12Immediate(Op.Val, Imm);
616 static uint32_t rotateL(uint32_t x) {
617 uint32_t bit31 = (x & (1 << 31)) >> 31;
622 static bool isUInt8Immediate(uint32_t x) {
626 static bool isRotInt8Immediate(uint32_t x) {
628 for (r = 0; r < 16; r++) {
629 if (isUInt8Immediate(x))
631 x = rotateL(rotateL(x));
636 bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
639 SDOperand &ShiftType) {
640 switch(N.getOpcode()) {
641 case ISD::Constant: {
642 uint32_t val = cast<ConstantSDNode>(N)->getValue();
643 if(!isRotInt8Immediate(val)) {
644 const Type *t = MVT::getTypeForValueType(MVT::i32);
645 Constant *C = ConstantUInt::get(t, val);
647 SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment);
648 SDOperand Z = CurDAG->getTargetConstant(0, MVT::i32);
649 SDNode *n = CurDAG->getTargetNode(ARM::ldr, MVT::i32, Z, Addr);
650 Arg = SDOperand(n, 0);
652 Arg = CurDAG->getTargetConstant(val, MVT::i32);
654 Shift = CurDAG->getTargetConstant(0, MVT::i32);
655 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
659 Arg = N.getOperand(0);
660 Shift = N.getOperand(1);
661 ShiftType = CurDAG->getTargetConstant(ARMShift::ASR, MVT::i32);
664 Arg = N.getOperand(0);
665 Shift = N.getOperand(1);
666 ShiftType = CurDAG->getTargetConstant(ARMShift::LSR, MVT::i32);
669 Arg = N.getOperand(0);
670 Shift = N.getOperand(1);
671 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
676 Shift = CurDAG->getTargetConstant(0, MVT::i32);
677 ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
681 //register plus/minus 12 bit offset
682 bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
684 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
685 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
686 Offset = CurDAG->getTargetConstant(0, MVT::i32);
689 if (N.getOpcode() == ISD::ADD) {
691 if (isInt12Immediate(N.getOperand(1), imm)) {
692 Offset = CurDAG->getTargetConstant(imm, MVT::i32);
693 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
694 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
696 Base = N.getOperand(0);
698 return true; // [r+i]
702 Offset = CurDAG->getTargetConstant(0, MVT::i32);
703 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
704 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
708 return true; //any address fits in a register
711 SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
714 switch (N->getOpcode()) {
716 return SelectCode(Op);
722 } // end anonymous namespace
724 /// createARMISelDag - This pass converts a legalized DAG into a
725 /// ARM-specific DAG, ready for instruction scheduling.
727 FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
728 return new ARMDAGToDAGISel(TM);