1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 //===--------------------------------------------------------------------===//
40 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
41 /// instructions for SelectionDAG operations.
44 class ARMDAGToDAGISel : public SelectionDAGISel {
45 ARMBaseTargetMachine &TM;
47 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
48 /// make the right decision when generating code for different targets.
49 const ARMSubtarget *Subtarget;
52 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
53 CodeGenOpt::Level OptLevel)
54 : SelectionDAGISel(tm, OptLevel), TM(tm),
55 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
58 virtual const char *getPassName() const {
59 return "ARM Instruction Selection";
62 /// getI32Imm - Return a target constant of type i32 with the specified
64 inline SDValue getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 SDNode *Select(SDValue Op);
69 virtual void InstructionSelect();
70 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
71 SDValue &B, SDValue &C);
72 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
73 SDValue &Offset, SDValue &Opc);
74 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
75 SDValue &Offset, SDValue &Opc);
76 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
77 SDValue &Offset, SDValue &Opc);
78 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
79 SDValue &Offset, SDValue &Opc);
80 bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
82 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
84 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
87 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
90 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
92 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
93 SDValue &Base, SDValue &OffImm,
95 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
96 SDValue &OffImm, SDValue &Offset);
97 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
98 SDValue &OffImm, SDValue &Offset);
99 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
100 SDValue &OffImm, SDValue &Offset);
101 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
104 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
105 SDValue &BaseReg, SDValue &Opc);
106 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
108 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
110 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
112 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
114 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
115 SDValue &OffReg, SDValue &ShImm);
117 // Include the pieces autogenerated from the target description.
118 #include "ARMGenDAGISel.inc"
121 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
123 SDNode *SelectARMIndexedLoad(SDValue Op);
124 SDNode *SelectT2IndexedLoad(SDValue Op);
126 /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
127 SDNode *SelectDYN_ALLOC(SDValue Op);
129 /// SelectV6T2BitfielsOp - Select SBFX/UBFX instructions for ARM.
130 SDNode *SelectV6T2BitfieldExtractOp(SDValue Op, unsigned Opc);
132 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
133 /// inline asm expressions.
134 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
136 std::vector<SDValue> &OutOps);
138 /// PairDRegs - Insert a pair of double registers into an implicit def to
139 /// form a quad register.
140 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
144 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
145 /// operand. If so Imm will receive the 32-bit value.
146 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
147 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
148 Imm = cast<ConstantSDNode>(N)->getZExtValue();
154 // isInt32Immediate - This method tests to see if a constant operand.
155 // If so Imm will receive the 32 bit value.
156 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
157 return isInt32Immediate(N.getNode(), Imm);
160 // isOpcWithIntImmediate - This method tests to see if the node is a specific
161 // opcode and that it has a immediate integer right operand.
162 // If so Imm will receive the 32 bit value.
163 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
164 return N->getOpcode() == Opc &&
165 isInt32Immediate(N->getOperand(1).getNode(), Imm);
169 void ARMDAGToDAGISel::InstructionSelect() {
173 CurDAG->RemoveDeadNodes();
176 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
181 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
183 // Don't match base register only case. That is matched to a separate
184 // lower complexity pattern with explicit register operand.
185 if (ShOpcVal == ARM_AM::no_shift) return false;
187 BaseReg = N.getOperand(0);
188 unsigned ShImmVal = 0;
189 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
190 ShReg = CurDAG->getRegister(0, MVT::i32);
191 ShImmVal = RHS->getZExtValue() & 31;
193 ShReg = N.getOperand(1);
195 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
200 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
201 SDValue &Base, SDValue &Offset,
203 if (N.getOpcode() == ISD::MUL) {
204 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
205 // X * [3,5,9] -> X + X * [2,4,8] etc.
206 int RHSC = (int)RHS->getZExtValue();
209 ARM_AM::AddrOpc AddSub = ARM_AM::add;
211 AddSub = ARM_AM::sub;
214 if (isPowerOf2_32(RHSC)) {
215 unsigned ShAmt = Log2_32(RHSC);
216 Base = Offset = N.getOperand(0);
217 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
226 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
228 if (N.getOpcode() == ISD::FrameIndex) {
229 int FI = cast<FrameIndexSDNode>(N)->getIndex();
230 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
231 } else if (N.getOpcode() == ARMISD::Wrapper) {
232 Base = N.getOperand(0);
234 Offset = CurDAG->getRegister(0, MVT::i32);
235 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
241 // Match simple R +/- imm12 operands.
242 if (N.getOpcode() == ISD::ADD)
243 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
244 int RHSC = (int)RHS->getZExtValue();
245 if ((RHSC >= 0 && RHSC < 0x1000) ||
246 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
247 Base = N.getOperand(0);
248 if (Base.getOpcode() == ISD::FrameIndex) {
249 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
250 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
252 Offset = CurDAG->getRegister(0, MVT::i32);
254 ARM_AM::AddrOpc AddSub = ARM_AM::add;
256 AddSub = ARM_AM::sub;
259 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
266 // Otherwise this is R +/- [possibly shifted] R
267 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
268 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
271 Base = N.getOperand(0);
272 Offset = N.getOperand(1);
274 if (ShOpcVal != ARM_AM::no_shift) {
275 // Check to see if the RHS of the shift is a constant, if not, we can't fold
277 if (ConstantSDNode *Sh =
278 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
279 ShAmt = Sh->getZExtValue();
280 Offset = N.getOperand(1).getOperand(0);
282 ShOpcVal = ARM_AM::no_shift;
286 // Try matching (R shl C) + (R).
287 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
288 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
289 if (ShOpcVal != ARM_AM::no_shift) {
290 // Check to see if the RHS of the shift is a constant, if not, we can't
292 if (ConstantSDNode *Sh =
293 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
294 ShAmt = Sh->getZExtValue();
295 Offset = N.getOperand(0).getOperand(0);
296 Base = N.getOperand(1);
298 ShOpcVal = ARM_AM::no_shift;
303 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
308 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
309 SDValue &Offset, SDValue &Opc) {
310 unsigned Opcode = Op.getOpcode();
311 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
312 ? cast<LoadSDNode>(Op)->getAddressingMode()
313 : cast<StoreSDNode>(Op)->getAddressingMode();
314 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
315 ? ARM_AM::add : ARM_AM::sub;
316 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
317 int Val = (int)C->getZExtValue();
318 if (Val >= 0 && Val < 0x1000) { // 12 bits.
319 Offset = CurDAG->getRegister(0, MVT::i32);
320 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
328 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
330 if (ShOpcVal != ARM_AM::no_shift) {
331 // Check to see if the RHS of the shift is a constant, if not, we can't fold
333 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
334 ShAmt = Sh->getZExtValue();
335 Offset = N.getOperand(0);
337 ShOpcVal = ARM_AM::no_shift;
341 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
347 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
348 SDValue &Base, SDValue &Offset,
350 if (N.getOpcode() == ISD::SUB) {
351 // X - C is canonicalize to X + -C, no need to handle it here.
352 Base = N.getOperand(0);
353 Offset = N.getOperand(1);
354 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
358 if (N.getOpcode() != ISD::ADD) {
360 if (N.getOpcode() == ISD::FrameIndex) {
361 int FI = cast<FrameIndexSDNode>(N)->getIndex();
362 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
364 Offset = CurDAG->getRegister(0, MVT::i32);
365 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
369 // If the RHS is +/- imm8, fold into addr mode.
370 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
371 int RHSC = (int)RHS->getZExtValue();
372 if ((RHSC >= 0 && RHSC < 256) ||
373 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
374 Base = N.getOperand(0);
375 if (Base.getOpcode() == ISD::FrameIndex) {
376 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
377 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
379 Offset = CurDAG->getRegister(0, MVT::i32);
381 ARM_AM::AddrOpc AddSub = ARM_AM::add;
383 AddSub = ARM_AM::sub;
386 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
391 Base = N.getOperand(0);
392 Offset = N.getOperand(1);
393 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
397 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
398 SDValue &Offset, SDValue &Opc) {
399 unsigned Opcode = Op.getOpcode();
400 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
401 ? cast<LoadSDNode>(Op)->getAddressingMode()
402 : cast<StoreSDNode>(Op)->getAddressingMode();
403 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
404 ? ARM_AM::add : ARM_AM::sub;
405 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
406 int Val = (int)C->getZExtValue();
407 if (Val >= 0 && Val < 256) {
408 Offset = CurDAG->getRegister(0, MVT::i32);
409 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
415 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
419 bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
420 SDValue &Addr, SDValue &Mode) {
422 Mode = CurDAG->getTargetConstant(0, MVT::i32);
426 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
427 SDValue &Base, SDValue &Offset) {
428 if (N.getOpcode() != ISD::ADD) {
430 if (N.getOpcode() == ISD::FrameIndex) {
431 int FI = cast<FrameIndexSDNode>(N)->getIndex();
432 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
433 } else if (N.getOpcode() == ARMISD::Wrapper) {
434 Base = N.getOperand(0);
436 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
441 // If the RHS is +/- imm8, fold into addr mode.
442 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
443 int RHSC = (int)RHS->getZExtValue();
444 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
446 if ((RHSC >= 0 && RHSC < 256) ||
447 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
448 Base = N.getOperand(0);
449 if (Base.getOpcode() == ISD::FrameIndex) {
450 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
451 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
454 ARM_AM::AddrOpc AddSub = ARM_AM::add;
456 AddSub = ARM_AM::sub;
459 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
467 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
472 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
473 SDValue &Addr, SDValue &Update,
476 // Default to no writeback.
477 Update = CurDAG->getRegister(0, MVT::i32);
478 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
482 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
483 SDValue &Offset, SDValue &Label) {
484 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
485 Offset = N.getOperand(0);
486 SDValue N1 = N.getOperand(1);
487 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
494 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
495 SDValue &Base, SDValue &Offset){
496 // FIXME dl should come from the parent load or store, not the address
497 DebugLoc dl = Op.getDebugLoc();
498 if (N.getOpcode() != ISD::ADD) {
499 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
500 if (!NC || NC->getZExtValue() != 0)
507 Base = N.getOperand(0);
508 Offset = N.getOperand(1);
513 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
514 unsigned Scale, SDValue &Base,
515 SDValue &OffImm, SDValue &Offset) {
517 SDValue TmpBase, TmpOffImm;
518 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
519 return false; // We want to select tLDRspi / tSTRspi instead.
520 if (N.getOpcode() == ARMISD::Wrapper &&
521 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
522 return false; // We want to select tLDRpci instead.
525 if (N.getOpcode() != ISD::ADD) {
526 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
527 Offset = CurDAG->getRegister(0, MVT::i32);
528 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
532 // Thumb does not have [sp, r] address mode.
533 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
534 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
535 if ((LHSR && LHSR->getReg() == ARM::SP) ||
536 (RHSR && RHSR->getReg() == ARM::SP)) {
538 Offset = CurDAG->getRegister(0, MVT::i32);
539 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
543 // If the RHS is + imm5 * scale, fold into addr mode.
544 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
545 int RHSC = (int)RHS->getZExtValue();
546 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
548 if (RHSC >= 0 && RHSC < 32) {
549 Base = N.getOperand(0);
550 Offset = CurDAG->getRegister(0, MVT::i32);
551 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
557 Base = N.getOperand(0);
558 Offset = N.getOperand(1);
559 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
563 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
564 SDValue &Base, SDValue &OffImm,
566 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
569 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
570 SDValue &Base, SDValue &OffImm,
572 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
575 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
576 SDValue &Base, SDValue &OffImm,
578 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
581 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
582 SDValue &Base, SDValue &OffImm) {
583 if (N.getOpcode() == ISD::FrameIndex) {
584 int FI = cast<FrameIndexSDNode>(N)->getIndex();
585 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
586 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
590 if (N.getOpcode() != ISD::ADD)
593 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
594 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
595 (LHSR && LHSR->getReg() == ARM::SP)) {
596 // If the RHS is + imm8 * scale, fold into addr mode.
597 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
598 int RHSC = (int)RHS->getZExtValue();
599 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
601 if (RHSC >= 0 && RHSC < 256) {
602 Base = N.getOperand(0);
603 if (Base.getOpcode() == ISD::FrameIndex) {
604 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
605 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
607 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
617 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
620 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
622 // Don't match base register only case. That is matched to a separate
623 // lower complexity pattern with explicit register operand.
624 if (ShOpcVal == ARM_AM::no_shift) return false;
626 BaseReg = N.getOperand(0);
627 unsigned ShImmVal = 0;
628 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
629 ShImmVal = RHS->getZExtValue() & 31;
630 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
637 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
638 SDValue &Base, SDValue &OffImm) {
639 // Match simple R + imm12 operands.
642 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
643 if (N.getOpcode() == ISD::FrameIndex) {
644 // Match frame index...
645 int FI = cast<FrameIndexSDNode>(N)->getIndex();
646 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
647 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
649 } else if (N.getOpcode() == ARMISD::Wrapper) {
650 Base = N.getOperand(0);
651 if (Base.getOpcode() == ISD::TargetConstantPool)
652 return false; // We want to select t2LDRpci instead.
655 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
659 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
660 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
661 // Let t2LDRi8 handle (R - imm8).
664 int RHSC = (int)RHS->getZExtValue();
665 if (N.getOpcode() == ISD::SUB)
668 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
669 Base = N.getOperand(0);
670 if (Base.getOpcode() == ISD::FrameIndex) {
671 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
672 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
674 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
681 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
685 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
686 SDValue &Base, SDValue &OffImm) {
687 // Match simple R - imm8 operands.
688 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
689 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
690 int RHSC = (int)RHS->getSExtValue();
691 if (N.getOpcode() == ISD::SUB)
694 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
695 Base = N.getOperand(0);
696 if (Base.getOpcode() == ISD::FrameIndex) {
697 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
698 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
700 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
709 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
711 unsigned Opcode = Op.getOpcode();
712 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
713 ? cast<LoadSDNode>(Op)->getAddressingMode()
714 : cast<StoreSDNode>(Op)->getAddressingMode();
715 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
716 int RHSC = (int)RHS->getZExtValue();
717 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
718 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
719 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
720 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
728 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
729 SDValue &Base, SDValue &OffImm) {
730 if (N.getOpcode() == ISD::ADD) {
731 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
732 int RHSC = (int)RHS->getZExtValue();
733 if (((RHSC & 0x3) == 0) &&
734 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
735 Base = N.getOperand(0);
736 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
740 } else if (N.getOpcode() == ISD::SUB) {
741 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
742 int RHSC = (int)RHS->getZExtValue();
743 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
744 Base = N.getOperand(0);
745 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
754 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
756 SDValue &OffReg, SDValue &ShImm) {
757 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
758 if (N.getOpcode() != ISD::ADD)
761 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
762 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
763 int RHSC = (int)RHS->getZExtValue();
764 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
766 else if (RHSC < 0 && RHSC >= -255) // 8 bits
770 // Look for (R + R) or (R + (R << [1,2,3])).
772 Base = N.getOperand(0);
773 OffReg = N.getOperand(1);
775 // Swap if it is ((R << c) + R).
776 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
777 if (ShOpcVal != ARM_AM::lsl) {
778 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
779 if (ShOpcVal == ARM_AM::lsl)
780 std::swap(Base, OffReg);
783 if (ShOpcVal == ARM_AM::lsl) {
784 // Check to see if the RHS of the shift is a constant, if not, we can't fold
786 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
787 ShAmt = Sh->getZExtValue();
790 ShOpcVal = ARM_AM::no_shift;
792 OffReg = OffReg.getOperand(0);
794 ShOpcVal = ARM_AM::no_shift;
798 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
803 //===--------------------------------------------------------------------===//
805 /// getAL - Returns a ARMCC::AL immediate node.
806 static inline SDValue getAL(SelectionDAG *CurDAG) {
807 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
810 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
811 LoadSDNode *LD = cast<LoadSDNode>(Op);
812 ISD::MemIndexedMode AM = LD->getAddressingMode();
813 if (AM == ISD::UNINDEXED)
816 EVT LoadedVT = LD->getMemoryVT();
817 SDValue Offset, AMOpc;
818 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
821 if (LoadedVT == MVT::i32 &&
822 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
823 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
825 } else if (LoadedVT == MVT::i16 &&
826 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
828 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
829 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
830 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
831 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
832 if (LD->getExtensionType() == ISD::SEXTLOAD) {
833 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
835 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
838 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
840 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
846 SDValue Chain = LD->getChain();
847 SDValue Base = LD->getBasePtr();
848 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
849 CurDAG->getRegister(0, MVT::i32), Chain };
850 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
857 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
858 LoadSDNode *LD = cast<LoadSDNode>(Op);
859 ISD::MemIndexedMode AM = LD->getAddressingMode();
860 if (AM == ISD::UNINDEXED)
863 EVT LoadedVT = LD->getMemoryVT();
864 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
866 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
869 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
870 switch (LoadedVT.getSimpleVT().SimpleTy) {
872 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
876 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
878 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
883 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
885 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
894 SDValue Chain = LD->getChain();
895 SDValue Base = LD->getBasePtr();
896 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
897 CurDAG->getRegister(0, MVT::i32), Chain };
898 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
905 SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
906 SDNode *N = Op.getNode();
907 DebugLoc dl = N->getDebugLoc();
908 EVT VT = Op.getValueType();
909 SDValue Chain = Op.getOperand(0);
910 SDValue Size = Op.getOperand(1);
911 SDValue Align = Op.getOperand(2);
912 SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
913 int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
915 // We need to align the stack. Use Thumb1 tAND which is the only thumb
916 // instruction that can read and write SP. This matches to a pseudo
917 // instruction that has a chain to ensure the result is written back to
918 // the stack pointer.
919 SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0);
921 bool isC = isa<ConstantSDNode>(Size);
922 uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
923 // Handle the most common case for both Thumb1 and Thumb2:
924 // tSUBspi - immediate is between 0 ... 508 inclusive.
925 if (C <= 508 && ((C & 3) == 0))
926 // FIXME: tSUBspi encode scale 4 implicitly.
927 return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
928 CurDAG->getTargetConstant(C/4, MVT::i32),
931 if (Subtarget->isThumb1Only()) {
932 // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
933 // should have negated the size operand already. FIXME: We can't insert
934 // new target independent node at this stage so we are forced to negate
935 // it earlier. Is there a better solution?
936 return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
938 } else if (Subtarget->isThumb2()) {
939 if (isC && Predicate_t2_so_imm(Size.getNode())) {
941 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
942 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
943 } else if (isC && Predicate_imm0_4095(Size.getNode())) {
945 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
946 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
949 SDValue Ops[] = { SP, Size,
950 getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
951 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
955 // FIXME: Add ADD / SUB sp instructions for ARM.
959 /// PairDRegs - Insert a pair of double registers into an implicit def to
960 /// form a quad register.
961 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
962 DebugLoc dl = V0.getNode()->getDebugLoc();
964 SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT), 0);
965 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
966 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
967 SDNode *Pair = CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
968 VT, Undef, V0, SubReg0);
969 return CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
970 VT, SDValue(Pair, 0), V1, SubReg1);
973 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDValue Op,
975 if (!Subtarget->hasV6T2Ops())
978 unsigned Shl_imm = 0;
979 if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)){
980 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
981 unsigned Srl_imm = 0;
982 if (isInt32Immediate(Op.getOperand(1), Srl_imm)) {
983 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
984 unsigned Width = 32 - Srl_imm;
985 int LSB = Srl_imm - Shl_imm;
986 if ((LSB + Width) > 32)
988 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
989 SDValue Ops[] = { Op.getOperand(0).getOperand(0),
990 CurDAG->getTargetConstant(LSB, MVT::i32),
991 CurDAG->getTargetConstant(Width, MVT::i32),
992 getAL(CurDAG), Reg0 };
993 return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32, Ops, 5);
999 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
1000 SDNode *N = Op.getNode();
1001 DebugLoc dl = N->getDebugLoc();
1003 if (N->isMachineOpcode())
1004 return NULL; // Already selected.
1006 switch (N->getOpcode()) {
1008 case ISD::Constant: {
1009 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1011 if (Subtarget->hasThumb2())
1012 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1013 // be done with MOV + MOVT, at worst.
1016 if (Subtarget->isThumb()) {
1017 UseCP = (Val > 255 && // MOV
1018 ~Val > 255 && // MOV + MVN
1019 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1021 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1022 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1023 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1028 CurDAG->getTargetConstantPool(ConstantInt::get(
1029 Type::getInt32Ty(*CurDAG->getContext()), Val),
1030 TLI.getPointerTy());
1033 if (Subtarget->isThumb1Only()) {
1034 SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
1035 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1036 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1037 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1042 CurDAG->getRegister(0, MVT::i32),
1043 CurDAG->getTargetConstant(0, MVT::i32),
1045 CurDAG->getRegister(0, MVT::i32),
1046 CurDAG->getEntryNode()
1048 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1051 ReplaceUses(Op, SDValue(ResNode, 0));
1055 // Other cases are autogenerated.
1058 case ISD::FrameIndex: {
1059 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1060 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1061 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1062 if (Subtarget->isThumb1Only()) {
1063 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1064 CurDAG->getTargetConstant(0, MVT::i32));
1066 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1067 ARM::t2ADDri : ARM::ADDri);
1068 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1069 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1070 CurDAG->getRegister(0, MVT::i32) };
1071 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1074 case ARMISD::DYN_ALLOC:
1075 return SelectDYN_ALLOC(Op);
1077 if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
1078 Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX))
1082 if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
1083 Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX))
1087 if (Subtarget->isThumb1Only())
1089 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1090 unsigned RHSV = C->getZExtValue();
1092 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1093 unsigned ShImm = Log2_32(RHSV-1);
1096 SDValue V = Op.getOperand(0);
1097 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1098 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1099 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1100 if (Subtarget->isThumb()) {
1101 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1102 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1104 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1105 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1108 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1109 unsigned ShImm = Log2_32(RHSV+1);
1112 SDValue V = Op.getOperand(0);
1113 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1114 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1115 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1116 if (Subtarget->isThumb()) {
1117 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1118 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1120 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1121 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1127 return CurDAG->getMachineNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
1128 Op.getOperand(0), getAL(CurDAG),
1129 CurDAG->getRegister(0, MVT::i32));
1130 case ISD::UMUL_LOHI: {
1131 if (Subtarget->isThumb1Only())
1133 if (Subtarget->isThumb()) {
1134 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1135 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1136 CurDAG->getRegister(0, MVT::i32) };
1137 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1139 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1140 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1141 CurDAG->getRegister(0, MVT::i32) };
1142 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1145 case ISD::SMUL_LOHI: {
1146 if (Subtarget->isThumb1Only())
1148 if (Subtarget->isThumb()) {
1149 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1150 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1151 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1153 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1154 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1155 CurDAG->getRegister(0, MVT::i32) };
1156 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1160 SDNode *ResNode = 0;
1161 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1162 ResNode = SelectT2IndexedLoad(Op);
1164 ResNode = SelectARMIndexedLoad(Op);
1167 // Other cases are autogenerated.
1170 case ARMISD::BRCOND: {
1171 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1172 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1173 // Pattern complexity = 6 cost = 1 size = 0
1175 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1176 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1177 // Pattern complexity = 6 cost = 1 size = 0
1179 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1180 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1181 // Pattern complexity = 6 cost = 1 size = 0
1183 unsigned Opc = Subtarget->isThumb() ?
1184 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1185 SDValue Chain = Op.getOperand(0);
1186 SDValue N1 = Op.getOperand(1);
1187 SDValue N2 = Op.getOperand(2);
1188 SDValue N3 = Op.getOperand(3);
1189 SDValue InFlag = Op.getOperand(4);
1190 assert(N1.getOpcode() == ISD::BasicBlock);
1191 assert(N2.getOpcode() == ISD::Constant);
1192 assert(N3.getOpcode() == ISD::Register);
1194 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1195 cast<ConstantSDNode>(N2)->getZExtValue()),
1197 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1198 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1200 Chain = SDValue(ResNode, 0);
1201 if (Op.getNode()->getNumValues() == 2) {
1202 InFlag = SDValue(ResNode, 1);
1203 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1205 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
1208 case ARMISD::CMOV: {
1209 EVT VT = Op.getValueType();
1210 SDValue N0 = Op.getOperand(0);
1211 SDValue N1 = Op.getOperand(1);
1212 SDValue N2 = Op.getOperand(2);
1213 SDValue N3 = Op.getOperand(3);
1214 SDValue InFlag = Op.getOperand(4);
1215 assert(N2.getOpcode() == ISD::Constant);
1216 assert(N3.getOpcode() == ISD::Register);
1218 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1219 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1220 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1221 // Pattern complexity = 18 cost = 1 size = 0
1225 if (Subtarget->isThumb()) {
1226 if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1227 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1228 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1231 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1232 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1233 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1234 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1236 llvm_unreachable("Unknown so_reg opcode!");
1240 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1241 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1242 cast<ConstantSDNode>(N2)->getZExtValue()),
1244 SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
1245 return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
1248 if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1249 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1250 cast<ConstantSDNode>(N2)->getZExtValue()),
1252 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1253 return CurDAG->SelectNodeTo(Op.getNode(),
1254 ARM::MOVCCs, MVT::i32, Ops, 7);
1258 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1259 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1261 // Emits: (MOVCCi:i32 GPR:i32:$false,
1262 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1263 // Pattern complexity = 10 cost = 1 size = 0
1264 if (N3.getOpcode() == ISD::Constant) {
1265 if (Subtarget->isThumb()) {
1266 if (Predicate_t2_so_imm(N3.getNode())) {
1267 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1268 cast<ConstantSDNode>(N1)->getZExtValue()),
1270 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1271 cast<ConstantSDNode>(N2)->getZExtValue()),
1273 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1274 return CurDAG->SelectNodeTo(Op.getNode(),
1275 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1278 if (Predicate_so_imm(N3.getNode())) {
1279 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1280 cast<ConstantSDNode>(N1)->getZExtValue()),
1282 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1283 cast<ConstantSDNode>(N2)->getZExtValue()),
1285 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1286 return CurDAG->SelectNodeTo(Op.getNode(),
1287 ARM::MOVCCi, MVT::i32, Ops, 5);
1293 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1294 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1295 // Pattern complexity = 6 cost = 1 size = 0
1297 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1298 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1299 // Pattern complexity = 6 cost = 11 size = 0
1301 // Also FCPYScc and FCPYDcc.
1302 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1303 cast<ConstantSDNode>(N2)->getZExtValue()),
1305 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1307 switch (VT.getSimpleVT().SimpleTy) {
1308 default: assert(false && "Illegal conditional move type!");
1311 Opc = Subtarget->isThumb()
1312 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1322 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1324 case ARMISD::CNEG: {
1325 EVT VT = Op.getValueType();
1326 SDValue N0 = Op.getOperand(0);
1327 SDValue N1 = Op.getOperand(1);
1328 SDValue N2 = Op.getOperand(2);
1329 SDValue N3 = Op.getOperand(3);
1330 SDValue InFlag = Op.getOperand(4);
1331 assert(N2.getOpcode() == ISD::Constant);
1332 assert(N3.getOpcode() == ISD::Register);
1334 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1335 cast<ConstantSDNode>(N2)->getZExtValue()),
1337 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1339 switch (VT.getSimpleVT().SimpleTy) {
1340 default: assert(false && "Illegal conditional move type!");
1349 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1352 case ARMISD::VZIP: {
1354 EVT VT = N->getValueType(0);
1355 switch (VT.getSimpleVT().SimpleTy) {
1356 default: return NULL;
1357 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1358 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1360 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1361 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1362 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1364 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1366 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1367 N->getOperand(0), N->getOperand(1));
1369 case ARMISD::VUZP: {
1371 EVT VT = N->getValueType(0);
1372 switch (VT.getSimpleVT().SimpleTy) {
1373 default: return NULL;
1374 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1375 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1377 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1378 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1379 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1381 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1383 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1384 N->getOperand(0), N->getOperand(1));
1386 case ARMISD::VTRN: {
1388 EVT VT = N->getValueType(0);
1389 switch (VT.getSimpleVT().SimpleTy) {
1390 default: return NULL;
1391 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1392 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1394 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1395 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1396 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1398 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1400 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1401 N->getOperand(0), N->getOperand(1));
1404 case ISD::INTRINSIC_VOID:
1405 case ISD::INTRINSIC_W_CHAIN: {
1406 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1407 EVT VT = N->getValueType(0);
1414 case Intrinsic::arm_neon_vld2: {
1415 SDValue MemAddr, MemUpdate, MemOpc;
1416 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1418 if (VT.is64BitVector()) {
1419 switch (VT.getSimpleVT().SimpleTy) {
1420 default: llvm_unreachable("unhandled vld2 type");
1421 case MVT::v8i8: Opc = ARM::VLD2d8; break;
1422 case MVT::v4i16: Opc = ARM::VLD2d16; break;
1424 case MVT::v2i32: Opc = ARM::VLD2d32; break;
1425 case MVT::v1i64: Opc = ARM::VLD2d64; break;
1427 SDValue Chain = N->getOperand(0);
1428 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1429 return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
1431 // Quad registers are loaded as pairs of double registers.
1433 switch (VT.getSimpleVT().SimpleTy) {
1434 default: llvm_unreachable("unhandled vld2 type");
1435 case MVT::v16i8: Opc = ARM::VLD2q8; RegVT = MVT::v8i8; break;
1436 case MVT::v8i16: Opc = ARM::VLD2q16; RegVT = MVT::v4i16; break;
1437 case MVT::v4f32: Opc = ARM::VLD2q32; RegVT = MVT::v2f32; break;
1438 case MVT::v4i32: Opc = ARM::VLD2q32; RegVT = MVT::v2i32; break;
1440 SDValue Chain = N->getOperand(0);
1441 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1442 std::vector<EVT> ResTys(4, RegVT);
1443 ResTys.push_back(MVT::Other);
1444 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
1445 SDNode *Q0 = PairDRegs(VT, SDValue(VLd, 0), SDValue(VLd, 1));
1446 SDNode *Q1 = PairDRegs(VT, SDValue(VLd, 2), SDValue(VLd, 3));
1447 ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
1448 ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
1449 ReplaceUses(SDValue(N, 2), SDValue(VLd, 4));
1453 case Intrinsic::arm_neon_vld3: {
1454 SDValue MemAddr, MemUpdate, MemOpc;
1455 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1457 if (VT.is64BitVector()) {
1458 switch (VT.getSimpleVT().SimpleTy) {
1459 default: llvm_unreachable("unhandled vld3 type");
1460 case MVT::v8i8: Opc = ARM::VLD3d8; break;
1461 case MVT::v4i16: Opc = ARM::VLD3d16; break;
1463 case MVT::v2i32: Opc = ARM::VLD3d32; break;
1464 case MVT::v1i64: Opc = ARM::VLD3d64; break;
1466 SDValue Chain = N->getOperand(0);
1467 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1468 return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
1470 // Quad registers are loaded with two separate instructions, where one
1471 // loads the even registers and the other loads the odd registers.
1474 switch (VT.getSimpleVT().SimpleTy) {
1475 default: llvm_unreachable("unhandled vld3 type");
1477 Opc = ARM::VLD3q8a; Opc2 = ARM::VLD3q8b; RegVT = MVT::v8i8; break;
1479 Opc = ARM::VLD3q16a; Opc2 = ARM::VLD3q16b; RegVT = MVT::v4i16; break;
1481 Opc = ARM::VLD3q32a; Opc2 = ARM::VLD3q32b; RegVT = MVT::v2f32; break;
1483 Opc = ARM::VLD3q32a; Opc2 = ARM::VLD3q32b; RegVT = MVT::v2i32; break;
1485 SDValue Chain = N->getOperand(0);
1486 // Enable writeback to the address register.
1487 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1489 std::vector<EVT> ResTys(3, RegVT);
1490 ResTys.push_back(MemAddr.getValueType());
1491 ResTys.push_back(MVT::Other);
1493 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
1494 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
1495 Chain = SDValue(VLdA, 4);
1497 const SDValue OpsB[] = { SDValue(VLdA, 3), MemUpdate, MemOpc, Chain };
1498 SDNode *VLdB = CurDAG->getMachineNode(Opc2, dl, ResTys, OpsB, 4);
1499 Chain = SDValue(VLdB, 4);
1501 SDNode *Q0 = PairDRegs(VT, SDValue(VLdA, 0), SDValue(VLdB, 0));
1502 SDNode *Q1 = PairDRegs(VT, SDValue(VLdA, 1), SDValue(VLdB, 1));
1503 SDNode *Q2 = PairDRegs(VT, SDValue(VLdA, 2), SDValue(VLdB, 2));
1504 ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
1505 ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
1506 ReplaceUses(SDValue(N, 2), SDValue(Q2, 0));
1507 ReplaceUses(SDValue(N, 3), Chain);
1511 case Intrinsic::arm_neon_vld4: {
1512 SDValue MemAddr, MemUpdate, MemOpc;
1513 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1515 if (VT.is64BitVector()) {
1516 switch (VT.getSimpleVT().SimpleTy) {
1517 default: llvm_unreachable("unhandled vld4 type");
1518 case MVT::v8i8: Opc = ARM::VLD4d8; break;
1519 case MVT::v4i16: Opc = ARM::VLD4d16; break;
1521 case MVT::v2i32: Opc = ARM::VLD4d32; break;
1522 case MVT::v1i64: Opc = ARM::VLD4d64; break;
1524 SDValue Chain = N->getOperand(0);
1525 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1526 std::vector<EVT> ResTys(4, VT);
1527 ResTys.push_back(MVT::Other);
1528 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
1530 // Quad registers are loaded with two separate instructions, where one
1531 // loads the even registers and the other loads the odd registers.
1534 switch (VT.getSimpleVT().SimpleTy) {
1535 default: llvm_unreachable("unhandled vld4 type");
1537 Opc = ARM::VLD4q8a; Opc2 = ARM::VLD4q8b; RegVT = MVT::v8i8; break;
1539 Opc = ARM::VLD4q16a; Opc2 = ARM::VLD4q16b; RegVT = MVT::v4i16; break;
1541 Opc = ARM::VLD4q32a; Opc2 = ARM::VLD4q32b; RegVT = MVT::v2f32; break;
1543 Opc = ARM::VLD4q32a; Opc2 = ARM::VLD4q32b; RegVT = MVT::v2i32; break;
1545 SDValue Chain = N->getOperand(0);
1546 // Enable writeback to the address register.
1547 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1549 std::vector<EVT> ResTys(4, RegVT);
1550 ResTys.push_back(MemAddr.getValueType());
1551 ResTys.push_back(MVT::Other);
1553 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
1554 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
1555 Chain = SDValue(VLdA, 5);
1557 const SDValue OpsB[] = { SDValue(VLdA, 4), MemUpdate, MemOpc, Chain };
1558 SDNode *VLdB = CurDAG->getMachineNode(Opc2, dl, ResTys, OpsB, 4);
1559 Chain = SDValue(VLdB, 5);
1561 SDNode *Q0 = PairDRegs(VT, SDValue(VLdA, 0), SDValue(VLdB, 0));
1562 SDNode *Q1 = PairDRegs(VT, SDValue(VLdA, 1), SDValue(VLdB, 1));
1563 SDNode *Q2 = PairDRegs(VT, SDValue(VLdA, 2), SDValue(VLdB, 2));
1564 SDNode *Q3 = PairDRegs(VT, SDValue(VLdA, 3), SDValue(VLdB, 3));
1565 ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
1566 ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
1567 ReplaceUses(SDValue(N, 2), SDValue(Q2, 0));
1568 ReplaceUses(SDValue(N, 3), SDValue(Q3, 0));
1569 ReplaceUses(SDValue(N, 4), Chain);
1573 case Intrinsic::arm_neon_vld2lane: {
1574 SDValue MemAddr, MemUpdate, MemOpc;
1575 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1577 if (VT.is64BitVector()) {
1578 switch (VT.getSimpleVT().SimpleTy) {
1579 default: llvm_unreachable("unhandled vld2lane type");
1580 case MVT::v8i8: Opc = ARM::VLD2LNd8; break;
1581 case MVT::v4i16: Opc = ARM::VLD2LNd16; break;
1583 case MVT::v2i32: Opc = ARM::VLD2LNd32; break;
1585 SDValue Chain = N->getOperand(0);
1586 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1587 N->getOperand(3), N->getOperand(4),
1588 N->getOperand(5), Chain };
1589 return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 7);
1591 // Quad registers are handled by extracting subregs, doing the load,
1592 // and then inserting the results as subregs.
1595 switch (VT.getSimpleVT().SimpleTy) {
1596 default: llvm_unreachable("unhandled vld2lane type");
1598 Opc = ARM::VLD2LNq16a;
1599 Opc2 = ARM::VLD2LNq16b;
1603 Opc = ARM::VLD2LNq32a;
1604 Opc2 = ARM::VLD2LNq32b;
1608 Opc = ARM::VLD2LNq32a;
1609 Opc2 = ARM::VLD2LNq32b;
1613 SDValue Chain = N->getOperand(0);
1614 unsigned Lane = cast<ConstantSDNode>(N->getOperand(5))->getZExtValue();
1615 unsigned NumElts = RegVT.getVectorNumElements();
1616 int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1618 SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1620 SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1622 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1,
1623 getI32Imm(Lane % NumElts), Chain };
1624 SDNode *VLdLn = CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
1625 dl, RegVT, RegVT, MVT::Other,
1627 SDValue Q0 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1630 SDValue Q1 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1633 Chain = SDValue(VLdLn, 2);
1634 ReplaceUses(SDValue(N, 0), Q0);
1635 ReplaceUses(SDValue(N, 1), Q1);
1636 ReplaceUses(SDValue(N, 2), Chain);
1640 case Intrinsic::arm_neon_vld3lane: {
1641 SDValue MemAddr, MemUpdate, MemOpc;
1642 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1644 if (VT.is64BitVector()) {
1645 switch (VT.getSimpleVT().SimpleTy) {
1646 default: llvm_unreachable("unhandled vld3lane type");
1647 case MVT::v8i8: Opc = ARM::VLD3LNd8; break;
1648 case MVT::v4i16: Opc = ARM::VLD3LNd16; break;
1650 case MVT::v2i32: Opc = ARM::VLD3LNd32; break;
1652 SDValue Chain = N->getOperand(0);
1653 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1654 N->getOperand(3), N->getOperand(4),
1655 N->getOperand(5), N->getOperand(6), Chain };
1656 return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8);
1658 // Quad registers are handled by extracting subregs, doing the load,
1659 // and then inserting the results as subregs.
1662 switch (VT.getSimpleVT().SimpleTy) {
1663 default: llvm_unreachable("unhandled vld3lane type");
1665 Opc = ARM::VLD3LNq16a;
1666 Opc2 = ARM::VLD3LNq16b;
1670 Opc = ARM::VLD3LNq32a;
1671 Opc2 = ARM::VLD3LNq32b;
1675 Opc = ARM::VLD3LNq32a;
1676 Opc2 = ARM::VLD3LNq32b;
1680 SDValue Chain = N->getOperand(0);
1681 unsigned Lane = cast<ConstantSDNode>(N->getOperand(6))->getZExtValue();
1682 unsigned NumElts = RegVT.getVectorNumElements();
1683 int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1685 SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1687 SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1689 SDValue D2 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1691 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1, D2,
1692 getI32Imm(Lane % NumElts), Chain };
1693 SDNode *VLdLn = CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
1694 dl, RegVT, RegVT, RegVT,
1695 MVT::Other, Ops, 8);
1696 SDValue Q0 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1699 SDValue Q1 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1702 SDValue Q2 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1705 Chain = SDValue(VLdLn, 3);
1706 ReplaceUses(SDValue(N, 0), Q0);
1707 ReplaceUses(SDValue(N, 1), Q1);
1708 ReplaceUses(SDValue(N, 2), Q2);
1709 ReplaceUses(SDValue(N, 3), Chain);
1713 case Intrinsic::arm_neon_vld4lane: {
1714 SDValue MemAddr, MemUpdate, MemOpc;
1715 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1717 if (VT.is64BitVector()) {
1718 switch (VT.getSimpleVT().SimpleTy) {
1719 default: llvm_unreachable("unhandled vld4lane type");
1720 case MVT::v8i8: Opc = ARM::VLD4LNd8; break;
1721 case MVT::v4i16: Opc = ARM::VLD4LNd16; break;
1723 case MVT::v2i32: Opc = ARM::VLD4LNd32; break;
1725 SDValue Chain = N->getOperand(0);
1726 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1727 N->getOperand(3), N->getOperand(4),
1728 N->getOperand(5), N->getOperand(6),
1729 N->getOperand(7), Chain };
1730 std::vector<EVT> ResTys(4, VT);
1731 ResTys.push_back(MVT::Other);
1732 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 9);
1734 // Quad registers are handled by extracting subregs, doing the load,
1735 // and then inserting the results as subregs.
1738 switch (VT.getSimpleVT().SimpleTy) {
1739 default: llvm_unreachable("unhandled vld4lane type");
1741 Opc = ARM::VLD4LNq16a;
1742 Opc2 = ARM::VLD4LNq16b;
1746 Opc = ARM::VLD4LNq32a;
1747 Opc2 = ARM::VLD4LNq32b;
1751 Opc = ARM::VLD4LNq32a;
1752 Opc2 = ARM::VLD4LNq32b;
1756 SDValue Chain = N->getOperand(0);
1757 unsigned Lane = cast<ConstantSDNode>(N->getOperand(7))->getZExtValue();
1758 unsigned NumElts = RegVT.getVectorNumElements();
1759 int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1761 SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1763 SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1765 SDValue D2 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1767 SDValue D3 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1769 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1, D2, D3,
1770 getI32Imm(Lane % NumElts), Chain };
1771 std::vector<EVT> ResTys(4, RegVT);
1772 ResTys.push_back(MVT::Other);
1773 SDNode *VLdLn = CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
1774 dl, ResTys, Ops, 9);
1775 SDValue Q0 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1778 SDValue Q1 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1781 SDValue Q2 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1784 SDValue Q3 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1787 Chain = SDValue(VLdLn, 4);
1788 ReplaceUses(SDValue(N, 0), Q0);
1789 ReplaceUses(SDValue(N, 1), Q1);
1790 ReplaceUses(SDValue(N, 2), Q2);
1791 ReplaceUses(SDValue(N, 3), Q3);
1792 ReplaceUses(SDValue(N, 4), Chain);
1796 case Intrinsic::arm_neon_vst2: {
1797 SDValue MemAddr, MemUpdate, MemOpc;
1798 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1800 VT = N->getOperand(3).getValueType();
1801 if (VT.is64BitVector()) {
1802 switch (VT.getSimpleVT().SimpleTy) {
1803 default: llvm_unreachable("unhandled vst2 type");
1804 case MVT::v8i8: Opc = ARM::VST2d8; break;
1805 case MVT::v4i16: Opc = ARM::VST2d16; break;
1807 case MVT::v2i32: Opc = ARM::VST2d32; break;
1808 case MVT::v1i64: Opc = ARM::VST2d64; break;
1810 SDValue Chain = N->getOperand(0);
1811 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1812 N->getOperand(3), N->getOperand(4), Chain };
1813 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6);
1815 // Quad registers are stored as pairs of double registers.
1817 switch (VT.getSimpleVT().SimpleTy) {
1818 default: llvm_unreachable("unhandled vst2 type");
1819 case MVT::v16i8: Opc = ARM::VST2q8; RegVT = MVT::v8i8; break;
1820 case MVT::v8i16: Opc = ARM::VST2q16; RegVT = MVT::v4i16; break;
1821 case MVT::v4f32: Opc = ARM::VST2q32; RegVT = MVT::v2f32; break;
1822 case MVT::v4i32: Opc = ARM::VST2q32; RegVT = MVT::v2i32; break;
1824 SDValue Chain = N->getOperand(0);
1825 SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1827 SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1829 SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1831 SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1833 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1834 D0, D1, D2, D3, Chain };
1835 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
1838 case Intrinsic::arm_neon_vst3: {
1839 SDValue MemAddr, MemUpdate, MemOpc;
1840 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1842 VT = N->getOperand(3).getValueType();
1843 if (VT.is64BitVector()) {
1844 switch (VT.getSimpleVT().SimpleTy) {
1845 default: llvm_unreachable("unhandled vst3 type");
1846 case MVT::v8i8: Opc = ARM::VST3d8; break;
1847 case MVT::v4i16: Opc = ARM::VST3d16; break;
1849 case MVT::v2i32: Opc = ARM::VST3d32; break;
1850 case MVT::v1i64: Opc = ARM::VST3d64; break;
1852 SDValue Chain = N->getOperand(0);
1853 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1854 N->getOperand(3), N->getOperand(4),
1855 N->getOperand(5), Chain };
1856 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
1858 // Quad registers are stored with two separate instructions, where one
1859 // stores the even registers and the other stores the odd registers.
1862 switch (VT.getSimpleVT().SimpleTy) {
1863 default: llvm_unreachable("unhandled vst3 type");
1865 Opc = ARM::VST3q8a; Opc2 = ARM::VST3q8b; RegVT = MVT::v8i8; break;
1867 Opc = ARM::VST3q16a; Opc2 = ARM::VST3q16b; RegVT = MVT::v4i16; break;
1869 Opc = ARM::VST3q32a; Opc2 = ARM::VST3q32b; RegVT = MVT::v2f32; break;
1871 Opc = ARM::VST3q32a; Opc2 = ARM::VST3q32b; RegVT = MVT::v2i32; break;
1873 SDValue Chain = N->getOperand(0);
1874 // Enable writeback to the address register.
1875 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1877 SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1879 SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1881 SDValue D4 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1883 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, D0, D2, D4, Chain };
1884 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1885 MVT::Other, OpsA, 7);
1886 Chain = SDValue(VStA, 1);
1888 SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1890 SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1892 SDValue D5 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1894 MemAddr = SDValue(VStA, 0);
1895 const SDValue OpsB[] = { MemAddr, MemUpdate, MemOpc, D1, D3, D5, Chain };
1896 SDNode *VStB = CurDAG->getMachineNode(Opc2, dl, MemAddr.getValueType(),
1897 MVT::Other, OpsB, 7);
1898 Chain = SDValue(VStB, 1);
1899 ReplaceUses(SDValue(N, 0), Chain);
1903 case Intrinsic::arm_neon_vst4: {
1904 SDValue MemAddr, MemUpdate, MemOpc;
1905 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1907 VT = N->getOperand(3).getValueType();
1908 if (VT.is64BitVector()) {
1909 switch (VT.getSimpleVT().SimpleTy) {
1910 default: llvm_unreachable("unhandled vst4 type");
1911 case MVT::v8i8: Opc = ARM::VST4d8; break;
1912 case MVT::v4i16: Opc = ARM::VST4d16; break;
1914 case MVT::v2i32: Opc = ARM::VST4d32; break;
1915 case MVT::v1i64: Opc = ARM::VST4d64; break;
1917 SDValue Chain = N->getOperand(0);
1918 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1919 N->getOperand(3), N->getOperand(4),
1920 N->getOperand(5), N->getOperand(6), Chain };
1921 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
1923 // Quad registers are stored with two separate instructions, where one
1924 // stores the even registers and the other stores the odd registers.
1927 switch (VT.getSimpleVT().SimpleTy) {
1928 default: llvm_unreachable("unhandled vst4 type");
1930 Opc = ARM::VST4q8a; Opc2 = ARM::VST4q8b; RegVT = MVT::v8i8; break;
1932 Opc = ARM::VST4q16a; Opc2 = ARM::VST4q16b; RegVT = MVT::v4i16; break;
1934 Opc = ARM::VST4q32a; Opc2 = ARM::VST4q32b; RegVT = MVT::v2f32; break;
1936 Opc = ARM::VST4q32a; Opc2 = ARM::VST4q32b; RegVT = MVT::v2i32; break;
1938 SDValue Chain = N->getOperand(0);
1939 // Enable writeback to the address register.
1940 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1942 SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1944 SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1946 SDValue D4 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1948 SDValue D6 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1950 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc,
1951 D0, D2, D4, D6, Chain };
1952 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1953 MVT::Other, OpsA, 8);
1954 Chain = SDValue(VStA, 1);
1956 SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1958 SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1960 SDValue D5 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1962 SDValue D7 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1964 MemAddr = SDValue(VStA, 0);
1965 const SDValue OpsB[] = { MemAddr, MemUpdate, MemOpc,
1966 D1, D3, D5, D7, Chain };
1967 SDNode *VStB = CurDAG->getMachineNode(Opc2, dl, MemAddr.getValueType(),
1968 MVT::Other, OpsB, 8);
1969 Chain = SDValue(VStB, 1);
1970 ReplaceUses(SDValue(N, 0), Chain);
1974 case Intrinsic::arm_neon_vst2lane: {
1975 SDValue MemAddr, MemUpdate, MemOpc;
1976 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1978 VT = N->getOperand(3).getValueType();
1979 if (VT.is64BitVector()) {
1980 switch (VT.getSimpleVT().SimpleTy) {
1981 default: llvm_unreachable("unhandled vst2lane type");
1982 case MVT::v8i8: Opc = ARM::VST2LNd8; break;
1983 case MVT::v4i16: Opc = ARM::VST2LNd16; break;
1985 case MVT::v2i32: Opc = ARM::VST2LNd32; break;
1987 SDValue Chain = N->getOperand(0);
1988 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1989 N->getOperand(3), N->getOperand(4),
1990 N->getOperand(5), Chain };
1991 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
1993 // Quad registers are handled by extracting subregs and then doing
1997 switch (VT.getSimpleVT().SimpleTy) {
1998 default: llvm_unreachable("unhandled vst2lane type");
2000 Opc = ARM::VST2LNq16a;
2001 Opc2 = ARM::VST2LNq16b;
2005 Opc = ARM::VST2LNq32a;
2006 Opc2 = ARM::VST2LNq32b;
2010 Opc = ARM::VST2LNq32a;
2011 Opc2 = ARM::VST2LNq32b;
2015 SDValue Chain = N->getOperand(0);
2016 unsigned Lane = cast<ConstantSDNode>(N->getOperand(5))->getZExtValue();
2017 unsigned NumElts = RegVT.getVectorNumElements();
2018 int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
2020 SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
2022 SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
2024 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1,
2025 getI32Imm(Lane % NumElts), Chain };
2026 return CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
2027 dl, MVT::Other, Ops, 7);
2030 case Intrinsic::arm_neon_vst3lane: {
2031 SDValue MemAddr, MemUpdate, MemOpc;
2032 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
2034 VT = N->getOperand(3).getValueType();
2035 if (VT.is64BitVector()) {
2036 switch (VT.getSimpleVT().SimpleTy) {
2037 default: llvm_unreachable("unhandled vst3lane type");
2038 case MVT::v8i8: Opc = ARM::VST3LNd8; break;
2039 case MVT::v4i16: Opc = ARM::VST3LNd16; break;
2041 case MVT::v2i32: Opc = ARM::VST3LNd32; break;
2043 SDValue Chain = N->getOperand(0);
2044 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
2045 N->getOperand(3), N->getOperand(4),
2046 N->getOperand(5), N->getOperand(6), Chain };
2047 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
2049 // Quad registers are handled by extracting subregs and then doing
2053 switch (VT.getSimpleVT().SimpleTy) {
2054 default: llvm_unreachable("unhandled vst3lane type");
2056 Opc = ARM::VST3LNq16a;
2057 Opc2 = ARM::VST3LNq16b;
2061 Opc = ARM::VST3LNq32a;
2062 Opc2 = ARM::VST3LNq32b;
2066 Opc = ARM::VST3LNq32a;
2067 Opc2 = ARM::VST3LNq32b;
2071 SDValue Chain = N->getOperand(0);
2072 unsigned Lane = cast<ConstantSDNode>(N->getOperand(6))->getZExtValue();
2073 unsigned NumElts = RegVT.getVectorNumElements();
2074 int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
2076 SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
2078 SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
2080 SDValue D2 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
2082 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1, D2,
2083 getI32Imm(Lane % NumElts), Chain };
2084 return CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
2085 dl, MVT::Other, Ops, 8);
2088 case Intrinsic::arm_neon_vst4lane: {
2089 SDValue MemAddr, MemUpdate, MemOpc;
2090 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
2092 VT = N->getOperand(3).getValueType();
2093 if (VT.is64BitVector()) {
2094 switch (VT.getSimpleVT().SimpleTy) {
2095 default: llvm_unreachable("unhandled vst4lane type");
2096 case MVT::v8i8: Opc = ARM::VST4LNd8; break;
2097 case MVT::v4i16: Opc = ARM::VST4LNd16; break;
2099 case MVT::v2i32: Opc = ARM::VST4LNd32; break;
2101 SDValue Chain = N->getOperand(0);
2102 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
2103 N->getOperand(3), N->getOperand(4),
2104 N->getOperand(5), N->getOperand(6),
2105 N->getOperand(7), Chain };
2106 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 9);
2108 // Quad registers are handled by extracting subregs and then doing
2112 switch (VT.getSimpleVT().SimpleTy) {
2113 default: llvm_unreachable("unhandled vst4lane type");
2115 Opc = ARM::VST4LNq16a;
2116 Opc2 = ARM::VST4LNq16b;
2120 Opc = ARM::VST4LNq32a;
2121 Opc2 = ARM::VST4LNq32b;
2125 Opc = ARM::VST4LNq32a;
2126 Opc2 = ARM::VST4LNq32b;
2130 SDValue Chain = N->getOperand(0);
2131 unsigned Lane = cast<ConstantSDNode>(N->getOperand(7))->getZExtValue();
2132 unsigned NumElts = RegVT.getVectorNumElements();
2133 int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
2135 SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
2137 SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
2139 SDValue D2 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
2141 SDValue D3 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
2143 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1, D2, D3,
2144 getI32Imm(Lane % NumElts), Chain };
2145 return CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
2146 dl, MVT::Other, Ops, 9);
2152 return SelectCode(Op);
2155 bool ARMDAGToDAGISel::
2156 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2157 std::vector<SDValue> &OutOps) {
2158 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2160 SDValue Base, Offset, Opc;
2161 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
2164 OutOps.push_back(Base);
2165 OutOps.push_back(Offset);
2166 OutOps.push_back(Opc);
2170 /// createARMISelDag - This pass converts a legalized DAG into a
2171 /// ARM-specific DAG, ready for instruction scheduling.
2173 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2174 CodeGenOpt::Level OptLevel) {
2175 return new ARMDAGToDAGISel(TM, OptLevel);