1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/DataLayout.h"
34 #include "llvm/DerivedTypes.h"
35 #include "llvm/GlobalVariable.h"
36 #include "llvm/Instructions.h"
37 #include "llvm/IntrinsicInst.h"
38 #include "llvm/Module.h"
39 #include "llvm/Operator.h"
40 #include "llvm/Support/CallSite.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/GetElementPtrTypeIterator.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
50 extern cl::opt<bool> EnableARMLongCalls;
54 // All possible address modes, plus some.
55 typedef struct Address {
68 // Innocuous defaults for our address.
70 : BaseType(RegBase), Offset(0) {
75 class ARMFastISel : public FastISel {
77 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
78 /// make the right decision when generating code for different targets.
79 const ARMSubtarget *Subtarget;
80 const TargetMachine &TM;
81 const TargetInstrInfo &TII;
82 const TargetLowering &TLI;
85 // Convenience variables to avoid some queries.
90 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
91 const TargetLibraryInfo *libInfo)
92 : FastISel(funcInfo, libInfo),
93 TM(funcInfo.MF->getTarget()),
94 TII(*TM.getInstrInfo()),
95 TLI(*TM.getTargetLowering()) {
96 Subtarget = &TM.getSubtarget<ARMSubtarget>();
97 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
98 isThumb2 = AFI->isThumbFunction();
99 Context = &funcInfo.Fn->getContext();
102 // Code from FastISel.cpp.
104 unsigned FastEmitInst_(unsigned MachineInstOpcode,
105 const TargetRegisterClass *RC);
106 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
107 const TargetRegisterClass *RC,
108 unsigned Op0, bool Op0IsKill);
109 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
110 const TargetRegisterClass *RC,
111 unsigned Op0, bool Op0IsKill,
112 unsigned Op1, bool Op1IsKill);
113 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
114 const TargetRegisterClass *RC,
115 unsigned Op0, bool Op0IsKill,
116 unsigned Op1, bool Op1IsKill,
117 unsigned Op2, bool Op2IsKill);
118 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill,
122 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
123 const TargetRegisterClass *RC,
124 unsigned Op0, bool Op0IsKill,
125 const ConstantFP *FPImm);
126 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
127 const TargetRegisterClass *RC,
128 unsigned Op0, bool Op0IsKill,
129 unsigned Op1, bool Op1IsKill,
131 unsigned FastEmitInst_i(unsigned MachineInstOpcode,
132 const TargetRegisterClass *RC,
134 unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
135 const TargetRegisterClass *RC,
136 uint64_t Imm1, uint64_t Imm2);
138 unsigned FastEmitInst_extractsubreg(MVT RetVT,
139 unsigned Op0, bool Op0IsKill,
142 // Backend specific FastISel code.
144 virtual bool TargetSelectInstruction(const Instruction *I);
145 virtual unsigned TargetMaterializeConstant(const Constant *C);
146 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
147 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
150 #include "ARMGenFastISel.inc"
152 // Instruction selection routines.
154 bool SelectLoad(const Instruction *I);
155 bool SelectStore(const Instruction *I);
156 bool SelectBranch(const Instruction *I);
157 bool SelectIndirectBr(const Instruction *I);
158 bool SelectCmp(const Instruction *I);
159 bool SelectFPExt(const Instruction *I);
160 bool SelectFPTrunc(const Instruction *I);
161 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
162 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
163 bool SelectIToFP(const Instruction *I, bool isSigned);
164 bool SelectFPToI(const Instruction *I, bool isSigned);
165 bool SelectDiv(const Instruction *I, bool isSigned);
166 bool SelectRem(const Instruction *I, bool isSigned);
167 bool SelectCall(const Instruction *I, const char *IntrMemName);
168 bool SelectIntrinsicCall(const IntrinsicInst &I);
169 bool SelectSelect(const Instruction *I);
170 bool SelectRet(const Instruction *I);
171 bool SelectTrunc(const Instruction *I);
172 bool SelectIntExt(const Instruction *I);
173 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
177 bool isTypeLegal(Type *Ty, MVT &VT);
178 bool isLoadTypeLegal(Type *Ty, MVT &VT);
179 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
181 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
182 unsigned Alignment = 0, bool isZExt = true,
183 bool allocReg = true);
184 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
185 unsigned Alignment = 0);
186 bool ARMComputeAddress(const Value *Obj, Address &Addr);
187 void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
188 bool ARMIsMemCpySmall(uint64_t Len);
189 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len);
190 unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
191 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
192 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
193 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
194 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
195 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
196 unsigned ARMSelectCallOp(bool UseReg);
197 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, EVT VT);
199 // Call handling routines.
201 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
204 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
205 SmallVectorImpl<unsigned> &ArgRegs,
206 SmallVectorImpl<MVT> &ArgVTs,
207 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
208 SmallVectorImpl<unsigned> &RegArgs,
212 unsigned getLibcallReg(const Twine &Name);
213 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
214 const Instruction *I, CallingConv::ID CC,
215 unsigned &NumBytes, bool isVarArg);
216 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
218 // OptionalDef handling routines.
220 bool isARMNEONPred(const MachineInstr *MI);
221 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
222 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
223 void AddLoadStoreOperands(EVT VT, Address &Addr,
224 const MachineInstrBuilder &MIB,
225 unsigned Flags, bool useAM3);
228 } // end anonymous namespace
230 #include "ARMGenCallingConv.inc"
232 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
233 // we don't care about implicit defs here, just places we'll need to add a
234 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
235 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
236 if (!MI->hasOptionalDef())
239 // Look to see if our OptionalDef is defining CPSR or CCR.
240 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
241 const MachineOperand &MO = MI->getOperand(i);
242 if (!MO.isReg() || !MO.isDef()) continue;
243 if (MO.getReg() == ARM::CPSR)
249 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
250 const MCInstrDesc &MCID = MI->getDesc();
252 // If we're a thumb2 or not NEON function we were handled via isPredicable.
253 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
254 AFI->isThumb2Function())
257 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
258 if (MCID.OpInfo[i].isPredicate())
264 // If the machine is predicable go ahead and add the predicate operands, if
265 // it needs default CC operands add those.
266 // TODO: If we want to support thumb1 then we'll need to deal with optional
267 // CPSR defs that need to be added before the remaining operands. See s_cc_out
268 // for descriptions why.
269 const MachineInstrBuilder &
270 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
271 MachineInstr *MI = &*MIB;
273 // Do we use a predicate? or...
274 // Are we NEON in ARM mode and have a predicate operand? If so, I know
275 // we're not predicable but add it anyways.
276 if (TII.isPredicable(MI) || isARMNEONPred(MI))
279 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
280 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
282 if (DefinesOptionalPredicate(MI, &CPSR)) {
291 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
292 const TargetRegisterClass* RC) {
293 unsigned ResultReg = createResultReg(RC);
294 const MCInstrDesc &II = TII.get(MachineInstOpcode);
296 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
300 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
301 const TargetRegisterClass *RC,
302 unsigned Op0, bool Op0IsKill) {
303 unsigned ResultReg = createResultReg(RC);
304 const MCInstrDesc &II = TII.get(MachineInstOpcode);
306 if (II.getNumDefs() >= 1) {
307 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
308 .addReg(Op0, Op0IsKill * RegState::Kill));
310 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
311 .addReg(Op0, Op0IsKill * RegState::Kill));
312 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
313 TII.get(TargetOpcode::COPY), ResultReg)
314 .addReg(II.ImplicitDefs[0]));
319 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
320 const TargetRegisterClass *RC,
321 unsigned Op0, bool Op0IsKill,
322 unsigned Op1, bool Op1IsKill) {
323 unsigned ResultReg = createResultReg(RC);
324 const MCInstrDesc &II = TII.get(MachineInstOpcode);
326 if (II.getNumDefs() >= 1) {
327 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
328 .addReg(Op0, Op0IsKill * RegState::Kill)
329 .addReg(Op1, Op1IsKill * RegState::Kill));
331 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
332 .addReg(Op0, Op0IsKill * RegState::Kill)
333 .addReg(Op1, Op1IsKill * RegState::Kill));
334 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
335 TII.get(TargetOpcode::COPY), ResultReg)
336 .addReg(II.ImplicitDefs[0]));
341 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
342 const TargetRegisterClass *RC,
343 unsigned Op0, bool Op0IsKill,
344 unsigned Op1, bool Op1IsKill,
345 unsigned Op2, bool Op2IsKill) {
346 unsigned ResultReg = createResultReg(RC);
347 const MCInstrDesc &II = TII.get(MachineInstOpcode);
349 if (II.getNumDefs() >= 1) {
350 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
351 .addReg(Op0, Op0IsKill * RegState::Kill)
352 .addReg(Op1, Op1IsKill * RegState::Kill)
353 .addReg(Op2, Op2IsKill * RegState::Kill));
355 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
356 .addReg(Op0, Op0IsKill * RegState::Kill)
357 .addReg(Op1, Op1IsKill * RegState::Kill)
358 .addReg(Op2, Op2IsKill * RegState::Kill));
359 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
360 TII.get(TargetOpcode::COPY), ResultReg)
361 .addReg(II.ImplicitDefs[0]));
366 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
367 const TargetRegisterClass *RC,
368 unsigned Op0, bool Op0IsKill,
370 unsigned ResultReg = createResultReg(RC);
371 const MCInstrDesc &II = TII.get(MachineInstOpcode);
373 if (II.getNumDefs() >= 1) {
374 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
375 .addReg(Op0, Op0IsKill * RegState::Kill)
378 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
379 .addReg(Op0, Op0IsKill * RegState::Kill)
381 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
382 TII.get(TargetOpcode::COPY), ResultReg)
383 .addReg(II.ImplicitDefs[0]));
388 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
389 const TargetRegisterClass *RC,
390 unsigned Op0, bool Op0IsKill,
391 const ConstantFP *FPImm) {
392 unsigned ResultReg = createResultReg(RC);
393 const MCInstrDesc &II = TII.get(MachineInstOpcode);
395 if (II.getNumDefs() >= 1) {
396 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
397 .addReg(Op0, Op0IsKill * RegState::Kill)
400 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
401 .addReg(Op0, Op0IsKill * RegState::Kill)
403 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
404 TII.get(TargetOpcode::COPY), ResultReg)
405 .addReg(II.ImplicitDefs[0]));
410 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
411 const TargetRegisterClass *RC,
412 unsigned Op0, bool Op0IsKill,
413 unsigned Op1, bool Op1IsKill,
415 unsigned ResultReg = createResultReg(RC);
416 const MCInstrDesc &II = TII.get(MachineInstOpcode);
418 if (II.getNumDefs() >= 1) {
419 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
420 .addReg(Op0, Op0IsKill * RegState::Kill)
421 .addReg(Op1, Op1IsKill * RegState::Kill)
424 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
425 .addReg(Op0, Op0IsKill * RegState::Kill)
426 .addReg(Op1, Op1IsKill * RegState::Kill)
428 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
429 TII.get(TargetOpcode::COPY), ResultReg)
430 .addReg(II.ImplicitDefs[0]));
435 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
436 const TargetRegisterClass *RC,
438 unsigned ResultReg = createResultReg(RC);
439 const MCInstrDesc &II = TII.get(MachineInstOpcode);
441 if (II.getNumDefs() >= 1) {
442 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
445 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
447 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
448 TII.get(TargetOpcode::COPY), ResultReg)
449 .addReg(II.ImplicitDefs[0]));
454 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
455 const TargetRegisterClass *RC,
456 uint64_t Imm1, uint64_t Imm2) {
457 unsigned ResultReg = createResultReg(RC);
458 const MCInstrDesc &II = TII.get(MachineInstOpcode);
460 if (II.getNumDefs() >= 1) {
461 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
462 .addImm(Imm1).addImm(Imm2));
464 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
465 .addImm(Imm1).addImm(Imm2));
466 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
467 TII.get(TargetOpcode::COPY),
469 .addReg(II.ImplicitDefs[0]));
474 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
475 unsigned Op0, bool Op0IsKill,
477 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
478 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
479 "Cannot yet extract from physregs");
481 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
482 DL, TII.get(TargetOpcode::COPY), ResultReg)
483 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
487 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
488 // checks from the various callers.
489 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
490 if (VT == MVT::f64) return 0;
492 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
493 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
494 TII.get(ARM::VMOVSR), MoveReg)
499 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
500 if (VT == MVT::i64) return 0;
502 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
503 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
504 TII.get(ARM::VMOVRS), MoveReg)
509 // For double width floating point we need to materialize two constants
510 // (the high and the low) into integer registers then use a move to get
511 // the combined constant into an FP reg.
512 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
513 const APFloat Val = CFP->getValueAPF();
514 bool is64bit = VT == MVT::f64;
516 // This checks to see if we can use VFP3 instructions to materialize
517 // a constant, otherwise we have to go through the constant pool.
518 if (TLI.isFPImmLegal(Val, VT)) {
522 Imm = ARM_AM::getFP64Imm(Val);
525 Imm = ARM_AM::getFP32Imm(Val);
528 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
529 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
535 // Require VFP2 for loading fp constants.
536 if (!Subtarget->hasVFP2()) return false;
538 // MachineConstantPool wants an explicit alignment.
539 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
541 // TODO: Figure out if this is correct.
542 Align = TD.getTypeAllocSize(CFP->getType());
544 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
545 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
546 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
548 // The extra reg is for addrmode5.
549 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
551 .addConstantPoolIndex(Idx)
556 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
558 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
561 // If we can do this in a single instruction without a constant pool entry
563 const ConstantInt *CI = cast<ConstantInt>(C);
564 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
565 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
566 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
568 unsigned ImmReg = createResultReg(RC);
569 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
570 TII.get(Opc), ImmReg)
571 .addImm(CI->getZExtValue()));
575 // Use MVN to emit negative constants.
576 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
577 unsigned Imm = (unsigned)~(CI->getSExtValue());
578 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
579 (ARM_AM::getSOImmVal(Imm) != -1);
581 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
582 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
583 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
584 TII.get(Opc), ImmReg)
590 // Load from constant pool. For now 32-bit only.
594 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
596 // MachineConstantPool wants an explicit alignment.
597 unsigned Align = TD.getPrefTypeAlignment(C->getType());
599 // TODO: Figure out if this is correct.
600 Align = TD.getTypeAllocSize(C->getType());
602 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
605 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
606 TII.get(ARM::t2LDRpci), DestReg)
607 .addConstantPoolIndex(Idx));
609 // The extra immediate is for addrmode2.
610 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
611 TII.get(ARM::LDRcp), DestReg)
612 .addConstantPoolIndex(Idx)
618 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
619 // For now 32-bit only.
620 if (VT != MVT::i32) return 0;
622 Reloc::Model RelocM = TM.getRelocationModel();
623 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
624 const TargetRegisterClass *RC = isThumb2 ?
625 (const TargetRegisterClass*)&ARM::rGPRRegClass :
626 (const TargetRegisterClass*)&ARM::GPRRegClass;
627 unsigned DestReg = createResultReg(RC);
629 // Use movw+movt when possible, it avoids constant pool entries.
630 // Darwin targets don't support movt with Reloc::Static, see
631 // ARMTargetLowering::LowerGlobalAddressDarwin. Other targets only support
632 // static movt relocations.
633 if (Subtarget->useMovt() &&
634 Subtarget->isTargetDarwin() == (RelocM != Reloc::Static)) {
638 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
640 case Reloc::DynamicNoPIC:
641 Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn;
644 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
647 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
648 DestReg).addGlobalAddress(GV));
650 // MachineConstantPool wants an explicit alignment.
651 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
653 // TODO: Figure out if this is correct.
654 Align = TD.getTypeAllocSize(GV->getType());
657 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
658 return ARMLowerPICELF(GV, Align, VT);
661 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
662 (Subtarget->isThumb() ? 4 : 8);
663 unsigned Id = AFI->createPICLabelUId();
664 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
667 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
670 MachineInstrBuilder MIB;
672 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
673 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
674 .addConstantPoolIndex(Idx);
675 if (RelocM == Reloc::PIC_)
677 AddOptionalDefs(MIB);
679 // The extra immediate is for addrmode2.
680 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
682 .addConstantPoolIndex(Idx)
684 AddOptionalDefs(MIB);
686 if (RelocM == Reloc::PIC_) {
687 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
688 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
690 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
691 DL, TII.get(Opc), NewDestReg)
694 AddOptionalDefs(MIB);
701 MachineInstrBuilder MIB;
702 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
704 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
705 TII.get(ARM::t2LDRi12), NewDestReg)
709 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
713 DestReg = NewDestReg;
714 AddOptionalDefs(MIB);
720 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
721 EVT VT = TLI.getValueType(C->getType(), true);
723 // Only handle simple types.
724 if (!VT.isSimple()) return 0;
726 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
727 return ARMMaterializeFP(CFP, VT);
728 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
729 return ARMMaterializeGV(GV, VT);
730 else if (isa<ConstantInt>(C))
731 return ARMMaterializeInt(C, VT);
736 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
738 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
739 // Don't handle dynamic allocas.
740 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
743 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
745 DenseMap<const AllocaInst*, int>::iterator SI =
746 FuncInfo.StaticAllocaMap.find(AI);
748 // This will get lowered later into the correct offsets and registers
749 // via rewriteXFrameIndex.
750 if (SI != FuncInfo.StaticAllocaMap.end()) {
751 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
752 unsigned ResultReg = createResultReg(RC);
753 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
754 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
755 TII.get(Opc), ResultReg)
756 .addFrameIndex(SI->second)
764 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
765 EVT evt = TLI.getValueType(Ty, true);
767 // Only handle simple types.
768 if (evt == MVT::Other || !evt.isSimple()) return false;
769 VT = evt.getSimpleVT();
771 // Handle all legal types, i.e. a register that will directly hold this
773 return TLI.isTypeLegal(VT);
776 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
777 if (isTypeLegal(Ty, VT)) return true;
779 // If this is a type than can be sign or zero-extended to a basic operation
780 // go ahead and accept it now.
781 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
787 // Computes the address to get to an object.
788 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
789 // Some boilerplate from the X86 FastISel.
790 const User *U = NULL;
791 unsigned Opcode = Instruction::UserOp1;
792 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
793 // Don't walk into other basic blocks unless the object is an alloca from
794 // another block, otherwise it may not have a virtual register assigned.
795 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
796 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
797 Opcode = I->getOpcode();
800 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
801 Opcode = C->getOpcode();
805 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
806 if (Ty->getAddressSpace() > 255)
807 // Fast instruction selection doesn't support the special
814 case Instruction::BitCast: {
815 // Look through bitcasts.
816 return ARMComputeAddress(U->getOperand(0), Addr);
818 case Instruction::IntToPtr: {
819 // Look past no-op inttoptrs.
820 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
821 return ARMComputeAddress(U->getOperand(0), Addr);
824 case Instruction::PtrToInt: {
825 // Look past no-op ptrtoints.
826 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
827 return ARMComputeAddress(U->getOperand(0), Addr);
830 case Instruction::GetElementPtr: {
831 Address SavedAddr = Addr;
832 int TmpOffset = Addr.Offset;
834 // Iterate through the GEP folding the constants into offsets where
836 gep_type_iterator GTI = gep_type_begin(U);
837 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
838 i != e; ++i, ++GTI) {
839 const Value *Op = *i;
840 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
841 const StructLayout *SL = TD.getStructLayout(STy);
842 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
843 TmpOffset += SL->getElementOffset(Idx);
845 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
847 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
848 // Constant-offset addressing.
849 TmpOffset += CI->getSExtValue() * S;
852 if (isa<AddOperator>(Op) &&
853 (!isa<Instruction>(Op) ||
854 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
856 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
857 // An add (in the same block) with a constant operand. Fold the
860 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
861 TmpOffset += CI->getSExtValue() * S;
862 // Iterate on the other operand.
863 Op = cast<AddOperator>(Op)->getOperand(0);
867 goto unsupported_gep;
872 // Try to grab the base operand now.
873 Addr.Offset = TmpOffset;
874 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
876 // We failed, restore everything and try the other options.
882 case Instruction::Alloca: {
883 const AllocaInst *AI = cast<AllocaInst>(Obj);
884 DenseMap<const AllocaInst*, int>::iterator SI =
885 FuncInfo.StaticAllocaMap.find(AI);
886 if (SI != FuncInfo.StaticAllocaMap.end()) {
887 Addr.BaseType = Address::FrameIndexBase;
888 Addr.Base.FI = SI->second;
895 // Try to get this in a register if nothing else has worked.
896 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
897 return Addr.Base.Reg != 0;
900 void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
902 assert(VT.isSimple() && "Non-simple types are invalid here!");
904 bool needsLowering = false;
905 switch (VT.getSimpleVT().SimpleTy) {
906 default: llvm_unreachable("Unhandled load/store type!");
912 // Integer loads/stores handle 12-bit offsets.
913 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
914 // Handle negative offsets.
915 if (needsLowering && isThumb2)
916 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
919 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
920 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
925 // Floating point operands handle 8-bit offsets.
926 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
930 // If this is a stack pointer and the offset needs to be simplified then
931 // put the alloca address into a register, set the base type back to
932 // register and continue. This should almost never happen.
933 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
934 const TargetRegisterClass *RC = isThumb2 ?
935 (const TargetRegisterClass*)&ARM::tGPRRegClass :
936 (const TargetRegisterClass*)&ARM::GPRRegClass;
937 unsigned ResultReg = createResultReg(RC);
938 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
939 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
940 TII.get(Opc), ResultReg)
941 .addFrameIndex(Addr.Base.FI)
943 Addr.Base.Reg = ResultReg;
944 Addr.BaseType = Address::RegBase;
947 // Since the offset is too large for the load/store instruction
948 // get the reg+offset into a register.
950 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
951 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
956 void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
957 const MachineInstrBuilder &MIB,
958 unsigned Flags, bool useAM3) {
959 // addrmode5 output depends on the selection dag addressing dividing the
960 // offset by 4 that it then later multiplies. Do this here as well.
961 if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
962 VT.getSimpleVT().SimpleTy == MVT::f64)
965 // Frame base works a bit differently. Handle it separately.
966 if (Addr.BaseType == Address::FrameIndexBase) {
967 int FI = Addr.Base.FI;
968 int Offset = Addr.Offset;
969 MachineMemOperand *MMO =
970 FuncInfo.MF->getMachineMemOperand(
971 MachinePointerInfo::getFixedStack(FI, Offset),
973 MFI.getObjectSize(FI),
974 MFI.getObjectAlignment(FI));
975 // Now add the rest of the operands.
976 MIB.addFrameIndex(FI);
978 // ARM halfword load/stores and signed byte loads need an additional
981 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
985 MIB.addImm(Addr.Offset);
987 MIB.addMemOperand(MMO);
989 // Now add the rest of the operands.
990 MIB.addReg(Addr.Base.Reg);
992 // ARM halfword load/stores and signed byte loads need an additional
995 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
999 MIB.addImm(Addr.Offset);
1002 AddOptionalDefs(MIB);
1005 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
1006 unsigned Alignment, bool isZExt, bool allocReg) {
1007 assert(VT.isSimple() && "Non-simple types are invalid here!");
1009 bool useAM3 = false;
1010 bool needVMOV = false;
1011 const TargetRegisterClass *RC;
1012 switch (VT.getSimpleVT().SimpleTy) {
1013 // This is mostly going to be Neon/vector support.
1014 default: return false;
1018 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1019 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
1021 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
1030 RC = &ARM::GPRRegClass;
1033 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1037 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1038 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1040 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1042 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1045 RC = &ARM::GPRRegClass;
1048 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1052 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1055 Opc = ARM::t2LDRi12;
1059 RC = &ARM::GPRRegClass;
1062 if (!Subtarget->hasVFP2()) return false;
1063 // Unaligned loads need special handling. Floats require word-alignment.
1064 if (Alignment && Alignment < 4) {
1067 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1068 RC = &ARM::GPRRegClass;
1071 RC = TLI.getRegClassFor(VT);
1075 if (!Subtarget->hasVFP2()) return false;
1076 // FIXME: Unaligned loads need special handling. Doublewords require
1078 if (Alignment && Alignment < 4)
1082 RC = TLI.getRegClassFor(VT);
1085 // Simplify this down to something we can handle.
1086 ARMSimplifyAddress(Addr, VT, useAM3);
1088 // Create the base instruction, then add the operands.
1090 ResultReg = createResultReg(RC);
1091 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1092 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1093 TII.get(Opc), ResultReg);
1094 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1096 // If we had an unaligned load of a float we've converted it to an regular
1097 // load. Now we must move from the GRP to the FP register.
1099 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1100 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1101 TII.get(ARM::VMOVSR), MoveReg)
1102 .addReg(ResultReg));
1103 ResultReg = MoveReg;
1108 bool ARMFastISel::SelectLoad(const Instruction *I) {
1109 // Atomic loads need special handling.
1110 if (cast<LoadInst>(I)->isAtomic())
1113 // Verify we have a legal type before going any further.
1115 if (!isLoadTypeLegal(I->getType(), VT))
1118 // See if we can handle this address.
1120 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1123 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1125 UpdateValueMap(I, ResultReg);
1129 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
1130 unsigned Alignment) {
1132 bool useAM3 = false;
1133 switch (VT.getSimpleVT().SimpleTy) {
1134 // This is mostly going to be Neon/vector support.
1135 default: return false;
1137 unsigned Res = createResultReg(isThumb2 ?
1138 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1139 (const TargetRegisterClass*)&ARM::GPRRegClass);
1140 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1141 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1143 .addReg(SrcReg).addImm(1));
1145 } // Fallthrough here.
1148 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1149 StrOpc = ARM::t2STRBi8;
1151 StrOpc = ARM::t2STRBi12;
1153 StrOpc = ARM::STRBi12;
1157 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1161 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1162 StrOpc = ARM::t2STRHi8;
1164 StrOpc = ARM::t2STRHi12;
1171 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1175 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1176 StrOpc = ARM::t2STRi8;
1178 StrOpc = ARM::t2STRi12;
1180 StrOpc = ARM::STRi12;
1184 if (!Subtarget->hasVFP2()) return false;
1185 // Unaligned stores need special handling. Floats require word-alignment.
1186 if (Alignment && Alignment < 4) {
1187 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1188 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1189 TII.get(ARM::VMOVRS), MoveReg)
1193 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1195 StrOpc = ARM::VSTRS;
1199 if (!Subtarget->hasVFP2()) return false;
1200 // FIXME: Unaligned stores need special handling. Doublewords require
1202 if (Alignment && Alignment < 4)
1205 StrOpc = ARM::VSTRD;
1208 // Simplify this down to something we can handle.
1209 ARMSimplifyAddress(Addr, VT, useAM3);
1211 // Create the base instruction, then add the operands.
1212 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1215 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1219 bool ARMFastISel::SelectStore(const Instruction *I) {
1220 Value *Op0 = I->getOperand(0);
1221 unsigned SrcReg = 0;
1223 // Atomic stores need special handling.
1224 if (cast<StoreInst>(I)->isAtomic())
1227 // Verify we have a legal type before going any further.
1229 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1232 // Get the value to be stored into a register.
1233 SrcReg = getRegForValue(Op0);
1234 if (SrcReg == 0) return false;
1236 // See if we can handle this address.
1238 if (!ARMComputeAddress(I->getOperand(1), Addr))
1241 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1246 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1248 // Needs two compares...
1249 case CmpInst::FCMP_ONE:
1250 case CmpInst::FCMP_UEQ:
1252 // AL is our "false" for now. The other two need more compares.
1254 case CmpInst::ICMP_EQ:
1255 case CmpInst::FCMP_OEQ:
1257 case CmpInst::ICMP_SGT:
1258 case CmpInst::FCMP_OGT:
1260 case CmpInst::ICMP_SGE:
1261 case CmpInst::FCMP_OGE:
1263 case CmpInst::ICMP_UGT:
1264 case CmpInst::FCMP_UGT:
1266 case CmpInst::FCMP_OLT:
1268 case CmpInst::ICMP_ULE:
1269 case CmpInst::FCMP_OLE:
1271 case CmpInst::FCMP_ORD:
1273 case CmpInst::FCMP_UNO:
1275 case CmpInst::FCMP_UGE:
1277 case CmpInst::ICMP_SLT:
1278 case CmpInst::FCMP_ULT:
1280 case CmpInst::ICMP_SLE:
1281 case CmpInst::FCMP_ULE:
1283 case CmpInst::FCMP_UNE:
1284 case CmpInst::ICMP_NE:
1286 case CmpInst::ICMP_UGE:
1288 case CmpInst::ICMP_ULT:
1293 bool ARMFastISel::SelectBranch(const Instruction *I) {
1294 const BranchInst *BI = cast<BranchInst>(I);
1295 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1296 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1298 // Simple branch support.
1300 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1302 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1303 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1305 // Get the compare predicate.
1306 // Try to take advantage of fallthrough opportunities.
1307 CmpInst::Predicate Predicate = CI->getPredicate();
1308 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1309 std::swap(TBB, FBB);
1310 Predicate = CmpInst::getInversePredicate(Predicate);
1313 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1315 // We may not handle every CC for now.
1316 if (ARMPred == ARMCC::AL) return false;
1318 // Emit the compare.
1319 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1322 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1323 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1324 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1325 FastEmitBranch(FBB, DL);
1326 FuncInfo.MBB->addSuccessor(TBB);
1329 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1331 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1332 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1333 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1334 unsigned OpReg = getRegForValue(TI->getOperand(0));
1335 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1337 .addReg(OpReg).addImm(1));
1339 unsigned CCMode = ARMCC::NE;
1340 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1341 std::swap(TBB, FBB);
1345 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1346 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1347 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1349 FastEmitBranch(FBB, DL);
1350 FuncInfo.MBB->addSuccessor(TBB);
1353 } else if (const ConstantInt *CI =
1354 dyn_cast<ConstantInt>(BI->getCondition())) {
1355 uint64_t Imm = CI->getZExtValue();
1356 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1357 FastEmitBranch(Target, DL);
1361 unsigned CmpReg = getRegForValue(BI->getCondition());
1362 if (CmpReg == 0) return false;
1364 // We've been divorced from our compare! Our block was split, and
1365 // now our compare lives in a predecessor block. We musn't
1366 // re-compare here, as the children of the compare aren't guaranteed
1367 // live across the block boundary (we *could* check for this).
1368 // Regardless, the compare has been done in the predecessor block,
1369 // and it left a value for us in a virtual register. Ergo, we test
1370 // the one-bit value left in the virtual register.
1371 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1372 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1373 .addReg(CmpReg).addImm(1));
1375 unsigned CCMode = ARMCC::NE;
1376 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1377 std::swap(TBB, FBB);
1381 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1382 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1383 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1384 FastEmitBranch(FBB, DL);
1385 FuncInfo.MBB->addSuccessor(TBB);
1389 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1390 unsigned AddrReg = getRegForValue(I->getOperand(0));
1391 if (AddrReg == 0) return false;
1393 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1394 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
1397 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1398 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1399 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1404 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1406 Type *Ty = Src1Value->getType();
1407 EVT SrcVT = TLI.getValueType(Ty, true);
1408 if (!SrcVT.isSimple()) return false;
1410 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1411 if (isFloat && !Subtarget->hasVFP2())
1414 // Check to see if the 2nd operand is a constant that we can encode directly
1417 bool UseImm = false;
1418 bool isNegativeImm = false;
1419 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1420 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1421 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1422 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1424 const APInt &CIVal = ConstInt->getValue();
1425 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1426 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1427 // then a cmn, because there is no way to represent 2147483648 as a
1428 // signed 32-bit int.
1429 if (Imm < 0 && Imm != (int)0x80000000) {
1430 isNegativeImm = true;
1433 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1434 (ARM_AM::getSOImmVal(Imm) != -1);
1436 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1437 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1438 if (ConstFP->isZero() && !ConstFP->isNegative())
1444 bool needsExt = false;
1445 switch (SrcVT.getSimpleVT().SimpleTy) {
1446 default: return false;
1447 // TODO: Verify compares.
1450 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1454 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1460 // Intentional fall-through.
1464 CmpOpc = ARM::t2CMPrr;
1466 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1469 CmpOpc = ARM::CMPrr;
1471 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1476 unsigned SrcReg1 = getRegForValue(Src1Value);
1477 if (SrcReg1 == 0) return false;
1479 unsigned SrcReg2 = 0;
1481 SrcReg2 = getRegForValue(Src2Value);
1482 if (SrcReg2 == 0) return false;
1485 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1487 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1488 if (SrcReg1 == 0) return false;
1490 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1491 if (SrcReg2 == 0) return false;
1496 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1498 .addReg(SrcReg1).addReg(SrcReg2));
1500 MachineInstrBuilder MIB;
1501 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1504 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1507 AddOptionalDefs(MIB);
1510 // For floating point we need to move the result to a comparison register
1511 // that we can then use for branches.
1512 if (Ty->isFloatTy() || Ty->isDoubleTy())
1513 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1514 TII.get(ARM::FMSTAT)));
1518 bool ARMFastISel::SelectCmp(const Instruction *I) {
1519 const CmpInst *CI = cast<CmpInst>(I);
1521 // Get the compare predicate.
1522 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1524 // We may not handle every CC for now.
1525 if (ARMPred == ARMCC::AL) return false;
1527 // Emit the compare.
1528 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1531 // Now set a register based on the comparison. Explicitly set the predicates
1533 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1534 const TargetRegisterClass *RC = isThumb2 ?
1535 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1536 (const TargetRegisterClass*)&ARM::GPRRegClass;
1537 unsigned DestReg = createResultReg(RC);
1538 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1539 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1540 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1541 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1542 .addReg(ZeroReg).addImm(1)
1543 .addImm(ARMPred).addReg(ARM::CPSR);
1545 UpdateValueMap(I, DestReg);
1549 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1550 // Make sure we have VFP and that we're extending float to double.
1551 if (!Subtarget->hasVFP2()) return false;
1553 Value *V = I->getOperand(0);
1554 if (!I->getType()->isDoubleTy() ||
1555 !V->getType()->isFloatTy()) return false;
1557 unsigned Op = getRegForValue(V);
1558 if (Op == 0) return false;
1560 unsigned Result = createResultReg(&ARM::DPRRegClass);
1561 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1562 TII.get(ARM::VCVTDS), Result)
1564 UpdateValueMap(I, Result);
1568 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1569 // Make sure we have VFP and that we're truncating double to float.
1570 if (!Subtarget->hasVFP2()) return false;
1572 Value *V = I->getOperand(0);
1573 if (!(I->getType()->isFloatTy() &&
1574 V->getType()->isDoubleTy())) return false;
1576 unsigned Op = getRegForValue(V);
1577 if (Op == 0) return false;
1579 unsigned Result = createResultReg(&ARM::SPRRegClass);
1580 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1581 TII.get(ARM::VCVTSD), Result)
1583 UpdateValueMap(I, Result);
1587 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1588 // Make sure we have VFP.
1589 if (!Subtarget->hasVFP2()) return false;
1592 Type *Ty = I->getType();
1593 if (!isTypeLegal(Ty, DstVT))
1596 Value *Src = I->getOperand(0);
1597 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1598 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1601 unsigned SrcReg = getRegForValue(Src);
1602 if (SrcReg == 0) return false;
1604 // Handle sign-extension.
1605 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1606 EVT DestVT = MVT::i32;
1607 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT,
1608 /*isZExt*/!isSigned);
1609 if (SrcReg == 0) return false;
1612 // The conversion routine works on fp-reg to fp-reg and the operand above
1613 // was an integer, move it to the fp registers if possible.
1614 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1615 if (FP == 0) return false;
1618 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1619 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1622 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1623 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1626 UpdateValueMap(I, ResultReg);
1630 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1631 // Make sure we have VFP.
1632 if (!Subtarget->hasVFP2()) return false;
1635 Type *RetTy = I->getType();
1636 if (!isTypeLegal(RetTy, DstVT))
1639 unsigned Op = getRegForValue(I->getOperand(0));
1640 if (Op == 0) return false;
1643 Type *OpTy = I->getOperand(0)->getType();
1644 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1645 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1648 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1649 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1650 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1654 // This result needs to be in an integer register, but the conversion only
1655 // takes place in fp-regs.
1656 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1657 if (IntReg == 0) return false;
1659 UpdateValueMap(I, IntReg);
1663 bool ARMFastISel::SelectSelect(const Instruction *I) {
1665 if (!isTypeLegal(I->getType(), VT))
1668 // Things need to be register sized for register moves.
1669 if (VT != MVT::i32) return false;
1671 unsigned CondReg = getRegForValue(I->getOperand(0));
1672 if (CondReg == 0) return false;
1673 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1674 if (Op1Reg == 0) return false;
1676 // Check to see if we can use an immediate in the conditional move.
1678 bool UseImm = false;
1679 bool isNegativeImm = false;
1680 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1681 assert (VT == MVT::i32 && "Expecting an i32.");
1682 Imm = (int)ConstInt->getValue().getZExtValue();
1684 isNegativeImm = true;
1687 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1688 (ARM_AM::getSOImmVal(Imm) != -1);
1691 unsigned Op2Reg = 0;
1693 Op2Reg = getRegForValue(I->getOperand(2));
1694 if (Op2Reg == 0) return false;
1697 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1698 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1699 .addReg(CondReg).addImm(0));
1702 const TargetRegisterClass *RC;
1704 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1705 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1707 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1709 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1711 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1713 unsigned ResultReg = createResultReg(RC);
1715 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1716 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1718 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1719 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1720 UpdateValueMap(I, ResultReg);
1724 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1726 Type *Ty = I->getType();
1727 if (!isTypeLegal(Ty, VT))
1730 // If we have integer div support we should have selected this automagically.
1731 // In case we have a real miss go ahead and return false and we'll pick
1733 if (Subtarget->hasDivide()) return false;
1735 // Otherwise emit a libcall.
1736 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1738 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1739 else if (VT == MVT::i16)
1740 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1741 else if (VT == MVT::i32)
1742 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1743 else if (VT == MVT::i64)
1744 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1745 else if (VT == MVT::i128)
1746 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1747 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1749 return ARMEmitLibcall(I, LC);
1752 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1754 Type *Ty = I->getType();
1755 if (!isTypeLegal(Ty, VT))
1758 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1760 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1761 else if (VT == MVT::i16)
1762 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1763 else if (VT == MVT::i32)
1764 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1765 else if (VT == MVT::i64)
1766 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1767 else if (VT == MVT::i128)
1768 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1769 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1771 return ARMEmitLibcall(I, LC);
1774 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1775 EVT DestVT = TLI.getValueType(I->getType(), true);
1777 // We can get here in the case when we have a binary operation on a non-legal
1778 // type and the target independent selector doesn't know how to handle it.
1779 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1783 switch (ISDOpcode) {
1784 default: return false;
1786 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1789 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1792 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1796 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1797 if (SrcReg1 == 0) return false;
1799 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1800 // in the instruction, rather then materializing the value in a register.
1801 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1802 if (SrcReg2 == 0) return false;
1804 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1805 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1806 TII.get(Opc), ResultReg)
1807 .addReg(SrcReg1).addReg(SrcReg2));
1808 UpdateValueMap(I, ResultReg);
1812 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1813 EVT VT = TLI.getValueType(I->getType(), true);
1815 // We can get here in the case when we want to use NEON for our fp
1816 // operations, but can't figure out how to. Just use the vfp instructions
1818 // FIXME: It'd be nice to use NEON instructions.
1819 Type *Ty = I->getType();
1820 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1821 if (isFloat && !Subtarget->hasVFP2())
1825 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1826 switch (ISDOpcode) {
1827 default: return false;
1829 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1832 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1835 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1838 unsigned Op1 = getRegForValue(I->getOperand(0));
1839 if (Op1 == 0) return false;
1841 unsigned Op2 = getRegForValue(I->getOperand(1));
1842 if (Op2 == 0) return false;
1844 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1845 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1846 TII.get(Opc), ResultReg)
1847 .addReg(Op1).addReg(Op2));
1848 UpdateValueMap(I, ResultReg);
1852 // Call Handling Code
1854 // This is largely taken directly from CCAssignFnForNode
1855 // TODO: We may not support all of this.
1856 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1861 llvm_unreachable("Unsupported calling convention");
1862 case CallingConv::Fast:
1863 if (Subtarget->hasVFP2() && !isVarArg) {
1864 if (!Subtarget->isAAPCS_ABI())
1865 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1866 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1867 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1870 case CallingConv::C:
1871 // Use target triple & subtarget features to do actual dispatch.
1872 if (Subtarget->isAAPCS_ABI()) {
1873 if (Subtarget->hasVFP2() &&
1874 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1875 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1877 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1879 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1880 case CallingConv::ARM_AAPCS_VFP:
1882 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1883 // Fall through to soft float variant, variadic functions don't
1884 // use hard floating point ABI.
1885 case CallingConv::ARM_AAPCS:
1886 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1887 case CallingConv::ARM_APCS:
1888 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1889 case CallingConv::GHC:
1891 llvm_unreachable("Can't return in GHC call convention");
1893 return CC_ARM_APCS_GHC;
1897 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1898 SmallVectorImpl<unsigned> &ArgRegs,
1899 SmallVectorImpl<MVT> &ArgVTs,
1900 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1901 SmallVectorImpl<unsigned> &RegArgs,
1905 SmallVector<CCValAssign, 16> ArgLocs;
1906 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1907 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1908 CCAssignFnForCall(CC, false, isVarArg));
1910 // Check that we can handle all of the arguments. If we can't, then bail out
1911 // now before we add code to the MBB.
1912 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1913 CCValAssign &VA = ArgLocs[i];
1914 MVT ArgVT = ArgVTs[VA.getValNo()];
1916 // We don't handle NEON/vector parameters yet.
1917 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1920 // Now copy/store arg to correct locations.
1921 if (VA.isRegLoc() && !VA.needsCustom()) {
1923 } else if (VA.needsCustom()) {
1924 // TODO: We need custom lowering for vector (v2f64) args.
1925 if (VA.getLocVT() != MVT::f64 ||
1926 // TODO: Only handle register args for now.
1927 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1930 switch (static_cast<EVT>(ArgVT).getSimpleVT().SimpleTy) {
1939 if (!Subtarget->hasVFP2())
1943 if (!Subtarget->hasVFP2())
1950 // At the point, we are able to handle the call's arguments in fast isel.
1952 // Get a count of how many bytes are to be pushed on the stack.
1953 NumBytes = CCInfo.getNextStackOffset();
1955 // Issue CALLSEQ_START
1956 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1957 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1958 TII.get(AdjStackDown))
1961 // Process the args.
1962 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1963 CCValAssign &VA = ArgLocs[i];
1964 unsigned Arg = ArgRegs[VA.getValNo()];
1965 MVT ArgVT = ArgVTs[VA.getValNo()];
1967 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1968 "We don't handle NEON/vector parameters yet.");
1970 // Handle arg promotion, etc.
1971 switch (VA.getLocInfo()) {
1972 case CCValAssign::Full: break;
1973 case CCValAssign::SExt: {
1974 MVT DestVT = VA.getLocVT();
1975 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1976 assert (Arg != 0 && "Failed to emit a sext");
1980 case CCValAssign::AExt:
1981 // Intentional fall-through. Handle AExt and ZExt.
1982 case CCValAssign::ZExt: {
1983 MVT DestVT = VA.getLocVT();
1984 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1985 assert (Arg != 0 && "Failed to emit a sext");
1989 case CCValAssign::BCvt: {
1990 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1991 /*TODO: Kill=*/false);
1992 assert(BC != 0 && "Failed to emit a bitcast!");
1994 ArgVT = VA.getLocVT();
1997 default: llvm_unreachable("Unknown arg promotion!");
2000 // Now copy/store arg to correct locations.
2001 if (VA.isRegLoc() && !VA.needsCustom()) {
2002 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2005 RegArgs.push_back(VA.getLocReg());
2006 } else if (VA.needsCustom()) {
2007 // TODO: We need custom lowering for vector (v2f64) args.
2008 assert(VA.getLocVT() == MVT::f64 &&
2009 "Custom lowering for v2f64 args not available");
2011 CCValAssign &NextVA = ArgLocs[++i];
2013 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2014 "We only handle register args!");
2016 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2017 TII.get(ARM::VMOVRRD), VA.getLocReg())
2018 .addReg(NextVA.getLocReg(), RegState::Define)
2020 RegArgs.push_back(VA.getLocReg());
2021 RegArgs.push_back(NextVA.getLocReg());
2023 assert(VA.isMemLoc());
2024 // Need to store on the stack.
2026 Addr.BaseType = Address::RegBase;
2027 Addr.Base.Reg = ARM::SP;
2028 Addr.Offset = VA.getLocMemOffset();
2030 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2031 assert(EmitRet && "Could not emit a store for argument!");
2038 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2039 const Instruction *I, CallingConv::ID CC,
2040 unsigned &NumBytes, bool isVarArg) {
2041 // Issue CALLSEQ_END
2042 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2043 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2044 TII.get(AdjStackUp))
2045 .addImm(NumBytes).addImm(0));
2047 // Now the return value.
2048 if (RetVT != MVT::isVoid) {
2049 SmallVector<CCValAssign, 16> RVLocs;
2050 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2051 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2053 // Copy all of the result registers out of their specified physreg.
2054 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2055 // For this move we copy into two registers and then move into the
2056 // double fp reg we want.
2057 EVT DestVT = RVLocs[0].getValVT();
2058 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2059 unsigned ResultReg = createResultReg(DstRC);
2060 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2061 TII.get(ARM::VMOVDRR), ResultReg)
2062 .addReg(RVLocs[0].getLocReg())
2063 .addReg(RVLocs[1].getLocReg()));
2065 UsedRegs.push_back(RVLocs[0].getLocReg());
2066 UsedRegs.push_back(RVLocs[1].getLocReg());
2068 // Finally update the result.
2069 UpdateValueMap(I, ResultReg);
2071 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2072 EVT CopyVT = RVLocs[0].getValVT();
2074 // Special handling for extended integers.
2075 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2078 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2080 unsigned ResultReg = createResultReg(DstRC);
2081 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2082 ResultReg).addReg(RVLocs[0].getLocReg());
2083 UsedRegs.push_back(RVLocs[0].getLocReg());
2085 // Finally update the result.
2086 UpdateValueMap(I, ResultReg);
2093 bool ARMFastISel::SelectRet(const Instruction *I) {
2094 const ReturnInst *Ret = cast<ReturnInst>(I);
2095 const Function &F = *I->getParent()->getParent();
2097 if (!FuncInfo.CanLowerReturn)
2100 CallingConv::ID CC = F.getCallingConv();
2101 if (Ret->getNumOperands() > 0) {
2102 SmallVector<ISD::OutputArg, 4> Outs;
2103 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
2106 // Analyze operands of the call, assigning locations to each operand.
2107 SmallVector<CCValAssign, 16> ValLocs;
2108 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
2109 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2112 const Value *RV = Ret->getOperand(0);
2113 unsigned Reg = getRegForValue(RV);
2117 // Only handle a single return value for now.
2118 if (ValLocs.size() != 1)
2121 CCValAssign &VA = ValLocs[0];
2123 // Don't bother handling odd stuff for now.
2124 if (VA.getLocInfo() != CCValAssign::Full)
2126 // Only handle register returns for now.
2130 unsigned SrcReg = Reg + VA.getValNo();
2131 EVT RVVT = TLI.getValueType(RV->getType());
2132 EVT DestVT = VA.getValVT();
2133 // Special handling for extended integers.
2134 if (RVVT != DestVT) {
2135 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2138 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2140 // Perform extension if flagged as either zext or sext. Otherwise, do
2142 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2143 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2144 if (SrcReg == 0) return false;
2149 unsigned DstReg = VA.getLocReg();
2150 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2151 // Avoid a cross-class copy. This is very unlikely.
2152 if (!SrcRC->contains(DstReg))
2154 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2155 DstReg).addReg(SrcReg);
2157 // Mark the register as live out of the function.
2158 MRI.addLiveOut(VA.getLocReg());
2161 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2162 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2167 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2169 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2171 return isThumb2 ? ARM::tBL : ARM::BL;
2174 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2175 GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
2176 GlobalValue::ExternalLinkage, 0, Name);
2177 return ARMMaterializeGV(GV, TLI.getValueType(GV->getType()));
2180 // A quick function that will emit a call for a named libcall in F with the
2181 // vector of passed arguments for the Instruction in I. We can assume that we
2182 // can emit a call for any libcall we can produce. This is an abridged version
2183 // of the full call infrastructure since we won't need to worry about things
2184 // like computed function pointers or strange arguments at call sites.
2185 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2187 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2188 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2190 // Handle *simple* calls for now.
2191 Type *RetTy = I->getType();
2193 if (RetTy->isVoidTy())
2194 RetVT = MVT::isVoid;
2195 else if (!isTypeLegal(RetTy, RetVT))
2198 // Can't handle non-double multi-reg retvals.
2199 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2200 SmallVector<CCValAssign, 16> RVLocs;
2201 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
2202 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2203 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2207 // Set up the argument vectors.
2208 SmallVector<Value*, 8> Args;
2209 SmallVector<unsigned, 8> ArgRegs;
2210 SmallVector<MVT, 8> ArgVTs;
2211 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2212 Args.reserve(I->getNumOperands());
2213 ArgRegs.reserve(I->getNumOperands());
2214 ArgVTs.reserve(I->getNumOperands());
2215 ArgFlags.reserve(I->getNumOperands());
2216 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2217 Value *Op = I->getOperand(i);
2218 unsigned Arg = getRegForValue(Op);
2219 if (Arg == 0) return false;
2221 Type *ArgTy = Op->getType();
2223 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2225 ISD::ArgFlagsTy Flags;
2226 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2227 Flags.setOrigAlign(OriginalAlignment);
2230 ArgRegs.push_back(Arg);
2231 ArgVTs.push_back(ArgVT);
2232 ArgFlags.push_back(Flags);
2235 // Handle the arguments now that we've gotten them.
2236 SmallVector<unsigned, 4> RegArgs;
2238 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2239 RegArgs, CC, NumBytes, false))
2242 unsigned CalleeReg = 0;
2243 if (EnableARMLongCalls) {
2244 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2245 if (CalleeReg == 0) return false;
2249 unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
2250 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2251 DL, TII.get(CallOpc));
2252 // BL / BLX don't take a predicate, but tBL / tBLX do.
2254 AddDefaultPred(MIB);
2255 if (EnableARMLongCalls)
2256 MIB.addReg(CalleeReg);
2258 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2260 // Add implicit physical register uses to the call.
2261 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2262 MIB.addReg(RegArgs[i], RegState::Implicit);
2264 // Add a register mask with the call-preserved registers.
2265 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2266 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2268 // Finish off the call including any return values.
2269 SmallVector<unsigned, 4> UsedRegs;
2270 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2272 // Set all unused physreg defs as dead.
2273 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2278 bool ARMFastISel::SelectCall(const Instruction *I,
2279 const char *IntrMemName = 0) {
2280 const CallInst *CI = cast<CallInst>(I);
2281 const Value *Callee = CI->getCalledValue();
2283 // Can't handle inline asm.
2284 if (isa<InlineAsm>(Callee)) return false;
2286 // Check the calling convention.
2287 ImmutableCallSite CS(CI);
2288 CallingConv::ID CC = CS.getCallingConv();
2290 // TODO: Avoid some calling conventions?
2292 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2293 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2294 bool isVarArg = FTy->isVarArg();
2296 // Handle *simple* calls for now.
2297 Type *RetTy = I->getType();
2299 if (RetTy->isVoidTy())
2300 RetVT = MVT::isVoid;
2301 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2302 RetVT != MVT::i8 && RetVT != MVT::i1)
2305 // Can't handle non-double multi-reg retvals.
2306 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2307 RetVT != MVT::i16 && RetVT != MVT::i32) {
2308 SmallVector<CCValAssign, 16> RVLocs;
2309 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2310 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2311 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2315 // Set up the argument vectors.
2316 SmallVector<Value*, 8> Args;
2317 SmallVector<unsigned, 8> ArgRegs;
2318 SmallVector<MVT, 8> ArgVTs;
2319 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2320 unsigned arg_size = CS.arg_size();
2321 Args.reserve(arg_size);
2322 ArgRegs.reserve(arg_size);
2323 ArgVTs.reserve(arg_size);
2324 ArgFlags.reserve(arg_size);
2325 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2327 // If we're lowering a memory intrinsic instead of a regular call, skip the
2328 // last two arguments, which shouldn't be passed to the underlying function.
2329 if (IntrMemName && e-i <= 2)
2332 ISD::ArgFlagsTy Flags;
2333 unsigned AttrInd = i - CS.arg_begin() + 1;
2334 if (CS.paramHasAttr(AttrInd, Attributes::SExt))
2336 if (CS.paramHasAttr(AttrInd, Attributes::ZExt))
2339 // FIXME: Only handle *easy* calls for now.
2340 if (CS.paramHasAttr(AttrInd, Attributes::InReg) ||
2341 CS.paramHasAttr(AttrInd, Attributes::StructRet) ||
2342 CS.paramHasAttr(AttrInd, Attributes::Nest) ||
2343 CS.paramHasAttr(AttrInd, Attributes::ByVal))
2346 Type *ArgTy = (*i)->getType();
2348 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2352 unsigned Arg = getRegForValue(*i);
2356 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2357 Flags.setOrigAlign(OriginalAlignment);
2360 ArgRegs.push_back(Arg);
2361 ArgVTs.push_back(ArgVT);
2362 ArgFlags.push_back(Flags);
2365 // Handle the arguments now that we've gotten them.
2366 SmallVector<unsigned, 4> RegArgs;
2368 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2369 RegArgs, CC, NumBytes, isVarArg))
2372 bool UseReg = false;
2373 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2374 if (!GV || EnableARMLongCalls) UseReg = true;
2376 unsigned CalleeReg = 0;
2379 CalleeReg = getLibcallReg(IntrMemName);
2381 CalleeReg = getRegForValue(Callee);
2383 if (CalleeReg == 0) return false;
2387 unsigned CallOpc = ARMSelectCallOp(UseReg);
2388 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2389 DL, TII.get(CallOpc));
2391 // ARM calls don't take a predicate, but tBL / tBLX do.
2393 AddDefaultPred(MIB);
2395 MIB.addReg(CalleeReg);
2396 else if (!IntrMemName)
2397 MIB.addGlobalAddress(GV, 0, 0);
2399 MIB.addExternalSymbol(IntrMemName, 0);
2401 // Add implicit physical register uses to the call.
2402 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2403 MIB.addReg(RegArgs[i], RegState::Implicit);
2405 // Add a register mask with the call-preserved registers.
2406 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2407 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2409 // Finish off the call including any return values.
2410 SmallVector<unsigned, 4> UsedRegs;
2411 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2414 // Set all unused physreg defs as dead.
2415 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2420 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2424 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2426 // Make sure we don't bloat code by inlining very large memcpy's.
2427 if (!ARMIsMemCpySmall(Len))
2430 // We don't care about alignment here since we just emit integer accesses.
2444 RV = ARMEmitLoad(VT, ResultReg, Src);
2445 assert (RV == true && "Should be able to handle this load.");
2446 RV = ARMEmitStore(VT, ResultReg, Dest);
2447 assert (RV == true && "Should be able to handle this store.");
2450 unsigned Size = VT.getSizeInBits()/8;
2452 Dest.Offset += Size;
2459 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2460 // FIXME: Handle more intrinsics.
2461 switch (I.getIntrinsicID()) {
2462 default: return false;
2463 case Intrinsic::frameaddress: {
2464 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2465 MFI->setFrameAddressIsTaken(true);
2468 const TargetRegisterClass *RC;
2470 LdrOpc = ARM::t2LDRi12;
2471 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2473 LdrOpc = ARM::LDRi12;
2474 RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2477 const ARMBaseRegisterInfo *RegInfo =
2478 static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
2479 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2480 unsigned SrcReg = FramePtr;
2482 // Recursively load frame address
2488 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2490 DestReg = createResultReg(RC);
2491 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2492 TII.get(LdrOpc), DestReg)
2493 .addReg(SrcReg).addImm(0));
2496 UpdateValueMap(&I, SrcReg);
2499 case Intrinsic::memcpy:
2500 case Intrinsic::memmove: {
2501 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2502 // Don't handle volatile.
2503 if (MTI.isVolatile())
2506 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2507 // we would emit dead code because we don't currently handle memmoves.
2508 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2509 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2510 // Small memcpy's are common enough that we want to do them without a call
2512 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2513 if (ARMIsMemCpySmall(Len)) {
2515 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2516 !ARMComputeAddress(MTI.getRawSource(), Src))
2518 if (ARMTryEmitSmallMemCpy(Dest, Src, Len))
2523 if (!MTI.getLength()->getType()->isIntegerTy(32))
2526 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2529 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2530 return SelectCall(&I, IntrMemName);
2532 case Intrinsic::memset: {
2533 const MemSetInst &MSI = cast<MemSetInst>(I);
2534 // Don't handle volatile.
2535 if (MSI.isVolatile())
2538 if (!MSI.getLength()->getType()->isIntegerTy(32))
2541 if (MSI.getDestAddressSpace() > 255)
2544 return SelectCall(&I, "memset");
2546 case Intrinsic::trap: {
2547 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::TRAP));
2553 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2554 // The high bits for a type smaller than the register size are assumed to be
2556 Value *Op = I->getOperand(0);
2559 SrcVT = TLI.getValueType(Op->getType(), true);
2560 DestVT = TLI.getValueType(I->getType(), true);
2562 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2564 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2567 unsigned SrcReg = getRegForValue(Op);
2568 if (!SrcReg) return false;
2570 // Because the high bits are undefined, a truncate doesn't generate
2572 UpdateValueMap(I, SrcReg);
2576 unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
2578 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2582 bool isBoolZext = false;
2583 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32);
2584 if (!SrcVT.isSimple()) return 0;
2585 switch (SrcVT.getSimpleVT().SimpleTy) {
2588 if (!Subtarget->hasV6Ops()) return 0;
2589 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
2591 Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
2593 Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
2596 if (!Subtarget->hasV6Ops()) return 0;
2597 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
2599 Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
2601 Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
2605 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
2606 Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
2613 unsigned ResultReg = createResultReg(RC);
2614 MachineInstrBuilder MIB;
2615 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
2621 AddOptionalDefs(MIB);
2625 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2626 // On ARM, in general, integer casts don't involve legal types; this code
2627 // handles promotable integers.
2628 Type *DestTy = I->getType();
2629 Value *Src = I->getOperand(0);
2630 Type *SrcTy = Src->getType();
2633 SrcVT = TLI.getValueType(SrcTy, true);
2634 DestVT = TLI.getValueType(DestTy, true);
2636 bool isZExt = isa<ZExtInst>(I);
2637 unsigned SrcReg = getRegForValue(Src);
2638 if (!SrcReg) return false;
2640 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2641 if (ResultReg == 0) return false;
2642 UpdateValueMap(I, ResultReg);
2646 bool ARMFastISel::SelectShift(const Instruction *I,
2647 ARM_AM::ShiftOpc ShiftTy) {
2648 // We handle thumb2 mode by target independent selector
2649 // or SelectionDAG ISel.
2653 // Only handle i32 now.
2654 EVT DestVT = TLI.getValueType(I->getType(), true);
2655 if (DestVT != MVT::i32)
2658 unsigned Opc = ARM::MOVsr;
2660 Value *Src2Value = I->getOperand(1);
2661 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2662 ShiftImm = CI->getZExtValue();
2664 // Fall back to selection DAG isel if the shift amount
2665 // is zero or greater than the width of the value type.
2666 if (ShiftImm == 0 || ShiftImm >=32)
2672 Value *Src1Value = I->getOperand(0);
2673 unsigned Reg1 = getRegForValue(Src1Value);
2674 if (Reg1 == 0) return false;
2677 if (Opc == ARM::MOVsr) {
2678 Reg2 = getRegForValue(Src2Value);
2679 if (Reg2 == 0) return false;
2682 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2683 if(ResultReg == 0) return false;
2685 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2686 TII.get(Opc), ResultReg)
2689 if (Opc == ARM::MOVsi)
2690 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2691 else if (Opc == ARM::MOVsr) {
2693 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2696 AddOptionalDefs(MIB);
2697 UpdateValueMap(I, ResultReg);
2701 // TODO: SoftFP support.
2702 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2704 switch (I->getOpcode()) {
2705 case Instruction::Load:
2706 return SelectLoad(I);
2707 case Instruction::Store:
2708 return SelectStore(I);
2709 case Instruction::Br:
2710 return SelectBranch(I);
2711 case Instruction::IndirectBr:
2712 return SelectIndirectBr(I);
2713 case Instruction::ICmp:
2714 case Instruction::FCmp:
2715 return SelectCmp(I);
2716 case Instruction::FPExt:
2717 return SelectFPExt(I);
2718 case Instruction::FPTrunc:
2719 return SelectFPTrunc(I);
2720 case Instruction::SIToFP:
2721 return SelectIToFP(I, /*isSigned*/ true);
2722 case Instruction::UIToFP:
2723 return SelectIToFP(I, /*isSigned*/ false);
2724 case Instruction::FPToSI:
2725 return SelectFPToI(I, /*isSigned*/ true);
2726 case Instruction::FPToUI:
2727 return SelectFPToI(I, /*isSigned*/ false);
2728 case Instruction::Add:
2729 return SelectBinaryIntOp(I, ISD::ADD);
2730 case Instruction::Or:
2731 return SelectBinaryIntOp(I, ISD::OR);
2732 case Instruction::Sub:
2733 return SelectBinaryIntOp(I, ISD::SUB);
2734 case Instruction::FAdd:
2735 return SelectBinaryFPOp(I, ISD::FADD);
2736 case Instruction::FSub:
2737 return SelectBinaryFPOp(I, ISD::FSUB);
2738 case Instruction::FMul:
2739 return SelectBinaryFPOp(I, ISD::FMUL);
2740 case Instruction::SDiv:
2741 return SelectDiv(I, /*isSigned*/ true);
2742 case Instruction::UDiv:
2743 return SelectDiv(I, /*isSigned*/ false);
2744 case Instruction::SRem:
2745 return SelectRem(I, /*isSigned*/ true);
2746 case Instruction::URem:
2747 return SelectRem(I, /*isSigned*/ false);
2748 case Instruction::Call:
2749 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2750 return SelectIntrinsicCall(*II);
2751 return SelectCall(I);
2752 case Instruction::Select:
2753 return SelectSelect(I);
2754 case Instruction::Ret:
2755 return SelectRet(I);
2756 case Instruction::Trunc:
2757 return SelectTrunc(I);
2758 case Instruction::ZExt:
2759 case Instruction::SExt:
2760 return SelectIntExt(I);
2761 case Instruction::Shl:
2762 return SelectShift(I, ARM_AM::lsl);
2763 case Instruction::LShr:
2764 return SelectShift(I, ARM_AM::lsr);
2765 case Instruction::AShr:
2766 return SelectShift(I, ARM_AM::asr);
2772 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
2773 /// vreg is being provided by the specified load instruction. If possible,
2774 /// try to fold the load as an operand to the instruction, returning true if
2776 bool ARMFastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
2777 const LoadInst *LI) {
2778 // Verify we have a legal type before going any further.
2780 if (!isLoadTypeLegal(LI->getType(), VT))
2783 // Combine load followed by zero- or sign-extend.
2784 // ldrb r1, [r0] ldrb r1, [r0]
2786 // mov r3, r2 mov r3, r1
2788 switch(MI->getOpcode()) {
2789 default: return false;
2807 // See if we can handle this address.
2809 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2811 unsigned ResultReg = MI->getOperand(0).getReg();
2812 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2814 MI->eraseFromParent();
2818 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2819 unsigned Align, EVT VT) {
2820 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2821 ARMConstantPoolConstant *CPV =
2822 ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2823 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
2826 unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
2829 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2830 TII.get(ARM::t2LDRpci), DestReg1)
2831 .addConstantPoolIndex(Idx));
2832 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
2834 // The extra immediate is for addrmode2.
2835 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2836 DL, TII.get(ARM::LDRcp), DestReg1)
2837 .addConstantPoolIndex(Idx).addImm(0));
2838 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
2841 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
2842 if (GlobalBaseReg == 0) {
2843 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
2844 AFI->setGlobalBaseReg(GlobalBaseReg);
2847 unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
2848 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2849 DL, TII.get(Opc), DestReg2)
2851 .addReg(GlobalBaseReg);
2854 AddOptionalDefs(MIB);
2860 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
2861 const TargetLibraryInfo *libInfo) {
2862 // Completely untested on non-iOS.
2863 const TargetMachine &TM = funcInfo.MF->getTarget();
2865 // Darwin and thumb1 only for now.
2866 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2867 if (Subtarget->isTargetIOS() && !Subtarget->isThumb1Only())
2868 return new ARMFastISel(funcInfo, libInfo);