1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMBaseInstrInfo.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMRegisterInfo.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/Target/TargetFrameLowering.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
34 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
35 cl::desc("Verify machine code after expanding ARM pseudos"));
38 class ARMExpandPseudo : public MachineFunctionPass {
41 ARMExpandPseudo() : MachineFunctionPass(ID) {}
43 const ARMBaseInstrInfo *TII;
44 const TargetRegisterInfo *TRI;
45 const ARMSubtarget *STI;
48 virtual bool runOnMachineFunction(MachineFunction &Fn);
50 virtual const char *getPassName() const {
51 return "ARM pseudo instruction expansion pass";
55 void TransferImpOps(MachineInstr &OldMI,
56 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
57 bool ExpandMI(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI);
59 bool ExpandMBB(MachineBasicBlock &MBB);
60 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
61 void ExpandVST(MachineBasicBlock::iterator &MBBI);
62 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
63 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
64 unsigned Opc, bool IsExt, unsigned NumRegs);
65 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
66 MachineBasicBlock::iterator &MBBI);
68 char ARMExpandPseudo::ID = 0;
71 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
72 /// the instructions created from the expansion.
73 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
74 MachineInstrBuilder &UseMI,
75 MachineInstrBuilder &DefMI) {
76 const MCInstrDesc &Desc = OldMI.getDesc();
77 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
79 const MachineOperand &MO = OldMI.getOperand(i);
80 assert(MO.isReg() && MO.getReg());
89 // Constants for register spacing in NEON load/store instructions.
90 // For quad-register load-lane and store-lane pseudo instructors, the
91 // spacing is initially assumed to be EvenDblSpc, and that is changed to
92 // OddDblSpc depending on the lane number operand.
99 // Entries for NEON load/store information table. The table is sorted by
100 // PseudoOpc for fast binary-search lookups.
101 struct NEONLdStTableEntry {
105 bool HasWritebackOperand;
106 NEONRegSpacing RegSpacing;
107 unsigned char NumRegs; // D registers loaded or stored
108 unsigned char RegElts; // elements per D register; used for lane ops
109 // FIXME: Temporary flag to denote whether the real instruction takes
110 // a single register (like the encoding) or all of the registers in
111 // the list (like the asm syntax and the isel DAG). When all definitions
112 // are converted to take only the single encoded register, this will
114 bool copyAllListRegs;
116 // Comparison methods for binary search of the table.
117 bool operator<(const NEONLdStTableEntry &TE) const {
118 return PseudoOpc < TE.PseudoOpc;
120 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
121 return TE.PseudoOpc < PseudoOpc;
123 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
124 const NEONLdStTableEntry &TE) {
125 return PseudoOpc < TE.PseudoOpc;
130 static const NEONLdStTableEntry NEONLdStTable[] = {
131 { ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, SingleSpc, 2, 4,true},
132 { ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, SingleSpc, 2, 4,true},
133 { ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, SingleSpc, 2, 2,true},
134 { ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, SingleSpc, 2, 2,true},
135 { ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, SingleSpc, 2, 8,true},
136 { ARM::VLD1DUPq8Pseudo_UPD, ARM::VLD1DUPq8_UPD, true, true, SingleSpc, 2, 8,true},
138 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 ,true},
139 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, EvenDblSpc, 1, 4 ,true},
140 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 ,true},
141 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, EvenDblSpc, 1, 2 ,true},
142 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 ,true},
143 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, EvenDblSpc, 1, 8 ,true},
145 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 ,false},
146 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 ,false},
147 { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 ,false},
148 { ARM::VLD1q16PseudoWB_fixed, ARM::VLD1q16wb_fixed,true,false,SingleSpc, 2, 4 ,false},
149 { ARM::VLD1q16PseudoWB_register, ARM::VLD1q16wb_register, true, true, SingleSpc, 2, 4 ,false},
150 { ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 ,false},
151 { ARM::VLD1q32PseudoWB_fixed, ARM::VLD1q32wb_fixed,true,false,SingleSpc, 2, 2 ,false},
152 { ARM::VLD1q32PseudoWB_register, ARM::VLD1q32wb_register, true, true, SingleSpc, 2, 2 ,false},
153 { ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 ,false},
154 { ARM::VLD1q64PseudoWB_fixed, ARM::VLD1q64wb_fixed,true,false,SingleSpc, 2, 2 ,false},
155 { ARM::VLD1q64PseudoWB_register, ARM::VLD1q64wb_register, true, true, SingleSpc, 2, 1 ,false},
156 { ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 ,false},
157 { ARM::VLD1q8PseudoWB_fixed, ARM::VLD1q8wb_fixed,true,false, SingleSpc, 2, 8 ,false},
158 { ARM::VLD1q8PseudoWB_register, ARM::VLD1q8wb_register,true,true,SingleSpc,2,8,false},
160 { ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, SingleSpc, 2, 4,true},
161 { ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, SingleSpc, 2, 4,true},
162 { ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, SingleSpc, 2, 2,true},
163 { ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, SingleSpc, 2, 2,true},
164 { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, SingleSpc, 2, 8,true},
165 { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd8_UPD, true, true, SingleSpc, 2, 8,true},
167 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 ,true},
168 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 ,true},
169 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 ,true},
170 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 ,true},
171 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 ,true},
172 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 ,true},
173 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 ,true},
174 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 ,true},
175 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 ,true},
176 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 ,true},
178 { ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 ,false},
179 { ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 ,false},
180 { ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 ,false},
181 { ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 ,false},
182 { ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 ,false},
183 { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 ,false},
185 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 ,false},
186 { ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 ,false},
187 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 ,false},
188 { ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 ,false},
189 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 ,false},
190 { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 ,false},
192 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, SingleSpc, 3, 4,true},
193 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, SingleSpc, 3, 4,true},
194 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, SingleSpc, 3, 2,true},
195 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, SingleSpc, 3, 2,true},
196 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, SingleSpc, 3, 8,true},
197 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, SingleSpc, 3, 8,true},
199 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 ,true},
200 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 ,true},
201 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 ,true},
202 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 ,true},
203 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 ,true},
204 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 ,true},
205 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 ,true},
206 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 ,true},
207 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 ,true},
208 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 ,true},
210 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 ,true},
211 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 ,true},
212 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 ,true},
213 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 ,true},
214 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 ,true},
215 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 ,true},
217 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 ,true},
218 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, OddDblSpc, 3, 4 ,true},
219 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 ,true},
220 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 ,true},
221 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, OddDblSpc, 3, 2 ,true},
222 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 ,true},
223 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 ,true},
224 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, OddDblSpc, 3, 8 ,true},
225 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 ,true},
227 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, SingleSpc, 4, 4,true},
228 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, SingleSpc, 4, 4,true},
229 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, SingleSpc, 4, 2,true},
230 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, SingleSpc, 4, 2,true},
231 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, SingleSpc, 4, 8,true},
232 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, SingleSpc, 4, 8,true},
234 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 ,true},
235 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 ,true},
236 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 ,true},
237 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 ,true},
238 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 ,true},
239 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 ,true},
240 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 ,true},
241 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 ,true},
242 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 ,true},
243 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 ,true},
245 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 ,true},
246 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 ,true},
247 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 ,true},
248 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 ,true},
249 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 ,true},
250 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 ,true},
252 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 ,true},
253 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, OddDblSpc, 4, 4 ,true},
254 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 ,true},
255 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 ,true},
256 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, OddDblSpc, 4, 2 ,true},
257 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 ,true},
258 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 ,true},
259 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, OddDblSpc, 4, 8 ,true},
260 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 ,true},
262 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, EvenDblSpc, 1, 4 ,true},
263 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,false, true, EvenDblSpc, 1, 4 ,true},
264 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, EvenDblSpc, 1, 2 ,true},
265 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,false, true, EvenDblSpc, 1, 2 ,true},
266 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, EvenDblSpc, 1, 8 ,true},
267 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, EvenDblSpc, 1, 8 ,true},
269 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 ,true},
270 { ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 ,true},
271 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 ,true},
272 { ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 ,true},
274 { ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 ,true},
275 { ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 ,true},
276 { ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 ,true},
277 { ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 ,true},
278 { ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 ,true},
279 { ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 ,true},
280 { ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 ,true},
281 { ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 ,true},
283 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 ,true},
284 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 ,true},
285 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 ,true},
286 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 ,true},
287 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 ,true},
288 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 ,true},
289 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4,true},
290 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4,true},
291 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2,true},
292 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2,true},
294 { ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 ,true},
295 { ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 ,true},
296 { ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 ,true},
297 { ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 ,true},
298 { ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 ,true},
299 { ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 ,true},
301 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 ,true},
302 { ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 ,true},
303 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 ,true},
304 { ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 ,true},
305 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 ,true},
306 { ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 ,true},
308 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 ,true},
309 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 ,true},
310 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 ,true},
311 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 ,true},
312 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 ,true},
313 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 ,true},
314 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4,true},
315 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4,true},
316 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2,true},
317 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2,true},
319 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 ,true},
320 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 ,true},
321 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 ,true},
322 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 ,true},
323 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 ,true},
324 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 ,true},
326 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 ,true},
327 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, OddDblSpc, 3, 4 ,true},
328 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 ,true},
329 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 ,true},
330 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, OddDblSpc, 3, 2 ,true},
331 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 ,true},
332 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 ,true},
333 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, OddDblSpc, 3, 8 ,true},
334 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 ,true},
336 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 ,true},
337 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 ,true},
338 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 ,true},
339 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 ,true},
340 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 ,true},
341 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 ,true},
342 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4,true},
343 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4,true},
344 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2,true},
345 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2,true},
347 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 ,true},
348 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 ,true},
349 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 ,true},
350 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 ,true},
351 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 ,true},
352 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 ,true},
354 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 ,true},
355 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, OddDblSpc, 4, 4 ,true},
356 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 ,true},
357 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 ,true},
358 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, OddDblSpc, 4, 2 ,true},
359 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 ,true},
360 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 ,true},
361 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, OddDblSpc, 4, 8 ,true},
362 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 ,true}
365 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
366 /// load or store pseudo instruction.
367 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
368 unsigned NumEntries = array_lengthof(NEONLdStTable);
371 // Make sure the table is sorted.
372 static bool TableChecked = false;
374 for (unsigned i = 0; i != NumEntries-1; ++i)
375 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
376 "NEONLdStTable is not sorted!");
381 const NEONLdStTableEntry *I =
382 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
383 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
388 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
389 /// corresponding to the specified register spacing. Not all of the results
390 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
391 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
392 const TargetRegisterInfo *TRI, unsigned &D0,
393 unsigned &D1, unsigned &D2, unsigned &D3) {
394 if (RegSpc == SingleSpc) {
395 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
396 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
397 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
398 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
399 } else if (RegSpc == EvenDblSpc) {
400 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
401 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
402 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
403 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
405 assert(RegSpc == OddDblSpc && "unknown register spacing");
406 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
407 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
408 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
409 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
413 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
414 /// operands to real VLD instructions with D register operands.
415 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
416 MachineInstr &MI = *MBBI;
417 MachineBasicBlock &MBB = *MI.getParent();
419 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
420 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
421 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
422 unsigned NumRegs = TableEntry->NumRegs;
424 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
425 TII->get(TableEntry->RealOpc));
428 bool DstIsDead = MI.getOperand(OpIdx).isDead();
429 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
430 unsigned D0, D1, D2, D3;
431 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
432 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
433 if (NumRegs > 1 && TableEntry->copyAllListRegs)
434 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
435 if (NumRegs > 2 && TableEntry->copyAllListRegs)
436 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
437 if (NumRegs > 3 && TableEntry->copyAllListRegs)
438 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
440 if (TableEntry->HasWritebackOperand)
441 MIB.addOperand(MI.getOperand(OpIdx++));
443 // Copy the addrmode6 operands.
444 MIB.addOperand(MI.getOperand(OpIdx++));
445 MIB.addOperand(MI.getOperand(OpIdx++));
446 // Copy the am6offset operand.
447 if (TableEntry->HasWritebackOperand)
448 MIB.addOperand(MI.getOperand(OpIdx++));
450 // For an instruction writing double-spaced subregs, the pseudo instruction
451 // has an extra operand that is a use of the super-register. Record the
452 // operand index and skip over it.
453 unsigned SrcOpIdx = 0;
454 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
457 // Copy the predicate operands.
458 MIB.addOperand(MI.getOperand(OpIdx++));
459 MIB.addOperand(MI.getOperand(OpIdx++));
461 // Copy the super-register source operand used for double-spaced subregs over
462 // to the new instruction as an implicit operand.
464 MachineOperand MO = MI.getOperand(SrcOpIdx);
465 MO.setImplicit(true);
468 // Add an implicit def for the super-register.
469 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
470 TransferImpOps(MI, MIB, MIB);
472 // Transfer memoperands.
473 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
475 MI.eraseFromParent();
478 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
479 /// operands to real VST instructions with D register operands.
480 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
481 MachineInstr &MI = *MBBI;
482 MachineBasicBlock &MBB = *MI.getParent();
484 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
485 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
486 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
487 unsigned NumRegs = TableEntry->NumRegs;
489 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
490 TII->get(TableEntry->RealOpc));
492 if (TableEntry->HasWritebackOperand)
493 MIB.addOperand(MI.getOperand(OpIdx++));
495 // Copy the addrmode6 operands.
496 MIB.addOperand(MI.getOperand(OpIdx++));
497 MIB.addOperand(MI.getOperand(OpIdx++));
498 // Copy the am6offset operand.
499 if (TableEntry->HasWritebackOperand)
500 MIB.addOperand(MI.getOperand(OpIdx++));
502 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
503 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
504 unsigned D0, D1, D2, D3;
505 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
506 MIB.addReg(D0).addReg(D1);
512 // Copy the predicate operands.
513 MIB.addOperand(MI.getOperand(OpIdx++));
514 MIB.addOperand(MI.getOperand(OpIdx++));
516 if (SrcIsKill) // Add an implicit kill for the super-reg.
517 MIB->addRegisterKilled(SrcReg, TRI, true);
518 TransferImpOps(MI, MIB, MIB);
520 // Transfer memoperands.
521 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
523 MI.eraseFromParent();
526 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
527 /// register operands to real instructions with D register operands.
528 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
529 MachineInstr &MI = *MBBI;
530 MachineBasicBlock &MBB = *MI.getParent();
532 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
533 assert(TableEntry && "NEONLdStTable lookup failed");
534 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
535 unsigned NumRegs = TableEntry->NumRegs;
536 unsigned RegElts = TableEntry->RegElts;
538 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
539 TII->get(TableEntry->RealOpc));
541 // The lane operand is always the 3rd from last operand, before the 2
542 // predicate operands.
543 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
545 // Adjust the lane and spacing as needed for Q registers.
546 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
547 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
551 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
553 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
555 bool DstIsDead = false;
556 if (TableEntry->IsLoad) {
557 DstIsDead = MI.getOperand(OpIdx).isDead();
558 DstReg = MI.getOperand(OpIdx++).getReg();
559 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
560 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
562 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
564 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
566 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
569 if (TableEntry->HasWritebackOperand)
570 MIB.addOperand(MI.getOperand(OpIdx++));
572 // Copy the addrmode6 operands.
573 MIB.addOperand(MI.getOperand(OpIdx++));
574 MIB.addOperand(MI.getOperand(OpIdx++));
575 // Copy the am6offset operand.
576 if (TableEntry->HasWritebackOperand)
577 MIB.addOperand(MI.getOperand(OpIdx++));
579 // Grab the super-register source.
580 MachineOperand MO = MI.getOperand(OpIdx++);
581 if (!TableEntry->IsLoad)
582 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
584 // Add the subregs as sources of the new instruction.
585 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
586 getKillRegState(MO.isKill()));
587 MIB.addReg(D0, SrcFlags);
589 MIB.addReg(D1, SrcFlags);
591 MIB.addReg(D2, SrcFlags);
593 MIB.addReg(D3, SrcFlags);
595 // Add the lane number operand.
599 // Copy the predicate operands.
600 MIB.addOperand(MI.getOperand(OpIdx++));
601 MIB.addOperand(MI.getOperand(OpIdx++));
603 // Copy the super-register source to be an implicit source.
604 MO.setImplicit(true);
606 if (TableEntry->IsLoad)
607 // Add an implicit def for the super-register.
608 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
609 TransferImpOps(MI, MIB, MIB);
610 MI.eraseFromParent();
613 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
614 /// register operands to real instructions with D register operands.
615 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
616 unsigned Opc, bool IsExt, unsigned NumRegs) {
617 MachineInstr &MI = *MBBI;
618 MachineBasicBlock &MBB = *MI.getParent();
620 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
623 // Transfer the destination register operand.
624 MIB.addOperand(MI.getOperand(OpIdx++));
626 MIB.addOperand(MI.getOperand(OpIdx++));
628 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
629 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
630 unsigned D0, D1, D2, D3;
631 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
632 MIB.addReg(D0).addReg(D1);
638 // Copy the other source register operand.
639 MIB.addOperand(MI.getOperand(OpIdx++));
641 // Copy the predicate operands.
642 MIB.addOperand(MI.getOperand(OpIdx++));
643 MIB.addOperand(MI.getOperand(OpIdx++));
645 if (SrcIsKill) // Add an implicit kill for the super-reg.
646 MIB->addRegisterKilled(SrcReg, TRI, true);
647 TransferImpOps(MI, MIB, MIB);
648 MI.eraseFromParent();
651 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
652 MachineBasicBlock::iterator &MBBI) {
653 MachineInstr &MI = *MBBI;
654 unsigned Opcode = MI.getOpcode();
655 unsigned PredReg = 0;
656 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
657 unsigned DstReg = MI.getOperand(0).getReg();
658 bool DstIsDead = MI.getOperand(0).isDead();
659 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
660 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
661 MachineInstrBuilder LO16, HI16;
663 if (!STI->hasV6T2Ops() &&
664 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
665 // Expand into a movi + orr.
666 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
667 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
668 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
671 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
672 unsigned ImmVal = (unsigned)MO.getImm();
673 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
674 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
675 LO16 = LO16.addImm(SOImmValV1);
676 HI16 = HI16.addImm(SOImmValV2);
677 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
678 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
679 LO16.addImm(Pred).addReg(PredReg).addReg(0);
680 HI16.addImm(Pred).addReg(PredReg).addReg(0);
681 TransferImpOps(MI, LO16, HI16);
682 MI.eraseFromParent();
686 unsigned LO16Opc = 0;
687 unsigned HI16Opc = 0;
688 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
689 LO16Opc = ARM::t2MOVi16;
690 HI16Opc = ARM::t2MOVTi16;
692 LO16Opc = ARM::MOVi16;
693 HI16Opc = ARM::MOVTi16;
696 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
697 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
698 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
702 unsigned Imm = MO.getImm();
703 unsigned Lo16 = Imm & 0xffff;
704 unsigned Hi16 = (Imm >> 16) & 0xffff;
705 LO16 = LO16.addImm(Lo16);
706 HI16 = HI16.addImm(Hi16);
708 const GlobalValue *GV = MO.getGlobal();
709 unsigned TF = MO.getTargetFlags();
710 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
711 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
714 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
715 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
716 LO16.addImm(Pred).addReg(PredReg);
717 HI16.addImm(Pred).addReg(PredReg);
719 TransferImpOps(MI, LO16, HI16);
720 MI.eraseFromParent();
723 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
724 MachineBasicBlock::iterator MBBI) {
725 MachineInstr &MI = *MBBI;
726 unsigned Opcode = MI.getOpcode();
732 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
733 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
734 MI.getOperand(1).getReg())
735 .addReg(MI.getOperand(2).getReg(),
736 getKillRegState(MI.getOperand(2).isKill()))
737 .addImm(MI.getOperand(3).getImm()) // 'pred'
738 .addReg(MI.getOperand(4).getReg());
740 MI.eraseFromParent();
745 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
746 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
747 MI.getOperand(1).getReg())
748 .addReg(MI.getOperand(2).getReg(),
749 getKillRegState(MI.getOperand(2).isKill()))
750 .addImm(MI.getOperand(3).getImm()) // 'pred'
751 .addReg(MI.getOperand(4).getReg())
752 .addReg(0); // 's' bit
754 MI.eraseFromParent();
758 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
759 (MI.getOperand(1).getReg()))
760 .addReg(MI.getOperand(2).getReg(),
761 getKillRegState(MI.getOperand(2).isKill()))
762 .addImm(MI.getOperand(3).getImm())
763 .addImm(MI.getOperand(4).getImm()) // 'pred'
764 .addReg(MI.getOperand(5).getReg())
765 .addReg(0); // 's' bit
767 MI.eraseFromParent();
772 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
773 (MI.getOperand(1).getReg()))
774 .addReg(MI.getOperand(2).getReg(),
775 getKillRegState(MI.getOperand(2).isKill()))
776 .addReg(MI.getOperand(3).getReg(),
777 getKillRegState(MI.getOperand(3).isKill()))
778 .addImm(MI.getOperand(4).getImm())
779 .addImm(MI.getOperand(5).getImm()) // 'pred'
780 .addReg(MI.getOperand(6).getReg())
781 .addReg(0); // 's' bit
783 MI.eraseFromParent();
786 case ARM::MOVCCi16: {
787 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi16),
788 MI.getOperand(1).getReg())
789 .addImm(MI.getOperand(2).getImm())
790 .addImm(MI.getOperand(3).getImm()) // 'pred'
791 .addReg(MI.getOperand(4).getReg());
793 MI.eraseFromParent();
798 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
799 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
800 MI.getOperand(1).getReg())
801 .addImm(MI.getOperand(2).getImm())
802 .addImm(MI.getOperand(3).getImm()) // 'pred'
803 .addReg(MI.getOperand(4).getReg())
804 .addReg(0); // 's' bit
806 MI.eraseFromParent();
810 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi),
811 MI.getOperand(1).getReg())
812 .addImm(MI.getOperand(2).getImm())
813 .addImm(MI.getOperand(3).getImm()) // 'pred'
814 .addReg(MI.getOperand(4).getReg())
815 .addReg(0); // 's' bit
817 MI.eraseFromParent();
820 case ARM::Int_eh_sjlj_dispatchsetup: {
821 MachineFunction &MF = *MI.getParent()->getParent();
822 const ARMBaseInstrInfo *AII =
823 static_cast<const ARMBaseInstrInfo*>(TII);
824 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
825 // For functions using a base pointer, we rematerialize it (via the frame
826 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
827 // for us. Otherwise, expand to nothing.
828 if (RI.hasBasePointer(MF)) {
829 int32_t NumBytes = AFI->getFramePtrSpillOffset();
830 unsigned FramePtr = RI.getFrameRegister(MF);
831 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
832 "base pointer without frame pointer?");
834 if (AFI->isThumb2Function()) {
835 llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
836 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
837 } else if (AFI->isThumbFunction()) {
838 llvm::emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
839 FramePtr, -NumBytes, *TII, RI);
841 llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
842 FramePtr, -NumBytes, ARMCC::AL, 0,
845 // If there's dynamic realignment, adjust for it.
846 if (RI.needsStackRealignment(MF)) {
847 MachineFrameInfo *MFI = MF.getFrameInfo();
848 unsigned MaxAlign = MFI->getMaxAlignment();
849 assert (!AFI->isThumb1OnlyFunction());
850 // Emit bic r6, r6, MaxAlign
851 unsigned bicOpc = AFI->isThumbFunction() ?
852 ARM::t2BICri : ARM::BICri;
853 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
854 TII->get(bicOpc), ARM::R6)
855 .addReg(ARM::R6, RegState::Kill)
856 .addImm(MaxAlign-1)));
860 MI.eraseFromParent();
864 case ARM::MOVsrl_flag:
865 case ARM::MOVsra_flag: {
866 // These are just fancy MOVs insructions.
867 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
868 MI.getOperand(0).getReg())
869 .addOperand(MI.getOperand(1))
870 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
871 ARM_AM::lsr : ARM_AM::asr),
873 .addReg(ARM::CPSR, RegState::Define);
874 MI.eraseFromParent();
878 // This encodes as "MOVs Rd, Rm, rrx
879 MachineInstrBuilder MIB =
880 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
881 MI.getOperand(0).getReg())
882 .addOperand(MI.getOperand(1))
883 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
885 TransferImpOps(MI, MIB, MIB);
886 MI.eraseFromParent();
891 MachineInstrBuilder MIB =
892 BuildMI(MBB, MBBI, MI.getDebugLoc(),
893 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
894 .addExternalSymbol("__aeabi_read_tp", 0);
896 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
897 TransferImpOps(MI, MIB, MIB);
898 MI.eraseFromParent();
901 case ARM::tLDRpci_pic:
902 case ARM::t2LDRpci_pic: {
903 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
904 ? ARM::tLDRpci : ARM::t2LDRpci;
905 unsigned DstReg = MI.getOperand(0).getReg();
906 bool DstIsDead = MI.getOperand(0).isDead();
907 MachineInstrBuilder MIB1 =
908 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
909 TII->get(NewLdOpc), DstReg)
910 .addOperand(MI.getOperand(1)));
911 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
912 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
913 TII->get(ARM::tPICADD))
914 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
916 .addOperand(MI.getOperand(2));
917 TransferImpOps(MI, MIB1, MIB2);
918 MI.eraseFromParent();
922 case ARM::MOV_ga_dyn:
923 case ARM::MOV_ga_pcrel:
924 case ARM::MOV_ga_pcrel_ldr:
925 case ARM::t2MOV_ga_dyn:
926 case ARM::t2MOV_ga_pcrel: {
927 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
928 unsigned LabelId = AFI->createPICLabelUId();
929 unsigned DstReg = MI.getOperand(0).getReg();
930 bool DstIsDead = MI.getOperand(0).isDead();
931 const MachineOperand &MO1 = MI.getOperand(1);
932 const GlobalValue *GV = MO1.getGlobal();
933 unsigned TF = MO1.getTargetFlags();
934 bool isARM = (Opcode != ARM::t2MOV_ga_pcrel && Opcode!=ARM::t2MOV_ga_dyn);
935 bool isPIC = (Opcode != ARM::MOV_ga_dyn && Opcode != ARM::t2MOV_ga_dyn);
936 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
937 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
938 unsigned LO16TF = isPIC
939 ? ARMII::MO_LO16_NONLAZY_PIC : ARMII::MO_LO16_NONLAZY;
940 unsigned HI16TF = isPIC
941 ? ARMII::MO_HI16_NONLAZY_PIC : ARMII::MO_HI16_NONLAZY;
942 unsigned PICAddOpc = isARM
943 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
945 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
946 TII->get(LO16Opc), DstReg)
947 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
949 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
950 TII->get(HI16Opc), DstReg)
952 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
955 TransferImpOps(MI, MIB1, MIB2);
956 MI.eraseFromParent();
960 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
962 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
963 .addReg(DstReg).addImm(LabelId);
965 AddDefaultPred(MIB3);
966 if (Opcode == ARM::MOV_ga_pcrel_ldr)
967 MIB2->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
969 TransferImpOps(MI, MIB1, MIB3);
970 MI.eraseFromParent();
975 case ARM::MOVCCi32imm:
976 case ARM::t2MOVi32imm:
977 case ARM::t2MOVCCi32imm:
978 ExpandMOV32BitImm(MBB, MBBI);
982 unsigned NewOpc = ARM::VLDMDIA;
983 MachineInstrBuilder MIB =
984 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
987 // Grab the Q register destination.
988 bool DstIsDead = MI.getOperand(OpIdx).isDead();
989 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
991 // Copy the source register.
992 MIB.addOperand(MI.getOperand(OpIdx++));
994 // Copy the predicate operands.
995 MIB.addOperand(MI.getOperand(OpIdx++));
996 MIB.addOperand(MI.getOperand(OpIdx++));
998 // Add the destination operands (D subregs).
999 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1000 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1001 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1002 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1004 // Add an implicit def for the super-register.
1005 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1006 TransferImpOps(MI, MIB, MIB);
1007 MI.eraseFromParent();
1011 case ARM::VSTMQIA: {
1012 unsigned NewOpc = ARM::VSTMDIA;
1013 MachineInstrBuilder MIB =
1014 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1017 // Grab the Q register source.
1018 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1019 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1021 // Copy the destination register.
1022 MIB.addOperand(MI.getOperand(OpIdx++));
1024 // Copy the predicate operands.
1025 MIB.addOperand(MI.getOperand(OpIdx++));
1026 MIB.addOperand(MI.getOperand(OpIdx++));
1028 // Add the source operands (D subregs).
1029 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1030 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1031 MIB.addReg(D0).addReg(D1);
1033 if (SrcIsKill) // Add an implicit kill for the Q register.
1034 MIB->addRegisterKilled(SrcReg, TRI, true);
1036 TransferImpOps(MI, MIB, MIB);
1037 MI.eraseFromParent();
1042 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q :
1044 MachineInstrBuilder MIB =
1045 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1047 unsigned SrcReg = MI.getOperand(1).getReg();
1048 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
1049 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
1050 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
1051 &ARM::DPR_VFP2RegClass);
1052 // The lane is [0,1] for the containing DReg superregister.
1053 // Copy the dst/src register operands.
1054 MIB.addOperand(MI.getOperand(OpIdx++));
1057 // Add the lane select operand.
1059 // Add the predicate operands.
1060 MIB.addOperand(MI.getOperand(OpIdx++));
1061 MIB.addOperand(MI.getOperand(OpIdx++));
1063 TransferImpOps(MI, MIB, MIB);
1064 MI.eraseFromParent();
1068 case ARM::VLD1q8Pseudo:
1069 case ARM::VLD1q16Pseudo:
1070 case ARM::VLD1q32Pseudo:
1071 case ARM::VLD1q64Pseudo:
1072 case ARM::VLD1q8PseudoWB_register:
1073 case ARM::VLD1q16PseudoWB_register:
1074 case ARM::VLD1q32PseudoWB_register:
1075 case ARM::VLD1q64PseudoWB_register:
1076 case ARM::VLD1q8PseudoWB_fixed:
1077 case ARM::VLD1q16PseudoWB_fixed:
1078 case ARM::VLD1q32PseudoWB_fixed:
1079 case ARM::VLD1q64PseudoWB_fixed:
1080 case ARM::VLD2d8Pseudo:
1081 case ARM::VLD2d16Pseudo:
1082 case ARM::VLD2d32Pseudo:
1083 case ARM::VLD2q8Pseudo:
1084 case ARM::VLD2q16Pseudo:
1085 case ARM::VLD2q32Pseudo:
1086 case ARM::VLD2d8Pseudo_UPD:
1087 case ARM::VLD2d16Pseudo_UPD:
1088 case ARM::VLD2d32Pseudo_UPD:
1089 case ARM::VLD2q8Pseudo_UPD:
1090 case ARM::VLD2q16Pseudo_UPD:
1091 case ARM::VLD2q32Pseudo_UPD:
1092 case ARM::VLD3d8Pseudo:
1093 case ARM::VLD3d16Pseudo:
1094 case ARM::VLD3d32Pseudo:
1095 case ARM::VLD1d64TPseudo:
1096 case ARM::VLD3d8Pseudo_UPD:
1097 case ARM::VLD3d16Pseudo_UPD:
1098 case ARM::VLD3d32Pseudo_UPD:
1099 case ARM::VLD3q8Pseudo_UPD:
1100 case ARM::VLD3q16Pseudo_UPD:
1101 case ARM::VLD3q32Pseudo_UPD:
1102 case ARM::VLD3q8oddPseudo:
1103 case ARM::VLD3q16oddPseudo:
1104 case ARM::VLD3q32oddPseudo:
1105 case ARM::VLD3q8oddPseudo_UPD:
1106 case ARM::VLD3q16oddPseudo_UPD:
1107 case ARM::VLD3q32oddPseudo_UPD:
1108 case ARM::VLD4d8Pseudo:
1109 case ARM::VLD4d16Pseudo:
1110 case ARM::VLD4d32Pseudo:
1111 case ARM::VLD1d64QPseudo:
1112 case ARM::VLD4d8Pseudo_UPD:
1113 case ARM::VLD4d16Pseudo_UPD:
1114 case ARM::VLD4d32Pseudo_UPD:
1115 case ARM::VLD4q8Pseudo_UPD:
1116 case ARM::VLD4q16Pseudo_UPD:
1117 case ARM::VLD4q32Pseudo_UPD:
1118 case ARM::VLD4q8oddPseudo:
1119 case ARM::VLD4q16oddPseudo:
1120 case ARM::VLD4q32oddPseudo:
1121 case ARM::VLD4q8oddPseudo_UPD:
1122 case ARM::VLD4q16oddPseudo_UPD:
1123 case ARM::VLD4q32oddPseudo_UPD:
1124 case ARM::VLD1DUPq8Pseudo:
1125 case ARM::VLD1DUPq16Pseudo:
1126 case ARM::VLD1DUPq32Pseudo:
1127 case ARM::VLD1DUPq8Pseudo_UPD:
1128 case ARM::VLD1DUPq16Pseudo_UPD:
1129 case ARM::VLD1DUPq32Pseudo_UPD:
1130 case ARM::VLD2DUPd8Pseudo:
1131 case ARM::VLD2DUPd16Pseudo:
1132 case ARM::VLD2DUPd32Pseudo:
1133 case ARM::VLD2DUPd8Pseudo_UPD:
1134 case ARM::VLD2DUPd16Pseudo_UPD:
1135 case ARM::VLD2DUPd32Pseudo_UPD:
1136 case ARM::VLD3DUPd8Pseudo:
1137 case ARM::VLD3DUPd16Pseudo:
1138 case ARM::VLD3DUPd32Pseudo:
1139 case ARM::VLD3DUPd8Pseudo_UPD:
1140 case ARM::VLD3DUPd16Pseudo_UPD:
1141 case ARM::VLD3DUPd32Pseudo_UPD:
1142 case ARM::VLD4DUPd8Pseudo:
1143 case ARM::VLD4DUPd16Pseudo:
1144 case ARM::VLD4DUPd32Pseudo:
1145 case ARM::VLD4DUPd8Pseudo_UPD:
1146 case ARM::VLD4DUPd16Pseudo_UPD:
1147 case ARM::VLD4DUPd32Pseudo_UPD:
1151 case ARM::VST1q8Pseudo:
1152 case ARM::VST1q16Pseudo:
1153 case ARM::VST1q32Pseudo:
1154 case ARM::VST1q64Pseudo:
1155 case ARM::VST1q8Pseudo_UPD:
1156 case ARM::VST1q16Pseudo_UPD:
1157 case ARM::VST1q32Pseudo_UPD:
1158 case ARM::VST1q64Pseudo_UPD:
1159 case ARM::VST2d8Pseudo:
1160 case ARM::VST2d16Pseudo:
1161 case ARM::VST2d32Pseudo:
1162 case ARM::VST2q8Pseudo:
1163 case ARM::VST2q16Pseudo:
1164 case ARM::VST2q32Pseudo:
1165 case ARM::VST2d8Pseudo_UPD:
1166 case ARM::VST2d16Pseudo_UPD:
1167 case ARM::VST2d32Pseudo_UPD:
1168 case ARM::VST2q8Pseudo_UPD:
1169 case ARM::VST2q16Pseudo_UPD:
1170 case ARM::VST2q32Pseudo_UPD:
1171 case ARM::VST3d8Pseudo:
1172 case ARM::VST3d16Pseudo:
1173 case ARM::VST3d32Pseudo:
1174 case ARM::VST1d64TPseudo:
1175 case ARM::VST3d8Pseudo_UPD:
1176 case ARM::VST3d16Pseudo_UPD:
1177 case ARM::VST3d32Pseudo_UPD:
1178 case ARM::VST1d64TPseudo_UPD:
1179 case ARM::VST3q8Pseudo_UPD:
1180 case ARM::VST3q16Pseudo_UPD:
1181 case ARM::VST3q32Pseudo_UPD:
1182 case ARM::VST3q8oddPseudo:
1183 case ARM::VST3q16oddPseudo:
1184 case ARM::VST3q32oddPseudo:
1185 case ARM::VST3q8oddPseudo_UPD:
1186 case ARM::VST3q16oddPseudo_UPD:
1187 case ARM::VST3q32oddPseudo_UPD:
1188 case ARM::VST4d8Pseudo:
1189 case ARM::VST4d16Pseudo:
1190 case ARM::VST4d32Pseudo:
1191 case ARM::VST1d64QPseudo:
1192 case ARM::VST4d8Pseudo_UPD:
1193 case ARM::VST4d16Pseudo_UPD:
1194 case ARM::VST4d32Pseudo_UPD:
1195 case ARM::VST1d64QPseudo_UPD:
1196 case ARM::VST4q8Pseudo_UPD:
1197 case ARM::VST4q16Pseudo_UPD:
1198 case ARM::VST4q32Pseudo_UPD:
1199 case ARM::VST4q8oddPseudo:
1200 case ARM::VST4q16oddPseudo:
1201 case ARM::VST4q32oddPseudo:
1202 case ARM::VST4q8oddPseudo_UPD:
1203 case ARM::VST4q16oddPseudo_UPD:
1204 case ARM::VST4q32oddPseudo_UPD:
1208 case ARM::VLD1LNq8Pseudo:
1209 case ARM::VLD1LNq16Pseudo:
1210 case ARM::VLD1LNq32Pseudo:
1211 case ARM::VLD1LNq8Pseudo_UPD:
1212 case ARM::VLD1LNq16Pseudo_UPD:
1213 case ARM::VLD1LNq32Pseudo_UPD:
1214 case ARM::VLD2LNd8Pseudo:
1215 case ARM::VLD2LNd16Pseudo:
1216 case ARM::VLD2LNd32Pseudo:
1217 case ARM::VLD2LNq16Pseudo:
1218 case ARM::VLD2LNq32Pseudo:
1219 case ARM::VLD2LNd8Pseudo_UPD:
1220 case ARM::VLD2LNd16Pseudo_UPD:
1221 case ARM::VLD2LNd32Pseudo_UPD:
1222 case ARM::VLD2LNq16Pseudo_UPD:
1223 case ARM::VLD2LNq32Pseudo_UPD:
1224 case ARM::VLD3LNd8Pseudo:
1225 case ARM::VLD3LNd16Pseudo:
1226 case ARM::VLD3LNd32Pseudo:
1227 case ARM::VLD3LNq16Pseudo:
1228 case ARM::VLD3LNq32Pseudo:
1229 case ARM::VLD3LNd8Pseudo_UPD:
1230 case ARM::VLD3LNd16Pseudo_UPD:
1231 case ARM::VLD3LNd32Pseudo_UPD:
1232 case ARM::VLD3LNq16Pseudo_UPD:
1233 case ARM::VLD3LNq32Pseudo_UPD:
1234 case ARM::VLD4LNd8Pseudo:
1235 case ARM::VLD4LNd16Pseudo:
1236 case ARM::VLD4LNd32Pseudo:
1237 case ARM::VLD4LNq16Pseudo:
1238 case ARM::VLD4LNq32Pseudo:
1239 case ARM::VLD4LNd8Pseudo_UPD:
1240 case ARM::VLD4LNd16Pseudo_UPD:
1241 case ARM::VLD4LNd32Pseudo_UPD:
1242 case ARM::VLD4LNq16Pseudo_UPD:
1243 case ARM::VLD4LNq32Pseudo_UPD:
1244 case ARM::VST1LNq8Pseudo:
1245 case ARM::VST1LNq16Pseudo:
1246 case ARM::VST1LNq32Pseudo:
1247 case ARM::VST1LNq8Pseudo_UPD:
1248 case ARM::VST1LNq16Pseudo_UPD:
1249 case ARM::VST1LNq32Pseudo_UPD:
1250 case ARM::VST2LNd8Pseudo:
1251 case ARM::VST2LNd16Pseudo:
1252 case ARM::VST2LNd32Pseudo:
1253 case ARM::VST2LNq16Pseudo:
1254 case ARM::VST2LNq32Pseudo:
1255 case ARM::VST2LNd8Pseudo_UPD:
1256 case ARM::VST2LNd16Pseudo_UPD:
1257 case ARM::VST2LNd32Pseudo_UPD:
1258 case ARM::VST2LNq16Pseudo_UPD:
1259 case ARM::VST2LNq32Pseudo_UPD:
1260 case ARM::VST3LNd8Pseudo:
1261 case ARM::VST3LNd16Pseudo:
1262 case ARM::VST3LNd32Pseudo:
1263 case ARM::VST3LNq16Pseudo:
1264 case ARM::VST3LNq32Pseudo:
1265 case ARM::VST3LNd8Pseudo_UPD:
1266 case ARM::VST3LNd16Pseudo_UPD:
1267 case ARM::VST3LNd32Pseudo_UPD:
1268 case ARM::VST3LNq16Pseudo_UPD:
1269 case ARM::VST3LNq32Pseudo_UPD:
1270 case ARM::VST4LNd8Pseudo:
1271 case ARM::VST4LNd16Pseudo:
1272 case ARM::VST4LNd32Pseudo:
1273 case ARM::VST4LNq16Pseudo:
1274 case ARM::VST4LNq32Pseudo:
1275 case ARM::VST4LNd8Pseudo_UPD:
1276 case ARM::VST4LNd16Pseudo_UPD:
1277 case ARM::VST4LNd32Pseudo_UPD:
1278 case ARM::VST4LNq16Pseudo_UPD:
1279 case ARM::VST4LNq32Pseudo_UPD:
1283 case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); return true;
1284 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); return true;
1285 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); return true;
1286 case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); return true;
1287 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); return true;
1288 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); return true;
1294 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1295 bool Modified = false;
1297 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1299 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
1300 Modified |= ExpandMI(MBB, MBBI);
1307 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1308 const TargetMachine &TM = MF.getTarget();
1309 TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
1310 TRI = TM.getRegisterInfo();
1311 STI = &TM.getSubtarget<ARMSubtarget>();
1312 AFI = MF.getInfo<ARMFunctionInfo>();
1314 bool Modified = false;
1315 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1317 Modified |= ExpandMBB(*MFI);
1318 if (VerifyARMPseudo)
1319 MF.verify(this, "After expanding ARM pseudo instructions.");
1323 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1325 FunctionPass *llvm::createARMExpandPseudoPass() {
1326 return new ARMExpandPseudo();