1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMBaseInstrInfo.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMRegisterInfo.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/Target/TargetFrameLowering.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
34 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
35 cl::desc("Verify machine code after expanding ARM pseudos"));
38 class ARMExpandPseudo : public MachineFunctionPass {
41 ARMExpandPseudo() : MachineFunctionPass(ID) {}
43 const ARMBaseInstrInfo *TII;
44 const TargetRegisterInfo *TRI;
45 const ARMSubtarget *STI;
48 virtual bool runOnMachineFunction(MachineFunction &Fn);
50 virtual const char *getPassName() const {
51 return "ARM pseudo instruction expansion pass";
55 void TransferImpOps(MachineInstr &OldMI,
56 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
57 bool ExpandMI(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI);
59 bool ExpandMBB(MachineBasicBlock &MBB);
60 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
61 void ExpandVST(MachineBasicBlock::iterator &MBBI);
62 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
63 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
64 unsigned Opc, bool IsExt, unsigned NumRegs);
65 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
66 MachineBasicBlock::iterator &MBBI);
68 char ARMExpandPseudo::ID = 0;
71 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
72 /// the instructions created from the expansion.
73 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
74 MachineInstrBuilder &UseMI,
75 MachineInstrBuilder &DefMI) {
76 const MCInstrDesc &Desc = OldMI.getDesc();
77 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
79 const MachineOperand &MO = OldMI.getOperand(i);
80 assert(MO.isReg() && MO.getReg());
89 // Constants for register spacing in NEON load/store instructions.
90 // For quad-register load-lane and store-lane pseudo instructors, the
91 // spacing is initially assumed to be EvenDblSpc, and that is changed to
92 // OddDblSpc depending on the lane number operand.
99 // Entries for NEON load/store information table. The table is sorted by
100 // PseudoOpc for fast binary-search lookups.
101 struct NEONLdStTableEntry {
105 bool HasWritebackOperand;
106 NEONRegSpacing RegSpacing;
107 unsigned char NumRegs; // D registers loaded or stored
108 unsigned char RegElts; // elements per D register; used for lane ops
109 // FIXME: Temporary flag to denote whether the real instruction takes
110 // a single register (like the encoding) or all of the registers in
111 // the list (like the asm syntax and the isel DAG). When all definitions
112 // are converted to take only the single encoded register, this will
114 bool copyAllListRegs;
116 // Comparison methods for binary search of the table.
117 bool operator<(const NEONLdStTableEntry &TE) const {
118 return PseudoOpc < TE.PseudoOpc;
120 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
121 return TE.PseudoOpc < PseudoOpc;
123 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
124 const NEONLdStTableEntry &TE) {
125 return PseudoOpc < TE.PseudoOpc;
130 static const NEONLdStTableEntry NEONLdStTable[] = {
131 { ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, SingleSpc, 2, 4,true},
132 { ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, SingleSpc, 2, 4,true},
133 { ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, SingleSpc, 2, 2,true},
134 { ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, SingleSpc, 2, 2,true},
135 { ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, SingleSpc, 2, 8,true},
136 { ARM::VLD1DUPq8Pseudo_UPD, ARM::VLD1DUPq8_UPD, true, true, SingleSpc, 2, 8,true},
138 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 ,true},
139 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, EvenDblSpc, 1, 4 ,true},
140 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 ,true},
141 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, EvenDblSpc, 1, 2 ,true},
142 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 ,true},
143 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, EvenDblSpc, 1, 8 ,true},
145 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 ,false},
146 { ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 ,false},
147 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 ,false},
148 { ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 ,false},
150 { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 ,false},
151 { ARM::VLD1q16PseudoWB_fixed, ARM::VLD1q16wb_fixed,true,false,SingleSpc, 2, 4 ,false},
152 { ARM::VLD1q16PseudoWB_register, ARM::VLD1q16wb_register, true, true, SingleSpc, 2, 4 ,false},
153 { ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 ,false},
154 { ARM::VLD1q32PseudoWB_fixed, ARM::VLD1q32wb_fixed,true,false,SingleSpc, 2, 2 ,false},
155 { ARM::VLD1q32PseudoWB_register, ARM::VLD1q32wb_register, true, true, SingleSpc, 2, 2 ,false},
156 { ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 ,false},
157 { ARM::VLD1q64PseudoWB_fixed, ARM::VLD1q64wb_fixed,true,false,SingleSpc, 2, 2 ,false},
158 { ARM::VLD1q64PseudoWB_register, ARM::VLD1q64wb_register, true, true, SingleSpc, 2, 1 ,false},
159 { ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 ,false},
160 { ARM::VLD1q8PseudoWB_fixed, ARM::VLD1q8wb_fixed,true,false, SingleSpc, 2, 8 ,false},
161 { ARM::VLD1q8PseudoWB_register, ARM::VLD1q8wb_register,true,true,SingleSpc,2,8,false},
163 { ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, SingleSpc, 2, 4,true},
164 { ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, SingleSpc, 2, 4,true},
165 { ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, SingleSpc, 2, 2,true},
166 { ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, SingleSpc, 2, 2,true},
167 { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, SingleSpc, 2, 8,true},
168 { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd8_UPD, true, true, SingleSpc, 2, 8,true},
170 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 ,true},
171 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 ,true},
172 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 ,true},
173 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 ,true},
174 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 ,true},
175 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 ,true},
176 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 ,true},
177 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 ,true},
178 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 ,true},
179 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 ,true},
181 { ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 ,false},
182 { ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 ,false},
183 { ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 ,false},
184 { ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 ,false},
185 { ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 ,false},
186 { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 ,false},
188 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 ,false},
189 { ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 ,false},
190 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 ,false},
191 { ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 ,false},
192 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 ,false},
193 { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 ,false},
195 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, SingleSpc, 3, 4,true},
196 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, SingleSpc, 3, 4,true},
197 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, SingleSpc, 3, 2,true},
198 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, SingleSpc, 3, 2,true},
199 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, SingleSpc, 3, 8,true},
200 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, SingleSpc, 3, 8,true},
202 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 ,true},
203 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 ,true},
204 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 ,true},
205 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 ,true},
206 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 ,true},
207 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 ,true},
208 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 ,true},
209 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 ,true},
210 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 ,true},
211 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 ,true},
213 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 ,true},
214 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 ,true},
215 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 ,true},
216 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 ,true},
217 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 ,true},
218 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 ,true},
220 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 ,true},
221 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, OddDblSpc, 3, 4 ,true},
222 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 ,true},
223 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 ,true},
224 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, OddDblSpc, 3, 2 ,true},
225 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 ,true},
226 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 ,true},
227 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, OddDblSpc, 3, 8 ,true},
228 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 ,true},
230 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, SingleSpc, 4, 4,true},
231 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, SingleSpc, 4, 4,true},
232 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, SingleSpc, 4, 2,true},
233 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, SingleSpc, 4, 2,true},
234 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, SingleSpc, 4, 8,true},
235 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, SingleSpc, 4, 8,true},
237 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 ,true},
238 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 ,true},
239 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 ,true},
240 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 ,true},
241 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 ,true},
242 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 ,true},
243 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 ,true},
244 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 ,true},
245 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 ,true},
246 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 ,true},
248 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 ,true},
249 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 ,true},
250 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 ,true},
251 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 ,true},
252 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 ,true},
253 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 ,true},
255 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 ,true},
256 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, OddDblSpc, 4, 4 ,true},
257 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 ,true},
258 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 ,true},
259 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, OddDblSpc, 4, 2 ,true},
260 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 ,true},
261 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 ,true},
262 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, OddDblSpc, 4, 8 ,true},
263 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 ,true},
265 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, EvenDblSpc, 1, 4 ,true},
266 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,false, true, EvenDblSpc, 1, 4 ,true},
267 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, EvenDblSpc, 1, 2 ,true},
268 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,false, true, EvenDblSpc, 1, 2 ,true},
269 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, EvenDblSpc, 1, 8 ,true},
270 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, EvenDblSpc, 1, 8 ,true},
272 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 ,true},
273 { ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 ,true},
274 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 ,true},
275 { ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 ,true},
277 { ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 ,true},
278 { ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 ,true},
279 { ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 ,true},
280 { ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 ,true},
281 { ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 ,true},
282 { ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 ,true},
283 { ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 ,true},
284 { ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 ,true},
286 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 ,true},
287 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 ,true},
288 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 ,true},
289 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 ,true},
290 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 ,true},
291 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 ,true},
292 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4,true},
293 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4,true},
294 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2,true},
295 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2,true},
297 { ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 ,true},
298 { ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 ,true},
299 { ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 ,true},
300 { ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 ,true},
301 { ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 ,true},
302 { ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 ,true},
304 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 ,true},
305 { ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 ,true},
306 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 ,true},
307 { ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 ,true},
308 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 ,true},
309 { ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 ,true},
311 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 ,true},
312 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 ,true},
313 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 ,true},
314 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 ,true},
315 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 ,true},
316 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 ,true},
317 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4,true},
318 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4,true},
319 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2,true},
320 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2,true},
322 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 ,true},
323 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 ,true},
324 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 ,true},
325 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 ,true},
326 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 ,true},
327 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 ,true},
329 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 ,true},
330 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, OddDblSpc, 3, 4 ,true},
331 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 ,true},
332 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 ,true},
333 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, OddDblSpc, 3, 2 ,true},
334 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 ,true},
335 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 ,true},
336 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, OddDblSpc, 3, 8 ,true},
337 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 ,true},
339 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 ,true},
340 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 ,true},
341 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 ,true},
342 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 ,true},
343 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 ,true},
344 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 ,true},
345 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4,true},
346 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4,true},
347 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2,true},
348 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2,true},
350 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 ,true},
351 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 ,true},
352 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 ,true},
353 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 ,true},
354 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 ,true},
355 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 ,true},
357 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 ,true},
358 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, OddDblSpc, 4, 4 ,true},
359 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 ,true},
360 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 ,true},
361 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, OddDblSpc, 4, 2 ,true},
362 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 ,true},
363 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 ,true},
364 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, OddDblSpc, 4, 8 ,true},
365 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 ,true}
368 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
369 /// load or store pseudo instruction.
370 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
371 unsigned NumEntries = array_lengthof(NEONLdStTable);
374 // Make sure the table is sorted.
375 static bool TableChecked = false;
377 for (unsigned i = 0; i != NumEntries-1; ++i)
378 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
379 "NEONLdStTable is not sorted!");
384 const NEONLdStTableEntry *I =
385 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
386 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
391 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
392 /// corresponding to the specified register spacing. Not all of the results
393 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
394 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
395 const TargetRegisterInfo *TRI, unsigned &D0,
396 unsigned &D1, unsigned &D2, unsigned &D3) {
397 if (RegSpc == SingleSpc) {
398 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
399 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
400 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
401 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
402 } else if (RegSpc == EvenDblSpc) {
403 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
404 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
405 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
406 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
408 assert(RegSpc == OddDblSpc && "unknown register spacing");
409 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
410 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
411 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
412 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
416 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
417 /// operands to real VLD instructions with D register operands.
418 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
419 MachineInstr &MI = *MBBI;
420 MachineBasicBlock &MBB = *MI.getParent();
422 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
423 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
424 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
425 unsigned NumRegs = TableEntry->NumRegs;
427 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
428 TII->get(TableEntry->RealOpc));
431 bool DstIsDead = MI.getOperand(OpIdx).isDead();
432 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
433 unsigned D0, D1, D2, D3;
434 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
435 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
436 if (NumRegs > 1 && TableEntry->copyAllListRegs)
437 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
438 if (NumRegs > 2 && TableEntry->copyAllListRegs)
439 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
440 if (NumRegs > 3 && TableEntry->copyAllListRegs)
441 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
443 if (TableEntry->HasWritebackOperand)
444 MIB.addOperand(MI.getOperand(OpIdx++));
446 // Copy the addrmode6 operands.
447 MIB.addOperand(MI.getOperand(OpIdx++));
448 MIB.addOperand(MI.getOperand(OpIdx++));
449 // Copy the am6offset operand.
450 if (TableEntry->HasWritebackOperand)
451 MIB.addOperand(MI.getOperand(OpIdx++));
453 // For an instruction writing double-spaced subregs, the pseudo instruction
454 // has an extra operand that is a use of the super-register. Record the
455 // operand index and skip over it.
456 unsigned SrcOpIdx = 0;
457 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
460 // Copy the predicate operands.
461 MIB.addOperand(MI.getOperand(OpIdx++));
462 MIB.addOperand(MI.getOperand(OpIdx++));
464 // Copy the super-register source operand used for double-spaced subregs over
465 // to the new instruction as an implicit operand.
467 MachineOperand MO = MI.getOperand(SrcOpIdx);
468 MO.setImplicit(true);
471 // Add an implicit def for the super-register.
472 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
473 TransferImpOps(MI, MIB, MIB);
475 // Transfer memoperands.
476 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
478 MI.eraseFromParent();
481 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
482 /// operands to real VST instructions with D register operands.
483 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
484 MachineInstr &MI = *MBBI;
485 MachineBasicBlock &MBB = *MI.getParent();
487 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
488 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
489 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
490 unsigned NumRegs = TableEntry->NumRegs;
492 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
493 TII->get(TableEntry->RealOpc));
495 if (TableEntry->HasWritebackOperand)
496 MIB.addOperand(MI.getOperand(OpIdx++));
498 // Copy the addrmode6 operands.
499 MIB.addOperand(MI.getOperand(OpIdx++));
500 MIB.addOperand(MI.getOperand(OpIdx++));
501 // Copy the am6offset operand.
502 if (TableEntry->HasWritebackOperand)
503 MIB.addOperand(MI.getOperand(OpIdx++));
505 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
506 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
507 unsigned D0, D1, D2, D3;
508 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
509 MIB.addReg(D0).addReg(D1);
515 // Copy the predicate operands.
516 MIB.addOperand(MI.getOperand(OpIdx++));
517 MIB.addOperand(MI.getOperand(OpIdx++));
519 if (SrcIsKill) // Add an implicit kill for the super-reg.
520 MIB->addRegisterKilled(SrcReg, TRI, true);
521 TransferImpOps(MI, MIB, MIB);
523 // Transfer memoperands.
524 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
526 MI.eraseFromParent();
529 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
530 /// register operands to real instructions with D register operands.
531 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
532 MachineInstr &MI = *MBBI;
533 MachineBasicBlock &MBB = *MI.getParent();
535 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
536 assert(TableEntry && "NEONLdStTable lookup failed");
537 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
538 unsigned NumRegs = TableEntry->NumRegs;
539 unsigned RegElts = TableEntry->RegElts;
541 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
542 TII->get(TableEntry->RealOpc));
544 // The lane operand is always the 3rd from last operand, before the 2
545 // predicate operands.
546 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
548 // Adjust the lane and spacing as needed for Q registers.
549 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
550 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
554 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
556 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
558 bool DstIsDead = false;
559 if (TableEntry->IsLoad) {
560 DstIsDead = MI.getOperand(OpIdx).isDead();
561 DstReg = MI.getOperand(OpIdx++).getReg();
562 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
563 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
565 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
567 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
569 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
572 if (TableEntry->HasWritebackOperand)
573 MIB.addOperand(MI.getOperand(OpIdx++));
575 // Copy the addrmode6 operands.
576 MIB.addOperand(MI.getOperand(OpIdx++));
577 MIB.addOperand(MI.getOperand(OpIdx++));
578 // Copy the am6offset operand.
579 if (TableEntry->HasWritebackOperand)
580 MIB.addOperand(MI.getOperand(OpIdx++));
582 // Grab the super-register source.
583 MachineOperand MO = MI.getOperand(OpIdx++);
584 if (!TableEntry->IsLoad)
585 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
587 // Add the subregs as sources of the new instruction.
588 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
589 getKillRegState(MO.isKill()));
590 MIB.addReg(D0, SrcFlags);
592 MIB.addReg(D1, SrcFlags);
594 MIB.addReg(D2, SrcFlags);
596 MIB.addReg(D3, SrcFlags);
598 // Add the lane number operand.
602 // Copy the predicate operands.
603 MIB.addOperand(MI.getOperand(OpIdx++));
604 MIB.addOperand(MI.getOperand(OpIdx++));
606 // Copy the super-register source to be an implicit source.
607 MO.setImplicit(true);
609 if (TableEntry->IsLoad)
610 // Add an implicit def for the super-register.
611 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
612 TransferImpOps(MI, MIB, MIB);
613 MI.eraseFromParent();
616 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
617 /// register operands to real instructions with D register operands.
618 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
619 unsigned Opc, bool IsExt, unsigned NumRegs) {
620 MachineInstr &MI = *MBBI;
621 MachineBasicBlock &MBB = *MI.getParent();
623 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
626 // Transfer the destination register operand.
627 MIB.addOperand(MI.getOperand(OpIdx++));
629 MIB.addOperand(MI.getOperand(OpIdx++));
631 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
632 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
633 unsigned D0, D1, D2, D3;
634 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
635 MIB.addReg(D0).addReg(D1);
641 // Copy the other source register operand.
642 MIB.addOperand(MI.getOperand(OpIdx++));
644 // Copy the predicate operands.
645 MIB.addOperand(MI.getOperand(OpIdx++));
646 MIB.addOperand(MI.getOperand(OpIdx++));
648 if (SrcIsKill) // Add an implicit kill for the super-reg.
649 MIB->addRegisterKilled(SrcReg, TRI, true);
650 TransferImpOps(MI, MIB, MIB);
651 MI.eraseFromParent();
654 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
655 MachineBasicBlock::iterator &MBBI) {
656 MachineInstr &MI = *MBBI;
657 unsigned Opcode = MI.getOpcode();
658 unsigned PredReg = 0;
659 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
660 unsigned DstReg = MI.getOperand(0).getReg();
661 bool DstIsDead = MI.getOperand(0).isDead();
662 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
663 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
664 MachineInstrBuilder LO16, HI16;
666 if (!STI->hasV6T2Ops() &&
667 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
668 // Expand into a movi + orr.
669 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
670 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
671 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
674 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
675 unsigned ImmVal = (unsigned)MO.getImm();
676 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
677 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
678 LO16 = LO16.addImm(SOImmValV1);
679 HI16 = HI16.addImm(SOImmValV2);
680 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
681 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
682 LO16.addImm(Pred).addReg(PredReg).addReg(0);
683 HI16.addImm(Pred).addReg(PredReg).addReg(0);
684 TransferImpOps(MI, LO16, HI16);
685 MI.eraseFromParent();
689 unsigned LO16Opc = 0;
690 unsigned HI16Opc = 0;
691 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
692 LO16Opc = ARM::t2MOVi16;
693 HI16Opc = ARM::t2MOVTi16;
695 LO16Opc = ARM::MOVi16;
696 HI16Opc = ARM::MOVTi16;
699 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
700 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
701 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
705 unsigned Imm = MO.getImm();
706 unsigned Lo16 = Imm & 0xffff;
707 unsigned Hi16 = (Imm >> 16) & 0xffff;
708 LO16 = LO16.addImm(Lo16);
709 HI16 = HI16.addImm(Hi16);
711 const GlobalValue *GV = MO.getGlobal();
712 unsigned TF = MO.getTargetFlags();
713 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
714 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
717 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
718 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
719 LO16.addImm(Pred).addReg(PredReg);
720 HI16.addImm(Pred).addReg(PredReg);
722 TransferImpOps(MI, LO16, HI16);
723 MI.eraseFromParent();
726 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
727 MachineBasicBlock::iterator MBBI) {
728 MachineInstr &MI = *MBBI;
729 unsigned Opcode = MI.getOpcode();
735 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
736 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
737 MI.getOperand(1).getReg())
738 .addReg(MI.getOperand(2).getReg(),
739 getKillRegState(MI.getOperand(2).isKill()))
740 .addImm(MI.getOperand(3).getImm()) // 'pred'
741 .addReg(MI.getOperand(4).getReg());
743 MI.eraseFromParent();
748 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
749 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
750 MI.getOperand(1).getReg())
751 .addReg(MI.getOperand(2).getReg(),
752 getKillRegState(MI.getOperand(2).isKill()))
753 .addImm(MI.getOperand(3).getImm()) // 'pred'
754 .addReg(MI.getOperand(4).getReg())
755 .addReg(0); // 's' bit
757 MI.eraseFromParent();
761 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
762 (MI.getOperand(1).getReg()))
763 .addReg(MI.getOperand(2).getReg(),
764 getKillRegState(MI.getOperand(2).isKill()))
765 .addImm(MI.getOperand(3).getImm())
766 .addImm(MI.getOperand(4).getImm()) // 'pred'
767 .addReg(MI.getOperand(5).getReg())
768 .addReg(0); // 's' bit
770 MI.eraseFromParent();
775 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
776 (MI.getOperand(1).getReg()))
777 .addReg(MI.getOperand(2).getReg(),
778 getKillRegState(MI.getOperand(2).isKill()))
779 .addReg(MI.getOperand(3).getReg(),
780 getKillRegState(MI.getOperand(3).isKill()))
781 .addImm(MI.getOperand(4).getImm())
782 .addImm(MI.getOperand(5).getImm()) // 'pred'
783 .addReg(MI.getOperand(6).getReg())
784 .addReg(0); // 's' bit
786 MI.eraseFromParent();
789 case ARM::MOVCCi16: {
790 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi16),
791 MI.getOperand(1).getReg())
792 .addImm(MI.getOperand(2).getImm())
793 .addImm(MI.getOperand(3).getImm()) // 'pred'
794 .addReg(MI.getOperand(4).getReg());
796 MI.eraseFromParent();
801 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
802 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
803 MI.getOperand(1).getReg())
804 .addImm(MI.getOperand(2).getImm())
805 .addImm(MI.getOperand(3).getImm()) // 'pred'
806 .addReg(MI.getOperand(4).getReg())
807 .addReg(0); // 's' bit
809 MI.eraseFromParent();
813 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi),
814 MI.getOperand(1).getReg())
815 .addImm(MI.getOperand(2).getImm())
816 .addImm(MI.getOperand(3).getImm()) // 'pred'
817 .addReg(MI.getOperand(4).getReg())
818 .addReg(0); // 's' bit
820 MI.eraseFromParent();
823 case ARM::Int_eh_sjlj_dispatchsetup: {
824 MachineFunction &MF = *MI.getParent()->getParent();
825 const ARMBaseInstrInfo *AII =
826 static_cast<const ARMBaseInstrInfo*>(TII);
827 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
828 // For functions using a base pointer, we rematerialize it (via the frame
829 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
830 // for us. Otherwise, expand to nothing.
831 if (RI.hasBasePointer(MF)) {
832 int32_t NumBytes = AFI->getFramePtrSpillOffset();
833 unsigned FramePtr = RI.getFrameRegister(MF);
834 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
835 "base pointer without frame pointer?");
837 if (AFI->isThumb2Function()) {
838 llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
839 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
840 } else if (AFI->isThumbFunction()) {
841 llvm::emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
842 FramePtr, -NumBytes, *TII, RI);
844 llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
845 FramePtr, -NumBytes, ARMCC::AL, 0,
848 // If there's dynamic realignment, adjust for it.
849 if (RI.needsStackRealignment(MF)) {
850 MachineFrameInfo *MFI = MF.getFrameInfo();
851 unsigned MaxAlign = MFI->getMaxAlignment();
852 assert (!AFI->isThumb1OnlyFunction());
853 // Emit bic r6, r6, MaxAlign
854 unsigned bicOpc = AFI->isThumbFunction() ?
855 ARM::t2BICri : ARM::BICri;
856 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
857 TII->get(bicOpc), ARM::R6)
858 .addReg(ARM::R6, RegState::Kill)
859 .addImm(MaxAlign-1)));
863 MI.eraseFromParent();
867 case ARM::MOVsrl_flag:
868 case ARM::MOVsra_flag: {
869 // These are just fancy MOVs insructions.
870 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
871 MI.getOperand(0).getReg())
872 .addOperand(MI.getOperand(1))
873 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
874 ARM_AM::lsr : ARM_AM::asr),
876 .addReg(ARM::CPSR, RegState::Define);
877 MI.eraseFromParent();
881 // This encodes as "MOVs Rd, Rm, rrx
882 MachineInstrBuilder MIB =
883 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
884 MI.getOperand(0).getReg())
885 .addOperand(MI.getOperand(1))
886 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
888 TransferImpOps(MI, MIB, MIB);
889 MI.eraseFromParent();
894 MachineInstrBuilder MIB =
895 BuildMI(MBB, MBBI, MI.getDebugLoc(),
896 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
897 .addExternalSymbol("__aeabi_read_tp", 0);
899 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
900 TransferImpOps(MI, MIB, MIB);
901 MI.eraseFromParent();
904 case ARM::tLDRpci_pic:
905 case ARM::t2LDRpci_pic: {
906 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
907 ? ARM::tLDRpci : ARM::t2LDRpci;
908 unsigned DstReg = MI.getOperand(0).getReg();
909 bool DstIsDead = MI.getOperand(0).isDead();
910 MachineInstrBuilder MIB1 =
911 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
912 TII->get(NewLdOpc), DstReg)
913 .addOperand(MI.getOperand(1)));
914 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
915 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
916 TII->get(ARM::tPICADD))
917 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
919 .addOperand(MI.getOperand(2));
920 TransferImpOps(MI, MIB1, MIB2);
921 MI.eraseFromParent();
925 case ARM::MOV_ga_dyn:
926 case ARM::MOV_ga_pcrel:
927 case ARM::MOV_ga_pcrel_ldr:
928 case ARM::t2MOV_ga_dyn:
929 case ARM::t2MOV_ga_pcrel: {
930 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
931 unsigned LabelId = AFI->createPICLabelUId();
932 unsigned DstReg = MI.getOperand(0).getReg();
933 bool DstIsDead = MI.getOperand(0).isDead();
934 const MachineOperand &MO1 = MI.getOperand(1);
935 const GlobalValue *GV = MO1.getGlobal();
936 unsigned TF = MO1.getTargetFlags();
937 bool isARM = (Opcode != ARM::t2MOV_ga_pcrel && Opcode!=ARM::t2MOV_ga_dyn);
938 bool isPIC = (Opcode != ARM::MOV_ga_dyn && Opcode != ARM::t2MOV_ga_dyn);
939 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
940 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
941 unsigned LO16TF = isPIC
942 ? ARMII::MO_LO16_NONLAZY_PIC : ARMII::MO_LO16_NONLAZY;
943 unsigned HI16TF = isPIC
944 ? ARMII::MO_HI16_NONLAZY_PIC : ARMII::MO_HI16_NONLAZY;
945 unsigned PICAddOpc = isARM
946 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
948 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
949 TII->get(LO16Opc), DstReg)
950 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
952 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
953 TII->get(HI16Opc), DstReg)
955 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
958 TransferImpOps(MI, MIB1, MIB2);
959 MI.eraseFromParent();
963 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
965 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
966 .addReg(DstReg).addImm(LabelId);
968 AddDefaultPred(MIB3);
969 if (Opcode == ARM::MOV_ga_pcrel_ldr)
970 MIB2->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
972 TransferImpOps(MI, MIB1, MIB3);
973 MI.eraseFromParent();
978 case ARM::MOVCCi32imm:
979 case ARM::t2MOVi32imm:
980 case ARM::t2MOVCCi32imm:
981 ExpandMOV32BitImm(MBB, MBBI);
985 unsigned NewOpc = ARM::VLDMDIA;
986 MachineInstrBuilder MIB =
987 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
990 // Grab the Q register destination.
991 bool DstIsDead = MI.getOperand(OpIdx).isDead();
992 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
994 // Copy the source register.
995 MIB.addOperand(MI.getOperand(OpIdx++));
997 // Copy the predicate operands.
998 MIB.addOperand(MI.getOperand(OpIdx++));
999 MIB.addOperand(MI.getOperand(OpIdx++));
1001 // Add the destination operands (D subregs).
1002 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1003 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1004 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1005 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1007 // Add an implicit def for the super-register.
1008 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1009 TransferImpOps(MI, MIB, MIB);
1010 MI.eraseFromParent();
1014 case ARM::VSTMQIA: {
1015 unsigned NewOpc = ARM::VSTMDIA;
1016 MachineInstrBuilder MIB =
1017 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1020 // Grab the Q register source.
1021 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1022 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1024 // Copy the destination register.
1025 MIB.addOperand(MI.getOperand(OpIdx++));
1027 // Copy the predicate operands.
1028 MIB.addOperand(MI.getOperand(OpIdx++));
1029 MIB.addOperand(MI.getOperand(OpIdx++));
1031 // Add the source operands (D subregs).
1032 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1033 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1034 MIB.addReg(D0).addReg(D1);
1036 if (SrcIsKill) // Add an implicit kill for the Q register.
1037 MIB->addRegisterKilled(SrcReg, TRI, true);
1039 TransferImpOps(MI, MIB, MIB);
1040 MI.eraseFromParent();
1045 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q :
1047 MachineInstrBuilder MIB =
1048 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1050 unsigned SrcReg = MI.getOperand(1).getReg();
1051 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
1052 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
1053 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
1054 &ARM::DPR_VFP2RegClass);
1055 // The lane is [0,1] for the containing DReg superregister.
1056 // Copy the dst/src register operands.
1057 MIB.addOperand(MI.getOperand(OpIdx++));
1060 // Add the lane select operand.
1062 // Add the predicate operands.
1063 MIB.addOperand(MI.getOperand(OpIdx++));
1064 MIB.addOperand(MI.getOperand(OpIdx++));
1066 TransferImpOps(MI, MIB, MIB);
1067 MI.eraseFromParent();
1071 case ARM::VLD1q8Pseudo:
1072 case ARM::VLD1q16Pseudo:
1073 case ARM::VLD1q32Pseudo:
1074 case ARM::VLD1q64Pseudo:
1075 case ARM::VLD1q8PseudoWB_register:
1076 case ARM::VLD1q16PseudoWB_register:
1077 case ARM::VLD1q32PseudoWB_register:
1078 case ARM::VLD1q64PseudoWB_register:
1079 case ARM::VLD1q8PseudoWB_fixed:
1080 case ARM::VLD1q16PseudoWB_fixed:
1081 case ARM::VLD1q32PseudoWB_fixed:
1082 case ARM::VLD1q64PseudoWB_fixed:
1083 case ARM::VLD2d8Pseudo:
1084 case ARM::VLD2d16Pseudo:
1085 case ARM::VLD2d32Pseudo:
1086 case ARM::VLD2q8Pseudo:
1087 case ARM::VLD2q16Pseudo:
1088 case ARM::VLD2q32Pseudo:
1089 case ARM::VLD2d8Pseudo_UPD:
1090 case ARM::VLD2d16Pseudo_UPD:
1091 case ARM::VLD2d32Pseudo_UPD:
1092 case ARM::VLD2q8Pseudo_UPD:
1093 case ARM::VLD2q16Pseudo_UPD:
1094 case ARM::VLD2q32Pseudo_UPD:
1095 case ARM::VLD3d8Pseudo:
1096 case ARM::VLD3d16Pseudo:
1097 case ARM::VLD3d32Pseudo:
1098 case ARM::VLD1d64TPseudo:
1099 case ARM::VLD3d8Pseudo_UPD:
1100 case ARM::VLD3d16Pseudo_UPD:
1101 case ARM::VLD3d32Pseudo_UPD:
1102 case ARM::VLD1d64TPseudo_UPD:
1103 case ARM::VLD3q8Pseudo_UPD:
1104 case ARM::VLD3q16Pseudo_UPD:
1105 case ARM::VLD3q32Pseudo_UPD:
1106 case ARM::VLD3q8oddPseudo:
1107 case ARM::VLD3q16oddPseudo:
1108 case ARM::VLD3q32oddPseudo:
1109 case ARM::VLD3q8oddPseudo_UPD:
1110 case ARM::VLD3q16oddPseudo_UPD:
1111 case ARM::VLD3q32oddPseudo_UPD:
1112 case ARM::VLD4d8Pseudo:
1113 case ARM::VLD4d16Pseudo:
1114 case ARM::VLD4d32Pseudo:
1115 case ARM::VLD1d64QPseudo:
1116 case ARM::VLD4d8Pseudo_UPD:
1117 case ARM::VLD4d16Pseudo_UPD:
1118 case ARM::VLD4d32Pseudo_UPD:
1119 case ARM::VLD1d64QPseudo_UPD:
1120 case ARM::VLD4q8Pseudo_UPD:
1121 case ARM::VLD4q16Pseudo_UPD:
1122 case ARM::VLD4q32Pseudo_UPD:
1123 case ARM::VLD4q8oddPseudo:
1124 case ARM::VLD4q16oddPseudo:
1125 case ARM::VLD4q32oddPseudo:
1126 case ARM::VLD4q8oddPseudo_UPD:
1127 case ARM::VLD4q16oddPseudo_UPD:
1128 case ARM::VLD4q32oddPseudo_UPD:
1129 case ARM::VLD1DUPq8Pseudo:
1130 case ARM::VLD1DUPq16Pseudo:
1131 case ARM::VLD1DUPq32Pseudo:
1132 case ARM::VLD1DUPq8Pseudo_UPD:
1133 case ARM::VLD1DUPq16Pseudo_UPD:
1134 case ARM::VLD1DUPq32Pseudo_UPD:
1135 case ARM::VLD2DUPd8Pseudo:
1136 case ARM::VLD2DUPd16Pseudo:
1137 case ARM::VLD2DUPd32Pseudo:
1138 case ARM::VLD2DUPd8Pseudo_UPD:
1139 case ARM::VLD2DUPd16Pseudo_UPD:
1140 case ARM::VLD2DUPd32Pseudo_UPD:
1141 case ARM::VLD3DUPd8Pseudo:
1142 case ARM::VLD3DUPd16Pseudo:
1143 case ARM::VLD3DUPd32Pseudo:
1144 case ARM::VLD3DUPd8Pseudo_UPD:
1145 case ARM::VLD3DUPd16Pseudo_UPD:
1146 case ARM::VLD3DUPd32Pseudo_UPD:
1147 case ARM::VLD4DUPd8Pseudo:
1148 case ARM::VLD4DUPd16Pseudo:
1149 case ARM::VLD4DUPd32Pseudo:
1150 case ARM::VLD4DUPd8Pseudo_UPD:
1151 case ARM::VLD4DUPd16Pseudo_UPD:
1152 case ARM::VLD4DUPd32Pseudo_UPD:
1156 case ARM::VST1q8Pseudo:
1157 case ARM::VST1q16Pseudo:
1158 case ARM::VST1q32Pseudo:
1159 case ARM::VST1q64Pseudo:
1160 case ARM::VST1q8Pseudo_UPD:
1161 case ARM::VST1q16Pseudo_UPD:
1162 case ARM::VST1q32Pseudo_UPD:
1163 case ARM::VST1q64Pseudo_UPD:
1164 case ARM::VST2d8Pseudo:
1165 case ARM::VST2d16Pseudo:
1166 case ARM::VST2d32Pseudo:
1167 case ARM::VST2q8Pseudo:
1168 case ARM::VST2q16Pseudo:
1169 case ARM::VST2q32Pseudo:
1170 case ARM::VST2d8Pseudo_UPD:
1171 case ARM::VST2d16Pseudo_UPD:
1172 case ARM::VST2d32Pseudo_UPD:
1173 case ARM::VST2q8Pseudo_UPD:
1174 case ARM::VST2q16Pseudo_UPD:
1175 case ARM::VST2q32Pseudo_UPD:
1176 case ARM::VST3d8Pseudo:
1177 case ARM::VST3d16Pseudo:
1178 case ARM::VST3d32Pseudo:
1179 case ARM::VST1d64TPseudo:
1180 case ARM::VST3d8Pseudo_UPD:
1181 case ARM::VST3d16Pseudo_UPD:
1182 case ARM::VST3d32Pseudo_UPD:
1183 case ARM::VST1d64TPseudo_UPD:
1184 case ARM::VST3q8Pseudo_UPD:
1185 case ARM::VST3q16Pseudo_UPD:
1186 case ARM::VST3q32Pseudo_UPD:
1187 case ARM::VST3q8oddPseudo:
1188 case ARM::VST3q16oddPseudo:
1189 case ARM::VST3q32oddPseudo:
1190 case ARM::VST3q8oddPseudo_UPD:
1191 case ARM::VST3q16oddPseudo_UPD:
1192 case ARM::VST3q32oddPseudo_UPD:
1193 case ARM::VST4d8Pseudo:
1194 case ARM::VST4d16Pseudo:
1195 case ARM::VST4d32Pseudo:
1196 case ARM::VST1d64QPseudo:
1197 case ARM::VST4d8Pseudo_UPD:
1198 case ARM::VST4d16Pseudo_UPD:
1199 case ARM::VST4d32Pseudo_UPD:
1200 case ARM::VST1d64QPseudo_UPD:
1201 case ARM::VST4q8Pseudo_UPD:
1202 case ARM::VST4q16Pseudo_UPD:
1203 case ARM::VST4q32Pseudo_UPD:
1204 case ARM::VST4q8oddPseudo:
1205 case ARM::VST4q16oddPseudo:
1206 case ARM::VST4q32oddPseudo:
1207 case ARM::VST4q8oddPseudo_UPD:
1208 case ARM::VST4q16oddPseudo_UPD:
1209 case ARM::VST4q32oddPseudo_UPD:
1213 case ARM::VLD1LNq8Pseudo:
1214 case ARM::VLD1LNq16Pseudo:
1215 case ARM::VLD1LNq32Pseudo:
1216 case ARM::VLD1LNq8Pseudo_UPD:
1217 case ARM::VLD1LNq16Pseudo_UPD:
1218 case ARM::VLD1LNq32Pseudo_UPD:
1219 case ARM::VLD2LNd8Pseudo:
1220 case ARM::VLD2LNd16Pseudo:
1221 case ARM::VLD2LNd32Pseudo:
1222 case ARM::VLD2LNq16Pseudo:
1223 case ARM::VLD2LNq32Pseudo:
1224 case ARM::VLD2LNd8Pseudo_UPD:
1225 case ARM::VLD2LNd16Pseudo_UPD:
1226 case ARM::VLD2LNd32Pseudo_UPD:
1227 case ARM::VLD2LNq16Pseudo_UPD:
1228 case ARM::VLD2LNq32Pseudo_UPD:
1229 case ARM::VLD3LNd8Pseudo:
1230 case ARM::VLD3LNd16Pseudo:
1231 case ARM::VLD3LNd32Pseudo:
1232 case ARM::VLD3LNq16Pseudo:
1233 case ARM::VLD3LNq32Pseudo:
1234 case ARM::VLD3LNd8Pseudo_UPD:
1235 case ARM::VLD3LNd16Pseudo_UPD:
1236 case ARM::VLD3LNd32Pseudo_UPD:
1237 case ARM::VLD3LNq16Pseudo_UPD:
1238 case ARM::VLD3LNq32Pseudo_UPD:
1239 case ARM::VLD4LNd8Pseudo:
1240 case ARM::VLD4LNd16Pseudo:
1241 case ARM::VLD4LNd32Pseudo:
1242 case ARM::VLD4LNq16Pseudo:
1243 case ARM::VLD4LNq32Pseudo:
1244 case ARM::VLD4LNd8Pseudo_UPD:
1245 case ARM::VLD4LNd16Pseudo_UPD:
1246 case ARM::VLD4LNd32Pseudo_UPD:
1247 case ARM::VLD4LNq16Pseudo_UPD:
1248 case ARM::VLD4LNq32Pseudo_UPD:
1249 case ARM::VST1LNq8Pseudo:
1250 case ARM::VST1LNq16Pseudo:
1251 case ARM::VST1LNq32Pseudo:
1252 case ARM::VST1LNq8Pseudo_UPD:
1253 case ARM::VST1LNq16Pseudo_UPD:
1254 case ARM::VST1LNq32Pseudo_UPD:
1255 case ARM::VST2LNd8Pseudo:
1256 case ARM::VST2LNd16Pseudo:
1257 case ARM::VST2LNd32Pseudo:
1258 case ARM::VST2LNq16Pseudo:
1259 case ARM::VST2LNq32Pseudo:
1260 case ARM::VST2LNd8Pseudo_UPD:
1261 case ARM::VST2LNd16Pseudo_UPD:
1262 case ARM::VST2LNd32Pseudo_UPD:
1263 case ARM::VST2LNq16Pseudo_UPD:
1264 case ARM::VST2LNq32Pseudo_UPD:
1265 case ARM::VST3LNd8Pseudo:
1266 case ARM::VST3LNd16Pseudo:
1267 case ARM::VST3LNd32Pseudo:
1268 case ARM::VST3LNq16Pseudo:
1269 case ARM::VST3LNq32Pseudo:
1270 case ARM::VST3LNd8Pseudo_UPD:
1271 case ARM::VST3LNd16Pseudo_UPD:
1272 case ARM::VST3LNd32Pseudo_UPD:
1273 case ARM::VST3LNq16Pseudo_UPD:
1274 case ARM::VST3LNq32Pseudo_UPD:
1275 case ARM::VST4LNd8Pseudo:
1276 case ARM::VST4LNd16Pseudo:
1277 case ARM::VST4LNd32Pseudo:
1278 case ARM::VST4LNq16Pseudo:
1279 case ARM::VST4LNq32Pseudo:
1280 case ARM::VST4LNd8Pseudo_UPD:
1281 case ARM::VST4LNd16Pseudo_UPD:
1282 case ARM::VST4LNd32Pseudo_UPD:
1283 case ARM::VST4LNq16Pseudo_UPD:
1284 case ARM::VST4LNq32Pseudo_UPD:
1288 case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); return true;
1289 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); return true;
1290 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); return true;
1291 case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); return true;
1292 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); return true;
1293 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); return true;
1299 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1300 bool Modified = false;
1302 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1304 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
1305 Modified |= ExpandMI(MBB, MBBI);
1312 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1313 const TargetMachine &TM = MF.getTarget();
1314 TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
1315 TRI = TM.getRegisterInfo();
1316 STI = &TM.getSubtarget<ARMSubtarget>();
1317 AFI = MF.getInfo<ARMFunctionInfo>();
1319 bool Modified = false;
1320 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1322 Modified |= ExpandMBB(*MFI);
1323 if (VerifyARMPseudo)
1324 MF.verify(this, "After expanding ARM pseudo instructions.");
1328 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1330 FunctionPass *llvm::createARMExpandPseudoPass() {
1331 return new ARMExpandPseudo();