1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMAddressingModes.h"
20 #include "ARMBaseInstrInfo.h"
21 #include "ARMBaseRegisterInfo.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMRegisterInfo.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
32 class ARMExpandPseudo : public MachineFunctionPass {
35 ARMExpandPseudo() : MachineFunctionPass(ID) {}
37 const ARMBaseInstrInfo *TII;
38 const TargetRegisterInfo *TRI;
40 virtual bool runOnMachineFunction(MachineFunction &Fn);
42 virtual const char *getPassName() const {
43 return "ARM pseudo instruction expansion pass";
47 void TransferImpOps(MachineInstr &OldMI,
48 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
49 bool ExpandMBB(MachineBasicBlock &MBB);
50 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
51 void ExpandVST(MachineBasicBlock::iterator &MBBI);
52 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
53 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
54 unsigned Opc, bool IsExt, unsigned NumRegs);
56 char ARMExpandPseudo::ID = 0;
59 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
60 /// the instructions created from the expansion.
61 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
62 MachineInstrBuilder &UseMI,
63 MachineInstrBuilder &DefMI) {
64 const TargetInstrDesc &Desc = OldMI.getDesc();
65 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
67 const MachineOperand &MO = OldMI.getOperand(i);
68 assert(MO.isReg() && MO.getReg());
77 // Constants for register spacing in NEON load/store instructions.
78 // For quad-register load-lane and store-lane pseudo instructors, the
79 // spacing is initially assumed to be EvenDblSpc, and that is changed to
80 // OddDblSpc depending on the lane number operand.
87 // Entries for NEON load/store information table. The table is sorted by
88 // PseudoOpc for fast binary-search lookups.
89 struct NEONLdStTableEntry {
94 NEONRegSpacing RegSpacing;
95 unsigned char NumRegs; // D registers loaded or stored
96 unsigned char RegElts; // elements per D register; used for lane ops
98 // Comparison methods for binary search of the table.
99 bool operator<(const NEONLdStTableEntry &TE) const {
100 return PseudoOpc < TE.PseudoOpc;
102 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
103 return TE.PseudoOpc < PseudoOpc;
105 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
106 const NEONLdStTableEntry &TE) {
107 return PseudoOpc < TE.PseudoOpc;
112 static const NEONLdStTableEntry NEONLdStTable[] = {
113 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 },
114 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, false, EvenDblSpc, 1, 4 },
115 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 },
116 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, false, EvenDblSpc, 1, 2 },
117 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 },
118 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, false, EvenDblSpc, 1, 8 },
120 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 },
121 { ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 },
122 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 },
123 { ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 },
125 { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 },
126 { ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 },
127 { ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 },
128 { ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 },
129 { ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 },
130 { ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 },
131 { ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 },
132 { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 },
134 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 },
135 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 },
136 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 },
137 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 },
138 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 },
139 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 },
140 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 },
141 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 },
142 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 },
143 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 },
145 { ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 },
146 { ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 },
147 { ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 },
148 { ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 },
149 { ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 },
150 { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 },
152 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 },
153 { ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 },
154 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 },
155 { ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 },
156 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 },
157 { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 },
159 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 },
160 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 },
161 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 },
162 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 },
163 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 },
164 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 },
165 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 },
166 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 },
167 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 },
168 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 },
170 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 },
171 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 },
172 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 },
173 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 },
174 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 },
175 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 },
177 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 },
178 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 },
179 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 },
180 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 },
181 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 },
182 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 },
184 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 },
185 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 },
186 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 },
187 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 },
188 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 },
189 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 },
190 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 },
191 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 },
192 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 },
193 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 },
195 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 },
196 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 },
197 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 },
198 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 },
199 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 },
200 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 },
202 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 },
203 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 },
204 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 },
205 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 },
206 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 },
207 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 },
209 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 },
210 { ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 },
211 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 },
212 { ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 },
214 { ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 },
215 { ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 },
216 { ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 },
217 { ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 },
218 { ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 },
219 { ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 },
220 { ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 },
221 { ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 },
223 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 },
224 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 },
225 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 },
226 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 },
227 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 },
228 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 },
229 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4},
230 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4},
231 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2},
232 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2},
234 { ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 },
235 { ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 },
236 { ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 },
237 { ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 },
238 { ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 },
239 { ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 },
241 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 },
242 { ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 },
243 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 },
244 { ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 },
245 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 },
246 { ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 },
248 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 },
249 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 },
250 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 },
251 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 },
252 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 },
253 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 },
254 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4},
255 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4},
256 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2},
257 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2},
259 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 },
260 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 },
261 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 },
262 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 },
263 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 },
264 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 },
266 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 },
267 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 },
268 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 },
269 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 },
270 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 },
271 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 },
273 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 },
274 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 },
275 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 },
276 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 },
277 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 },
278 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 },
279 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4},
280 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4},
281 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2},
282 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2},
284 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 },
285 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 },
286 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 },
287 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 },
288 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 },
289 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 },
291 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 },
292 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 },
293 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 },
294 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 },
295 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 },
296 { ARM::VST4q8oddPseudo_UPD , ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 }
299 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
300 /// load or store pseudo instruction.
301 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
302 unsigned NumEntries = array_lengthof(NEONLdStTable);
305 // Make sure the table is sorted.
306 static bool TableChecked = false;
308 for (unsigned i = 0; i != NumEntries-1; ++i)
309 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
310 "NEONLdStTable is not sorted!");
315 const NEONLdStTableEntry *I =
316 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
317 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
322 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
323 /// corresponding to the specified register spacing. Not all of the results
324 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
325 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
326 const TargetRegisterInfo *TRI, unsigned &D0,
327 unsigned &D1, unsigned &D2, unsigned &D3) {
328 if (RegSpc == SingleSpc) {
329 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
330 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
331 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
332 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
333 } else if (RegSpc == EvenDblSpc) {
334 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
335 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
336 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
337 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
339 assert(RegSpc == OddDblSpc && "unknown register spacing");
340 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
341 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
342 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
343 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
347 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
348 /// operands to real VLD instructions with D register operands.
349 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
350 MachineInstr &MI = *MBBI;
351 MachineBasicBlock &MBB = *MI.getParent();
353 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
354 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
355 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
356 unsigned NumRegs = TableEntry->NumRegs;
358 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
359 TII->get(TableEntry->RealOpc));
362 bool DstIsDead = MI.getOperand(OpIdx).isDead();
363 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
364 unsigned D0, D1, D2, D3;
365 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
366 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
367 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
369 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
371 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
373 if (TableEntry->HasWriteBack)
374 MIB.addOperand(MI.getOperand(OpIdx++));
376 // Copy the addrmode6 operands.
377 MIB.addOperand(MI.getOperand(OpIdx++));
378 MIB.addOperand(MI.getOperand(OpIdx++));
379 // Copy the am6offset operand.
380 if (TableEntry->HasWriteBack)
381 MIB.addOperand(MI.getOperand(OpIdx++));
383 // For an instruction writing double-spaced subregs, the pseudo instruction
384 // has an extra operand that is a use of the super-register. Record the
385 // operand index and skip over it.
386 unsigned SrcOpIdx = 0;
387 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
390 // Copy the predicate operands.
391 MIB.addOperand(MI.getOperand(OpIdx++));
392 MIB.addOperand(MI.getOperand(OpIdx++));
394 // Copy the super-register source operand used for double-spaced subregs over
395 // to the new instruction as an implicit operand.
397 MachineOperand MO = MI.getOperand(SrcOpIdx);
398 MO.setImplicit(true);
401 // Add an implicit def for the super-register.
402 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
403 TransferImpOps(MI, MIB, MIB);
404 MI.eraseFromParent();
407 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
408 /// operands to real VST instructions with D register operands.
409 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
410 MachineInstr &MI = *MBBI;
411 MachineBasicBlock &MBB = *MI.getParent();
413 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
414 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
415 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
416 unsigned NumRegs = TableEntry->NumRegs;
418 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
419 TII->get(TableEntry->RealOpc));
421 if (TableEntry->HasWriteBack)
422 MIB.addOperand(MI.getOperand(OpIdx++));
424 // Copy the addrmode6 operands.
425 MIB.addOperand(MI.getOperand(OpIdx++));
426 MIB.addOperand(MI.getOperand(OpIdx++));
427 // Copy the am6offset operand.
428 if (TableEntry->HasWriteBack)
429 MIB.addOperand(MI.getOperand(OpIdx++));
431 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
432 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
433 unsigned D0, D1, D2, D3;
434 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
435 MIB.addReg(D0).addReg(D1);
441 // Copy the predicate operands.
442 MIB.addOperand(MI.getOperand(OpIdx++));
443 MIB.addOperand(MI.getOperand(OpIdx++));
446 // Add an implicit kill for the super-reg.
447 (*MIB).addRegisterKilled(SrcReg, TRI, true);
448 TransferImpOps(MI, MIB, MIB);
449 MI.eraseFromParent();
452 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
453 /// register operands to real instructions with D register operands.
454 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
455 MachineInstr &MI = *MBBI;
456 MachineBasicBlock &MBB = *MI.getParent();
458 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
459 assert(TableEntry && "NEONLdStTable lookup failed");
460 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
461 unsigned NumRegs = TableEntry->NumRegs;
462 unsigned RegElts = TableEntry->RegElts;
464 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
465 TII->get(TableEntry->RealOpc));
467 // The lane operand is always the 3rd from last operand, before the 2
468 // predicate operands.
469 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
471 // Adjust the lane and spacing as needed for Q registers.
472 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
473 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
477 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
479 unsigned D0, D1, D2, D3;
481 bool DstIsDead = false;
482 if (TableEntry->IsLoad) {
483 DstIsDead = MI.getOperand(OpIdx).isDead();
484 DstReg = MI.getOperand(OpIdx++).getReg();
485 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
486 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
488 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
490 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
492 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
495 if (TableEntry->HasWriteBack)
496 MIB.addOperand(MI.getOperand(OpIdx++));
498 // Copy the addrmode6 operands.
499 MIB.addOperand(MI.getOperand(OpIdx++));
500 MIB.addOperand(MI.getOperand(OpIdx++));
501 // Copy the am6offset operand.
502 if (TableEntry->HasWriteBack)
503 MIB.addOperand(MI.getOperand(OpIdx++));
505 // Grab the super-register source.
506 MachineOperand MO = MI.getOperand(OpIdx++);
507 if (!TableEntry->IsLoad)
508 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
510 // Add the subregs as sources of the new instruction.
511 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
512 getKillRegState(MO.isKill()));
513 MIB.addReg(D0, SrcFlags);
515 MIB.addReg(D1, SrcFlags);
517 MIB.addReg(D2, SrcFlags);
519 MIB.addReg(D3, SrcFlags);
521 // Add the lane number operand.
525 // Copy the predicate operands.
526 MIB.addOperand(MI.getOperand(OpIdx++));
527 MIB.addOperand(MI.getOperand(OpIdx++));
529 // Copy the super-register source to be an implicit source.
530 MO.setImplicit(true);
532 if (TableEntry->IsLoad)
533 // Add an implicit def for the super-register.
534 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
535 TransferImpOps(MI, MIB, MIB);
536 MI.eraseFromParent();
539 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
540 /// register operands to real instructions with D register operands.
541 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
542 unsigned Opc, bool IsExt, unsigned NumRegs) {
543 MachineInstr &MI = *MBBI;
544 MachineBasicBlock &MBB = *MI.getParent();
546 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
549 // Transfer the destination register operand.
550 MIB.addOperand(MI.getOperand(OpIdx++));
552 MIB.addOperand(MI.getOperand(OpIdx++));
554 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
555 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
556 unsigned D0, D1, D2, D3;
557 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
558 MIB.addReg(D0).addReg(D1);
564 // Copy the other source register operand.
565 MIB.addOperand(MI.getOperand(OpIdx++));
567 // Copy the predicate operands.
568 MIB.addOperand(MI.getOperand(OpIdx++));
569 MIB.addOperand(MI.getOperand(OpIdx++));
572 // Add an implicit kill for the super-reg.
573 (*MIB).addRegisterKilled(SrcReg, TRI, true);
574 TransferImpOps(MI, MIB, MIB);
575 MI.eraseFromParent();
578 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
579 bool Modified = false;
581 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
583 MachineInstr &MI = *MBBI;
584 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
586 bool ModifiedOp = true;
587 unsigned Opcode = MI.getOpcode();
593 case ARM::Int_eh_sjlj_dispatchsetup: {
594 MachineFunction &MF = *MI.getParent()->getParent();
595 const ARMBaseInstrInfo *AII =
596 static_cast<const ARMBaseInstrInfo*>(TII);
597 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
598 // For functions using a base pointer, we rematerialize it (via the frame
599 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
600 // for us. Otherwise, expand to nothing.
601 if (RI.hasBasePointer(MF)) {
602 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
603 int32_t NumBytes = AFI->getFramePtrSpillOffset();
604 unsigned FramePtr = RI.getFrameRegister(MF);
605 assert (RI.hasFP(MF) && "base pointer without frame pointer?");
607 if (AFI->isThumb2Function()) {
608 llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
609 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
610 } else if (AFI->isThumbFunction()) {
611 llvm::emitThumbRegPlusImmediate(MBB, MBBI, ARM::R6,
613 *TII, RI, MI.getDebugLoc());
615 llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
616 FramePtr, -NumBytes, ARMCC::AL, 0,
619 // If there's dynamic realignment, adjust for it.
620 if (RI.needsStackRealignment(MF)) {
621 MachineFrameInfo *MFI = MF.getFrameInfo();
622 unsigned MaxAlign = MFI->getMaxAlignment();
623 assert (!AFI->isThumb1OnlyFunction());
624 // Emit bic r6, r6, MaxAlign
625 unsigned bicOpc = AFI->isThumbFunction() ?
626 ARM::t2BICri : ARM::BICri;
627 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
628 TII->get(bicOpc), ARM::R6)
629 .addReg(ARM::R6, RegState::Kill)
630 .addImm(MaxAlign-1)));
634 MI.eraseFromParent();
638 case ARM::MOVsrl_flag:
639 case ARM::MOVsra_flag: {
640 // These are just fancy MOVs insructions.
641 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
642 MI.getOperand(0).getReg())
643 .addOperand(MI.getOperand(1))
645 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr
647 .addReg(ARM::CPSR, RegState::Define);
648 MI.eraseFromParent();
652 // This encodes as "MOVs Rd, Rm, rrx
653 MachineInstrBuilder MIB =
654 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
655 MI.getOperand(0).getReg())
656 .addOperand(MI.getOperand(1))
657 .addOperand(MI.getOperand(1))
658 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
660 TransferImpOps(MI, MIB, MIB);
661 MI.eraseFromParent();
664 case ARM::tLDRpci_pic:
665 case ARM::t2LDRpci_pic: {
666 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
667 ? ARM::tLDRpci : ARM::t2LDRpci;
668 unsigned DstReg = MI.getOperand(0).getReg();
669 bool DstIsDead = MI.getOperand(0).isDead();
670 MachineInstrBuilder MIB1 =
671 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
672 TII->get(NewLdOpc), DstReg)
673 .addOperand(MI.getOperand(1)));
674 (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
675 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
676 TII->get(ARM::tPICADD))
677 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
679 .addOperand(MI.getOperand(2));
680 TransferImpOps(MI, MIB1, MIB2);
681 MI.eraseFromParent();
686 case ARM::t2MOVi32imm: {
687 unsigned PredReg = 0;
688 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
689 unsigned DstReg = MI.getOperand(0).getReg();
690 bool DstIsDead = MI.getOperand(0).isDead();
691 const MachineOperand &MO = MI.getOperand(1);
692 MachineInstrBuilder LO16, HI16;
694 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
695 TII->get(Opcode == ARM::MOVi32imm ?
696 ARM::MOVi16 : ARM::t2MOVi16),
698 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
699 TII->get(Opcode == ARM::MOVi32imm ?
700 ARM::MOVTi16 : ARM::t2MOVTi16))
701 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
705 unsigned Imm = MO.getImm();
706 unsigned Lo16 = Imm & 0xffff;
707 unsigned Hi16 = (Imm >> 16) & 0xffff;
708 LO16 = LO16.addImm(Lo16);
709 HI16 = HI16.addImm(Hi16);
711 const GlobalValue *GV = MO.getGlobal();
712 unsigned TF = MO.getTargetFlags();
713 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
714 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
716 (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
717 (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
718 LO16.addImm(Pred).addReg(PredReg);
719 HI16.addImm(Pred).addReg(PredReg);
720 TransferImpOps(MI, LO16, HI16);
721 MI.eraseFromParent();
725 case ARM::MOVi2pieces: {
726 unsigned PredReg = 0;
727 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
728 unsigned DstReg = MI.getOperand(0).getReg();
729 bool DstIsDead = MI.getOperand(0).isDead();
730 const MachineOperand &MO = MI.getOperand(1);
731 MachineInstrBuilder LO16, HI16;
733 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
734 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
735 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
738 assert (MO.isImm() && "MOVi2pieces w/ non-immediate source operand!");
739 unsigned ImmVal = (unsigned)MO.getImm();
740 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
741 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
742 LO16 = LO16.addImm(SOImmValV1);
743 HI16 = HI16.addImm(SOImmValV2);
744 (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
745 (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
746 LO16.addImm(Pred).addReg(PredReg).addReg(0);
747 HI16.addImm(Pred).addReg(PredReg).addReg(0);
748 TransferImpOps(MI, LO16, HI16);
749 MI.eraseFromParent();
754 unsigned DstReg = MI.getOperand(0).getReg();
755 bool DstIsDead = MI.getOperand(0).isDead();
756 unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
757 unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1);
758 unsigned SrcReg = MI.getOperand(1).getReg();
759 bool SrcIsKill = MI.getOperand(1).isKill();
760 unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
761 unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1);
762 MachineInstrBuilder Even =
763 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
764 TII->get(ARM::VMOVQ))
766 RegState::Define | getDeadRegState(DstIsDead))
767 .addReg(EvenSrc, getKillRegState(SrcIsKill)));
768 MachineInstrBuilder Odd =
769 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
770 TII->get(ARM::VMOVQ))
772 RegState::Define | getDeadRegState(DstIsDead))
773 .addReg(OddSrc, getKillRegState(SrcIsKill)));
774 TransferImpOps(MI, Even, Odd);
775 MI.eraseFromParent();
780 MachineInstrBuilder MIB =
781 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VLDMD));
783 // Grab the Q register destination.
784 bool DstIsDead = MI.getOperand(OpIdx).isDead();
785 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
786 // Copy the addrmode4 operands.
787 MIB.addOperand(MI.getOperand(OpIdx++));
788 MIB.addOperand(MI.getOperand(OpIdx++));
789 // Copy the predicate operands.
790 MIB.addOperand(MI.getOperand(OpIdx++));
791 MIB.addOperand(MI.getOperand(OpIdx++));
792 // Add the destination operands (D subregs).
793 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
794 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
795 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
796 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
797 // Add an implicit def for the super-register.
798 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
799 TransferImpOps(MI, MIB, MIB);
800 MI.eraseFromParent();
805 MachineInstrBuilder MIB =
806 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VSTMD));
808 // Grab the Q register source.
809 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
810 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
811 // Copy the addrmode4 operands.
812 MIB.addOperand(MI.getOperand(OpIdx++));
813 MIB.addOperand(MI.getOperand(OpIdx++));
814 // Copy the predicate operands.
815 MIB.addOperand(MI.getOperand(OpIdx++));
816 MIB.addOperand(MI.getOperand(OpIdx++));
817 // Add the source operands (D subregs).
818 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
819 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
820 MIB.addReg(D0).addReg(D1);
822 // Add an implicit kill for the Q register.
823 (*MIB).addRegisterKilled(SrcReg, TRI, true);
824 TransferImpOps(MI, MIB, MIB);
825 MI.eraseFromParent();
830 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLNfq : ARM::VDUPLNfd;
831 MachineInstrBuilder MIB =
832 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
834 unsigned SrcReg = MI.getOperand(1).getReg();
835 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
836 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
837 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
838 // The lane is [0,1] for the containing DReg superregister.
839 // Copy the dst/src register operands.
840 MIB.addOperand(MI.getOperand(OpIdx++));
843 // Add the lane select operand.
845 // Add the predicate operands.
846 MIB.addOperand(MI.getOperand(OpIdx++));
847 MIB.addOperand(MI.getOperand(OpIdx++));
849 TransferImpOps(MI, MIB, MIB);
850 MI.eraseFromParent();
854 case ARM::VLD1q8Pseudo:
855 case ARM::VLD1q16Pseudo:
856 case ARM::VLD1q32Pseudo:
857 case ARM::VLD1q64Pseudo:
858 case ARM::VLD1q8Pseudo_UPD:
859 case ARM::VLD1q16Pseudo_UPD:
860 case ARM::VLD1q32Pseudo_UPD:
861 case ARM::VLD1q64Pseudo_UPD:
862 case ARM::VLD2d8Pseudo:
863 case ARM::VLD2d16Pseudo:
864 case ARM::VLD2d32Pseudo:
865 case ARM::VLD2q8Pseudo:
866 case ARM::VLD2q16Pseudo:
867 case ARM::VLD2q32Pseudo:
868 case ARM::VLD2d8Pseudo_UPD:
869 case ARM::VLD2d16Pseudo_UPD:
870 case ARM::VLD2d32Pseudo_UPD:
871 case ARM::VLD2q8Pseudo_UPD:
872 case ARM::VLD2q16Pseudo_UPD:
873 case ARM::VLD2q32Pseudo_UPD:
874 case ARM::VLD3d8Pseudo:
875 case ARM::VLD3d16Pseudo:
876 case ARM::VLD3d32Pseudo:
877 case ARM::VLD1d64TPseudo:
878 case ARM::VLD3d8Pseudo_UPD:
879 case ARM::VLD3d16Pseudo_UPD:
880 case ARM::VLD3d32Pseudo_UPD:
881 case ARM::VLD1d64TPseudo_UPD:
882 case ARM::VLD3q8Pseudo_UPD:
883 case ARM::VLD3q16Pseudo_UPD:
884 case ARM::VLD3q32Pseudo_UPD:
885 case ARM::VLD3q8oddPseudo_UPD:
886 case ARM::VLD3q16oddPseudo_UPD:
887 case ARM::VLD3q32oddPseudo_UPD:
888 case ARM::VLD4d8Pseudo:
889 case ARM::VLD4d16Pseudo:
890 case ARM::VLD4d32Pseudo:
891 case ARM::VLD1d64QPseudo:
892 case ARM::VLD4d8Pseudo_UPD:
893 case ARM::VLD4d16Pseudo_UPD:
894 case ARM::VLD4d32Pseudo_UPD:
895 case ARM::VLD1d64QPseudo_UPD:
896 case ARM::VLD4q8Pseudo_UPD:
897 case ARM::VLD4q16Pseudo_UPD:
898 case ARM::VLD4q32Pseudo_UPD:
899 case ARM::VLD4q8oddPseudo_UPD:
900 case ARM::VLD4q16oddPseudo_UPD:
901 case ARM::VLD4q32oddPseudo_UPD:
905 case ARM::VST1q8Pseudo:
906 case ARM::VST1q16Pseudo:
907 case ARM::VST1q32Pseudo:
908 case ARM::VST1q64Pseudo:
909 case ARM::VST1q8Pseudo_UPD:
910 case ARM::VST1q16Pseudo_UPD:
911 case ARM::VST1q32Pseudo_UPD:
912 case ARM::VST1q64Pseudo_UPD:
913 case ARM::VST2d8Pseudo:
914 case ARM::VST2d16Pseudo:
915 case ARM::VST2d32Pseudo:
916 case ARM::VST2q8Pseudo:
917 case ARM::VST2q16Pseudo:
918 case ARM::VST2q32Pseudo:
919 case ARM::VST2d8Pseudo_UPD:
920 case ARM::VST2d16Pseudo_UPD:
921 case ARM::VST2d32Pseudo_UPD:
922 case ARM::VST2q8Pseudo_UPD:
923 case ARM::VST2q16Pseudo_UPD:
924 case ARM::VST2q32Pseudo_UPD:
925 case ARM::VST3d8Pseudo:
926 case ARM::VST3d16Pseudo:
927 case ARM::VST3d32Pseudo:
928 case ARM::VST1d64TPseudo:
929 case ARM::VST3d8Pseudo_UPD:
930 case ARM::VST3d16Pseudo_UPD:
931 case ARM::VST3d32Pseudo_UPD:
932 case ARM::VST1d64TPseudo_UPD:
933 case ARM::VST3q8Pseudo_UPD:
934 case ARM::VST3q16Pseudo_UPD:
935 case ARM::VST3q32Pseudo_UPD:
936 case ARM::VST3q8oddPseudo_UPD:
937 case ARM::VST3q16oddPseudo_UPD:
938 case ARM::VST3q32oddPseudo_UPD:
939 case ARM::VST4d8Pseudo:
940 case ARM::VST4d16Pseudo:
941 case ARM::VST4d32Pseudo:
942 case ARM::VST1d64QPseudo:
943 case ARM::VST4d8Pseudo_UPD:
944 case ARM::VST4d16Pseudo_UPD:
945 case ARM::VST4d32Pseudo_UPD:
946 case ARM::VST1d64QPseudo_UPD:
947 case ARM::VST4q8Pseudo_UPD:
948 case ARM::VST4q16Pseudo_UPD:
949 case ARM::VST4q32Pseudo_UPD:
950 case ARM::VST4q8oddPseudo_UPD:
951 case ARM::VST4q16oddPseudo_UPD:
952 case ARM::VST4q32oddPseudo_UPD:
956 case ARM::VLD1LNq8Pseudo:
957 case ARM::VLD1LNq16Pseudo:
958 case ARM::VLD1LNq32Pseudo:
959 case ARM::VLD1LNq8Pseudo_UPD:
960 case ARM::VLD1LNq16Pseudo_UPD:
961 case ARM::VLD1LNq32Pseudo_UPD:
962 case ARM::VLD2LNd8Pseudo:
963 case ARM::VLD2LNd16Pseudo:
964 case ARM::VLD2LNd32Pseudo:
965 case ARM::VLD2LNq16Pseudo:
966 case ARM::VLD2LNq32Pseudo:
967 case ARM::VLD2LNd8Pseudo_UPD:
968 case ARM::VLD2LNd16Pseudo_UPD:
969 case ARM::VLD2LNd32Pseudo_UPD:
970 case ARM::VLD2LNq16Pseudo_UPD:
971 case ARM::VLD2LNq32Pseudo_UPD:
972 case ARM::VLD3LNd8Pseudo:
973 case ARM::VLD3LNd16Pseudo:
974 case ARM::VLD3LNd32Pseudo:
975 case ARM::VLD3LNq16Pseudo:
976 case ARM::VLD3LNq32Pseudo:
977 case ARM::VLD3LNd8Pseudo_UPD:
978 case ARM::VLD3LNd16Pseudo_UPD:
979 case ARM::VLD3LNd32Pseudo_UPD:
980 case ARM::VLD3LNq16Pseudo_UPD:
981 case ARM::VLD3LNq32Pseudo_UPD:
982 case ARM::VLD4LNd8Pseudo:
983 case ARM::VLD4LNd16Pseudo:
984 case ARM::VLD4LNd32Pseudo:
985 case ARM::VLD4LNq16Pseudo:
986 case ARM::VLD4LNq32Pseudo:
987 case ARM::VLD4LNd8Pseudo_UPD:
988 case ARM::VLD4LNd16Pseudo_UPD:
989 case ARM::VLD4LNd32Pseudo_UPD:
990 case ARM::VLD4LNq16Pseudo_UPD:
991 case ARM::VLD4LNq32Pseudo_UPD:
992 case ARM::VST2LNd8Pseudo:
993 case ARM::VST2LNd16Pseudo:
994 case ARM::VST2LNd32Pseudo:
995 case ARM::VST2LNq16Pseudo:
996 case ARM::VST2LNq32Pseudo:
997 case ARM::VST2LNd8Pseudo_UPD:
998 case ARM::VST2LNd16Pseudo_UPD:
999 case ARM::VST2LNd32Pseudo_UPD:
1000 case ARM::VST2LNq16Pseudo_UPD:
1001 case ARM::VST2LNq32Pseudo_UPD:
1002 case ARM::VST3LNd8Pseudo:
1003 case ARM::VST3LNd16Pseudo:
1004 case ARM::VST3LNd32Pseudo:
1005 case ARM::VST3LNq16Pseudo:
1006 case ARM::VST3LNq32Pseudo:
1007 case ARM::VST3LNd8Pseudo_UPD:
1008 case ARM::VST3LNd16Pseudo_UPD:
1009 case ARM::VST3LNd32Pseudo_UPD:
1010 case ARM::VST3LNq16Pseudo_UPD:
1011 case ARM::VST3LNq32Pseudo_UPD:
1012 case ARM::VST4LNd8Pseudo:
1013 case ARM::VST4LNd16Pseudo:
1014 case ARM::VST4LNd32Pseudo:
1015 case ARM::VST4LNq16Pseudo:
1016 case ARM::VST4LNq32Pseudo:
1017 case ARM::VST4LNd8Pseudo_UPD:
1018 case ARM::VST4LNd16Pseudo_UPD:
1019 case ARM::VST4LNd32Pseudo_UPD:
1020 case ARM::VST4LNq16Pseudo_UPD:
1021 case ARM::VST4LNq32Pseudo_UPD:
1025 case ARM::VTBL2Pseudo:
1026 ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break;
1027 case ARM::VTBL3Pseudo:
1028 ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break;
1029 case ARM::VTBL4Pseudo:
1030 ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break;
1031 case ARM::VTBX2Pseudo:
1032 ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break;
1033 case ARM::VTBX3Pseudo:
1034 ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break;
1035 case ARM::VTBX4Pseudo:
1036 ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break;
1047 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1048 TII = static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1049 TRI = MF.getTarget().getRegisterInfo();
1051 bool Modified = false;
1052 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1054 Modified |= ExpandMBB(*MFI);
1058 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1060 FunctionPass *llvm::createARMExpandPseudoPass() {
1061 return new ARMExpandPseudo();