1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/Debug.h"
41 STATISTIC(NumEmitted, "Number of machine instructions emitted");
44 class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
46 const ARMInstrInfo *II;
49 MachineCodeEmitter &MCE;
50 const std::vector<MachineConstantPoolEntry> *MCPEs;
51 const std::vector<MachineJumpTableEntry> *MJTEs;
56 explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
57 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
58 MCE(mce), MCPEs(0), MJTEs(0),
59 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
60 ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
61 const ARMInstrInfo &ii, const TargetData &td)
62 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
63 MCE(mce), MCPEs(0), MJTEs(0),
64 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
66 bool runOnMachineFunction(MachineFunction &MF);
68 virtual const char *getPassName() const {
69 return "ARM Machine Code Emitter";
72 void emitInstruction(const MachineInstr &MI);
76 void emitWordLE(unsigned Binary);
78 void emitDWordLE(uint64_t Binary);
80 void emitConstPoolInstruction(const MachineInstr &MI);
82 void emitMOVi2piecesInstruction(const MachineInstr &MI);
84 void emitLEApcrelJTInstruction(const MachineInstr &MI);
86 void addPCLabel(unsigned LabelID);
88 void emitPseudoInstruction(const MachineInstr &MI);
90 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
91 const TargetInstrDesc &TID,
92 const MachineOperand &MO,
95 unsigned getMachineSoImmOpValue(unsigned SoImm);
97 unsigned getAddrModeSBit(const MachineInstr &MI,
98 const TargetInstrDesc &TID) const;
100 void emitDataProcessingInstruction(const MachineInstr &MI,
101 unsigned ImplicitRd = 0,
102 unsigned ImplicitRn = 0);
104 void emitLoadStoreInstruction(const MachineInstr &MI,
105 unsigned ImplicitRd = 0,
106 unsigned ImplicitRn = 0);
108 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
113 void emitMulFrmInstruction(const MachineInstr &MI);
115 void emitExtendInstruction(const MachineInstr &MI);
117 void emitMiscArithInstruction(const MachineInstr &MI);
119 void emitBranchInstruction(const MachineInstr &MI);
121 void emitInlineJumpTable(unsigned JTIndex);
123 void emitMiscBranchInstruction(const MachineInstr &MI);
125 void emitVFPArithInstruction(const MachineInstr &MI);
127 void emitVFPConversionInstruction(const MachineInstr &MI);
129 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
131 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
133 void emitMiscInstruction(const MachineInstr &MI);
135 /// getBinaryCodeForInstr - This function, generated by the
136 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
137 /// machine instructions.
139 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
141 /// getMachineOpValue - Return binary encoding of operand. If the machine
142 /// operand requires relocation, record the relocation and return zero.
143 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
144 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
145 return getMachineOpValue(MI, MI.getOperand(OpIdx));
148 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
150 unsigned getShiftOp(unsigned Imm) const ;
152 /// Routines that handle operands which add machine relocations which are
153 /// fixed up by the relocation stage.
154 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
155 bool NeedStub, intptr_t ACPV = 0);
156 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
157 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
158 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
159 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
160 intptr_t JTBase = 0);
162 char ARMCodeEmitter::ID = 0;
165 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
166 /// to the specified MCE object.
167 FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
168 MachineCodeEmitter &MCE) {
169 return new ARMCodeEmitter(TM, MCE);
172 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
173 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
174 MF.getTarget().getRelocationModel() != Reloc::Static) &&
175 "JIT relocation model must be set to static or default!");
176 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
177 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
178 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
179 MCPEs = &MF.getConstantPool()->getConstants();
180 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
181 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
182 JTI->Initialize(MF, IsPIC);
185 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
186 MCE.startFunction(MF);
187 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
189 MCE.StartMachineBasicBlock(MBB);
190 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
194 } while (MCE.finishFunction(MF));
199 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
201 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
202 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
203 default: assert(0 && "Unknown shift opc!");
204 case ARM_AM::asr: return 2;
205 case ARM_AM::lsl: return 0;
206 case ARM_AM::lsr: return 1;
208 case ARM_AM::rrx: return 3;
213 /// getMachineOpValue - Return binary encoding of operand. If the machine
214 /// operand requires relocation, record the relocation and return zero.
215 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
216 const MachineOperand &MO) {
218 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
220 return static_cast<unsigned>(MO.getImm());
221 else if (MO.isGlobal())
222 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
223 else if (MO.isSymbol())
224 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
225 else if (MO.isCPI()) {
226 const TargetInstrDesc &TID = MI.getDesc();
227 // For VFP load, the immediate offset is multiplied by 4.
228 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
229 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
230 emitConstPoolAddress(MO.getIndex(), Reloc);
231 } else if (MO.isJTI())
232 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
234 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
236 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
242 /// emitGlobalAddress - Emit the specified address to the code stream.
244 void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
245 bool NeedStub, intptr_t ACPV) {
246 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
247 Reloc, GV, ACPV, NeedStub));
250 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
251 /// be emitted to the current location in the function, and allow it to be PC
253 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
254 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
258 /// emitConstPoolAddress - Arrange for the address of an constant pool
259 /// to be emitted to the current location in the function, and allow it to be PC
261 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
262 // Tell JIT emitter we'll resolve the address.
263 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
264 Reloc, CPI, 0, true));
267 /// emitJumpTableAddress - Arrange for the address of a jump table to
268 /// be emitted to the current location in the function, and allow it to be PC
270 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
271 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
272 Reloc, JTIndex, 0, true));
275 /// emitMachineBasicBlock - Emit the specified address basic block.
276 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
277 unsigned Reloc, intptr_t JTBase) {
278 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
282 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
284 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
285 << Binary << std::dec << "\n";
287 MCE.emitWordLE(Binary);
290 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
292 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
293 << (unsigned)Binary << std::dec << "\n";
294 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
295 << (unsigned)(Binary >> 32) << std::dec << "\n";
297 MCE.emitDWordLE(Binary);
300 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
301 DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
303 NumEmitted++; // Keep track of the # of mi's emitted
304 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
306 assert(0 && "Unhandled instruction encoding format!");
309 emitPseudoInstruction(MI);
312 case ARMII::DPSoRegFrm:
313 emitDataProcessingInstruction(MI);
317 emitLoadStoreInstruction(MI);
319 case ARMII::LdMiscFrm:
320 case ARMII::StMiscFrm:
321 emitMiscLoadStoreInstruction(MI);
323 case ARMII::LdMulFrm:
324 case ARMII::StMulFrm:
325 emitLoadStoreMultipleInstruction(MI);
328 emitMulFrmInstruction(MI);
331 emitExtendInstruction(MI);
333 case ARMII::ArithMiscFrm:
334 emitMiscArithInstruction(MI);
337 emitBranchInstruction(MI);
339 case ARMII::BrMiscFrm:
340 emitMiscBranchInstruction(MI);
343 case ARMII::VFPUnaryFrm:
344 case ARMII::VFPBinaryFrm:
345 emitVFPArithInstruction(MI);
347 case ARMII::VFPConv1Frm:
348 case ARMII::VFPConv2Frm:
349 case ARMII::VFPConv3Frm:
350 case ARMII::VFPConv4Frm:
351 case ARMII::VFPConv5Frm:
352 emitVFPConversionInstruction(MI);
354 case ARMII::VFPLdStFrm:
355 emitVFPLoadStoreInstruction(MI);
357 case ARMII::VFPLdStMulFrm:
358 emitVFPLoadStoreMultipleInstruction(MI);
360 case ARMII::VFPMiscFrm:
361 emitMiscInstruction(MI);
366 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
367 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
368 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
369 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
371 // Remember the CONSTPOOL_ENTRY address for later relocation.
372 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
374 // Emit constpool island entry. In most cases, the actual values will be
375 // resolved and relocated after code emission.
376 if (MCPE.isMachineConstantPoolEntry()) {
377 ARMConstantPoolValue *ACPV =
378 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
380 DOUT << " ** ARM constant pool #" << CPI << " @ "
381 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
383 GlobalValue *GV = ACPV->getGV();
385 assert(!ACPV->isStub() && "Don't know how to deal this yet!");
386 if (ACPV->isNonLazyPointer())
387 MCE.addRelocation(MachineRelocation::getIndirectSymbol(
388 MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
389 (intptr_t)ACPV, false));
391 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
392 ACPV->isStub(), (intptr_t)ACPV);
394 assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
395 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
399 Constant *CV = MCPE.Val.ConstVal;
401 DOUT << " ** Constant pool #" << CPI << " @ "
402 << (void*)MCE.getCurrentPCValue() << " " << *CV << '\n';
404 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
405 emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
407 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
408 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
410 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
411 if (CFP->getType() == Type::FloatTy)
412 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
413 else if (CFP->getType() == Type::DoubleTy)
414 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
416 assert(0 && "Unable to handle this constantpool entry!");
420 assert(0 && "Unable to handle this constantpool entry!");
426 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
427 const MachineOperand &MO0 = MI.getOperand(0);
428 const MachineOperand &MO1 = MI.getOperand(1);
429 assert(MO1.isImm() && "Not a valid so_imm value!");
430 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
431 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
433 // Emit the 'mov' instruction.
434 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
436 // Set the conditional execution predicate.
437 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
440 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
443 // Set bit I(25) to identify this is the immediate form of <shifter_op>
444 Binary |= 1 << ARMII::I_BitShift;
445 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
448 // Now the 'orr' instruction.
449 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
451 // Set the conditional execution predicate.
452 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
455 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
458 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
461 // Set bit I(25) to identify this is the immediate form of <shifter_op>
462 Binary |= 1 << ARMII::I_BitShift;
463 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
467 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
468 // It's basically add r, pc, (LJTI - $+8)
470 const TargetInstrDesc &TID = MI.getDesc();
472 // Emit the 'add' instruction.
473 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
475 // Set the conditional execution predicate
476 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
478 // Encode S bit if MI modifies CPSR.
479 Binary |= getAddrModeSBit(MI, TID);
482 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
484 // Encode Rn which is PC.
485 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
487 // Encode the displacement.
488 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
489 Binary |= 1 << ARMII::I_BitShift;
490 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
495 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
496 DOUT << " ** LPC" << LabelID << " @ "
497 << (void*)MCE.getCurrentPCValue() << '\n';
498 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
501 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
502 unsigned Opcode = MI.getDesc().Opcode;
506 case ARM::CONSTPOOL_ENTRY:
507 emitConstPoolInstruction(MI);
510 // Remember of the address of the PC label for relocation later.
511 addPCLabel(MI.getOperand(2).getImm());
512 // PICADD is just an add instruction that implicitly read pc.
513 emitDataProcessingInstruction(MI, 0, ARM::PC);
520 // Remember of the address of the PC label for relocation later.
521 addPCLabel(MI.getOperand(2).getImm());
522 // These are just load / store instructions that implicitly read pc.
523 emitLoadStoreInstruction(MI, 0, ARM::PC);
530 // Remember of the address of the PC label for relocation later.
531 addPCLabel(MI.getOperand(2).getImm());
532 // These are just load / store instructions that implicitly read pc.
533 emitMiscLoadStoreInstruction(MI, ARM::PC);
536 case ARM::MOVi2pieces:
537 // Two instructions to materialize a constant.
538 emitMOVi2piecesInstruction(MI);
540 case ARM::LEApcrelJT:
541 // Materialize jumptable address.
542 emitLEApcrelJTInstruction(MI);
548 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
549 const TargetInstrDesc &TID,
550 const MachineOperand &MO,
552 unsigned Binary = getMachineOpValue(MI, MO);
554 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
555 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
556 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
558 // Encode the shift opcode.
560 unsigned Rs = MO1.getReg();
562 // Set shift operand (bit[7:4]).
567 // RRX - 0110 and bit[11:8] clear.
569 default: assert(0 && "Unknown shift opc!");
570 case ARM_AM::lsl: SBits = 0x1; break;
571 case ARM_AM::lsr: SBits = 0x3; break;
572 case ARM_AM::asr: SBits = 0x5; break;
573 case ARM_AM::ror: SBits = 0x7; break;
574 case ARM_AM::rrx: SBits = 0x6; break;
577 // Set shift operand (bit[6:4]).
583 default: assert(0 && "Unknown shift opc!");
584 case ARM_AM::lsl: SBits = 0x0; break;
585 case ARM_AM::lsr: SBits = 0x2; break;
586 case ARM_AM::asr: SBits = 0x4; break;
587 case ARM_AM::ror: SBits = 0x6; break;
590 Binary |= SBits << 4;
591 if (SOpc == ARM_AM::rrx)
594 // Encode the shift operation Rs or shift_imm (except rrx).
596 // Encode Rs bit[11:8].
597 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
599 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
602 // Encode shift_imm bit[11:7].
603 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
606 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
607 // Encode rotate_imm.
608 unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
609 << ARMII::SoRotImmShift;
612 Binary |= ARM_AM::getSOImmValImm(SoImm);
616 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
617 const TargetInstrDesc &TID) const {
618 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
619 const MachineOperand &MO = MI.getOperand(i-1);
620 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
621 return 1 << ARMII::S_BitShift;
626 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
628 unsigned ImplicitRn) {
629 const TargetInstrDesc &TID = MI.getDesc();
631 // Part of binary is determined by TableGn.
632 unsigned Binary = getBinaryCodeForInstr(MI);
634 // Set the conditional execution predicate
635 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
637 // Encode S bit if MI modifies CPSR.
638 Binary |= getAddrModeSBit(MI, TID);
640 // Encode register def if there is one.
641 unsigned NumDefs = TID.getNumDefs();
644 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
646 // Special handling for implicit use (e.g. PC).
647 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
648 << ARMII::RegRdShift);
650 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
651 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
654 // Encode first non-shifter register operand if there is one.
655 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
658 // Special handling for implicit use (e.g. PC).
659 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
660 << ARMII::RegRnShift);
662 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
667 // Encode shifter operand.
668 const MachineOperand &MO = MI.getOperand(OpIdx);
669 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
671 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
676 // Encode register Rm.
677 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
682 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
683 Binary |= 1 << ARMII::I_BitShift;
684 Binary |= getMachineSoImmOpValue(MO.getImm());
689 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
691 unsigned ImplicitRn) {
692 const TargetInstrDesc &TID = MI.getDesc();
694 // Part of binary is determined by TableGn.
695 unsigned Binary = getBinaryCodeForInstr(MI);
697 // Set the conditional execution predicate
698 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
703 // Special handling for implicit use (e.g. PC).
704 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
705 << ARMII::RegRdShift);
707 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
709 // Set second operand
711 // Special handling for implicit use (e.g. PC).
712 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
713 << ARMII::RegRnShift);
715 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
717 // If this is a two-address operand, skip it. e.g. LDR_PRE.
718 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
721 const MachineOperand &MO2 = MI.getOperand(OpIdx);
722 unsigned AM2Opc = (ImplicitRn == ARM::PC)
723 ? 0 : MI.getOperand(OpIdx+1).getImm();
725 // Set bit U(23) according to sign of immed value (positive or negative).
726 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
728 if (!MO2.getReg()) { // is immediate
729 if (ARM_AM::getAM2Offset(AM2Opc))
730 // Set the value of offset_12 field
731 Binary |= ARM_AM::getAM2Offset(AM2Opc);
736 // Set bit I(25), because this is not in immediate enconding.
737 Binary |= 1 << ARMII::I_BitShift;
738 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
739 // Set bit[3:0] to the corresponding Rm register
740 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
742 // if this instr is in scaled register offset/index instruction, set
743 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
744 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
745 Binary |= getShiftOp(AM2Opc) << 5; // shift
746 Binary |= ShImm << 7; // shift_immed
752 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
753 unsigned ImplicitRn) {
754 const TargetInstrDesc &TID = MI.getDesc();
756 // Part of binary is determined by TableGn.
757 unsigned Binary = getBinaryCodeForInstr(MI);
759 // Set the conditional execution predicate
760 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
763 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
765 // Set second operand
768 // Special handling for implicit use (e.g. PC).
769 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
770 << ARMII::RegRnShift);
772 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
774 // If this is a two-address operand, skip it. e.g. LDRH_POST.
775 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
778 const MachineOperand &MO2 = MI.getOperand(OpIdx);
779 unsigned AM3Opc = (ImplicitRn == ARM::PC)
780 ? 0 : MI.getOperand(OpIdx+1).getImm();
782 // Set bit U(23) according to sign of immed value (positive or negative)
783 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
786 // If this instr is in register offset/index encoding, set bit[3:0]
787 // to the corresponding Rm register.
789 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
794 // This instr is in immediate offset/index encoding, set bit 22 to 1.
795 Binary |= 1 << ARMII::AM3_I_BitShift;
796 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
798 Binary |= (ImmOffs >> 4) << 8; // immedH
799 Binary |= (ImmOffs & ~0xF); // immedL
805 static unsigned getAddrModeUPBits(unsigned Mode) {
808 // Set addressing mode by modifying bits U(23) and P(24)
809 // IA - Increment after - bit U = 1 and bit P = 0
810 // IB - Increment before - bit U = 1 and bit P = 1
811 // DA - Decrement after - bit U = 0 and bit P = 0
812 // DB - Decrement before - bit U = 0 and bit P = 1
814 default: assert(0 && "Unknown addressing sub-mode!");
815 case ARM_AM::da: break;
816 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
817 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
818 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
824 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
825 // Part of binary is determined by TableGn.
826 unsigned Binary = getBinaryCodeForInstr(MI);
828 // Set the conditional execution predicate
829 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
831 // Set base address operand
832 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
834 // Set addressing mode by modifying bits U(23) and P(24)
835 const MachineOperand &MO = MI.getOperand(1);
836 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
839 if (ARM_AM::getAM4WBFlag(MO.getImm()))
840 Binary |= 0x1 << ARMII::W_BitShift;
843 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
844 const MachineOperand &MO = MI.getOperand(i);
845 if (!MO.isReg() || MO.isImplicit())
847 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
848 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
850 Binary |= 0x1 << RegNum;
856 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
857 const TargetInstrDesc &TID = MI.getDesc();
859 // Part of binary is determined by TableGn.
860 unsigned Binary = getBinaryCodeForInstr(MI);
862 // Set the conditional execution predicate
863 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
865 // Encode S bit if MI modifies CPSR.
866 Binary |= getAddrModeSBit(MI, TID);
868 // 32x32->64bit operations have two destination registers. The number
869 // of register definitions will tell us if that's what we're dealing with.
871 if (TID.getNumDefs() == 2)
872 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
875 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
878 Binary |= getMachineOpValue(MI, OpIdx++);
881 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
883 // Many multiple instructions (e.g. MLA) have three src operands. Encode
884 // it as Rn (for multiply, that's in the same offset as RdLo.
885 if (TID.getNumOperands() > OpIdx &&
886 !TID.OpInfo[OpIdx].isPredicate() &&
887 !TID.OpInfo[OpIdx].isOptionalDef())
888 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
893 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
894 const TargetInstrDesc &TID = MI.getDesc();
896 // Part of binary is determined by TableGn.
897 unsigned Binary = getBinaryCodeForInstr(MI);
899 // Set the conditional execution predicate
900 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
905 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
907 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
908 const MachineOperand &MO2 = MI.getOperand(OpIdx);
910 // Two register operand form.
912 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
915 Binary |= getMachineOpValue(MI, MO2);
918 Binary |= getMachineOpValue(MI, MO1);
921 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
922 if (MI.getOperand(OpIdx).isImm() &&
923 !TID.OpInfo[OpIdx].isPredicate() &&
924 !TID.OpInfo[OpIdx].isOptionalDef())
925 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
930 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
931 const TargetInstrDesc &TID = MI.getDesc();
933 // Part of binary is determined by TableGn.
934 unsigned Binary = getBinaryCodeForInstr(MI);
936 // Set the conditional execution predicate
937 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
942 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
944 const MachineOperand &MO = MI.getOperand(OpIdx++);
945 if (OpIdx == TID.getNumOperands() ||
946 TID.OpInfo[OpIdx].isPredicate() ||
947 TID.OpInfo[OpIdx].isOptionalDef()) {
948 // Encode Rm and it's done.
949 Binary |= getMachineOpValue(MI, MO);
955 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
958 Binary |= getMachineOpValue(MI, OpIdx++);
961 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
962 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
963 Binary |= ShiftAmt << ARMII::ShiftShift;
968 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
969 const TargetInstrDesc &TID = MI.getDesc();
971 if (TID.Opcode == ARM::TPsoft)
974 // Part of binary is determined by TableGn.
975 unsigned Binary = getBinaryCodeForInstr(MI);
977 // Set the conditional execution predicate
978 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
980 // Set signed_immed_24 field
981 Binary |= getMachineOpValue(MI, 0);
986 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
987 // Remember the base address of the inline jump table.
988 intptr_t JTBase = MCE.getCurrentPCValue();
989 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
990 DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
992 // Now emit the jump table entries.
993 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
994 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
996 // DestBB address - JT base.
997 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
999 // Absolute DestBB address.
1000 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1005 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1006 const TargetInstrDesc &TID = MI.getDesc();
1008 // Handle jump tables.
1009 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1010 // First emit a ldr pc, [] instruction.
1011 emitDataProcessingInstruction(MI, ARM::PC);
1013 // Then emit the inline jump table.
1014 unsigned JTIndex = (TID.Opcode == ARM::BR_JTr)
1015 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1016 emitInlineJumpTable(JTIndex);
1018 } else if (TID.Opcode == ARM::BR_JTm) {
1019 // First emit a ldr pc, [] instruction.
1020 emitLoadStoreInstruction(MI, ARM::PC);
1022 // Then emit the inline jump table.
1023 emitInlineJumpTable(MI.getOperand(3).getIndex());
1027 // Part of binary is determined by TableGn.
1028 unsigned Binary = getBinaryCodeForInstr(MI);
1030 // Set the conditional execution predicate
1031 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1033 if (TID.Opcode == ARM::BX_RET)
1034 // The return register is LR.
1035 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1037 // otherwise, set the return register
1038 Binary |= getMachineOpValue(MI, 0);
1043 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1044 const TargetInstrDesc &TID = MI.getDesc();
1046 // Part of binary is determined by TableGn.
1047 unsigned Binary = getBinaryCodeForInstr(MI);
1049 // Set the conditional execution predicate
1050 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1053 assert((Binary & ARMII::D_BitShift) == 0 &&
1054 (Binary & ARMII::N_BitShift) == 0 &&
1055 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1058 unsigned RegD = MI.getOperand(OpIdx++).getReg();
1059 bool isSPVFP = false;
1060 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1062 Binary |= RegD << ARMII::RegRdShift;
1064 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1065 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1069 // If this is a two-address operand, skip it, e.g. FMACD.
1070 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1074 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) {
1075 unsigned RegN = MI.getOperand(OpIdx++).getReg();
1077 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1079 Binary |= RegN << ARMII::RegRnShift;
1081 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1082 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1087 unsigned RegM = MI.getOperand(OpIdx++).getReg();
1089 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1093 Binary |= ((RegM & 0x1E) >> 1);
1094 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1100 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1101 unsigned RegD = MI.getOperand(OpIdx).getReg();
1102 unsigned Binary = 0;
1103 bool isSPVFP = false;
1104 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1106 Binary |= RegD << ARMII::RegRdShift;
1108 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1109 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1114 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1115 unsigned RegN = MI.getOperand(OpIdx).getReg();
1116 unsigned Binary = 0;
1117 bool isSPVFP = false;
1118 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1120 Binary |= RegN << ARMII::RegRnShift;
1122 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1123 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1128 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1129 unsigned RegM = MI.getOperand(OpIdx).getReg();
1130 unsigned Binary = 0;
1131 bool isSPVFP = false;
1132 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1136 Binary |= ((RegM & 0x1E) >> 1);
1137 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1142 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1143 const TargetInstrDesc &TID = MI.getDesc();
1144 unsigned Form = TID.TSFlags & ARMII::FormMask;
1146 // Part of binary is determined by TableGn.
1147 unsigned Binary = getBinaryCodeForInstr(MI);
1149 // Set the conditional execution predicate
1150 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1154 case ARMII::VFPConv1Frm:
1155 case ARMII::VFPConv2Frm:
1156 case ARMII::VFPConv3Frm:
1158 Binary |= encodeVFPRd(MI, 0);
1160 case ARMII::VFPConv4Frm:
1162 Binary |= encodeVFPRn(MI, 0);
1164 case ARMII::VFPConv5Frm:
1166 Binary |= encodeVFPRm(MI, 0);
1172 case ARMII::VFPConv1Frm:
1174 Binary |= encodeVFPRm(MI, 1);
1175 case ARMII::VFPConv2Frm:
1176 case ARMII::VFPConv3Frm:
1178 Binary |= encodeVFPRn(MI, 1);
1180 case ARMII::VFPConv4Frm:
1181 case ARMII::VFPConv5Frm:
1183 Binary |= encodeVFPRd(MI, 1);
1187 if (Form == ARMII::VFPConv5Frm)
1189 Binary |= encodeVFPRn(MI, 2);
1190 else if (Form == ARMII::VFPConv3Frm)
1192 Binary |= encodeVFPRm(MI, 2);
1197 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1198 // Part of binary is determined by TableGn.
1199 unsigned Binary = getBinaryCodeForInstr(MI);
1201 // Set the conditional execution predicate
1202 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1207 unsigned RegD = MI.getOperand(OpIdx++).getReg();
1208 bool isSPVFP = false;
1209 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1211 Binary |= RegD << ARMII::RegRdShift;
1213 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1214 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1217 // Encode address base.
1218 const MachineOperand &Base = MI.getOperand(OpIdx++);
1219 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1221 // If there is a non-zero immediate offset, encode it.
1223 const MachineOperand &Offset = MI.getOperand(OpIdx);
1224 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1225 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1226 Binary |= 1 << ARMII::U_BitShift;
1227 // Immediate offset is multiplied by 4.
1228 Binary |= ImmOffs >> 2;
1234 // If immediate offset is omitted, default to +0.
1235 Binary |= 1 << ARMII::U_BitShift;
1241 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1242 // Part of binary is determined by TableGn.
1243 unsigned Binary = getBinaryCodeForInstr(MI);
1245 // Set the conditional execution predicate
1246 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1248 // Set base address operand
1249 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1251 // Set addressing mode by modifying bits U(23) and P(24)
1252 const MachineOperand &MO = MI.getOperand(1);
1253 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1256 if (ARM_AM::getAM5WBFlag(MO.getImm()))
1257 Binary |= 0x1 << ARMII::W_BitShift;
1259 // First register is encoded in Dd.
1260 unsigned RegD = MI.getOperand(4).getReg();
1261 bool isSPVFP = false;
1262 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1264 Binary |= RegD << ARMII::RegRdShift;
1266 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1267 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1270 // Number of registers are encoded in offset field.
1271 unsigned NumRegs = 1;
1272 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1273 const MachineOperand &MO = MI.getOperand(i);
1274 if (!MO.isReg() || MO.isImplicit())
1278 Binary |= NumRegs * 2;
1283 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1284 // Part of binary is determined by TableGn.
1285 unsigned Binary = getBinaryCodeForInstr(MI);
1287 // Set the conditional execution predicate
1288 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1293 #include "ARMGenCodeEmitter.inc"