1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
172 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
188 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
190 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
192 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
194 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
196 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
198 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
200 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
202 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
203 unsigned Op) const { return 0; }
204 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
206 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
209 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
212 // {12} = (U)nsigned (add == '1', sub == '0')
214 const MachineOperand &MO = MI.getOperand(Op);
215 const MachineOperand &MO1 = MI.getOperand(Op + 1);
217 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
220 unsigned Reg = getARMRegisterNumbering(MO.getReg());
221 int32_t Imm12 = MO1.getImm();
223 Binary = Imm12 & 0xfff;
226 Binary |= (Reg << 13);
230 unsigned getMovtImmOpValue(const MachineInstr &MI, unsigned Op) const {
234 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
236 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
238 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
240 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
242 uint32_t getAddrModeS4OpValue(const MachineInstr &MI, unsigned Op)
244 uint32_t getAddrModeS2OpValue(const MachineInstr &MI, unsigned Op)
246 uint32_t getAddrModeS1OpValue(const MachineInstr &MI, unsigned Op)
248 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
250 // {12} = (U)nsigned (add == '1', sub == '0')
252 const MachineOperand &MO = MI.getOperand(Op);
253 const MachineOperand &MO1 = MI.getOperand(Op + 1);
255 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
258 unsigned Reg = getARMRegisterNumbering(MO.getReg());
259 int32_t Imm12 = MO1.getImm();
261 // Special value for #-0
262 if (Imm12 == INT32_MIN)
265 // Immediate is always encoded as positive. The 'U' bit controls add vs
273 uint32_t Binary = Imm12 & 0xfff;
276 Binary |= (Reg << 13);
279 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
282 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
285 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
286 /// machine operand requires relocation, record the relocation and return
288 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
291 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
293 unsigned getShiftOp(unsigned Imm) const ;
295 /// Routines that handle operands which add machine relocations which are
296 /// fixed up by the relocation stage.
297 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
298 bool MayNeedFarStub, bool Indirect,
299 intptr_t ACPV = 0) const;
300 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
301 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
302 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
303 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
304 intptr_t JTBase = 0) const;
308 char ARMCodeEmitter::ID = 0;
310 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
311 /// code to the specified MCE object.
312 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
313 JITCodeEmitter &JCE) {
314 return new ARMCodeEmitter(TM, JCE);
317 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
318 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
319 MF.getTarget().getRelocationModel() != Reloc::Static) &&
320 "JIT relocation model must be set to static or default!");
321 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
322 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
323 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
324 Subtarget = &TM.getSubtarget<ARMSubtarget>();
325 MCPEs = &MF.getConstantPool()->getConstants();
327 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
328 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
329 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
330 JTI->Initialize(MF, IsPIC);
331 MMI = &getAnalysis<MachineModuleInfo>();
332 MCE.setModuleInfo(MMI);
335 DEBUG(errs() << "JITTing function '"
336 << MF.getFunction()->getName() << "'\n");
337 MCE.startFunction(MF);
338 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
340 MCE.StartMachineBasicBlock(MBB);
341 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
345 } while (MCE.finishFunction(MF));
350 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
352 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
353 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
354 default: llvm_unreachable("Unknown shift opc!");
355 case ARM_AM::asr: return 2;
356 case ARM_AM::lsl: return 0;
357 case ARM_AM::lsr: return 1;
359 case ARM_AM::rrx: return 3;
364 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
365 /// machine operand requires relocation, record the relocation and return zero.
366 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
367 const MachineOperand &MO,
369 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
370 && "Relocation to this function should be for movt or movw");
373 return static_cast<unsigned>(MO.getImm());
374 else if (MO.isGlobal())
375 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
376 else if (MO.isSymbol())
377 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
379 emitMachineBasicBlock(MO.getMBB(), Reloc);
384 llvm_unreachable("Unsupported operand type for movw/movt");
389 /// getMachineOpValue - Return binary encoding of operand. If the machine
390 /// operand requires relocation, record the relocation and return zero.
391 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
392 const MachineOperand &MO) const {
394 return getARMRegisterNumbering(MO.getReg());
396 return static_cast<unsigned>(MO.getImm());
397 else if (MO.isGlobal())
398 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
399 else if (MO.isSymbol())
400 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
401 else if (MO.isCPI()) {
402 const TargetInstrDesc &TID = MI.getDesc();
403 // For VFP load, the immediate offset is multiplied by 4.
404 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
405 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
406 emitConstPoolAddress(MO.getIndex(), Reloc);
407 } else if (MO.isJTI())
408 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
410 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
412 llvm_unreachable("Unable to encode MachineOperand!");
416 /// emitGlobalAddress - Emit the specified address to the code stream.
418 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
419 bool MayNeedFarStub, bool Indirect,
420 intptr_t ACPV) const {
421 MachineRelocation MR = Indirect
422 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
423 const_cast<GlobalValue *>(GV),
424 ACPV, MayNeedFarStub)
425 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
426 const_cast<GlobalValue *>(GV), ACPV,
428 MCE.addRelocation(MR);
431 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
432 /// be emitted to the current location in the function, and allow it to be PC
434 void ARMCodeEmitter::
435 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
436 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
440 /// emitConstPoolAddress - Arrange for the address of an constant pool
441 /// to be emitted to the current location in the function, and allow it to be PC
443 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
444 // Tell JIT emitter we'll resolve the address.
445 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
446 Reloc, CPI, 0, true));
449 /// emitJumpTableAddress - Arrange for the address of a jump table to
450 /// be emitted to the current location in the function, and allow it to be PC
452 void ARMCodeEmitter::
453 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
454 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
455 Reloc, JTIndex, 0, true));
458 /// emitMachineBasicBlock - Emit the specified address basic block.
459 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
461 intptr_t JTBase) const {
462 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
466 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
467 DEBUG(errs() << " 0x";
468 errs().write_hex(Binary) << "\n");
469 MCE.emitWordLE(Binary);
472 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
473 DEBUG(errs() << " 0x";
474 errs().write_hex(Binary) << "\n");
475 MCE.emitDWordLE(Binary);
478 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
479 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
481 MCE.processDebugLoc(MI.getDebugLoc(), true);
483 ++NumEmitted; // Keep track of the # of mi's emitted
484 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
486 llvm_unreachable("Unhandled instruction encoding format!");
490 if (MI.getOpcode() == ARM::LEApcrelJT) {
491 // Materialize jumptable address.
492 emitLEApcrelJTInstruction(MI);
495 llvm_unreachable("Unhandled instruction encoding!");
498 emitPseudoInstruction(MI);
501 case ARMII::DPSoRegFrm:
502 emitDataProcessingInstruction(MI);
506 emitLoadStoreInstruction(MI);
508 case ARMII::LdMiscFrm:
509 case ARMII::StMiscFrm:
510 emitMiscLoadStoreInstruction(MI);
512 case ARMII::LdStMulFrm:
513 emitLoadStoreMultipleInstruction(MI);
516 emitMulFrmInstruction(MI);
519 emitExtendInstruction(MI);
521 case ARMII::ArithMiscFrm:
522 emitMiscArithInstruction(MI);
525 emitSaturateInstruction(MI);
528 emitBranchInstruction(MI);
530 case ARMII::BrMiscFrm:
531 emitMiscBranchInstruction(MI);
534 case ARMII::VFPUnaryFrm:
535 case ARMII::VFPBinaryFrm:
536 emitVFPArithInstruction(MI);
538 case ARMII::VFPConv1Frm:
539 case ARMII::VFPConv2Frm:
540 case ARMII::VFPConv3Frm:
541 case ARMII::VFPConv4Frm:
542 case ARMII::VFPConv5Frm:
543 emitVFPConversionInstruction(MI);
545 case ARMII::VFPLdStFrm:
546 emitVFPLoadStoreInstruction(MI);
548 case ARMII::VFPLdStMulFrm:
549 emitVFPLoadStoreMultipleInstruction(MI);
552 // NEON instructions.
553 case ARMII::NGetLnFrm:
554 case ARMII::NSetLnFrm:
555 emitNEONLaneInstruction(MI);
558 emitNEONDupInstruction(MI);
560 case ARMII::N1RegModImmFrm:
561 emitNEON1RegModImmInstruction(MI);
563 case ARMII::N2RegFrm:
564 emitNEON2RegInstruction(MI);
566 case ARMII::N3RegFrm:
567 emitNEON3RegInstruction(MI);
570 MCE.processDebugLoc(MI.getDebugLoc(), false);
573 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
574 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
575 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
576 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
578 // Remember the CONSTPOOL_ENTRY address for later relocation.
579 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
581 // Emit constpool island entry. In most cases, the actual values will be
582 // resolved and relocated after code emission.
583 if (MCPE.isMachineConstantPoolEntry()) {
584 ARMConstantPoolValue *ACPV =
585 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
587 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
588 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
590 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
591 const GlobalValue *GV = ACPV->getGV();
593 Reloc::Model RelocM = TM.getRelocationModel();
594 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
596 Subtarget->GVIsIndirectSymbol(GV, RelocM),
599 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
603 const Constant *CV = MCPE.Val.ConstVal;
606 errs() << " ** Constant pool #" << CPI << " @ "
607 << (void*)MCE.getCurrentPCValue() << " ";
608 if (const Function *F = dyn_cast<Function>(CV))
609 errs() << F->getName();
615 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
616 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
618 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
619 uint32_t Val = uint32_t(*CI->getValue().getRawData());
621 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
622 if (CFP->getType()->isFloatTy())
623 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
624 else if (CFP->getType()->isDoubleTy())
625 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
627 llvm_unreachable("Unable to handle this constantpool entry!");
630 llvm_unreachable("Unable to handle this constantpool entry!");
635 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
636 const MachineOperand &MO0 = MI.getOperand(0);
637 const MachineOperand &MO1 = MI.getOperand(1);
639 // Emit the 'movw' instruction.
640 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
642 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
644 // Set the conditional execution predicate.
645 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
648 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
650 // Encode imm16 as imm4:imm12
651 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
652 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
655 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
656 // Emit the 'movt' instruction.
657 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
659 // Set the conditional execution predicate.
660 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
663 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
665 // Encode imm16 as imm4:imm1, same as movw above.
666 Binary |= Hi16 & 0xFFF;
667 Binary |= ((Hi16 >> 12) & 0xF) << 16;
671 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
672 const MachineOperand &MO0 = MI.getOperand(0);
673 const MachineOperand &MO1 = MI.getOperand(1);
674 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
675 "Not a valid so_imm value!");
676 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
677 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
679 // Emit the 'mov' instruction.
680 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
682 // Set the conditional execution predicate.
683 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
686 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
689 // Set bit I(25) to identify this is the immediate form of <shifter_op>
690 Binary |= 1 << ARMII::I_BitShift;
691 Binary |= getMachineSoImmOpValue(V1);
694 // Now the 'orr' instruction.
695 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
697 // Set the conditional execution predicate.
698 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
701 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
704 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
707 // Set bit I(25) to identify this is the immediate form of <shifter_op>
708 Binary |= 1 << ARMII::I_BitShift;
709 Binary |= getMachineSoImmOpValue(V2);
713 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
714 // It's basically add r, pc, (LJTI - $+8)
716 const TargetInstrDesc &TID = MI.getDesc();
718 // Emit the 'add' instruction.
719 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
721 // Set the conditional execution predicate
722 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
724 // Encode S bit if MI modifies CPSR.
725 Binary |= getAddrModeSBit(MI, TID);
728 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
730 // Encode Rn which is PC.
731 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
733 // Encode the displacement.
734 Binary |= 1 << ARMII::I_BitShift;
735 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
740 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
741 unsigned Opcode = MI.getDesc().Opcode;
743 // Part of binary is determined by TableGn.
744 unsigned Binary = getBinaryCodeForInstr(MI);
746 // Set the conditional execution predicate
747 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
749 // Encode S bit if MI modifies CPSR.
750 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
751 Binary |= 1 << ARMII::S_BitShift;
753 // Encode register def if there is one.
754 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
756 // Encode the shift operation.
763 case ARM::MOVsrl_flag:
765 Binary |= (0x2 << 4) | (1 << 7);
767 case ARM::MOVsra_flag:
769 Binary |= (0x4 << 4) | (1 << 7);
773 // Encode register Rm.
774 Binary |= getMachineOpValue(MI, 1);
779 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
780 DEBUG(errs() << " ** LPC" << LabelID << " @ "
781 << (void*)MCE.getCurrentPCValue() << '\n');
782 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
785 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
786 unsigned Opcode = MI.getDesc().Opcode;
789 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
791 case ARM::BMOVPCRX_CALL:
793 case ARM::BMOVPCRXr9_CALL: {
794 // First emit mov lr, pc
795 unsigned Binary = 0x01a0e00f;
796 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
799 // and then emit the branch.
800 emitMiscBranchInstruction(MI);
803 case TargetOpcode::INLINEASM: {
804 // We allow inline assembler nodes with empty bodies - they can
805 // implicitly define registers, which is ok for JIT.
806 if (MI.getOperand(0).getSymbolName()[0]) {
807 report_fatal_error("JIT does not support inline asm!");
811 case TargetOpcode::PROLOG_LABEL:
812 case TargetOpcode::EH_LABEL:
813 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
815 case TargetOpcode::IMPLICIT_DEF:
816 case TargetOpcode::KILL:
819 case ARM::CONSTPOOL_ENTRY:
820 emitConstPoolInstruction(MI);
823 // Remember of the address of the PC label for relocation later.
824 addPCLabel(MI.getOperand(2).getImm());
825 // PICADD is just an add instruction that implicitly read pc.
826 emitDataProcessingInstruction(MI, 0, ARM::PC);
833 // Remember of the address of the PC label for relocation later.
834 addPCLabel(MI.getOperand(2).getImm());
835 // These are just load / store instructions that implicitly read pc.
836 emitLoadStoreInstruction(MI, 0, ARM::PC);
843 // Remember of the address of the PC label for relocation later.
844 addPCLabel(MI.getOperand(2).getImm());
845 // These are just load / store instructions that implicitly read pc.
846 emitMiscLoadStoreInstruction(MI, ARM::PC);
851 // Two instructions to materialize a constant.
852 if (Subtarget->hasV6T2Ops())
853 emitMOVi32immInstruction(MI);
855 emitMOVi2piecesInstruction(MI);
858 case ARM::LEApcrelJT:
859 // Materialize jumptable address.
860 emitLEApcrelJTInstruction(MI);
863 case ARM::MOVsrl_flag:
864 case ARM::MOVsra_flag:
865 emitPseudoMoveInstruction(MI);
870 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
871 const TargetInstrDesc &TID,
872 const MachineOperand &MO,
874 unsigned Binary = getMachineOpValue(MI, MO);
876 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
877 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
878 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
880 // Encode the shift opcode.
882 unsigned Rs = MO1.getReg();
884 // Set shift operand (bit[7:4]).
889 // RRX - 0110 and bit[11:8] clear.
891 default: llvm_unreachable("Unknown shift opc!");
892 case ARM_AM::lsl: SBits = 0x1; break;
893 case ARM_AM::lsr: SBits = 0x3; break;
894 case ARM_AM::asr: SBits = 0x5; break;
895 case ARM_AM::ror: SBits = 0x7; break;
896 case ARM_AM::rrx: SBits = 0x6; break;
899 // Set shift operand (bit[6:4]).
905 default: llvm_unreachable("Unknown shift opc!");
906 case ARM_AM::lsl: SBits = 0x0; break;
907 case ARM_AM::lsr: SBits = 0x2; break;
908 case ARM_AM::asr: SBits = 0x4; break;
909 case ARM_AM::ror: SBits = 0x6; break;
912 Binary |= SBits << 4;
913 if (SOpc == ARM_AM::rrx)
916 // Encode the shift operation Rs or shift_imm (except rrx).
918 // Encode Rs bit[11:8].
919 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
920 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
923 // Encode shift_imm bit[11:7].
924 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
927 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
928 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
929 assert(SoImmVal != -1 && "Not a valid so_imm value!");
931 // Encode rotate_imm.
932 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
933 << ARMII::SoRotImmShift;
936 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
940 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
941 const TargetInstrDesc &TID) const {
942 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
943 const MachineOperand &MO = MI.getOperand(i-1);
944 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
945 return 1 << ARMII::S_BitShift;
950 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
952 unsigned ImplicitRn) {
953 const TargetInstrDesc &TID = MI.getDesc();
955 // Part of binary is determined by TableGn.
956 unsigned Binary = getBinaryCodeForInstr(MI);
958 // Set the conditional execution predicate
959 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
961 // Encode S bit if MI modifies CPSR.
962 Binary |= getAddrModeSBit(MI, TID);
964 // Encode register def if there is one.
965 unsigned NumDefs = TID.getNumDefs();
968 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
970 // Special handling for implicit use (e.g. PC).
971 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
973 if (TID.Opcode == ARM::MOVi16) {
974 // Get immediate from MI.
975 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
976 ARM::reloc_arm_movw);
977 // Encode imm which is the same as in emitMOVi32immInstruction().
978 Binary |= Lo16 & 0xFFF;
979 Binary |= ((Lo16 >> 12) & 0xF) << 16;
982 } else if(TID.Opcode == ARM::MOVTi16) {
983 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
984 ARM::reloc_arm_movt) >> 16);
985 Binary |= Hi16 & 0xFFF;
986 Binary |= ((Hi16 >> 12) & 0xF) << 16;
989 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
990 uint32_t v = ~MI.getOperand(2).getImm();
991 int32_t lsb = CountTrailingZeros_32(v);
992 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
993 // Instr{20-16} = msb, Instr{11-7} = lsb
994 Binary |= (msb & 0x1F) << 16;
995 Binary |= (lsb & 0x1F) << 7;
998 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
999 // Encode Rn in Instr{0-3}
1000 Binary |= getMachineOpValue(MI, OpIdx++);
1002 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1003 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1005 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1006 Binary |= (widthm1 & 0x1F) << 16;
1007 Binary |= (lsb & 0x1F) << 7;
1012 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1013 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1016 // Encode first non-shifter register operand if there is one.
1017 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
1020 // Special handling for implicit use (e.g. PC).
1021 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1023 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1028 // Encode shifter operand.
1029 const MachineOperand &MO = MI.getOperand(OpIdx);
1030 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1032 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
1037 // Encode register Rm.
1038 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1043 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1048 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1049 unsigned ImplicitRd,
1050 unsigned ImplicitRn) {
1051 const TargetInstrDesc &TID = MI.getDesc();
1052 unsigned Form = TID.TSFlags & ARMII::FormMask;
1053 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1055 // Part of binary is determined by TableGn.
1056 unsigned Binary = getBinaryCodeForInstr(MI);
1058 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1059 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1060 MI.getOpcode() == ARM::STRi12) {
1065 // Set the conditional execution predicate
1066 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1070 // Operand 0 of a pre- and post-indexed store is the address base
1071 // writeback. Skip it.
1072 bool Skipped = false;
1073 if (IsPrePost && Form == ARMII::StFrm) {
1078 // Set first operand
1080 // Special handling for implicit use (e.g. PC).
1081 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1083 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1085 // Set second operand
1087 // Special handling for implicit use (e.g. PC).
1088 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1090 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1092 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1093 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1096 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1097 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1098 ? 0 : MI.getOperand(OpIdx+1).getImm();
1100 // Set bit U(23) according to sign of immed value (positive or negative).
1101 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1103 if (!MO2.getReg()) { // is immediate
1104 if (ARM_AM::getAM2Offset(AM2Opc))
1105 // Set the value of offset_12 field
1106 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1111 // Set bit I(25), because this is not in immediate encoding.
1112 Binary |= 1 << ARMII::I_BitShift;
1113 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1114 // Set bit[3:0] to the corresponding Rm register
1115 Binary |= getARMRegisterNumbering(MO2.getReg());
1117 // If this instr is in scaled register offset/index instruction, set
1118 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1119 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1120 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1121 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1127 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1128 unsigned ImplicitRn) {
1129 const TargetInstrDesc &TID = MI.getDesc();
1130 unsigned Form = TID.TSFlags & ARMII::FormMask;
1131 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1133 // Part of binary is determined by TableGn.
1134 unsigned Binary = getBinaryCodeForInstr(MI);
1136 // Set the conditional execution predicate
1137 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1141 // Operand 0 of a pre- and post-indexed store is the address base
1142 // writeback. Skip it.
1143 bool Skipped = false;
1144 if (IsPrePost && Form == ARMII::StMiscFrm) {
1149 // Set first operand
1150 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1152 // Skip LDRD and STRD's second operand.
1153 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1156 // Set second operand
1158 // Special handling for implicit use (e.g. PC).
1159 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1161 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1163 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1164 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1167 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1168 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1169 ? 0 : MI.getOperand(OpIdx+1).getImm();
1171 // Set bit U(23) according to sign of immed value (positive or negative)
1172 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1175 // If this instr is in register offset/index encoding, set bit[3:0]
1176 // to the corresponding Rm register.
1178 Binary |= getARMRegisterNumbering(MO2.getReg());
1183 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1184 Binary |= 1 << ARMII::AM3_I_BitShift;
1185 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1187 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1188 Binary |= (ImmOffs & 0xF); // immedL
1194 static unsigned getAddrModeUPBits(unsigned Mode) {
1195 unsigned Binary = 0;
1197 // Set addressing mode by modifying bits U(23) and P(24)
1198 // IA - Increment after - bit U = 1 and bit P = 0
1199 // IB - Increment before - bit U = 1 and bit P = 1
1200 // DA - Decrement after - bit U = 0 and bit P = 0
1201 // DB - Decrement before - bit U = 0 and bit P = 1
1203 default: llvm_unreachable("Unknown addressing sub-mode!");
1204 case ARM_AM::da: break;
1205 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1206 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1207 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1213 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1214 const TargetInstrDesc &TID = MI.getDesc();
1215 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1217 // Part of binary is determined by TableGn.
1218 unsigned Binary = getBinaryCodeForInstr(MI);
1220 // Set the conditional execution predicate
1221 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1223 // Skip operand 0 of an instruction with base register update.
1228 // Set base address operand
1229 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1231 // Set addressing mode by modifying bits U(23) and P(24)
1232 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1233 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1237 Binary |= 0x1 << ARMII::W_BitShift;
1240 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1241 const MachineOperand &MO = MI.getOperand(i);
1242 if (!MO.isReg() || MO.isImplicit())
1244 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1245 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1247 Binary |= 0x1 << RegNum;
1253 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1254 const TargetInstrDesc &TID = MI.getDesc();
1256 // Part of binary is determined by TableGn.
1257 unsigned Binary = getBinaryCodeForInstr(MI);
1259 // Set the conditional execution predicate
1260 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1262 // Encode S bit if MI modifies CPSR.
1263 Binary |= getAddrModeSBit(MI, TID);
1265 // 32x32->64bit operations have two destination registers. The number
1266 // of register definitions will tell us if that's what we're dealing with.
1268 if (TID.getNumDefs() == 2)
1269 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1272 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1275 Binary |= getMachineOpValue(MI, OpIdx++);
1278 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1280 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1281 // it as Rn (for multiply, that's in the same offset as RdLo.
1282 if (TID.getNumOperands() > OpIdx &&
1283 !TID.OpInfo[OpIdx].isPredicate() &&
1284 !TID.OpInfo[OpIdx].isOptionalDef())
1285 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1290 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1291 const TargetInstrDesc &TID = MI.getDesc();
1293 // Part of binary is determined by TableGn.
1294 unsigned Binary = getBinaryCodeForInstr(MI);
1296 // Set the conditional execution predicate
1297 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1302 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1304 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1305 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1307 // Two register operand form.
1309 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1312 Binary |= getMachineOpValue(MI, MO2);
1315 Binary |= getMachineOpValue(MI, MO1);
1318 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1319 if (MI.getOperand(OpIdx).isImm() &&
1320 !TID.OpInfo[OpIdx].isPredicate() &&
1321 !TID.OpInfo[OpIdx].isOptionalDef())
1322 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1327 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1328 const TargetInstrDesc &TID = MI.getDesc();
1330 // Part of binary is determined by TableGn.
1331 unsigned Binary = getBinaryCodeForInstr(MI);
1333 // Set the conditional execution predicate
1334 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1339 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1341 const MachineOperand &MO = MI.getOperand(OpIdx++);
1342 if (OpIdx == TID.getNumOperands() ||
1343 TID.OpInfo[OpIdx].isPredicate() ||
1344 TID.OpInfo[OpIdx].isOptionalDef()) {
1345 // Encode Rm and it's done.
1346 Binary |= getMachineOpValue(MI, MO);
1352 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1355 Binary |= getMachineOpValue(MI, OpIdx++);
1357 // Encode shift_imm.
1358 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1359 if (TID.Opcode == ARM::PKHTB) {
1360 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1364 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1365 Binary |= ShiftAmt << ARMII::ShiftShift;
1370 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1371 const TargetInstrDesc &TID = MI.getDesc();
1373 // Part of binary is determined by TableGen.
1374 unsigned Binary = getBinaryCodeForInstr(MI);
1376 // Set the conditional execution predicate
1377 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1380 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1382 // Encode saturate bit position.
1383 unsigned Pos = MI.getOperand(1).getImm();
1384 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1386 assert((Pos < 16 || (Pos < 32 &&
1387 TID.Opcode != ARM::SSAT16 &&
1388 TID.Opcode != ARM::USAT16)) &&
1389 "saturate bit position out of range");
1390 Binary |= Pos << 16;
1393 Binary |= getMachineOpValue(MI, 2);
1395 // Encode shift_imm.
1396 if (TID.getNumOperands() == 4) {
1397 unsigned ShiftOp = MI.getOperand(3).getImm();
1398 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1399 if (Opc == ARM_AM::asr)
1401 unsigned ShiftAmt = MI.getOperand(3).getImm();
1402 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1404 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1405 Binary |= ShiftAmt << ARMII::ShiftShift;
1411 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1412 const TargetInstrDesc &TID = MI.getDesc();
1414 if (TID.Opcode == ARM::TPsoft) {
1415 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1418 // Part of binary is determined by TableGn.
1419 unsigned Binary = getBinaryCodeForInstr(MI);
1421 // Set the conditional execution predicate
1422 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1424 // Set signed_immed_24 field
1425 Binary |= getMachineOpValue(MI, 0);
1430 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1431 // Remember the base address of the inline jump table.
1432 uintptr_t JTBase = MCE.getCurrentPCValue();
1433 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1434 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1437 // Now emit the jump table entries.
1438 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1439 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1441 // DestBB address - JT base.
1442 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1444 // Absolute DestBB address.
1445 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1450 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1451 const TargetInstrDesc &TID = MI.getDesc();
1453 // Handle jump tables.
1454 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1455 // First emit a ldr pc, [] instruction.
1456 emitDataProcessingInstruction(MI, ARM::PC);
1458 // Then emit the inline jump table.
1460 (TID.Opcode == ARM::BR_JTr)
1461 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1462 emitInlineJumpTable(JTIndex);
1464 } else if (TID.Opcode == ARM::BR_JTm) {
1465 // First emit a ldr pc, [] instruction.
1466 emitLoadStoreInstruction(MI, ARM::PC);
1468 // Then emit the inline jump table.
1469 emitInlineJumpTable(MI.getOperand(3).getIndex());
1473 // Part of binary is determined by TableGn.
1474 unsigned Binary = getBinaryCodeForInstr(MI);
1476 // Set the conditional execution predicate
1477 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1479 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1480 // The return register is LR.
1481 Binary |= getARMRegisterNumbering(ARM::LR);
1483 // otherwise, set the return register
1484 Binary |= getMachineOpValue(MI, 0);
1489 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1490 unsigned RegD = MI.getOperand(OpIdx).getReg();
1491 unsigned Binary = 0;
1492 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1493 RegD = getARMRegisterNumbering(RegD);
1495 Binary |= RegD << ARMII::RegRdShift;
1497 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1498 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1503 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1504 unsigned RegN = MI.getOperand(OpIdx).getReg();
1505 unsigned Binary = 0;
1506 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1507 RegN = getARMRegisterNumbering(RegN);
1509 Binary |= RegN << ARMII::RegRnShift;
1511 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1512 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1517 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1518 unsigned RegM = MI.getOperand(OpIdx).getReg();
1519 unsigned Binary = 0;
1520 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1521 RegM = getARMRegisterNumbering(RegM);
1525 Binary |= ((RegM & 0x1E) >> 1);
1526 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1531 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1532 const TargetInstrDesc &TID = MI.getDesc();
1534 // Part of binary is determined by TableGn.
1535 unsigned Binary = getBinaryCodeForInstr(MI);
1537 // Set the conditional execution predicate
1538 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1541 assert((Binary & ARMII::D_BitShift) == 0 &&
1542 (Binary & ARMII::N_BitShift) == 0 &&
1543 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1546 Binary |= encodeVFPRd(MI, OpIdx++);
1548 // If this is a two-address operand, skip it, e.g. FMACD.
1549 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1553 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1554 Binary |= encodeVFPRn(MI, OpIdx++);
1556 if (OpIdx == TID.getNumOperands() ||
1557 TID.OpInfo[OpIdx].isPredicate() ||
1558 TID.OpInfo[OpIdx].isOptionalDef()) {
1559 // FCMPEZD etc. has only one operand.
1565 Binary |= encodeVFPRm(MI, OpIdx);
1570 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1571 const TargetInstrDesc &TID = MI.getDesc();
1572 unsigned Form = TID.TSFlags & ARMII::FormMask;
1574 // Part of binary is determined by TableGn.
1575 unsigned Binary = getBinaryCodeForInstr(MI);
1577 // Set the conditional execution predicate
1578 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1582 case ARMII::VFPConv1Frm:
1583 case ARMII::VFPConv2Frm:
1584 case ARMII::VFPConv3Frm:
1586 Binary |= encodeVFPRd(MI, 0);
1588 case ARMII::VFPConv4Frm:
1590 Binary |= encodeVFPRn(MI, 0);
1592 case ARMII::VFPConv5Frm:
1594 Binary |= encodeVFPRm(MI, 0);
1600 case ARMII::VFPConv1Frm:
1602 Binary |= encodeVFPRm(MI, 1);
1604 case ARMII::VFPConv2Frm:
1605 case ARMII::VFPConv3Frm:
1607 Binary |= encodeVFPRn(MI, 1);
1609 case ARMII::VFPConv4Frm:
1610 case ARMII::VFPConv5Frm:
1612 Binary |= encodeVFPRd(MI, 1);
1616 if (Form == ARMII::VFPConv5Frm)
1618 Binary |= encodeVFPRn(MI, 2);
1619 else if (Form == ARMII::VFPConv3Frm)
1621 Binary |= encodeVFPRm(MI, 2);
1626 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1627 // Part of binary is determined by TableGn.
1628 unsigned Binary = getBinaryCodeForInstr(MI);
1630 // Set the conditional execution predicate
1631 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1636 Binary |= encodeVFPRd(MI, OpIdx++);
1638 // Encode address base.
1639 const MachineOperand &Base = MI.getOperand(OpIdx++);
1640 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1642 // If there is a non-zero immediate offset, encode it.
1644 const MachineOperand &Offset = MI.getOperand(OpIdx);
1645 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1646 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1647 Binary |= 1 << ARMII::U_BitShift;
1654 // If immediate offset is omitted, default to +0.
1655 Binary |= 1 << ARMII::U_BitShift;
1661 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1662 const TargetInstrDesc &TID = MI.getDesc();
1663 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1665 // Part of binary is determined by TableGn.
1666 unsigned Binary = getBinaryCodeForInstr(MI);
1668 // Set the conditional execution predicate
1669 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1671 // Skip operand 0 of an instruction with base register update.
1676 // Set base address operand
1677 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1679 // Set addressing mode by modifying bits U(23) and P(24)
1680 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1681 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1685 Binary |= 0x1 << ARMII::W_BitShift;
1687 // First register is encoded in Dd.
1688 Binary |= encodeVFPRd(MI, OpIdx+2);
1690 // Count the number of registers.
1691 unsigned NumRegs = 1;
1692 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1693 const MachineOperand &MO = MI.getOperand(i);
1694 if (!MO.isReg() || MO.isImplicit())
1698 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1699 // Otherwise, it will be 0, in the case of 32-bit registers.
1701 Binary |= NumRegs * 2;
1708 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1709 unsigned RegD = MI.getOperand(OpIdx).getReg();
1710 unsigned Binary = 0;
1711 RegD = getARMRegisterNumbering(RegD);
1712 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1713 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1717 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1718 unsigned RegN = MI.getOperand(OpIdx).getReg();
1719 unsigned Binary = 0;
1720 RegN = getARMRegisterNumbering(RegN);
1721 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1722 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1726 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1727 unsigned RegM = MI.getOperand(OpIdx).getReg();
1728 unsigned Binary = 0;
1729 RegM = getARMRegisterNumbering(RegM);
1730 Binary |= (RegM & 0xf);
1731 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1735 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1736 /// data-processing instruction to the corresponding Thumb encoding.
1737 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1738 assert((Binary & 0xfe000000) == 0xf2000000 &&
1739 "not an ARM NEON data-processing instruction");
1740 unsigned UBit = (Binary >> 24) & 1;
1741 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1744 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1745 unsigned Binary = getBinaryCodeForInstr(MI);
1747 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1748 const TargetInstrDesc &TID = MI.getDesc();
1749 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1753 } else { // ARMII::NSetLnFrm
1759 // Set the conditional execution predicate
1760 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1762 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1763 RegT = getARMRegisterNumbering(RegT);
1764 Binary |= (RegT << ARMII::RegRdShift);
1765 Binary |= encodeNEONRn(MI, RegNOpIdx);
1768 if ((Binary & (1 << 22)) != 0)
1769 LaneShift = 0; // 8-bit elements
1770 else if ((Binary & (1 << 5)) != 0)
1771 LaneShift = 1; // 16-bit elements
1773 LaneShift = 2; // 32-bit elements
1775 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1776 unsigned Opc1 = Lane >> 2;
1777 unsigned Opc2 = Lane & 3;
1778 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1779 Binary |= (Opc1 << 21);
1780 Binary |= (Opc2 << 5);
1785 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1786 unsigned Binary = getBinaryCodeForInstr(MI);
1788 // Set the conditional execution predicate
1789 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1791 unsigned RegT = MI.getOperand(1).getReg();
1792 RegT = getARMRegisterNumbering(RegT);
1793 Binary |= (RegT << ARMII::RegRdShift);
1794 Binary |= encodeNEONRn(MI, 0);
1798 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1799 unsigned Binary = getBinaryCodeForInstr(MI);
1800 // Destination register is encoded in Dd.
1801 Binary |= encodeNEONRd(MI, 0);
1802 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1803 unsigned Imm = MI.getOperand(1).getImm();
1804 unsigned Op = (Imm >> 12) & 1;
1805 unsigned Cmode = (Imm >> 8) & 0xf;
1806 unsigned I = (Imm >> 7) & 1;
1807 unsigned Imm3 = (Imm >> 4) & 0x7;
1808 unsigned Imm4 = Imm & 0xf;
1809 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1811 Binary = convertNEONDataProcToThumb(Binary);
1815 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1816 const TargetInstrDesc &TID = MI.getDesc();
1817 unsigned Binary = getBinaryCodeForInstr(MI);
1818 // Destination register is encoded in Dd; source register in Dm.
1820 Binary |= encodeNEONRd(MI, OpIdx++);
1821 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1823 Binary |= encodeNEONRm(MI, OpIdx);
1825 Binary = convertNEONDataProcToThumb(Binary);
1826 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1830 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1831 const TargetInstrDesc &TID = MI.getDesc();
1832 unsigned Binary = getBinaryCodeForInstr(MI);
1833 // Destination register is encoded in Dd; source registers in Dn and Dm.
1835 Binary |= encodeNEONRd(MI, OpIdx++);
1836 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1838 Binary |= encodeNEONRn(MI, OpIdx++);
1839 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1841 Binary |= encodeNEONRm(MI, OpIdx);
1843 Binary = convertNEONDataProcToThumb(Binary);
1844 // FIXME: This does not handle VMOVDneon or VMOVQ.
1848 #include "ARMGenCodeEmitter.inc"