1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
105 unsigned getAddrModeSBit(const MachineInstr &MI,
106 const TargetInstrDesc &TID) const;
108 void emitDataProcessingInstruction(const MachineInstr &MI,
109 unsigned ImplicitRd = 0,
110 unsigned ImplicitRn = 0);
112 void emitLoadStoreInstruction(const MachineInstr &MI,
113 unsigned ImplicitRd = 0,
114 unsigned ImplicitRn = 0);
116 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117 unsigned ImplicitRn = 0);
119 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121 void emitMulFrmInstruction(const MachineInstr &MI);
123 void emitExtendInstruction(const MachineInstr &MI);
125 void emitMiscArithInstruction(const MachineInstr &MI);
127 void emitSaturateInstruction(const MachineInstr &MI);
129 void emitBranchInstruction(const MachineInstr &MI);
131 void emitInlineJumpTable(unsigned JTIndex);
133 void emitMiscBranchInstruction(const MachineInstr &MI);
135 void emitVFPArithInstruction(const MachineInstr &MI);
137 void emitVFPConversionInstruction(const MachineInstr &MI);
139 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
141 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
143 void emitMiscInstruction(const MachineInstr &MI);
145 void emitNEONLaneInstruction(const MachineInstr &MI);
146 void emitNEONDupInstruction(const MachineInstr &MI);
147 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
148 void emitNEON2RegInstruction(const MachineInstr &MI);
149 void emitNEON3RegInstruction(const MachineInstr &MI);
151 /// getMachineOpValue - Return binary encoding of operand. If the machine
152 /// operand requires relocation, record the relocation and return zero.
153 unsigned getMachineOpValue(const MachineInstr &MI,
154 const MachineOperand &MO) const;
155 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
156 return getMachineOpValue(MI, MI.getOperand(OpIdx));
159 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
160 // TableGen'erated getBinaryCodeForInstr() function to encode any
161 // operand values, instead querying getMachineOpValue() directly for
162 // each operand it needs to encode. Thus, any of the new encoder
163 // helper functions can simply return 0 as the values the return
164 // are already handled elsewhere. They are placeholders to allow this
165 // encoder to continue to function until the MC encoder is sufficiently
166 // far along that this one can be eliminated entirely.
167 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
169 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
171 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
173 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
175 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
178 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
179 /// machine operand requires relocation, record the relocation and return
181 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
184 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
186 unsigned getShiftOp(unsigned Imm) const ;
188 /// Routines that handle operands which add machine relocations which are
189 /// fixed up by the relocation stage.
190 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
191 bool MayNeedFarStub, bool Indirect,
192 intptr_t ACPV = 0) const;
193 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
194 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
195 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
196 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
197 intptr_t JTBase = 0) const;
201 char ARMCodeEmitter::ID = 0;
203 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
204 /// code to the specified MCE object.
205 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
206 JITCodeEmitter &JCE) {
207 return new ARMCodeEmitter(TM, JCE);
210 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
211 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
212 MF.getTarget().getRelocationModel() != Reloc::Static) &&
213 "JIT relocation model must be set to static or default!");
214 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
215 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
216 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
217 Subtarget = &TM.getSubtarget<ARMSubtarget>();
218 MCPEs = &MF.getConstantPool()->getConstants();
220 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
221 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
222 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
223 JTI->Initialize(MF, IsPIC);
224 MMI = &getAnalysis<MachineModuleInfo>();
225 MCE.setModuleInfo(MMI);
228 DEBUG(errs() << "JITTing function '"
229 << MF.getFunction()->getName() << "'\n");
230 MCE.startFunction(MF);
231 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
233 MCE.StartMachineBasicBlock(MBB);
234 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
238 } while (MCE.finishFunction(MF));
243 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
245 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
246 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
247 default: llvm_unreachable("Unknown shift opc!");
248 case ARM_AM::asr: return 2;
249 case ARM_AM::lsl: return 0;
250 case ARM_AM::lsr: return 1;
252 case ARM_AM::rrx: return 3;
257 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
258 /// machine operand requires relocation, record the relocation and return zero.
259 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
260 const MachineOperand &MO,
262 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
263 && "Relocation to this function should be for movt or movw");
266 return static_cast<unsigned>(MO.getImm());
267 else if (MO.isGlobal())
268 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
269 else if (MO.isSymbol())
270 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
272 emitMachineBasicBlock(MO.getMBB(), Reloc);
277 llvm_unreachable("Unsupported operand type for movw/movt");
282 /// getMachineOpValue - Return binary encoding of operand. If the machine
283 /// operand requires relocation, record the relocation and return zero.
284 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
285 const MachineOperand &MO) const {
287 return getARMRegisterNumbering(MO.getReg());
289 return static_cast<unsigned>(MO.getImm());
290 else if (MO.isGlobal())
291 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
292 else if (MO.isSymbol())
293 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
294 else if (MO.isCPI()) {
295 const TargetInstrDesc &TID = MI.getDesc();
296 // For VFP load, the immediate offset is multiplied by 4.
297 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
298 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
299 emitConstPoolAddress(MO.getIndex(), Reloc);
300 } else if (MO.isJTI())
301 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
303 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
313 /// emitGlobalAddress - Emit the specified address to the code stream.
315 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
316 bool MayNeedFarStub, bool Indirect,
317 intptr_t ACPV) const {
318 MachineRelocation MR = Indirect
319 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
320 const_cast<GlobalValue *>(GV),
321 ACPV, MayNeedFarStub)
322 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
323 const_cast<GlobalValue *>(GV), ACPV,
325 MCE.addRelocation(MR);
328 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
329 /// be emitted to the current location in the function, and allow it to be PC
331 void ARMCodeEmitter::
332 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
333 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
337 /// emitConstPoolAddress - Arrange for the address of an constant pool
338 /// to be emitted to the current location in the function, and allow it to be PC
340 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
341 // Tell JIT emitter we'll resolve the address.
342 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
343 Reloc, CPI, 0, true));
346 /// emitJumpTableAddress - Arrange for the address of a jump table to
347 /// be emitted to the current location in the function, and allow it to be PC
349 void ARMCodeEmitter::
350 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
351 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
352 Reloc, JTIndex, 0, true));
355 /// emitMachineBasicBlock - Emit the specified address basic block.
356 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
358 intptr_t JTBase) const {
359 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
363 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
364 DEBUG(errs() << " 0x";
365 errs().write_hex(Binary) << "\n");
366 MCE.emitWordLE(Binary);
369 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
370 DEBUG(errs() << " 0x";
371 errs().write_hex(Binary) << "\n");
372 MCE.emitDWordLE(Binary);
375 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
376 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
378 MCE.processDebugLoc(MI.getDebugLoc(), true);
380 ++NumEmitted; // Keep track of the # of mi's emitted
381 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
383 llvm_unreachable("Unhandled instruction encoding format!");
387 emitPseudoInstruction(MI);
390 case ARMII::DPSoRegFrm:
391 emitDataProcessingInstruction(MI);
395 emitLoadStoreInstruction(MI);
397 case ARMII::LdMiscFrm:
398 case ARMII::StMiscFrm:
399 emitMiscLoadStoreInstruction(MI);
401 case ARMII::LdStMulFrm:
402 emitLoadStoreMultipleInstruction(MI);
405 emitMulFrmInstruction(MI);
408 emitExtendInstruction(MI);
410 case ARMII::ArithMiscFrm:
411 emitMiscArithInstruction(MI);
414 emitSaturateInstruction(MI);
417 emitBranchInstruction(MI);
419 case ARMII::BrMiscFrm:
420 emitMiscBranchInstruction(MI);
423 case ARMII::VFPUnaryFrm:
424 case ARMII::VFPBinaryFrm:
425 emitVFPArithInstruction(MI);
427 case ARMII::VFPConv1Frm:
428 case ARMII::VFPConv2Frm:
429 case ARMII::VFPConv3Frm:
430 case ARMII::VFPConv4Frm:
431 case ARMII::VFPConv5Frm:
432 emitVFPConversionInstruction(MI);
434 case ARMII::VFPLdStFrm:
435 emitVFPLoadStoreInstruction(MI);
437 case ARMII::VFPLdStMulFrm:
438 emitVFPLoadStoreMultipleInstruction(MI);
440 case ARMII::VFPMiscFrm:
441 emitMiscInstruction(MI);
443 // NEON instructions.
444 case ARMII::NGetLnFrm:
445 case ARMII::NSetLnFrm:
446 emitNEONLaneInstruction(MI);
449 emitNEONDupInstruction(MI);
451 case ARMII::N1RegModImmFrm:
452 emitNEON1RegModImmInstruction(MI);
454 case ARMII::N2RegFrm:
455 emitNEON2RegInstruction(MI);
457 case ARMII::N3RegFrm:
458 emitNEON3RegInstruction(MI);
461 MCE.processDebugLoc(MI.getDebugLoc(), false);
464 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
465 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
466 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
467 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
469 // Remember the CONSTPOOL_ENTRY address for later relocation.
470 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
472 // Emit constpool island entry. In most cases, the actual values will be
473 // resolved and relocated after code emission.
474 if (MCPE.isMachineConstantPoolEntry()) {
475 ARMConstantPoolValue *ACPV =
476 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
478 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
479 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
481 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
482 const GlobalValue *GV = ACPV->getGV();
484 Reloc::Model RelocM = TM.getRelocationModel();
485 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
487 Subtarget->GVIsIndirectSymbol(GV, RelocM),
490 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
494 const Constant *CV = MCPE.Val.ConstVal;
497 errs() << " ** Constant pool #" << CPI << " @ "
498 << (void*)MCE.getCurrentPCValue() << " ";
499 if (const Function *F = dyn_cast<Function>(CV))
500 errs() << F->getName();
506 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
507 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
509 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
510 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
512 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
513 if (CFP->getType()->isFloatTy())
514 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
515 else if (CFP->getType()->isDoubleTy())
516 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
518 llvm_unreachable("Unable to handle this constantpool entry!");
521 llvm_unreachable("Unable to handle this constantpool entry!");
526 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
527 const MachineOperand &MO0 = MI.getOperand(0);
528 const MachineOperand &MO1 = MI.getOperand(1);
530 // Emit the 'movw' instruction.
531 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
533 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
535 // Set the conditional execution predicate.
536 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
539 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
541 // Encode imm16 as imm4:imm12
542 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
543 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
546 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
547 // Emit the 'movt' instruction.
548 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
550 // Set the conditional execution predicate.
551 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
554 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
556 // Encode imm16 as imm4:imm1, same as movw above.
557 Binary |= Hi16 & 0xFFF;
558 Binary |= ((Hi16 >> 12) & 0xF) << 16;
562 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
563 const MachineOperand &MO0 = MI.getOperand(0);
564 const MachineOperand &MO1 = MI.getOperand(1);
565 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
566 "Not a valid so_imm value!");
567 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
568 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
570 // Emit the 'mov' instruction.
571 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
573 // Set the conditional execution predicate.
574 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
577 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
580 // Set bit I(25) to identify this is the immediate form of <shifter_op>
581 Binary |= 1 << ARMII::I_BitShift;
582 Binary |= getMachineSoImmOpValue(V1);
585 // Now the 'orr' instruction.
586 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
588 // Set the conditional execution predicate.
589 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
592 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
595 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
598 // Set bit I(25) to identify this is the immediate form of <shifter_op>
599 Binary |= 1 << ARMII::I_BitShift;
600 Binary |= getMachineSoImmOpValue(V2);
604 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
605 // It's basically add r, pc, (LJTI - $+8)
607 const TargetInstrDesc &TID = MI.getDesc();
609 // Emit the 'add' instruction.
610 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
612 // Set the conditional execution predicate
613 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
615 // Encode S bit if MI modifies CPSR.
616 Binary |= getAddrModeSBit(MI, TID);
619 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
621 // Encode Rn which is PC.
622 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
624 // Encode the displacement.
625 Binary |= 1 << ARMII::I_BitShift;
626 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
631 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
632 unsigned Opcode = MI.getDesc().Opcode;
634 // Part of binary is determined by TableGn.
635 unsigned Binary = getBinaryCodeForInstr(MI);
637 // Set the conditional execution predicate
638 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
640 // Encode S bit if MI modifies CPSR.
641 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
642 Binary |= 1 << ARMII::S_BitShift;
644 // Encode register def if there is one.
645 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
647 // Encode the shift operation.
654 case ARM::MOVsrl_flag:
656 Binary |= (0x2 << 4) | (1 << 7);
658 case ARM::MOVsra_flag:
660 Binary |= (0x4 << 4) | (1 << 7);
664 // Encode register Rm.
665 Binary |= getMachineOpValue(MI, 1);
670 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
671 DEBUG(errs() << " ** LPC" << LabelID << " @ "
672 << (void*)MCE.getCurrentPCValue() << '\n');
673 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
676 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
677 unsigned Opcode = MI.getDesc().Opcode;
680 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
684 case ARM::BMOVPCRXr9: {
685 // First emit mov lr, pc
686 unsigned Binary = 0x01a0e00f;
687 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
690 // and then emit the branch.
691 emitMiscBranchInstruction(MI);
694 case TargetOpcode::INLINEASM: {
695 // We allow inline assembler nodes with empty bodies - they can
696 // implicitly define registers, which is ok for JIT.
697 if (MI.getOperand(0).getSymbolName()[0]) {
698 report_fatal_error("JIT does not support inline asm!");
702 case TargetOpcode::PROLOG_LABEL:
703 case TargetOpcode::EH_LABEL:
704 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
706 case TargetOpcode::IMPLICIT_DEF:
707 case TargetOpcode::KILL:
710 case ARM::CONSTPOOL_ENTRY:
711 emitConstPoolInstruction(MI);
714 // Remember of the address of the PC label for relocation later.
715 addPCLabel(MI.getOperand(2).getImm());
716 // PICADD is just an add instruction that implicitly read pc.
717 emitDataProcessingInstruction(MI, 0, ARM::PC);
724 // Remember of the address of the PC label for relocation later.
725 addPCLabel(MI.getOperand(2).getImm());
726 // These are just load / store instructions that implicitly read pc.
727 emitLoadStoreInstruction(MI, 0, ARM::PC);
734 // Remember of the address of the PC label for relocation later.
735 addPCLabel(MI.getOperand(2).getImm());
736 // These are just load / store instructions that implicitly read pc.
737 emitMiscLoadStoreInstruction(MI, ARM::PC);
742 emitMOVi32immInstruction(MI);
745 case ARM::MOVi2pieces:
746 // Two instructions to materialize a constant.
747 emitMOVi2piecesInstruction(MI);
749 case ARM::LEApcrelJT:
750 // Materialize jumptable address.
751 emitLEApcrelJTInstruction(MI);
754 case ARM::MOVsrl_flag:
755 case ARM::MOVsra_flag:
756 emitPseudoMoveInstruction(MI);
761 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
762 const TargetInstrDesc &TID,
763 const MachineOperand &MO,
765 unsigned Binary = getMachineOpValue(MI, MO);
767 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
768 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
769 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
771 // Encode the shift opcode.
773 unsigned Rs = MO1.getReg();
775 // Set shift operand (bit[7:4]).
780 // RRX - 0110 and bit[11:8] clear.
782 default: llvm_unreachable("Unknown shift opc!");
783 case ARM_AM::lsl: SBits = 0x1; break;
784 case ARM_AM::lsr: SBits = 0x3; break;
785 case ARM_AM::asr: SBits = 0x5; break;
786 case ARM_AM::ror: SBits = 0x7; break;
787 case ARM_AM::rrx: SBits = 0x6; break;
790 // Set shift operand (bit[6:4]).
796 default: llvm_unreachable("Unknown shift opc!");
797 case ARM_AM::lsl: SBits = 0x0; break;
798 case ARM_AM::lsr: SBits = 0x2; break;
799 case ARM_AM::asr: SBits = 0x4; break;
800 case ARM_AM::ror: SBits = 0x6; break;
803 Binary |= SBits << 4;
804 if (SOpc == ARM_AM::rrx)
807 // Encode the shift operation Rs or shift_imm (except rrx).
809 // Encode Rs bit[11:8].
810 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
811 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
814 // Encode shift_imm bit[11:7].
815 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
818 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
819 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
820 assert(SoImmVal != -1 && "Not a valid so_imm value!");
822 // Encode rotate_imm.
823 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
824 << ARMII::SoRotImmShift;
827 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
831 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
832 const TargetInstrDesc &TID) const {
833 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
834 const MachineOperand &MO = MI.getOperand(i-1);
835 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
836 return 1 << ARMII::S_BitShift;
841 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
843 unsigned ImplicitRn) {
844 const TargetInstrDesc &TID = MI.getDesc();
846 // Part of binary is determined by TableGn.
847 unsigned Binary = getBinaryCodeForInstr(MI);
849 // Set the conditional execution predicate
850 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
852 // Encode S bit if MI modifies CPSR.
853 Binary |= getAddrModeSBit(MI, TID);
855 // Encode register def if there is one.
856 unsigned NumDefs = TID.getNumDefs();
859 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
861 // Special handling for implicit use (e.g. PC).
862 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
864 if (TID.Opcode == ARM::MOVi16) {
865 // Get immediate from MI.
866 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
867 ARM::reloc_arm_movw);
868 // Encode imm which is the same as in emitMOVi32immInstruction().
869 Binary |= Lo16 & 0xFFF;
870 Binary |= ((Lo16 >> 12) & 0xF) << 16;
873 } else if(TID.Opcode == ARM::MOVTi16) {
874 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
875 ARM::reloc_arm_movt) >> 16);
876 Binary |= Hi16 & 0xFFF;
877 Binary |= ((Hi16 >> 12) & 0xF) << 16;
880 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
881 uint32_t v = ~MI.getOperand(2).getImm();
882 int32_t lsb = CountTrailingZeros_32(v);
883 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
884 // Instr{20-16} = msb, Instr{11-7} = lsb
885 Binary |= (msb & 0x1F) << 16;
886 Binary |= (lsb & 0x1F) << 7;
889 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
890 // Encode Rn in Instr{0-3}
891 Binary |= getMachineOpValue(MI, OpIdx++);
893 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
894 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
896 // Instr{20-16} = widthm1, Instr{11-7} = lsb
897 Binary |= (widthm1 & 0x1F) << 16;
898 Binary |= (lsb & 0x1F) << 7;
903 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
904 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
907 // Encode first non-shifter register operand if there is one.
908 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
911 // Special handling for implicit use (e.g. PC).
912 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
914 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
919 // Encode shifter operand.
920 const MachineOperand &MO = MI.getOperand(OpIdx);
921 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
923 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
928 // Encode register Rm.
929 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
934 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
939 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
941 unsigned ImplicitRn) {
942 const TargetInstrDesc &TID = MI.getDesc();
943 unsigned Form = TID.TSFlags & ARMII::FormMask;
944 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
946 // Part of binary is determined by TableGn.
947 unsigned Binary = getBinaryCodeForInstr(MI);
949 // Set the conditional execution predicate
950 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
954 // Operand 0 of a pre- and post-indexed store is the address base
955 // writeback. Skip it.
956 bool Skipped = false;
957 if (IsPrePost && Form == ARMII::StFrm) {
964 // Special handling for implicit use (e.g. PC).
965 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
967 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
969 // Set second operand
971 // Special handling for implicit use (e.g. PC).
972 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
974 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
976 // If this is a two-address operand, skip it. e.g. LDR_PRE.
977 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
980 const MachineOperand &MO2 = MI.getOperand(OpIdx);
981 unsigned AM2Opc = (ImplicitRn == ARM::PC)
982 ? 0 : MI.getOperand(OpIdx+1).getImm();
984 // Set bit U(23) according to sign of immed value (positive or negative).
985 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
987 if (!MO2.getReg()) { // is immediate
988 if (ARM_AM::getAM2Offset(AM2Opc))
989 // Set the value of offset_12 field
990 Binary |= ARM_AM::getAM2Offset(AM2Opc);
995 // Set bit I(25), because this is not in immediate enconding.
996 Binary |= 1 << ARMII::I_BitShift;
997 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
998 // Set bit[3:0] to the corresponding Rm register
999 Binary |= getARMRegisterNumbering(MO2.getReg());
1001 // If this instr is in scaled register offset/index instruction, set
1002 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1003 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1004 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1005 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1011 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1012 unsigned ImplicitRn) {
1013 const TargetInstrDesc &TID = MI.getDesc();
1014 unsigned Form = TID.TSFlags & ARMII::FormMask;
1015 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1017 // Part of binary is determined by TableGn.
1018 unsigned Binary = getBinaryCodeForInstr(MI);
1020 // Set the conditional execution predicate
1021 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1025 // Operand 0 of a pre- and post-indexed store is the address base
1026 // writeback. Skip it.
1027 bool Skipped = false;
1028 if (IsPrePost && Form == ARMII::StMiscFrm) {
1033 // Set first operand
1034 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1036 // Skip LDRD and STRD's second operand.
1037 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1040 // Set second operand
1042 // Special handling for implicit use (e.g. PC).
1043 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1045 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1047 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1048 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1051 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1052 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1053 ? 0 : MI.getOperand(OpIdx+1).getImm();
1055 // Set bit U(23) according to sign of immed value (positive or negative)
1056 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1059 // If this instr is in register offset/index encoding, set bit[3:0]
1060 // to the corresponding Rm register.
1062 Binary |= getARMRegisterNumbering(MO2.getReg());
1067 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1068 Binary |= 1 << ARMII::AM3_I_BitShift;
1069 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1071 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1072 Binary |= (ImmOffs & 0xF); // immedL
1078 static unsigned getAddrModeUPBits(unsigned Mode) {
1079 unsigned Binary = 0;
1081 // Set addressing mode by modifying bits U(23) and P(24)
1082 // IA - Increment after - bit U = 1 and bit P = 0
1083 // IB - Increment before - bit U = 1 and bit P = 1
1084 // DA - Decrement after - bit U = 0 and bit P = 0
1085 // DB - Decrement before - bit U = 0 and bit P = 1
1087 default: llvm_unreachable("Unknown addressing sub-mode!");
1088 case ARM_AM::da: break;
1089 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1090 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1091 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1097 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1098 const TargetInstrDesc &TID = MI.getDesc();
1099 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1101 // Part of binary is determined by TableGn.
1102 unsigned Binary = getBinaryCodeForInstr(MI);
1104 // Set the conditional execution predicate
1105 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1107 // Skip operand 0 of an instruction with base register update.
1112 // Set base address operand
1113 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1115 // Set addressing mode by modifying bits U(23) and P(24)
1116 const MachineOperand &MO = MI.getOperand(OpIdx++);
1117 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1121 Binary |= 0x1 << ARMII::W_BitShift;
1124 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1125 const MachineOperand &MO = MI.getOperand(i);
1126 if (!MO.isReg() || MO.isImplicit())
1128 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1129 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1131 Binary |= 0x1 << RegNum;
1137 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1138 const TargetInstrDesc &TID = MI.getDesc();
1140 // Part of binary is determined by TableGn.
1141 unsigned Binary = getBinaryCodeForInstr(MI);
1143 // Set the conditional execution predicate
1144 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1146 // Encode S bit if MI modifies CPSR.
1147 Binary |= getAddrModeSBit(MI, TID);
1149 // 32x32->64bit operations have two destination registers. The number
1150 // of register definitions will tell us if that's what we're dealing with.
1152 if (TID.getNumDefs() == 2)
1153 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1156 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1159 Binary |= getMachineOpValue(MI, OpIdx++);
1162 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1164 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1165 // it as Rn (for multiply, that's in the same offset as RdLo.
1166 if (TID.getNumOperands() > OpIdx &&
1167 !TID.OpInfo[OpIdx].isPredicate() &&
1168 !TID.OpInfo[OpIdx].isOptionalDef())
1169 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1174 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1175 const TargetInstrDesc &TID = MI.getDesc();
1177 // Part of binary is determined by TableGn.
1178 unsigned Binary = getBinaryCodeForInstr(MI);
1180 // Set the conditional execution predicate
1181 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1186 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1188 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1189 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1191 // Two register operand form.
1193 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1196 Binary |= getMachineOpValue(MI, MO2);
1199 Binary |= getMachineOpValue(MI, MO1);
1202 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1203 if (MI.getOperand(OpIdx).isImm() &&
1204 !TID.OpInfo[OpIdx].isPredicate() &&
1205 !TID.OpInfo[OpIdx].isOptionalDef())
1206 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1211 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1212 const TargetInstrDesc &TID = MI.getDesc();
1214 // Part of binary is determined by TableGn.
1215 unsigned Binary = getBinaryCodeForInstr(MI);
1217 // Set the conditional execution predicate
1218 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1223 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1225 const MachineOperand &MO = MI.getOperand(OpIdx++);
1226 if (OpIdx == TID.getNumOperands() ||
1227 TID.OpInfo[OpIdx].isPredicate() ||
1228 TID.OpInfo[OpIdx].isOptionalDef()) {
1229 // Encode Rm and it's done.
1230 Binary |= getMachineOpValue(MI, MO);
1236 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1239 Binary |= getMachineOpValue(MI, OpIdx++);
1241 // Encode shift_imm.
1242 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1243 if (TID.Opcode == ARM::PKHTB) {
1244 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1248 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1249 Binary |= ShiftAmt << ARMII::ShiftShift;
1254 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1255 const TargetInstrDesc &TID = MI.getDesc();
1257 // Part of binary is determined by TableGen.
1258 unsigned Binary = getBinaryCodeForInstr(MI);
1260 // Set the conditional execution predicate
1261 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1264 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1266 // Encode saturate bit position.
1267 unsigned Pos = MI.getOperand(1).getImm();
1268 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1270 assert((Pos < 16 || (Pos < 32 &&
1271 TID.Opcode != ARM::SSAT16 &&
1272 TID.Opcode != ARM::USAT16)) &&
1273 "saturate bit position out of range");
1274 Binary |= Pos << 16;
1277 Binary |= getMachineOpValue(MI, 2);
1279 // Encode shift_imm.
1280 if (TID.getNumOperands() == 4) {
1281 unsigned ShiftOp = MI.getOperand(3).getImm();
1282 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1283 if (Opc == ARM_AM::asr)
1285 unsigned ShiftAmt = MI.getOperand(3).getImm();
1286 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1288 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1289 Binary |= ShiftAmt << ARMII::ShiftShift;
1295 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1296 const TargetInstrDesc &TID = MI.getDesc();
1298 if (TID.Opcode == ARM::TPsoft) {
1299 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1302 // Part of binary is determined by TableGn.
1303 unsigned Binary = getBinaryCodeForInstr(MI);
1305 // Set the conditional execution predicate
1306 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1308 // Set signed_immed_24 field
1309 Binary |= getMachineOpValue(MI, 0);
1314 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1315 // Remember the base address of the inline jump table.
1316 uintptr_t JTBase = MCE.getCurrentPCValue();
1317 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1318 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1321 // Now emit the jump table entries.
1322 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1323 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1325 // DestBB address - JT base.
1326 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1328 // Absolute DestBB address.
1329 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1334 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1335 const TargetInstrDesc &TID = MI.getDesc();
1337 // Handle jump tables.
1338 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1339 // First emit a ldr pc, [] instruction.
1340 emitDataProcessingInstruction(MI, ARM::PC);
1342 // Then emit the inline jump table.
1344 (TID.Opcode == ARM::BR_JTr)
1345 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1346 emitInlineJumpTable(JTIndex);
1348 } else if (TID.Opcode == ARM::BR_JTm) {
1349 // First emit a ldr pc, [] instruction.
1350 emitLoadStoreInstruction(MI, ARM::PC);
1352 // Then emit the inline jump table.
1353 emitInlineJumpTable(MI.getOperand(3).getIndex());
1357 // Part of binary is determined by TableGn.
1358 unsigned Binary = getBinaryCodeForInstr(MI);
1360 // Set the conditional execution predicate
1361 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1363 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1364 // The return register is LR.
1365 Binary |= getARMRegisterNumbering(ARM::LR);
1367 // otherwise, set the return register
1368 Binary |= getMachineOpValue(MI, 0);
1373 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1374 unsigned RegD = MI.getOperand(OpIdx).getReg();
1375 unsigned Binary = 0;
1376 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1377 RegD = getARMRegisterNumbering(RegD);
1379 Binary |= RegD << ARMII::RegRdShift;
1381 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1382 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1387 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1388 unsigned RegN = MI.getOperand(OpIdx).getReg();
1389 unsigned Binary = 0;
1390 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1391 RegN = getARMRegisterNumbering(RegN);
1393 Binary |= RegN << ARMII::RegRnShift;
1395 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1396 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1401 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1402 unsigned RegM = MI.getOperand(OpIdx).getReg();
1403 unsigned Binary = 0;
1404 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1405 RegM = getARMRegisterNumbering(RegM);
1409 Binary |= ((RegM & 0x1E) >> 1);
1410 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1415 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1416 const TargetInstrDesc &TID = MI.getDesc();
1418 // Part of binary is determined by TableGn.
1419 unsigned Binary = getBinaryCodeForInstr(MI);
1421 // Set the conditional execution predicate
1422 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1425 assert((Binary & ARMII::D_BitShift) == 0 &&
1426 (Binary & ARMII::N_BitShift) == 0 &&
1427 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1430 Binary |= encodeVFPRd(MI, OpIdx++);
1432 // If this is a two-address operand, skip it, e.g. FMACD.
1433 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1437 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1438 Binary |= encodeVFPRn(MI, OpIdx++);
1440 if (OpIdx == TID.getNumOperands() ||
1441 TID.OpInfo[OpIdx].isPredicate() ||
1442 TID.OpInfo[OpIdx].isOptionalDef()) {
1443 // FCMPEZD etc. has only one operand.
1449 Binary |= encodeVFPRm(MI, OpIdx);
1454 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1455 const TargetInstrDesc &TID = MI.getDesc();
1456 unsigned Form = TID.TSFlags & ARMII::FormMask;
1458 // Part of binary is determined by TableGn.
1459 unsigned Binary = getBinaryCodeForInstr(MI);
1461 // Set the conditional execution predicate
1462 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1466 case ARMII::VFPConv1Frm:
1467 case ARMII::VFPConv2Frm:
1468 case ARMII::VFPConv3Frm:
1470 Binary |= encodeVFPRd(MI, 0);
1472 case ARMII::VFPConv4Frm:
1474 Binary |= encodeVFPRn(MI, 0);
1476 case ARMII::VFPConv5Frm:
1478 Binary |= encodeVFPRm(MI, 0);
1484 case ARMII::VFPConv1Frm:
1486 Binary |= encodeVFPRm(MI, 1);
1488 case ARMII::VFPConv2Frm:
1489 case ARMII::VFPConv3Frm:
1491 Binary |= encodeVFPRn(MI, 1);
1493 case ARMII::VFPConv4Frm:
1494 case ARMII::VFPConv5Frm:
1496 Binary |= encodeVFPRd(MI, 1);
1500 if (Form == ARMII::VFPConv5Frm)
1502 Binary |= encodeVFPRn(MI, 2);
1503 else if (Form == ARMII::VFPConv3Frm)
1505 Binary |= encodeVFPRm(MI, 2);
1510 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1511 // Part of binary is determined by TableGn.
1512 unsigned Binary = getBinaryCodeForInstr(MI);
1514 // Set the conditional execution predicate
1515 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1520 Binary |= encodeVFPRd(MI, OpIdx++);
1522 // Encode address base.
1523 const MachineOperand &Base = MI.getOperand(OpIdx++);
1524 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1526 // If there is a non-zero immediate offset, encode it.
1528 const MachineOperand &Offset = MI.getOperand(OpIdx);
1529 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1530 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1531 Binary |= 1 << ARMII::U_BitShift;
1538 // If immediate offset is omitted, default to +0.
1539 Binary |= 1 << ARMII::U_BitShift;
1545 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1546 const TargetInstrDesc &TID = MI.getDesc();
1547 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1549 // Part of binary is determined by TableGn.
1550 unsigned Binary = getBinaryCodeForInstr(MI);
1552 // Set the conditional execution predicate
1553 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1555 // Skip operand 0 of an instruction with base register update.
1560 // Set base address operand
1561 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1563 // Set addressing mode by modifying bits U(23) and P(24)
1564 const MachineOperand &MO = MI.getOperand(OpIdx++);
1565 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1569 Binary |= 0x1 << ARMII::W_BitShift;
1571 // First register is encoded in Dd.
1572 Binary |= encodeVFPRd(MI, OpIdx+2);
1574 // Count the number of registers.
1575 unsigned NumRegs = 1;
1576 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1577 const MachineOperand &MO = MI.getOperand(i);
1578 if (!MO.isReg() || MO.isImplicit())
1582 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1583 // Otherwise, it will be 0, in the case of 32-bit registers.
1585 Binary |= NumRegs * 2;
1592 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1593 unsigned Opcode = MI.getDesc().Opcode;
1594 // Part of binary is determined by TableGn.
1595 unsigned Binary = getBinaryCodeForInstr(MI);
1597 // Set the conditional execution predicate
1598 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1602 llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1605 case ARM::FCONSTS: {
1607 Binary |= encodeVFPRd(MI, 0);
1609 // Encode imm., Table A7-18 VFP modified immediate constants
1610 const MachineOperand &MO1 = MI.getOperand(1);
1611 unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1612 .bitcastToAPInt().getHiBits(32).getLimitedValue());
1613 unsigned ModifiedImm;
1615 if(Opcode == ARM::FCONSTS)
1616 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1617 (Imm & 0x03F80000) >> 19; // bcdefgh
1618 else // Opcode == ARM::FCONSTD
1619 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1620 (Imm & 0x007F0000) >> 16; // bcdefgh
1622 // Insts{19-16} = abcd, Insts{3-0} = efgh
1623 Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1624 Binary |= (ModifiedImm & 0xF);
1632 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1633 unsigned RegD = MI.getOperand(OpIdx).getReg();
1634 unsigned Binary = 0;
1635 RegD = getARMRegisterNumbering(RegD);
1636 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1637 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1641 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1642 unsigned RegN = MI.getOperand(OpIdx).getReg();
1643 unsigned Binary = 0;
1644 RegN = getARMRegisterNumbering(RegN);
1645 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1646 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1650 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1651 unsigned RegM = MI.getOperand(OpIdx).getReg();
1652 unsigned Binary = 0;
1653 RegM = getARMRegisterNumbering(RegM);
1654 Binary |= (RegM & 0xf);
1655 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1659 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1660 /// data-processing instruction to the corresponding Thumb encoding.
1661 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1662 assert((Binary & 0xfe000000) == 0xf2000000 &&
1663 "not an ARM NEON data-processing instruction");
1664 unsigned UBit = (Binary >> 24) & 1;
1665 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1668 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1669 unsigned Binary = getBinaryCodeForInstr(MI);
1671 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1672 const TargetInstrDesc &TID = MI.getDesc();
1673 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1677 } else { // ARMII::NSetLnFrm
1683 // Set the conditional execution predicate
1684 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1686 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1687 RegT = getARMRegisterNumbering(RegT);
1688 Binary |= (RegT << ARMII::RegRdShift);
1689 Binary |= encodeNEONRn(MI, RegNOpIdx);
1692 if ((Binary & (1 << 22)) != 0)
1693 LaneShift = 0; // 8-bit elements
1694 else if ((Binary & (1 << 5)) != 0)
1695 LaneShift = 1; // 16-bit elements
1697 LaneShift = 2; // 32-bit elements
1699 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1700 unsigned Opc1 = Lane >> 2;
1701 unsigned Opc2 = Lane & 3;
1702 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1703 Binary |= (Opc1 << 21);
1704 Binary |= (Opc2 << 5);
1709 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1710 unsigned Binary = getBinaryCodeForInstr(MI);
1712 // Set the conditional execution predicate
1713 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1715 unsigned RegT = MI.getOperand(1).getReg();
1716 RegT = getARMRegisterNumbering(RegT);
1717 Binary |= (RegT << ARMII::RegRdShift);
1718 Binary |= encodeNEONRn(MI, 0);
1722 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1723 unsigned Binary = getBinaryCodeForInstr(MI);
1724 // Destination register is encoded in Dd.
1725 Binary |= encodeNEONRd(MI, 0);
1726 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1727 unsigned Imm = MI.getOperand(1).getImm();
1728 unsigned Op = (Imm >> 12) & 1;
1729 unsigned Cmode = (Imm >> 8) & 0xf;
1730 unsigned I = (Imm >> 7) & 1;
1731 unsigned Imm3 = (Imm >> 4) & 0x7;
1732 unsigned Imm4 = Imm & 0xf;
1733 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1735 Binary = convertNEONDataProcToThumb(Binary);
1739 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1740 const TargetInstrDesc &TID = MI.getDesc();
1741 unsigned Binary = getBinaryCodeForInstr(MI);
1742 // Destination register is encoded in Dd; source register in Dm.
1744 Binary |= encodeNEONRd(MI, OpIdx++);
1745 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1747 Binary |= encodeNEONRm(MI, OpIdx);
1749 Binary = convertNEONDataProcToThumb(Binary);
1750 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1754 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1755 const TargetInstrDesc &TID = MI.getDesc();
1756 unsigned Binary = getBinaryCodeForInstr(MI);
1757 // Destination register is encoded in Dd; source registers in Dn and Dm.
1759 Binary |= encodeNEONRd(MI, OpIdx++);
1760 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1762 Binary |= encodeNEONRn(MI, OpIdx++);
1763 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1765 Binary |= encodeNEONRm(MI, OpIdx);
1767 Binary = convertNEONDataProcToThumb(Binary);
1768 // FIXME: This does not handle VMOVDneon or VMOVQ.
1772 #include "ARMGenCodeEmitter.inc"