1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/JITCodeEmitter.h"
29 #include "llvm/CodeGen/ObjectCodeEmitter.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
45 STATISTIC(NumEmitted, "Number of machine instructions emitted");
49 class ARMCodeEmitter {
51 /// getBinaryCodeForInstr - This function, generated by the
52 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
53 /// machine instructions.
54 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
57 template<class CodeEmitter>
58 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
59 public ARMCodeEmitter {
61 const ARMInstrInfo *II;
63 const ARMSubtarget *Subtarget;
66 const std::vector<MachineConstantPoolEntry> *MCPEs;
67 const std::vector<MachineJumpTableEntry> *MJTEs;
72 explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
73 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
74 MCE(mce), MCPEs(0), MJTEs(0),
75 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
76 Emitter(TargetMachine &tm, CodeEmitter &mce,
77 const ARMInstrInfo &ii, const TargetData &td)
78 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
79 MCE(mce), MCPEs(0), MJTEs(0),
80 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
82 bool runOnMachineFunction(MachineFunction &MF);
84 virtual const char *getPassName() const {
85 return "ARM Machine Code Emitter";
88 void emitInstruction(const MachineInstr &MI);
92 void emitWordLE(unsigned Binary);
94 void emitDWordLE(uint64_t Binary);
96 void emitConstPoolInstruction(const MachineInstr &MI);
98 void emitMOVi2piecesInstruction(const MachineInstr &MI);
100 void emitLEApcrelJTInstruction(const MachineInstr &MI);
102 void emitPseudoMoveInstruction(const MachineInstr &MI);
104 void addPCLabel(unsigned LabelID);
106 void emitPseudoInstruction(const MachineInstr &MI);
108 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
109 const TargetInstrDesc &TID,
110 const MachineOperand &MO,
113 unsigned getMachineSoImmOpValue(unsigned SoImm);
115 unsigned getAddrModeSBit(const MachineInstr &MI,
116 const TargetInstrDesc &TID) const;
118 void emitDataProcessingInstruction(const MachineInstr &MI,
119 unsigned ImplicitRd = 0,
120 unsigned ImplicitRn = 0);
122 void emitLoadStoreInstruction(const MachineInstr &MI,
123 unsigned ImplicitRd = 0,
124 unsigned ImplicitRn = 0);
126 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
127 unsigned ImplicitRn = 0);
129 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
131 void emitMulFrmInstruction(const MachineInstr &MI);
133 void emitExtendInstruction(const MachineInstr &MI);
135 void emitMiscArithInstruction(const MachineInstr &MI);
137 void emitBranchInstruction(const MachineInstr &MI);
139 void emitInlineJumpTable(unsigned JTIndex);
141 void emitMiscBranchInstruction(const MachineInstr &MI);
143 void emitVFPArithInstruction(const MachineInstr &MI);
145 void emitVFPConversionInstruction(const MachineInstr &MI);
147 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
149 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
151 void emitMiscInstruction(const MachineInstr &MI);
153 /// getMachineOpValue - Return binary encoding of operand. If the machine
154 /// operand requires relocation, record the relocation and return zero.
155 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
157 return getMachineOpValue(MI, MI.getOperand(OpIdx));
160 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
162 unsigned getShiftOp(unsigned Imm) const ;
164 /// Routines that handle operands which add machine relocations which are
165 /// fixed up by the relocation stage.
166 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
167 bool NeedStub, bool Indirect, intptr_t ACPV = 0);
168 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
169 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
170 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
171 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
172 intptr_t JTBase = 0);
174 template <class CodeEmitter>
175 char Emitter<CodeEmitter>::ID = 0;
178 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
179 /// to the specified MCE object.
181 FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
182 MachineCodeEmitter &MCE) {
183 return new Emitter<MachineCodeEmitter>(TM, MCE);
185 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
186 JITCodeEmitter &JCE) {
187 return new Emitter<JITCodeEmitter>(TM, JCE);
189 FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
190 ObjectCodeEmitter &OCE) {
191 return new Emitter<ObjectCodeEmitter>(TM, OCE);
194 template<class CodeEmitter>
195 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
196 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
197 MF.getTarget().getRelocationModel() != Reloc::Static) &&
198 "JIT relocation model must be set to static or default!");
199 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
200 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
201 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
202 Subtarget = &TM.getSubtarget<ARMSubtarget>();
203 MCPEs = &MF.getConstantPool()->getConstants();
204 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
205 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
206 JTI->Initialize(MF, IsPIC);
209 DEBUG(errs() << "JITTing function '"
210 << MF.getFunction()->getName() << "'\n");
211 MCE.startFunction(MF);
212 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
214 MCE.StartMachineBasicBlock(MBB);
215 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
219 } while (MCE.finishFunction(MF));
224 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
226 template<class CodeEmitter>
227 unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
228 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
229 default: llvm_unreachable("Unknown shift opc!");
230 case ARM_AM::asr: return 2;
231 case ARM_AM::lsl: return 0;
232 case ARM_AM::lsr: return 1;
234 case ARM_AM::rrx: return 3;
239 /// getMachineOpValue - Return binary encoding of operand. If the machine
240 /// operand requires relocation, record the relocation and return zero.
241 template<class CodeEmitter>
242 unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
243 const MachineOperand &MO) {
245 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
247 return static_cast<unsigned>(MO.getImm());
248 else if (MO.isGlobal())
249 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
250 else if (MO.isSymbol())
251 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
252 else if (MO.isCPI()) {
253 const TargetInstrDesc &TID = MI.getDesc();
254 // For VFP load, the immediate offset is multiplied by 4.
255 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
256 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
257 emitConstPoolAddress(MO.getIndex(), Reloc);
258 } else if (MO.isJTI())
259 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
261 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
271 /// emitGlobalAddress - Emit the specified address to the code stream.
273 template<class CodeEmitter>
274 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
275 bool NeedStub, bool Indirect,
277 MachineRelocation MR = Indirect
278 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
280 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
282 MCE.addRelocation(MR);
285 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
286 /// be emitted to the current location in the function, and allow it to be PC
288 template<class CodeEmitter>
289 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
291 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
295 /// emitConstPoolAddress - Arrange for the address of an constant pool
296 /// to be emitted to the current location in the function, and allow it to be PC
298 template<class CodeEmitter>
299 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
301 // Tell JIT emitter we'll resolve the address.
302 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
303 Reloc, CPI, 0, true));
306 /// emitJumpTableAddress - Arrange for the address of a jump table to
307 /// be emitted to the current location in the function, and allow it to be PC
309 template<class CodeEmitter>
310 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
312 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
313 Reloc, JTIndex, 0, true));
316 /// emitMachineBasicBlock - Emit the specified address basic block.
317 template<class CodeEmitter>
318 void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
319 unsigned Reloc, intptr_t JTBase) {
320 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
324 template<class CodeEmitter>
325 void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
326 DEBUG(errs() << " 0x";
327 errs().write_hex(Binary) << "\n");
328 MCE.emitWordLE(Binary);
331 template<class CodeEmitter>
332 void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
333 DEBUG(errs() << " 0x";
334 errs().write_hex(Binary) << "\n");
335 MCE.emitDWordLE(Binary);
338 template<class CodeEmitter>
339 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
340 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
342 MCE.processDebugLoc(MI.getDebugLoc());
344 NumEmitted++; // Keep track of the # of mi's emitted
345 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
347 llvm_unreachable("Unhandled instruction encoding format!");
351 emitPseudoInstruction(MI);
354 case ARMII::DPSoRegFrm:
355 emitDataProcessingInstruction(MI);
359 emitLoadStoreInstruction(MI);
361 case ARMII::LdMiscFrm:
362 case ARMII::StMiscFrm:
363 emitMiscLoadStoreInstruction(MI);
365 case ARMII::LdStMulFrm:
366 emitLoadStoreMultipleInstruction(MI);
369 emitMulFrmInstruction(MI);
372 emitExtendInstruction(MI);
374 case ARMII::ArithMiscFrm:
375 emitMiscArithInstruction(MI);
378 emitBranchInstruction(MI);
380 case ARMII::BrMiscFrm:
381 emitMiscBranchInstruction(MI);
384 case ARMII::VFPUnaryFrm:
385 case ARMII::VFPBinaryFrm:
386 emitVFPArithInstruction(MI);
388 case ARMII::VFPConv1Frm:
389 case ARMII::VFPConv2Frm:
390 case ARMII::VFPConv3Frm:
391 case ARMII::VFPConv4Frm:
392 case ARMII::VFPConv5Frm:
393 emitVFPConversionInstruction(MI);
395 case ARMII::VFPLdStFrm:
396 emitVFPLoadStoreInstruction(MI);
398 case ARMII::VFPLdStMulFrm:
399 emitVFPLoadStoreMultipleInstruction(MI);
401 case ARMII::VFPMiscFrm:
402 emitMiscInstruction(MI);
407 template<class CodeEmitter>
408 void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
409 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
410 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
411 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
413 // Remember the CONSTPOOL_ENTRY address for later relocation.
414 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
416 // Emit constpool island entry. In most cases, the actual values will be
417 // resolved and relocated after code emission.
418 if (MCPE.isMachineConstantPoolEntry()) {
419 ARMConstantPoolValue *ACPV =
420 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
422 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
423 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
425 GlobalValue *GV = ACPV->getGV();
427 Reloc::Model RelocM = TM.getRelocationModel();
428 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
430 Subtarget->GVIsIndirectSymbol(GV, RelocM),
433 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
437 Constant *CV = MCPE.Val.ConstVal;
440 errs() << " ** Constant pool #" << CPI << " @ "
441 << (void*)MCE.getCurrentPCValue() << " ";
442 if (const Function *F = dyn_cast<Function>(CV))
443 errs() << F->getName();
449 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
450 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
452 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
453 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
455 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
456 if (CFP->getType() == Type::getFloatTy(CFP->getContext()))
457 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
458 else if (CFP->getType() == Type::getDoubleTy(CFP->getContext()))
459 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
461 llvm_unreachable("Unable to handle this constantpool entry!");
464 llvm_unreachable("Unable to handle this constantpool entry!");
469 template<class CodeEmitter>
470 void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
471 const MachineOperand &MO0 = MI.getOperand(0);
472 const MachineOperand &MO1 = MI.getOperand(1);
473 assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 &&
474 "Not a valid so_imm value!");
475 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
476 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
478 // Emit the 'mov' instruction.
479 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
481 // Set the conditional execution predicate.
482 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
485 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
488 // Set bit I(25) to identify this is the immediate form of <shifter_op>
489 Binary |= 1 << ARMII::I_BitShift;
490 Binary |= getMachineSoImmOpValue(V1);
493 // Now the 'orr' instruction.
494 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
496 // Set the conditional execution predicate.
497 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
500 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
503 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
506 // Set bit I(25) to identify this is the immediate form of <shifter_op>
507 Binary |= 1 << ARMII::I_BitShift;
508 Binary |= getMachineSoImmOpValue(V2);
512 template<class CodeEmitter>
513 void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
514 // It's basically add r, pc, (LJTI - $+8)
516 const TargetInstrDesc &TID = MI.getDesc();
518 // Emit the 'add' instruction.
519 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
521 // Set the conditional execution predicate
522 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
524 // Encode S bit if MI modifies CPSR.
525 Binary |= getAddrModeSBit(MI, TID);
528 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
530 // Encode Rn which is PC.
531 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
533 // Encode the displacement.
534 Binary |= 1 << ARMII::I_BitShift;
535 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
540 template<class CodeEmitter>
541 void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
542 unsigned Opcode = MI.getDesc().Opcode;
544 // Part of binary is determined by TableGn.
545 unsigned Binary = getBinaryCodeForInstr(MI);
547 // Set the conditional execution predicate
548 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
550 // Encode S bit if MI modifies CPSR.
551 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
552 Binary |= 1 << ARMII::S_BitShift;
554 // Encode register def if there is one.
555 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
557 // Encode the shift operation.
564 case ARM::MOVsrl_flag:
566 Binary |= (0x2 << 4) | (1 << 7);
568 case ARM::MOVsra_flag:
570 Binary |= (0x4 << 4) | (1 << 7);
574 // Encode register Rm.
575 Binary |= getMachineOpValue(MI, 1);
580 template<class CodeEmitter>
581 void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
582 DEBUG(errs() << " ** LPC" << LabelID << " @ "
583 << (void*)MCE.getCurrentPCValue() << '\n');
584 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
587 template<class CodeEmitter>
588 void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
589 unsigned Opcode = MI.getDesc().Opcode;
592 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
593 case TargetInstrInfo::INLINEASM: {
594 // We allow inline assembler nodes with empty bodies - they can
595 // implicitly define registers, which is ok for JIT.
596 if (MI.getOperand(0).getSymbolName()[0]) {
597 llvm_report_error("JIT does not support inline asm!");
601 case TargetInstrInfo::DBG_LABEL:
602 case TargetInstrInfo::EH_LABEL:
603 MCE.emitLabel(MI.getOperand(0).getImm());
605 case TargetInstrInfo::IMPLICIT_DEF:
609 case ARM::CONSTPOOL_ENTRY:
610 emitConstPoolInstruction(MI);
613 // Remember of the address of the PC label for relocation later.
614 addPCLabel(MI.getOperand(2).getImm());
615 // PICADD is just an add instruction that implicitly read pc.
616 emitDataProcessingInstruction(MI, 0, ARM::PC);
623 // Remember of the address of the PC label for relocation later.
624 addPCLabel(MI.getOperand(2).getImm());
625 // These are just load / store instructions that implicitly read pc.
626 emitLoadStoreInstruction(MI, 0, ARM::PC);
633 // Remember of the address of the PC label for relocation later.
634 addPCLabel(MI.getOperand(2).getImm());
635 // These are just load / store instructions that implicitly read pc.
636 emitMiscLoadStoreInstruction(MI, ARM::PC);
639 case ARM::MOVi2pieces:
640 // Two instructions to materialize a constant.
641 emitMOVi2piecesInstruction(MI);
643 case ARM::LEApcrelJT:
644 // Materialize jumptable address.
645 emitLEApcrelJTInstruction(MI);
648 case ARM::MOVsrl_flag:
649 case ARM::MOVsra_flag:
650 emitPseudoMoveInstruction(MI);
655 template<class CodeEmitter>
656 unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
657 const MachineInstr &MI,
658 const TargetInstrDesc &TID,
659 const MachineOperand &MO,
661 unsigned Binary = getMachineOpValue(MI, MO);
663 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
664 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
665 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
667 // Encode the shift opcode.
669 unsigned Rs = MO1.getReg();
671 // Set shift operand (bit[7:4]).
676 // RRX - 0110 and bit[11:8] clear.
678 default: llvm_unreachable("Unknown shift opc!");
679 case ARM_AM::lsl: SBits = 0x1; break;
680 case ARM_AM::lsr: SBits = 0x3; break;
681 case ARM_AM::asr: SBits = 0x5; break;
682 case ARM_AM::ror: SBits = 0x7; break;
683 case ARM_AM::rrx: SBits = 0x6; break;
686 // Set shift operand (bit[6:4]).
692 default: llvm_unreachable("Unknown shift opc!");
693 case ARM_AM::lsl: SBits = 0x0; break;
694 case ARM_AM::lsr: SBits = 0x2; break;
695 case ARM_AM::asr: SBits = 0x4; break;
696 case ARM_AM::ror: SBits = 0x6; break;
699 Binary |= SBits << 4;
700 if (SOpc == ARM_AM::rrx)
703 // Encode the shift operation Rs or shift_imm (except rrx).
705 // Encode Rs bit[11:8].
706 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
708 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
711 // Encode shift_imm bit[11:7].
712 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
715 template<class CodeEmitter>
716 unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
717 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
718 assert(SoImmVal != -1 && "Not a valid so_imm value!");
720 // Encode rotate_imm.
721 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
722 << ARMII::SoRotImmShift;
725 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
729 template<class CodeEmitter>
730 unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
731 const TargetInstrDesc &TID) const {
732 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
733 const MachineOperand &MO = MI.getOperand(i-1);
734 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
735 return 1 << ARMII::S_BitShift;
740 template<class CodeEmitter>
741 void Emitter<CodeEmitter>::emitDataProcessingInstruction(
742 const MachineInstr &MI,
744 unsigned ImplicitRn) {
745 const TargetInstrDesc &TID = MI.getDesc();
747 if (TID.Opcode == ARM::BFC) {
748 llvm_report_error("ARMv6t2 JIT is not yet supported.");
751 // Part of binary is determined by TableGn.
752 unsigned Binary = getBinaryCodeForInstr(MI);
754 // Set the conditional execution predicate
755 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
757 // Encode S bit if MI modifies CPSR.
758 Binary |= getAddrModeSBit(MI, TID);
760 // Encode register def if there is one.
761 unsigned NumDefs = TID.getNumDefs();
764 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
766 // Special handling for implicit use (e.g. PC).
767 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
768 << ARMII::RegRdShift);
770 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
771 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
774 // Encode first non-shifter register operand if there is one.
775 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
778 // Special handling for implicit use (e.g. PC).
779 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
780 << ARMII::RegRnShift);
782 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
787 // Encode shifter operand.
788 const MachineOperand &MO = MI.getOperand(OpIdx);
789 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
791 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
796 // Encode register Rm.
797 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
802 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
807 template<class CodeEmitter>
808 void Emitter<CodeEmitter>::emitLoadStoreInstruction(
809 const MachineInstr &MI,
811 unsigned ImplicitRn) {
812 const TargetInstrDesc &TID = MI.getDesc();
813 unsigned Form = TID.TSFlags & ARMII::FormMask;
814 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
816 // Part of binary is determined by TableGn.
817 unsigned Binary = getBinaryCodeForInstr(MI);
819 // Set the conditional execution predicate
820 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
824 // Operand 0 of a pre- and post-indexed store is the address base
825 // writeback. Skip it.
826 bool Skipped = false;
827 if (IsPrePost && Form == ARMII::StFrm) {
834 // Special handling for implicit use (e.g. PC).
835 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
836 << ARMII::RegRdShift);
838 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
840 // Set second operand
842 // Special handling for implicit use (e.g. PC).
843 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
844 << ARMII::RegRnShift);
846 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
848 // If this is a two-address operand, skip it. e.g. LDR_PRE.
849 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
852 const MachineOperand &MO2 = MI.getOperand(OpIdx);
853 unsigned AM2Opc = (ImplicitRn == ARM::PC)
854 ? 0 : MI.getOperand(OpIdx+1).getImm();
856 // Set bit U(23) according to sign of immed value (positive or negative).
857 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
859 if (!MO2.getReg()) { // is immediate
860 if (ARM_AM::getAM2Offset(AM2Opc))
861 // Set the value of offset_12 field
862 Binary |= ARM_AM::getAM2Offset(AM2Opc);
867 // Set bit I(25), because this is not in immediate enconding.
868 Binary |= 1 << ARMII::I_BitShift;
869 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
870 // Set bit[3:0] to the corresponding Rm register
871 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
873 // If this instr is in scaled register offset/index instruction, set
874 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
875 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
876 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
877 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
883 template<class CodeEmitter>
884 void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
885 unsigned ImplicitRn) {
886 const TargetInstrDesc &TID = MI.getDesc();
887 unsigned Form = TID.TSFlags & ARMII::FormMask;
888 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
890 // Part of binary is determined by TableGn.
891 unsigned Binary = getBinaryCodeForInstr(MI);
893 // Set the conditional execution predicate
894 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
898 // Operand 0 of a pre- and post-indexed store is the address base
899 // writeback. Skip it.
900 bool Skipped = false;
901 if (IsPrePost && Form == ARMII::StMiscFrm) {
907 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
909 // Skip LDRD and STRD's second operand.
910 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
913 // Set second operand
915 // Special handling for implicit use (e.g. PC).
916 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
917 << ARMII::RegRnShift);
919 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
921 // If this is a two-address operand, skip it. e.g. LDRH_POST.
922 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
925 const MachineOperand &MO2 = MI.getOperand(OpIdx);
926 unsigned AM3Opc = (ImplicitRn == ARM::PC)
927 ? 0 : MI.getOperand(OpIdx+1).getImm();
929 // Set bit U(23) according to sign of immed value (positive or negative)
930 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
933 // If this instr is in register offset/index encoding, set bit[3:0]
934 // to the corresponding Rm register.
936 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
941 // This instr is in immediate offset/index encoding, set bit 22 to 1.
942 Binary |= 1 << ARMII::AM3_I_BitShift;
943 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
945 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
946 Binary |= (ImmOffs & 0xF); // immedL
952 static unsigned getAddrModeUPBits(unsigned Mode) {
955 // Set addressing mode by modifying bits U(23) and P(24)
956 // IA - Increment after - bit U = 1 and bit P = 0
957 // IB - Increment before - bit U = 1 and bit P = 1
958 // DA - Decrement after - bit U = 0 and bit P = 0
959 // DB - Decrement before - bit U = 0 and bit P = 1
961 default: llvm_unreachable("Unknown addressing sub-mode!");
962 case ARM_AM::da: break;
963 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
964 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
965 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
971 template<class CodeEmitter>
972 void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
973 const MachineInstr &MI) {
974 // Part of binary is determined by TableGn.
975 unsigned Binary = getBinaryCodeForInstr(MI);
977 // Set the conditional execution predicate
978 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
980 // Set base address operand
981 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
983 // Set addressing mode by modifying bits U(23) and P(24)
984 const MachineOperand &MO = MI.getOperand(1);
985 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
988 if (ARM_AM::getAM4WBFlag(MO.getImm()))
989 Binary |= 0x1 << ARMII::W_BitShift;
992 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
993 const MachineOperand &MO = MI.getOperand(i);
994 if (!MO.isReg() || MO.isImplicit())
996 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
997 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
999 Binary |= 0x1 << RegNum;
1005 template<class CodeEmitter>
1006 void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1007 const TargetInstrDesc &TID = MI.getDesc();
1009 // Part of binary is determined by TableGn.
1010 unsigned Binary = getBinaryCodeForInstr(MI);
1012 // Set the conditional execution predicate
1013 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1015 // Encode S bit if MI modifies CPSR.
1016 Binary |= getAddrModeSBit(MI, TID);
1018 // 32x32->64bit operations have two destination registers. The number
1019 // of register definitions will tell us if that's what we're dealing with.
1021 if (TID.getNumDefs() == 2)
1022 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1025 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1028 Binary |= getMachineOpValue(MI, OpIdx++);
1031 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1033 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1034 // it as Rn (for multiply, that's in the same offset as RdLo.
1035 if (TID.getNumOperands() > OpIdx &&
1036 !TID.OpInfo[OpIdx].isPredicate() &&
1037 !TID.OpInfo[OpIdx].isOptionalDef())
1038 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1043 template<class CodeEmitter>
1044 void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1045 const TargetInstrDesc &TID = MI.getDesc();
1047 // Part of binary is determined by TableGn.
1048 unsigned Binary = getBinaryCodeForInstr(MI);
1050 // Set the conditional execution predicate
1051 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1056 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1058 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1059 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1061 // Two register operand form.
1063 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1066 Binary |= getMachineOpValue(MI, MO2);
1069 Binary |= getMachineOpValue(MI, MO1);
1072 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1073 if (MI.getOperand(OpIdx).isImm() &&
1074 !TID.OpInfo[OpIdx].isPredicate() &&
1075 !TID.OpInfo[OpIdx].isOptionalDef())
1076 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1081 template<class CodeEmitter>
1082 void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1083 const TargetInstrDesc &TID = MI.getDesc();
1085 // Part of binary is determined by TableGn.
1086 unsigned Binary = getBinaryCodeForInstr(MI);
1088 // Set the conditional execution predicate
1089 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1094 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1096 const MachineOperand &MO = MI.getOperand(OpIdx++);
1097 if (OpIdx == TID.getNumOperands() ||
1098 TID.OpInfo[OpIdx].isPredicate() ||
1099 TID.OpInfo[OpIdx].isOptionalDef()) {
1100 // Encode Rm and it's done.
1101 Binary |= getMachineOpValue(MI, MO);
1107 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1110 Binary |= getMachineOpValue(MI, OpIdx++);
1112 // Encode shift_imm.
1113 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1114 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1115 Binary |= ShiftAmt << ARMII::ShiftShift;
1120 template<class CodeEmitter>
1121 void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1122 const TargetInstrDesc &TID = MI.getDesc();
1124 if (TID.Opcode == ARM::TPsoft) {
1125 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1128 // Part of binary is determined by TableGn.
1129 unsigned Binary = getBinaryCodeForInstr(MI);
1131 // Set the conditional execution predicate
1132 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1134 // Set signed_immed_24 field
1135 Binary |= getMachineOpValue(MI, 0);
1140 template<class CodeEmitter>
1141 void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1142 // Remember the base address of the inline jump table.
1143 uintptr_t JTBase = MCE.getCurrentPCValue();
1144 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1145 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1148 // Now emit the jump table entries.
1149 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1150 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1152 // DestBB address - JT base.
1153 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1155 // Absolute DestBB address.
1156 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1161 template<class CodeEmitter>
1162 void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1163 const TargetInstrDesc &TID = MI.getDesc();
1165 // Handle jump tables.
1166 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1167 // First emit a ldr pc, [] instruction.
1168 emitDataProcessingInstruction(MI, ARM::PC);
1170 // Then emit the inline jump table.
1172 (TID.Opcode == ARM::BR_JTr)
1173 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1174 emitInlineJumpTable(JTIndex);
1176 } else if (TID.Opcode == ARM::BR_JTm) {
1177 // First emit a ldr pc, [] instruction.
1178 emitLoadStoreInstruction(MI, ARM::PC);
1180 // Then emit the inline jump table.
1181 emitInlineJumpTable(MI.getOperand(3).getIndex());
1185 // Part of binary is determined by TableGn.
1186 unsigned Binary = getBinaryCodeForInstr(MI);
1188 // Set the conditional execution predicate
1189 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1191 if (TID.Opcode == ARM::BX_RET)
1192 // The return register is LR.
1193 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1195 // otherwise, set the return register
1196 Binary |= getMachineOpValue(MI, 0);
1201 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1202 unsigned RegD = MI.getOperand(OpIdx).getReg();
1203 unsigned Binary = 0;
1204 bool isSPVFP = false;
1205 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1207 Binary |= RegD << ARMII::RegRdShift;
1209 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1210 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1215 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1216 unsigned RegN = MI.getOperand(OpIdx).getReg();
1217 unsigned Binary = 0;
1218 bool isSPVFP = false;
1219 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1221 Binary |= RegN << ARMII::RegRnShift;
1223 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1224 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1229 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1230 unsigned RegM = MI.getOperand(OpIdx).getReg();
1231 unsigned Binary = 0;
1232 bool isSPVFP = false;
1233 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1237 Binary |= ((RegM & 0x1E) >> 1);
1238 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1243 template<class CodeEmitter>
1244 void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1245 const TargetInstrDesc &TID = MI.getDesc();
1247 // Part of binary is determined by TableGn.
1248 unsigned Binary = getBinaryCodeForInstr(MI);
1250 // Set the conditional execution predicate
1251 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1254 assert((Binary & ARMII::D_BitShift) == 0 &&
1255 (Binary & ARMII::N_BitShift) == 0 &&
1256 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1259 Binary |= encodeVFPRd(MI, OpIdx++);
1261 // If this is a two-address operand, skip it, e.g. FMACD.
1262 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1266 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1267 Binary |= encodeVFPRn(MI, OpIdx++);
1269 if (OpIdx == TID.getNumOperands() ||
1270 TID.OpInfo[OpIdx].isPredicate() ||
1271 TID.OpInfo[OpIdx].isOptionalDef()) {
1272 // FCMPEZD etc. has only one operand.
1278 Binary |= encodeVFPRm(MI, OpIdx);
1283 template<class CodeEmitter>
1284 void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1285 const MachineInstr &MI) {
1286 const TargetInstrDesc &TID = MI.getDesc();
1287 unsigned Form = TID.TSFlags & ARMII::FormMask;
1289 // Part of binary is determined by TableGn.
1290 unsigned Binary = getBinaryCodeForInstr(MI);
1292 // Set the conditional execution predicate
1293 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1297 case ARMII::VFPConv1Frm:
1298 case ARMII::VFPConv2Frm:
1299 case ARMII::VFPConv3Frm:
1301 Binary |= encodeVFPRd(MI, 0);
1303 case ARMII::VFPConv4Frm:
1305 Binary |= encodeVFPRn(MI, 0);
1307 case ARMII::VFPConv5Frm:
1309 Binary |= encodeVFPRm(MI, 0);
1315 case ARMII::VFPConv1Frm:
1317 Binary |= encodeVFPRm(MI, 1);
1319 case ARMII::VFPConv2Frm:
1320 case ARMII::VFPConv3Frm:
1322 Binary |= encodeVFPRn(MI, 1);
1324 case ARMII::VFPConv4Frm:
1325 case ARMII::VFPConv5Frm:
1327 Binary |= encodeVFPRd(MI, 1);
1331 if (Form == ARMII::VFPConv5Frm)
1333 Binary |= encodeVFPRn(MI, 2);
1334 else if (Form == ARMII::VFPConv3Frm)
1336 Binary |= encodeVFPRm(MI, 2);
1341 template<class CodeEmitter>
1342 void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1343 // Part of binary is determined by TableGn.
1344 unsigned Binary = getBinaryCodeForInstr(MI);
1346 // Set the conditional execution predicate
1347 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1352 Binary |= encodeVFPRd(MI, OpIdx++);
1354 // Encode address base.
1355 const MachineOperand &Base = MI.getOperand(OpIdx++);
1356 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1358 // If there is a non-zero immediate offset, encode it.
1360 const MachineOperand &Offset = MI.getOperand(OpIdx);
1361 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1362 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1363 Binary |= 1 << ARMII::U_BitShift;
1370 // If immediate offset is omitted, default to +0.
1371 Binary |= 1 << ARMII::U_BitShift;
1376 template<class CodeEmitter>
1377 void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1378 const MachineInstr &MI) {
1379 // Part of binary is determined by TableGn.
1380 unsigned Binary = getBinaryCodeForInstr(MI);
1382 // Set the conditional execution predicate
1383 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1385 // Set base address operand
1386 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1388 // Set addressing mode by modifying bits U(23) and P(24)
1389 const MachineOperand &MO = MI.getOperand(1);
1390 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1393 if (ARM_AM::getAM5WBFlag(MO.getImm()))
1394 Binary |= 0x1 << ARMII::W_BitShift;
1396 // First register is encoded in Dd.
1397 Binary |= encodeVFPRd(MI, 4);
1399 // Number of registers are encoded in offset field.
1400 unsigned NumRegs = 1;
1401 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1402 const MachineOperand &MO = MI.getOperand(i);
1403 if (!MO.isReg() || MO.isImplicit())
1407 Binary |= NumRegs * 2;
1412 template<class CodeEmitter>
1413 void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1414 // Part of binary is determined by TableGn.
1415 unsigned Binary = getBinaryCodeForInstr(MI);
1417 // Set the conditional execution predicate
1418 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1423 #include "ARMGenCodeEmitter.inc"