1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(&ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
105 unsigned getAddrModeSBit(const MachineInstr &MI,
106 const TargetInstrDesc &TID) const;
108 void emitDataProcessingInstruction(const MachineInstr &MI,
109 unsigned ImplicitRd = 0,
110 unsigned ImplicitRn = 0);
112 void emitLoadStoreInstruction(const MachineInstr &MI,
113 unsigned ImplicitRd = 0,
114 unsigned ImplicitRn = 0);
116 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117 unsigned ImplicitRn = 0);
119 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121 void emitMulFrmInstruction(const MachineInstr &MI);
123 void emitExtendInstruction(const MachineInstr &MI);
125 void emitMiscArithInstruction(const MachineInstr &MI);
127 void emitBranchInstruction(const MachineInstr &MI);
129 void emitInlineJumpTable(unsigned JTIndex);
131 void emitMiscBranchInstruction(const MachineInstr &MI);
133 void emitVFPArithInstruction(const MachineInstr &MI);
135 void emitVFPConversionInstruction(const MachineInstr &MI);
137 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
139 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
141 void emitMiscInstruction(const MachineInstr &MI);
143 void emitNEONLaneInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
151 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
152 return getMachineOpValue(MI, MI.getOperand(OpIdx));
155 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
156 /// machine operand requires relocation, record the relocation and return
158 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
160 unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
162 return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
165 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
167 unsigned getShiftOp(unsigned Imm) const ;
169 /// Routines that handle operands which add machine relocations which are
170 /// fixed up by the relocation stage.
171 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
172 bool MayNeedFarStub, bool Indirect,
174 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
175 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
176 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
177 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
178 intptr_t JTBase = 0);
182 char ARMCodeEmitter::ID = 0;
184 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
185 /// code to the specified MCE object.
186 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
187 JITCodeEmitter &JCE) {
188 return new ARMCodeEmitter(TM, JCE);
191 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
192 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
193 MF.getTarget().getRelocationModel() != Reloc::Static) &&
194 "JIT relocation model must be set to static or default!");
195 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
196 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
197 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
198 Subtarget = &TM.getSubtarget<ARMSubtarget>();
199 MCPEs = &MF.getConstantPool()->getConstants();
201 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
202 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
203 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
204 JTI->Initialize(MF, IsPIC);
205 MMI = &getAnalysis<MachineModuleInfo>();
206 MCE.setModuleInfo(MMI);
209 DEBUG(errs() << "JITTing function '"
210 << MF.getFunction()->getName() << "'\n");
211 MCE.startFunction(MF);
212 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
214 MCE.StartMachineBasicBlock(MBB);
215 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
219 } while (MCE.finishFunction(MF));
224 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
226 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
227 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
228 default: llvm_unreachable("Unknown shift opc!");
229 case ARM_AM::asr: return 2;
230 case ARM_AM::lsl: return 0;
231 case ARM_AM::lsr: return 1;
233 case ARM_AM::rrx: return 3;
238 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
239 /// machine operand requires relocation, record the relocation and return zero.
240 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
241 const MachineOperand &MO,
243 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
244 && "Relocation to this function should be for movt or movw");
247 return static_cast<unsigned>(MO.getImm());
248 else if (MO.isGlobal())
249 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
250 else if (MO.isSymbol())
251 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
253 emitMachineBasicBlock(MO.getMBB(), Reloc);
258 llvm_unreachable("Unsupported operand type for movw/movt");
263 /// getMachineOpValue - Return binary encoding of operand. If the machine
264 /// operand requires relocation, record the relocation and return zero.
265 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
266 const MachineOperand &MO) {
268 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
270 return static_cast<unsigned>(MO.getImm());
271 else if (MO.isGlobal())
272 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
273 else if (MO.isSymbol())
274 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
275 else if (MO.isCPI()) {
276 const TargetInstrDesc &TID = MI.getDesc();
277 // For VFP load, the immediate offset is multiplied by 4.
278 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
279 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
280 emitConstPoolAddress(MO.getIndex(), Reloc);
281 } else if (MO.isJTI())
282 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
284 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
294 /// emitGlobalAddress - Emit the specified address to the code stream.
296 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
297 bool MayNeedFarStub, bool Indirect,
299 MachineRelocation MR = Indirect
300 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
301 const_cast<GlobalValue *>(GV),
302 ACPV, MayNeedFarStub)
303 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
304 const_cast<GlobalValue *>(GV), ACPV,
306 MCE.addRelocation(MR);
309 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
310 /// be emitted to the current location in the function, and allow it to be PC
312 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
313 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
317 /// emitConstPoolAddress - Arrange for the address of an constant pool
318 /// to be emitted to the current location in the function, and allow it to be PC
320 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
321 // Tell JIT emitter we'll resolve the address.
322 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
323 Reloc, CPI, 0, true));
326 /// emitJumpTableAddress - Arrange for the address of a jump table to
327 /// be emitted to the current location in the function, and allow it to be PC
329 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
330 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
331 Reloc, JTIndex, 0, true));
334 /// emitMachineBasicBlock - Emit the specified address basic block.
335 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
336 unsigned Reloc, intptr_t JTBase) {
337 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
341 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
342 DEBUG(errs() << " 0x";
343 errs().write_hex(Binary) << "\n");
344 MCE.emitWordLE(Binary);
347 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
348 DEBUG(errs() << " 0x";
349 errs().write_hex(Binary) << "\n");
350 MCE.emitDWordLE(Binary);
353 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
354 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
356 MCE.processDebugLoc(MI.getDebugLoc(), true);
358 ++NumEmitted; // Keep track of the # of mi's emitted
359 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
361 llvm_unreachable("Unhandled instruction encoding format!");
365 emitPseudoInstruction(MI);
368 case ARMII::DPSoRegFrm:
369 emitDataProcessingInstruction(MI);
373 emitLoadStoreInstruction(MI);
375 case ARMII::LdMiscFrm:
376 case ARMII::StMiscFrm:
377 emitMiscLoadStoreInstruction(MI);
379 case ARMII::LdStMulFrm:
380 emitLoadStoreMultipleInstruction(MI);
383 emitMulFrmInstruction(MI);
386 emitExtendInstruction(MI);
388 case ARMII::ArithMiscFrm:
389 emitMiscArithInstruction(MI);
392 emitBranchInstruction(MI);
394 case ARMII::BrMiscFrm:
395 emitMiscBranchInstruction(MI);
398 case ARMII::VFPUnaryFrm:
399 case ARMII::VFPBinaryFrm:
400 emitVFPArithInstruction(MI);
402 case ARMII::VFPConv1Frm:
403 case ARMII::VFPConv2Frm:
404 case ARMII::VFPConv3Frm:
405 case ARMII::VFPConv4Frm:
406 case ARMII::VFPConv5Frm:
407 emitVFPConversionInstruction(MI);
409 case ARMII::VFPLdStFrm:
410 emitVFPLoadStoreInstruction(MI);
412 case ARMII::VFPLdStMulFrm:
413 emitVFPLoadStoreMultipleInstruction(MI);
415 case ARMII::VFPMiscFrm:
416 emitMiscInstruction(MI);
418 // NEON instructions.
419 case ARMII::NGetLnFrm:
420 case ARMII::NSetLnFrm:
421 emitNEONLaneInstruction(MI);
423 case ARMII::N1RegModImmFrm:
424 emitNEON1RegModImmInstruction(MI);
426 case ARMII::N2RegFrm:
427 emitNEON2RegInstruction(MI);
429 case ARMII::N3RegFrm:
430 emitNEON3RegInstruction(MI);
433 MCE.processDebugLoc(MI.getDebugLoc(), false);
436 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
437 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
438 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
439 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
441 // Remember the CONSTPOOL_ENTRY address for later relocation.
442 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
444 // Emit constpool island entry. In most cases, the actual values will be
445 // resolved and relocated after code emission.
446 if (MCPE.isMachineConstantPoolEntry()) {
447 ARMConstantPoolValue *ACPV =
448 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
450 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
451 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
453 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
454 const GlobalValue *GV = ACPV->getGV();
456 Reloc::Model RelocM = TM.getRelocationModel();
457 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
459 Subtarget->GVIsIndirectSymbol(GV, RelocM),
462 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
466 const Constant *CV = MCPE.Val.ConstVal;
469 errs() << " ** Constant pool #" << CPI << " @ "
470 << (void*)MCE.getCurrentPCValue() << " ";
471 if (const Function *F = dyn_cast<Function>(CV))
472 errs() << F->getName();
478 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
479 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
481 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
482 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
484 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
485 if (CFP->getType()->isFloatTy())
486 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
487 else if (CFP->getType()->isDoubleTy())
488 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
490 llvm_unreachable("Unable to handle this constantpool entry!");
493 llvm_unreachable("Unable to handle this constantpool entry!");
498 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
499 const MachineOperand &MO0 = MI.getOperand(0);
500 const MachineOperand &MO1 = MI.getOperand(1);
502 // Emit the 'movw' instruction.
503 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
505 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
507 // Set the conditional execution predicate.
508 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
511 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
513 // Encode imm16 as imm4:imm12
514 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
515 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
518 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
519 // Emit the 'movt' instruction.
520 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
522 // Set the conditional execution predicate.
523 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
526 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
528 // Encode imm16 as imm4:imm1, same as movw above.
529 Binary |= Hi16 & 0xFFF;
530 Binary |= ((Hi16 >> 12) & 0xF) << 16;
534 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
535 const MachineOperand &MO0 = MI.getOperand(0);
536 const MachineOperand &MO1 = MI.getOperand(1);
537 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
538 "Not a valid so_imm value!");
539 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
540 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
542 // Emit the 'mov' instruction.
543 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
545 // Set the conditional execution predicate.
546 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
549 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
552 // Set bit I(25) to identify this is the immediate form of <shifter_op>
553 Binary |= 1 << ARMII::I_BitShift;
554 Binary |= getMachineSoImmOpValue(V1);
557 // Now the 'orr' instruction.
558 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
560 // Set the conditional execution predicate.
561 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
564 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
567 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
570 // Set bit I(25) to identify this is the immediate form of <shifter_op>
571 Binary |= 1 << ARMII::I_BitShift;
572 Binary |= getMachineSoImmOpValue(V2);
576 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
577 // It's basically add r, pc, (LJTI - $+8)
579 const TargetInstrDesc &TID = MI.getDesc();
581 // Emit the 'add' instruction.
582 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
584 // Set the conditional execution predicate
585 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
587 // Encode S bit if MI modifies CPSR.
588 Binary |= getAddrModeSBit(MI, TID);
591 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
593 // Encode Rn which is PC.
594 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
596 // Encode the displacement.
597 Binary |= 1 << ARMII::I_BitShift;
598 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
603 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
604 unsigned Opcode = MI.getDesc().Opcode;
606 // Part of binary is determined by TableGn.
607 unsigned Binary = getBinaryCodeForInstr(MI);
609 // Set the conditional execution predicate
610 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
612 // Encode S bit if MI modifies CPSR.
613 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
614 Binary |= 1 << ARMII::S_BitShift;
616 // Encode register def if there is one.
617 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
619 // Encode the shift operation.
626 case ARM::MOVsrl_flag:
628 Binary |= (0x2 << 4) | (1 << 7);
630 case ARM::MOVsra_flag:
632 Binary |= (0x4 << 4) | (1 << 7);
636 // Encode register Rm.
637 Binary |= getMachineOpValue(MI, 1);
642 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
643 DEBUG(errs() << " ** LPC" << LabelID << " @ "
644 << (void*)MCE.getCurrentPCValue() << '\n');
645 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
648 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
649 unsigned Opcode = MI.getDesc().Opcode;
652 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
653 case TargetOpcode::INLINEASM: {
654 // We allow inline assembler nodes with empty bodies - they can
655 // implicitly define registers, which is ok for JIT.
656 if (MI.getOperand(0).getSymbolName()[0]) {
657 report_fatal_error("JIT does not support inline asm!");
661 case TargetOpcode::DBG_LABEL:
662 case TargetOpcode::EH_LABEL:
663 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
665 case TargetOpcode::IMPLICIT_DEF:
666 case TargetOpcode::KILL:
669 case ARM::CONSTPOOL_ENTRY:
670 emitConstPoolInstruction(MI);
673 // Remember of the address of the PC label for relocation later.
674 addPCLabel(MI.getOperand(2).getImm());
675 // PICADD is just an add instruction that implicitly read pc.
676 emitDataProcessingInstruction(MI, 0, ARM::PC);
683 // Remember of the address of the PC label for relocation later.
684 addPCLabel(MI.getOperand(2).getImm());
685 // These are just load / store instructions that implicitly read pc.
686 emitLoadStoreInstruction(MI, 0, ARM::PC);
693 // Remember of the address of the PC label for relocation later.
694 addPCLabel(MI.getOperand(2).getImm());
695 // These are just load / store instructions that implicitly read pc.
696 emitMiscLoadStoreInstruction(MI, ARM::PC);
701 emitMOVi32immInstruction(MI);
704 case ARM::MOVi2pieces:
705 // Two instructions to materialize a constant.
706 emitMOVi2piecesInstruction(MI);
708 case ARM::LEApcrelJT:
709 // Materialize jumptable address.
710 emitLEApcrelJTInstruction(MI);
713 case ARM::MOVsrl_flag:
714 case ARM::MOVsra_flag:
715 emitPseudoMoveInstruction(MI);
720 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
721 const TargetInstrDesc &TID,
722 const MachineOperand &MO,
724 unsigned Binary = getMachineOpValue(MI, MO);
726 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
727 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
728 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
730 // Encode the shift opcode.
732 unsigned Rs = MO1.getReg();
734 // Set shift operand (bit[7:4]).
739 // RRX - 0110 and bit[11:8] clear.
741 default: llvm_unreachable("Unknown shift opc!");
742 case ARM_AM::lsl: SBits = 0x1; break;
743 case ARM_AM::lsr: SBits = 0x3; break;
744 case ARM_AM::asr: SBits = 0x5; break;
745 case ARM_AM::ror: SBits = 0x7; break;
746 case ARM_AM::rrx: SBits = 0x6; break;
749 // Set shift operand (bit[6:4]).
755 default: llvm_unreachable("Unknown shift opc!");
756 case ARM_AM::lsl: SBits = 0x0; break;
757 case ARM_AM::lsr: SBits = 0x2; break;
758 case ARM_AM::asr: SBits = 0x4; break;
759 case ARM_AM::ror: SBits = 0x6; break;
762 Binary |= SBits << 4;
763 if (SOpc == ARM_AM::rrx)
766 // Encode the shift operation Rs or shift_imm (except rrx).
768 // Encode Rs bit[11:8].
769 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
771 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
774 // Encode shift_imm bit[11:7].
775 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
778 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
779 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
780 assert(SoImmVal != -1 && "Not a valid so_imm value!");
782 // Encode rotate_imm.
783 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
784 << ARMII::SoRotImmShift;
787 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
791 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
792 const TargetInstrDesc &TID) const {
793 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
794 const MachineOperand &MO = MI.getOperand(i-1);
795 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
796 return 1 << ARMII::S_BitShift;
801 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
803 unsigned ImplicitRn) {
804 const TargetInstrDesc &TID = MI.getDesc();
806 // Part of binary is determined by TableGn.
807 unsigned Binary = getBinaryCodeForInstr(MI);
809 // Set the conditional execution predicate
810 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
812 // Encode S bit if MI modifies CPSR.
813 Binary |= getAddrModeSBit(MI, TID);
815 // Encode register def if there is one.
816 unsigned NumDefs = TID.getNumDefs();
819 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
821 // Special handling for implicit use (e.g. PC).
822 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
823 << ARMII::RegRdShift);
825 if (TID.Opcode == ARM::MOVi16) {
826 // Get immediate from MI.
827 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
828 ARM::reloc_arm_movw);
829 // Encode imm which is the same as in emitMOVi32immInstruction().
830 Binary |= Lo16 & 0xFFF;
831 Binary |= ((Lo16 >> 12) & 0xF) << 16;
834 } else if(TID.Opcode == ARM::MOVTi16) {
835 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
836 ARM::reloc_arm_movt) >> 16);
837 Binary |= Hi16 & 0xFFF;
838 Binary |= ((Hi16 >> 12) & 0xF) << 16;
841 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
842 uint32_t v = ~MI.getOperand(2).getImm();
843 int32_t lsb = CountTrailingZeros_32(v);
844 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
845 // Instr{20-16} = msb, Instr{11-7} = lsb
846 Binary |= (msb & 0x1F) << 16;
847 Binary |= (lsb & 0x1F) << 7;
850 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
851 // Encode Rn in Instr{0-3}
852 Binary |= getMachineOpValue(MI, OpIdx++);
854 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
855 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
857 // Instr{20-16} = widthm1, Instr{11-7} = lsb
858 Binary |= (widthm1 & 0x1F) << 16;
859 Binary |= (lsb & 0x1F) << 7;
864 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
865 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
868 // Encode first non-shifter register operand if there is one.
869 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
872 // Special handling for implicit use (e.g. PC).
873 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
874 << ARMII::RegRnShift);
876 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
881 // Encode shifter operand.
882 const MachineOperand &MO = MI.getOperand(OpIdx);
883 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
885 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
890 // Encode register Rm.
891 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
896 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
901 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
903 unsigned ImplicitRn) {
904 const TargetInstrDesc &TID = MI.getDesc();
905 unsigned Form = TID.TSFlags & ARMII::FormMask;
906 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
908 // Part of binary is determined by TableGn.
909 unsigned Binary = getBinaryCodeForInstr(MI);
911 // Set the conditional execution predicate
912 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
916 // Operand 0 of a pre- and post-indexed store is the address base
917 // writeback. Skip it.
918 bool Skipped = false;
919 if (IsPrePost && Form == ARMII::StFrm) {
926 // Special handling for implicit use (e.g. PC).
927 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
928 << ARMII::RegRdShift);
930 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
932 // Set second operand
934 // Special handling for implicit use (e.g. PC).
935 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
936 << ARMII::RegRnShift);
938 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
940 // If this is a two-address operand, skip it. e.g. LDR_PRE.
941 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
944 const MachineOperand &MO2 = MI.getOperand(OpIdx);
945 unsigned AM2Opc = (ImplicitRn == ARM::PC)
946 ? 0 : MI.getOperand(OpIdx+1).getImm();
948 // Set bit U(23) according to sign of immed value (positive or negative).
949 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
951 if (!MO2.getReg()) { // is immediate
952 if (ARM_AM::getAM2Offset(AM2Opc))
953 // Set the value of offset_12 field
954 Binary |= ARM_AM::getAM2Offset(AM2Opc);
959 // Set bit I(25), because this is not in immediate enconding.
960 Binary |= 1 << ARMII::I_BitShift;
961 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
962 // Set bit[3:0] to the corresponding Rm register
963 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
965 // If this instr is in scaled register offset/index instruction, set
966 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
967 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
968 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
969 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
975 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
976 unsigned ImplicitRn) {
977 const TargetInstrDesc &TID = MI.getDesc();
978 unsigned Form = TID.TSFlags & ARMII::FormMask;
979 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
981 // Part of binary is determined by TableGn.
982 unsigned Binary = getBinaryCodeForInstr(MI);
984 // Set the conditional execution predicate
985 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
989 // Operand 0 of a pre- and post-indexed store is the address base
990 // writeback. Skip it.
991 bool Skipped = false;
992 if (IsPrePost && Form == ARMII::StMiscFrm) {
998 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1000 // Skip LDRD and STRD's second operand.
1001 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1004 // Set second operand
1006 // Special handling for implicit use (e.g. PC).
1007 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
1008 << ARMII::RegRnShift);
1010 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1012 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1013 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1016 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1017 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1018 ? 0 : MI.getOperand(OpIdx+1).getImm();
1020 // Set bit U(23) according to sign of immed value (positive or negative)
1021 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1024 // If this instr is in register offset/index encoding, set bit[3:0]
1025 // to the corresponding Rm register.
1027 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
1032 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1033 Binary |= 1 << ARMII::AM3_I_BitShift;
1034 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1036 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1037 Binary |= (ImmOffs & 0xF); // immedL
1043 static unsigned getAddrModeUPBits(unsigned Mode) {
1044 unsigned Binary = 0;
1046 // Set addressing mode by modifying bits U(23) and P(24)
1047 // IA - Increment after - bit U = 1 and bit P = 0
1048 // IB - Increment before - bit U = 1 and bit P = 1
1049 // DA - Decrement after - bit U = 0 and bit P = 0
1050 // DB - Decrement before - bit U = 0 and bit P = 1
1052 default: llvm_unreachable("Unknown addressing sub-mode!");
1053 case ARM_AM::da: break;
1054 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1055 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1056 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1062 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1063 const TargetInstrDesc &TID = MI.getDesc();
1064 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1066 // Part of binary is determined by TableGn.
1067 unsigned Binary = getBinaryCodeForInstr(MI);
1069 // Set the conditional execution predicate
1070 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1072 // Skip operand 0 of an instruction with base register update.
1077 // Set base address operand
1078 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1080 // Set addressing mode by modifying bits U(23) and P(24)
1081 const MachineOperand &MO = MI.getOperand(OpIdx++);
1082 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1086 Binary |= 0x1 << ARMII::W_BitShift;
1089 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1090 const MachineOperand &MO = MI.getOperand(i);
1091 if (!MO.isReg() || MO.isImplicit())
1093 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1094 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1096 Binary |= 0x1 << RegNum;
1102 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1103 const TargetInstrDesc &TID = MI.getDesc();
1105 // Part of binary is determined by TableGn.
1106 unsigned Binary = getBinaryCodeForInstr(MI);
1108 // Set the conditional execution predicate
1109 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1111 // Encode S bit if MI modifies CPSR.
1112 Binary |= getAddrModeSBit(MI, TID);
1114 // 32x32->64bit operations have two destination registers. The number
1115 // of register definitions will tell us if that's what we're dealing with.
1117 if (TID.getNumDefs() == 2)
1118 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1121 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1124 Binary |= getMachineOpValue(MI, OpIdx++);
1127 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1129 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1130 // it as Rn (for multiply, that's in the same offset as RdLo.
1131 if (TID.getNumOperands() > OpIdx &&
1132 !TID.OpInfo[OpIdx].isPredicate() &&
1133 !TID.OpInfo[OpIdx].isOptionalDef())
1134 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1139 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1140 const TargetInstrDesc &TID = MI.getDesc();
1142 // Part of binary is determined by TableGn.
1143 unsigned Binary = getBinaryCodeForInstr(MI);
1145 // Set the conditional execution predicate
1146 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1151 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1153 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1154 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1156 // Two register operand form.
1158 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1161 Binary |= getMachineOpValue(MI, MO2);
1164 Binary |= getMachineOpValue(MI, MO1);
1167 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1168 if (MI.getOperand(OpIdx).isImm() &&
1169 !TID.OpInfo[OpIdx].isPredicate() &&
1170 !TID.OpInfo[OpIdx].isOptionalDef())
1171 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1176 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1177 const TargetInstrDesc &TID = MI.getDesc();
1179 // Part of binary is determined by TableGn.
1180 unsigned Binary = getBinaryCodeForInstr(MI);
1182 // Set the conditional execution predicate
1183 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1188 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1190 const MachineOperand &MO = MI.getOperand(OpIdx++);
1191 if (OpIdx == TID.getNumOperands() ||
1192 TID.OpInfo[OpIdx].isPredicate() ||
1193 TID.OpInfo[OpIdx].isOptionalDef()) {
1194 // Encode Rm and it's done.
1195 Binary |= getMachineOpValue(MI, MO);
1201 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1204 Binary |= getMachineOpValue(MI, OpIdx++);
1206 // Encode shift_imm.
1207 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1208 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1209 Binary |= ShiftAmt << ARMII::ShiftShift;
1214 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1215 const TargetInstrDesc &TID = MI.getDesc();
1217 if (TID.Opcode == ARM::TPsoft) {
1218 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1221 // Part of binary is determined by TableGn.
1222 unsigned Binary = getBinaryCodeForInstr(MI);
1224 // Set the conditional execution predicate
1225 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1227 // Set signed_immed_24 field
1228 Binary |= getMachineOpValue(MI, 0);
1233 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1234 // Remember the base address of the inline jump table.
1235 uintptr_t JTBase = MCE.getCurrentPCValue();
1236 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1237 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1240 // Now emit the jump table entries.
1241 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1242 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1244 // DestBB address - JT base.
1245 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1247 // Absolute DestBB address.
1248 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1253 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1254 const TargetInstrDesc &TID = MI.getDesc();
1256 // Handle jump tables.
1257 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1258 // First emit a ldr pc, [] instruction.
1259 emitDataProcessingInstruction(MI, ARM::PC);
1261 // Then emit the inline jump table.
1263 (TID.Opcode == ARM::BR_JTr)
1264 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1265 emitInlineJumpTable(JTIndex);
1267 } else if (TID.Opcode == ARM::BR_JTm) {
1268 // First emit a ldr pc, [] instruction.
1269 emitLoadStoreInstruction(MI, ARM::PC);
1271 // Then emit the inline jump table.
1272 emitInlineJumpTable(MI.getOperand(3).getIndex());
1276 // Part of binary is determined by TableGn.
1277 unsigned Binary = getBinaryCodeForInstr(MI);
1279 // Set the conditional execution predicate
1280 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1282 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1283 // The return register is LR.
1284 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1286 // otherwise, set the return register
1287 Binary |= getMachineOpValue(MI, 0);
1292 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1293 unsigned RegD = MI.getOperand(OpIdx).getReg();
1294 unsigned Binary = 0;
1295 bool isSPVFP = false;
1296 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1298 Binary |= RegD << ARMII::RegRdShift;
1300 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1301 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1306 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1307 unsigned RegN = MI.getOperand(OpIdx).getReg();
1308 unsigned Binary = 0;
1309 bool isSPVFP = false;
1310 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1312 Binary |= RegN << ARMII::RegRnShift;
1314 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1315 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1320 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1321 unsigned RegM = MI.getOperand(OpIdx).getReg();
1322 unsigned Binary = 0;
1323 bool isSPVFP = false;
1324 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1328 Binary |= ((RegM & 0x1E) >> 1);
1329 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1334 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1335 const TargetInstrDesc &TID = MI.getDesc();
1337 // Part of binary is determined by TableGn.
1338 unsigned Binary = getBinaryCodeForInstr(MI);
1340 // Set the conditional execution predicate
1341 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1344 assert((Binary & ARMII::D_BitShift) == 0 &&
1345 (Binary & ARMII::N_BitShift) == 0 &&
1346 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1349 Binary |= encodeVFPRd(MI, OpIdx++);
1351 // If this is a two-address operand, skip it, e.g. FMACD.
1352 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1356 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1357 Binary |= encodeVFPRn(MI, OpIdx++);
1359 if (OpIdx == TID.getNumOperands() ||
1360 TID.OpInfo[OpIdx].isPredicate() ||
1361 TID.OpInfo[OpIdx].isOptionalDef()) {
1362 // FCMPEZD etc. has only one operand.
1368 Binary |= encodeVFPRm(MI, OpIdx);
1373 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1374 const TargetInstrDesc &TID = MI.getDesc();
1375 unsigned Form = TID.TSFlags & ARMII::FormMask;
1377 // Part of binary is determined by TableGn.
1378 unsigned Binary = getBinaryCodeForInstr(MI);
1380 // Set the conditional execution predicate
1381 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1385 case ARMII::VFPConv1Frm:
1386 case ARMII::VFPConv2Frm:
1387 case ARMII::VFPConv3Frm:
1389 Binary |= encodeVFPRd(MI, 0);
1391 case ARMII::VFPConv4Frm:
1393 Binary |= encodeVFPRn(MI, 0);
1395 case ARMII::VFPConv5Frm:
1397 Binary |= encodeVFPRm(MI, 0);
1403 case ARMII::VFPConv1Frm:
1405 Binary |= encodeVFPRm(MI, 1);
1407 case ARMII::VFPConv2Frm:
1408 case ARMII::VFPConv3Frm:
1410 Binary |= encodeVFPRn(MI, 1);
1412 case ARMII::VFPConv4Frm:
1413 case ARMII::VFPConv5Frm:
1415 Binary |= encodeVFPRd(MI, 1);
1419 if (Form == ARMII::VFPConv5Frm)
1421 Binary |= encodeVFPRn(MI, 2);
1422 else if (Form == ARMII::VFPConv3Frm)
1424 Binary |= encodeVFPRm(MI, 2);
1429 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1430 // Part of binary is determined by TableGn.
1431 unsigned Binary = getBinaryCodeForInstr(MI);
1433 // Set the conditional execution predicate
1434 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1439 Binary |= encodeVFPRd(MI, OpIdx++);
1441 // Encode address base.
1442 const MachineOperand &Base = MI.getOperand(OpIdx++);
1443 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1445 // If there is a non-zero immediate offset, encode it.
1447 const MachineOperand &Offset = MI.getOperand(OpIdx);
1448 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1449 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1450 Binary |= 1 << ARMII::U_BitShift;
1457 // If immediate offset is omitted, default to +0.
1458 Binary |= 1 << ARMII::U_BitShift;
1464 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1465 const TargetInstrDesc &TID = MI.getDesc();
1466 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1468 // Part of binary is determined by TableGn.
1469 unsigned Binary = getBinaryCodeForInstr(MI);
1471 // Set the conditional execution predicate
1472 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1474 // Skip operand 0 of an instruction with base register update.
1479 // Set base address operand
1480 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1482 // Set addressing mode by modifying bits U(23) and P(24)
1483 const MachineOperand &MO = MI.getOperand(OpIdx++);
1484 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1488 Binary |= 0x1 << ARMII::W_BitShift;
1490 // First register is encoded in Dd.
1491 Binary |= encodeVFPRd(MI, OpIdx+2);
1493 // Number of registers are encoded in offset field.
1494 unsigned NumRegs = 1;
1495 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1496 const MachineOperand &MO = MI.getOperand(i);
1497 if (!MO.isReg() || MO.isImplicit())
1501 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1502 // Otherwise, it will be 0, in the case of 32-bit registers.
1504 Binary |= NumRegs * 2;
1511 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1512 unsigned Opcode = MI.getDesc().Opcode;
1513 // Part of binary is determined by TableGn.
1514 unsigned Binary = getBinaryCodeForInstr(MI);
1516 // Set the conditional execution predicate
1517 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1521 llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1524 // No further encoding needed.
1529 const MachineOperand &MO0 = MI.getOperand(0);
1531 Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
1532 << ARMII::RegRdShift;
1537 case ARM::FCONSTS: {
1539 Binary |= encodeVFPRd(MI, 0);
1541 // Encode imm., Table A7-18 VFP modified immediate constants
1542 const MachineOperand &MO1 = MI.getOperand(1);
1543 unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1544 .bitcastToAPInt().getHiBits(32).getLimitedValue());
1545 unsigned ModifiedImm;
1547 if(Opcode == ARM::FCONSTS)
1548 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1549 (Imm & 0x03F80000) >> 19; // bcdefgh
1550 else // Opcode == ARM::FCONSTD
1551 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1552 (Imm & 0x007F0000) >> 16; // bcdefgh
1554 // Insts{19-16} = abcd, Insts{3-0} = efgh
1555 Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1556 Binary |= (ModifiedImm & 0xF);
1564 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1565 unsigned RegD = MI.getOperand(OpIdx).getReg();
1566 unsigned Binary = 0;
1567 RegD = ARMRegisterInfo::getRegisterNumbering(RegD);
1568 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1569 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1573 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1574 unsigned RegN = MI.getOperand(OpIdx).getReg();
1575 unsigned Binary = 0;
1576 RegN = ARMRegisterInfo::getRegisterNumbering(RegN);
1577 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1578 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1582 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1583 unsigned RegM = MI.getOperand(OpIdx).getReg();
1584 unsigned Binary = 0;
1585 RegM = ARMRegisterInfo::getRegisterNumbering(RegM);
1586 Binary |= (RegM & 0xf);
1587 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1591 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1592 /// data-processing instruction to the corresponding Thumb encoding.
1593 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1594 assert((Binary & 0xfe000000) == 0xf2000000 &&
1595 "not an ARM NEON data-processing instruction");
1596 unsigned UBit = (Binary >> 24) & 1;
1597 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1600 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1601 unsigned Binary = getBinaryCodeForInstr(MI);
1603 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1604 const TargetInstrDesc &TID = MI.getDesc();
1605 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1609 } else { // ARMII::NSetLnFrm
1615 // Set the conditional execution predicate
1616 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1618 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1619 RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1620 Binary |= (RegT << ARMII::RegRdShift);
1621 Binary |= encodeNEONRn(MI, RegNOpIdx);
1624 if ((Binary & (1 << 22)) != 0)
1625 LaneShift = 0; // 8-bit elements
1626 else if ((Binary & (1 << 5)) != 0)
1627 LaneShift = 1; // 16-bit elements
1629 LaneShift = 2; // 32-bit elements
1631 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1632 unsigned Opc1 = Lane >> 2;
1633 unsigned Opc2 = Lane & 3;
1634 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1635 Binary |= (Opc1 << 21);
1636 Binary |= (Opc2 << 5);
1641 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1642 unsigned Binary = getBinaryCodeForInstr(MI);
1643 // Destination register is encoded in Dd.
1644 Binary |= encodeNEONRd(MI, 0);
1645 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1646 unsigned Imm = MI.getOperand(1).getImm();
1647 unsigned Op = (Imm >> 12) & 1;
1648 unsigned Cmode = (Imm >> 8) & 0xf;
1649 unsigned I = (Imm >> 7) & 1;
1650 unsigned Imm3 = (Imm >> 4) & 0x7;
1651 unsigned Imm4 = Imm & 0xf;
1652 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1654 Binary = convertNEONDataProcToThumb(Binary);
1658 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1659 const TargetInstrDesc &TID = MI.getDesc();
1660 unsigned Binary = getBinaryCodeForInstr(MI);
1661 // Destination register is encoded in Dd; source register in Dm.
1663 Binary |= encodeNEONRd(MI, OpIdx++);
1664 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1666 Binary |= encodeNEONRm(MI, OpIdx);
1668 Binary = convertNEONDataProcToThumb(Binary);
1669 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1673 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1674 const TargetInstrDesc &TID = MI.getDesc();
1675 unsigned Binary = getBinaryCodeForInstr(MI);
1676 // Destination register is encoded in Dd; source registers in Dn and Dm.
1678 Binary |= encodeNEONRd(MI, OpIdx++);
1679 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1681 Binary |= encodeNEONRn(MI, OpIdx++);
1682 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1684 Binary |= encodeNEONRm(MI, OpIdx);
1686 Binary = convertNEONDataProcToThumb(Binary);
1687 // FIXME: This does not handle VMOVDneon or VMOVQ.
1691 #include "ARMGenCodeEmitter.inc"