1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/Debug.h"
41 STATISTIC(NumEmitted, "Number of machine instructions emitted");
44 class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
46 const ARMInstrInfo *II;
49 MachineCodeEmitter &MCE;
50 const std::vector<MachineConstantPoolEntry> *MCPEs;
51 const std::vector<MachineJumpTableEntry> *MJTEs;
56 explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
57 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
58 MCE(mce), MCPEs(0), MJTEs(0),
59 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
60 ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
61 const ARMInstrInfo &ii, const TargetData &td)
62 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
63 MCE(mce), MCPEs(0), MJTEs(0),
64 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
66 bool runOnMachineFunction(MachineFunction &MF);
68 virtual const char *getPassName() const {
69 return "ARM Machine Code Emitter";
72 void emitInstruction(const MachineInstr &MI);
76 void emitWordLE(unsigned Binary);
78 void emitDWordLE(uint64_t Binary);
80 void emitConstPoolInstruction(const MachineInstr &MI);
82 void emitMOVi2piecesInstruction(const MachineInstr &MI);
84 void emitLEApcrelJTInstruction(const MachineInstr &MI);
86 void addPCLabel(unsigned LabelID);
88 void emitPseudoInstruction(const MachineInstr &MI);
90 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
91 const TargetInstrDesc &TID,
92 const MachineOperand &MO,
95 unsigned getMachineSoImmOpValue(unsigned SoImm);
97 unsigned getAddrModeSBit(const MachineInstr &MI,
98 const TargetInstrDesc &TID) const;
100 void emitDataProcessingInstruction(const MachineInstr &MI,
101 unsigned ImplicitRd = 0,
102 unsigned ImplicitRn = 0);
104 void emitLoadStoreInstruction(const MachineInstr &MI,
105 unsigned ImplicitRd = 0,
106 unsigned ImplicitRn = 0);
108 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
113 void emitMulFrmInstruction(const MachineInstr &MI);
115 void emitExtendInstruction(const MachineInstr &MI);
117 void emitMiscArithInstruction(const MachineInstr &MI);
119 void emitBranchInstruction(const MachineInstr &MI);
121 void emitInlineJumpTable(unsigned JTIndex);
123 void emitMiscBranchInstruction(const MachineInstr &MI);
125 void emitVFPArithInstruction(const MachineInstr &MI);
127 void emitVFPConversionInstruction(const MachineInstr &MI);
129 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
131 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
133 void emitMiscInstruction(const MachineInstr &MI);
135 /// getBinaryCodeForInstr - This function, generated by the
136 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
137 /// machine instructions.
139 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
141 /// getMachineOpValue - Return binary encoding of operand. If the machine
142 /// operand requires relocation, record the relocation and return zero.
143 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
144 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
145 return getMachineOpValue(MI, MI.getOperand(OpIdx));
148 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
150 unsigned getShiftOp(unsigned Imm) const ;
152 /// Routines that handle operands which add machine relocations which are
153 /// fixed up by the relocation stage.
154 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
155 bool NeedStub, intptr_t ACPV = 0);
156 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
157 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
158 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
159 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
160 intptr_t JTBase = 0);
162 char ARMCodeEmitter::ID = 0;
165 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
166 /// to the specified MCE object.
167 FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
168 MachineCodeEmitter &MCE) {
169 return new ARMCodeEmitter(TM, MCE);
172 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
173 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
174 MF.getTarget().getRelocationModel() != Reloc::Static) &&
175 "JIT relocation model must be set to static or default!");
176 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
177 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
178 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
179 MCPEs = &MF.getConstantPool()->getConstants();
180 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
181 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
182 JTI->Initialize(MF, IsPIC);
185 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
186 MCE.startFunction(MF);
187 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
189 MCE.StartMachineBasicBlock(MBB);
190 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
194 } while (MCE.finishFunction(MF));
199 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
201 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
202 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
203 default: assert(0 && "Unknown shift opc!");
204 case ARM_AM::asr: return 2;
205 case ARM_AM::lsl: return 0;
206 case ARM_AM::lsr: return 1;
208 case ARM_AM::rrx: return 3;
213 /// getMachineOpValue - Return binary encoding of operand. If the machine
214 /// operand requires relocation, record the relocation and return zero.
215 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
216 const MachineOperand &MO) {
218 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
220 return static_cast<unsigned>(MO.getImm());
221 else if (MO.isGlobal())
222 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
223 else if (MO.isSymbol())
224 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
226 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
228 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
230 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
232 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
238 /// emitGlobalAddress - Emit the specified address to the code stream.
240 void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
241 bool NeedStub, intptr_t ACPV) {
242 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
243 Reloc, GV, ACPV, NeedStub));
246 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
247 /// be emitted to the current location in the function, and allow it to be PC
249 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
250 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
254 /// emitConstPoolAddress - Arrange for the address of an constant pool
255 /// to be emitted to the current location in the function, and allow it to be PC
257 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
258 // Tell JIT emitter we'll resolve the address.
259 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
260 Reloc, CPI, 0, true));
263 /// emitJumpTableAddress - Arrange for the address of a jump table to
264 /// be emitted to the current location in the function, and allow it to be PC
266 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
267 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
268 Reloc, JTIndex, 0, true));
271 /// emitMachineBasicBlock - Emit the specified address basic block.
272 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
273 unsigned Reloc, intptr_t JTBase) {
274 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
278 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
280 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
281 << Binary << std::dec << "\n";
283 MCE.emitWordLE(Binary);
286 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
288 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
289 << (unsigned)Binary << std::dec << "\n";
290 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
291 << (unsigned)(Binary >> 32) << std::dec << "\n";
293 MCE.emitDWordLE(Binary);
296 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
297 DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
299 NumEmitted++; // Keep track of the # of mi's emitted
300 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
302 assert(0 && "Unhandled instruction encoding format!");
305 emitPseudoInstruction(MI);
308 case ARMII::DPSoRegFrm:
309 emitDataProcessingInstruction(MI);
313 emitLoadStoreInstruction(MI);
315 case ARMII::LdMiscFrm:
316 case ARMII::StMiscFrm:
317 emitMiscLoadStoreInstruction(MI);
319 case ARMII::LdMulFrm:
320 case ARMII::StMulFrm:
321 emitLoadStoreMultipleInstruction(MI);
324 emitMulFrmInstruction(MI);
327 emitExtendInstruction(MI);
329 case ARMII::ArithMiscFrm:
330 emitMiscArithInstruction(MI);
333 emitBranchInstruction(MI);
335 case ARMII::BrMiscFrm:
336 emitMiscBranchInstruction(MI);
339 case ARMII::VFPUnaryFrm:
340 case ARMII::VFPBinaryFrm:
341 emitVFPArithInstruction(MI);
343 case ARMII::VFPConv1Frm:
344 case ARMII::VFPConv2Frm:
345 emitVFPConversionInstruction(MI);
347 case ARMII::VFPLdStFrm:
348 emitVFPLoadStoreInstruction(MI);
350 case ARMII::VFPLdStMulFrm:
351 emitVFPLoadStoreMultipleInstruction(MI);
353 case ARMII::VFPMiscFrm:
354 emitMiscInstruction(MI);
359 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
360 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
361 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
362 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
364 // Remember the CONSTPOOL_ENTRY address for later relocation.
365 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
367 // Emit constpool island entry. In most cases, the actual values will be
368 // resolved and relocated after code emission.
369 if (MCPE.isMachineConstantPoolEntry()) {
370 ARMConstantPoolValue *ACPV =
371 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
373 DOUT << " ** ARM constant pool #" << CPI << " @ "
374 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
376 GlobalValue *GV = ACPV->getGV();
378 assert(!ACPV->isStub() && "Don't know how to deal this yet!");
379 if (ACPV->isNonLazyPointer())
380 MCE.addRelocation(MachineRelocation::getIndirectSymbol(
381 MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
382 (intptr_t)ACPV, false));
384 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
385 ACPV->isStub(), (intptr_t)ACPV);
387 assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
388 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
392 Constant *CV = MCPE.Val.ConstVal;
394 DOUT << " ** Constant pool #" << CPI << " @ "
395 << (void*)MCE.getCurrentPCValue() << " " << *CV << '\n';
397 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
398 emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
400 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
401 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
403 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
404 if (CFP->getType() == Type::FloatTy)
405 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
406 else if (CFP->getType() == Type::DoubleTy)
407 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
409 assert(0 && "Unable to handle this constantpool entry!");
413 assert(0 && "Unable to handle this constantpool entry!");
419 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
420 const MachineOperand &MO0 = MI.getOperand(0);
421 const MachineOperand &MO1 = MI.getOperand(1);
422 assert(MO1.isImm() && "Not a valid so_imm value!");
423 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
424 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
426 // Emit the 'mov' instruction.
427 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
429 // Set the conditional execution predicate.
430 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
433 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
436 // Set bit I(25) to identify this is the immediate form of <shifter_op>
437 Binary |= 1 << ARMII::I_BitShift;
438 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
441 // Now the 'orr' instruction.
442 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
444 // Set the conditional execution predicate.
445 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
448 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
451 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
454 // Set bit I(25) to identify this is the immediate form of <shifter_op>
455 Binary |= 1 << ARMII::I_BitShift;
456 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
460 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
461 // It's basically add r, pc, (LJTI - $+8)
463 const TargetInstrDesc &TID = MI.getDesc();
465 // Emit the 'add' instruction.
466 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
468 // Set the conditional execution predicate
469 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
471 // Encode S bit if MI modifies CPSR.
472 Binary |= getAddrModeSBit(MI, TID);
475 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
477 // Encode Rn which is PC.
478 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
480 // Encode the displacement.
481 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
482 Binary |= 1 << ARMII::I_BitShift;
483 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
488 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
489 DOUT << " ** LPC" << LabelID << " @ "
490 << (void*)MCE.getCurrentPCValue() << '\n';
491 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
494 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
495 unsigned Opcode = MI.getDesc().Opcode;
499 case ARM::CONSTPOOL_ENTRY:
500 emitConstPoolInstruction(MI);
503 // Remember of the address of the PC label for relocation later.
504 addPCLabel(MI.getOperand(2).getImm());
505 // PICADD is just an add instruction that implicitly read pc.
506 emitDataProcessingInstruction(MI, 0, ARM::PC);
513 // Remember of the address of the PC label for relocation later.
514 addPCLabel(MI.getOperand(2).getImm());
515 // These are just load / store instructions that implicitly read pc.
516 emitLoadStoreInstruction(MI, 0, ARM::PC);
523 // Remember of the address of the PC label for relocation later.
524 addPCLabel(MI.getOperand(2).getImm());
525 // These are just load / store instructions that implicitly read pc.
526 emitMiscLoadStoreInstruction(MI, ARM::PC);
529 case ARM::MOVi2pieces:
530 // Two instructions to materialize a constant.
531 emitMOVi2piecesInstruction(MI);
533 case ARM::LEApcrelJT:
534 // Materialize jumptable address.
535 emitLEApcrelJTInstruction(MI);
541 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
542 const TargetInstrDesc &TID,
543 const MachineOperand &MO,
545 unsigned Binary = getMachineOpValue(MI, MO);
547 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
548 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
549 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
551 // Encode the shift opcode.
553 unsigned Rs = MO1.getReg();
555 // Set shift operand (bit[7:4]).
560 // RRX - 0110 and bit[11:8] clear.
562 default: assert(0 && "Unknown shift opc!");
563 case ARM_AM::lsl: SBits = 0x1; break;
564 case ARM_AM::lsr: SBits = 0x3; break;
565 case ARM_AM::asr: SBits = 0x5; break;
566 case ARM_AM::ror: SBits = 0x7; break;
567 case ARM_AM::rrx: SBits = 0x6; break;
570 // Set shift operand (bit[6:4]).
576 default: assert(0 && "Unknown shift opc!");
577 case ARM_AM::lsl: SBits = 0x0; break;
578 case ARM_AM::lsr: SBits = 0x2; break;
579 case ARM_AM::asr: SBits = 0x4; break;
580 case ARM_AM::ror: SBits = 0x6; break;
583 Binary |= SBits << 4;
584 if (SOpc == ARM_AM::rrx)
587 // Encode the shift operation Rs or shift_imm (except rrx).
589 // Encode Rs bit[11:8].
590 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
592 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
595 // Encode shift_imm bit[11:7].
596 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
599 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
600 // Encode rotate_imm.
601 unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
602 << ARMII::SoRotImmShift;
605 Binary |= ARM_AM::getSOImmValImm(SoImm);
609 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
610 const TargetInstrDesc &TID) const {
611 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
612 const MachineOperand &MO = MI.getOperand(i-1);
613 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
614 return 1 << ARMII::S_BitShift;
619 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
621 unsigned ImplicitRn) {
622 const TargetInstrDesc &TID = MI.getDesc();
624 // Part of binary is determined by TableGn.
625 unsigned Binary = getBinaryCodeForInstr(MI);
627 // Set the conditional execution predicate
628 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
630 // Encode S bit if MI modifies CPSR.
631 Binary |= getAddrModeSBit(MI, TID);
633 // Encode register def if there is one.
634 unsigned NumDefs = TID.getNumDefs();
637 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
639 // Special handling for implicit use (e.g. PC).
640 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
641 << ARMII::RegRdShift);
643 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
644 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
647 // Encode first non-shifter register operand if there is one.
648 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
651 // Special handling for implicit use (e.g. PC).
652 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
653 << ARMII::RegRnShift);
655 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
660 // Encode shifter operand.
661 const MachineOperand &MO = MI.getOperand(OpIdx);
662 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
664 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
669 // Encode register Rm.
670 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
675 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
676 Binary |= 1 << ARMII::I_BitShift;
677 Binary |= getMachineSoImmOpValue(MO.getImm());
682 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
684 unsigned ImplicitRn) {
685 const TargetInstrDesc &TID = MI.getDesc();
687 // Part of binary is determined by TableGn.
688 unsigned Binary = getBinaryCodeForInstr(MI);
690 // Set the conditional execution predicate
691 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
696 // Special handling for implicit use (e.g. PC).
697 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
698 << ARMII::RegRdShift);
700 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
702 // Set second operand
704 // Special handling for implicit use (e.g. PC).
705 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
706 << ARMII::RegRnShift);
708 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
710 // If this is a two-address operand, skip it. e.g. LDR_PRE.
711 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
714 const MachineOperand &MO2 = MI.getOperand(OpIdx);
715 unsigned AM2Opc = (ImplicitRn == ARM::PC)
716 ? 0 : MI.getOperand(OpIdx+1).getImm();
718 // Set bit U(23) according to sign of immed value (positive or negative).
719 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
721 if (!MO2.getReg()) { // is immediate
722 if (ARM_AM::getAM2Offset(AM2Opc))
723 // Set the value of offset_12 field
724 Binary |= ARM_AM::getAM2Offset(AM2Opc);
729 // Set bit I(25), because this is not in immediate enconding.
730 Binary |= 1 << ARMII::I_BitShift;
731 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
732 // Set bit[3:0] to the corresponding Rm register
733 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
735 // if this instr is in scaled register offset/index instruction, set
736 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
737 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
738 Binary |= getShiftOp(AM2Opc) << 5; // shift
739 Binary |= ShImm << 7; // shift_immed
745 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
746 unsigned ImplicitRn) {
747 const TargetInstrDesc &TID = MI.getDesc();
749 // Part of binary is determined by TableGn.
750 unsigned Binary = getBinaryCodeForInstr(MI);
752 // Set the conditional execution predicate
753 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
756 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
758 // Set second operand
761 // Special handling for implicit use (e.g. PC).
762 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
763 << ARMII::RegRnShift);
765 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
767 // If this is a two-address operand, skip it. e.g. LDRH_POST.
768 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
771 const MachineOperand &MO2 = MI.getOperand(OpIdx);
772 unsigned AM3Opc = (ImplicitRn == ARM::PC)
773 ? 0 : MI.getOperand(OpIdx+1).getImm();
775 // Set bit U(23) according to sign of immed value (positive or negative)
776 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
779 // If this instr is in register offset/index encoding, set bit[3:0]
780 // to the corresponding Rm register.
782 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
787 // This instr is in immediate offset/index encoding, set bit 22 to 1.
788 Binary |= 1 << ARMII::AM3_I_BitShift;
789 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
791 Binary |= (ImmOffs >> 4) << 8; // immedH
792 Binary |= (ImmOffs & ~0xF); // immedL
798 static unsigned getAddrModeUPBits(unsigned Mode) {
801 // Set addressing mode by modifying bits U(23) and P(24)
802 // IA - Increment after - bit U = 1 and bit P = 0
803 // IB - Increment before - bit U = 1 and bit P = 1
804 // DA - Decrement after - bit U = 0 and bit P = 0
805 // DB - Decrement before - bit U = 0 and bit P = 1
807 default: assert(0 && "Unknown addressing sub-mode!");
808 case ARM_AM::da: break;
809 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
810 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
811 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
817 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
818 // Part of binary is determined by TableGn.
819 unsigned Binary = getBinaryCodeForInstr(MI);
821 // Set the conditional execution predicate
822 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
824 // Set base address operand
825 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
827 // Set addressing mode by modifying bits U(23) and P(24)
828 const MachineOperand &MO = MI.getOperand(1);
829 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
832 if (ARM_AM::getAM4WBFlag(MO.getImm()))
833 Binary |= 0x1 << ARMII::W_BitShift;
836 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
837 const MachineOperand &MO = MI.getOperand(i);
838 if (!MO.isReg() || MO.isImplicit())
840 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
841 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
843 Binary |= 0x1 << RegNum;
849 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
850 const TargetInstrDesc &TID = MI.getDesc();
852 // Part of binary is determined by TableGn.
853 unsigned Binary = getBinaryCodeForInstr(MI);
855 // Set the conditional execution predicate
856 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
858 // Encode S bit if MI modifies CPSR.
859 Binary |= getAddrModeSBit(MI, TID);
861 // 32x32->64bit operations have two destination registers. The number
862 // of register definitions will tell us if that's what we're dealing with.
864 if (TID.getNumDefs() == 2)
865 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
868 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
871 Binary |= getMachineOpValue(MI, OpIdx++);
874 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
876 // Many multiple instructions (e.g. MLA) have three src operands. Encode
877 // it as Rn (for multiply, that's in the same offset as RdLo.
878 if (TID.getNumOperands() > OpIdx &&
879 !TID.OpInfo[OpIdx].isPredicate() &&
880 !TID.OpInfo[OpIdx].isOptionalDef())
881 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
886 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
887 const TargetInstrDesc &TID = MI.getDesc();
889 // Part of binary is determined by TableGn.
890 unsigned Binary = getBinaryCodeForInstr(MI);
892 // Set the conditional execution predicate
893 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
898 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
900 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
901 const MachineOperand &MO2 = MI.getOperand(OpIdx);
903 // Two register operand form.
905 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
908 Binary |= getMachineOpValue(MI, MO2);
911 Binary |= getMachineOpValue(MI, MO1);
914 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
915 if (MI.getOperand(OpIdx).isImm() &&
916 !TID.OpInfo[OpIdx].isPredicate() &&
917 !TID.OpInfo[OpIdx].isOptionalDef())
918 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
923 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
924 const TargetInstrDesc &TID = MI.getDesc();
926 // Part of binary is determined by TableGn.
927 unsigned Binary = getBinaryCodeForInstr(MI);
929 // Set the conditional execution predicate
930 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
935 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
937 const MachineOperand &MO = MI.getOperand(OpIdx++);
938 if (OpIdx == TID.getNumOperands() ||
939 TID.OpInfo[OpIdx].isPredicate() ||
940 TID.OpInfo[OpIdx].isOptionalDef()) {
941 // Encode Rm and it's done.
942 Binary |= getMachineOpValue(MI, MO);
948 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
951 Binary |= getMachineOpValue(MI, OpIdx++);
954 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
955 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
956 Binary |= ShiftAmt << ARMII::ShiftShift;
961 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
962 const TargetInstrDesc &TID = MI.getDesc();
964 if (TID.Opcode == ARM::TPsoft)
967 // Part of binary is determined by TableGn.
968 unsigned Binary = getBinaryCodeForInstr(MI);
970 // Set the conditional execution predicate
971 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
973 // Set signed_immed_24 field
974 Binary |= getMachineOpValue(MI, 0);
979 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
980 // Remember the base address of the inline jump table.
981 intptr_t JTBase = MCE.getCurrentPCValue();
982 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
983 DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
985 // Now emit the jump table entries.
986 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
987 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
989 // DestBB address - JT base.
990 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
992 // Absolute DestBB address.
993 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
998 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
999 const TargetInstrDesc &TID = MI.getDesc();
1001 // Handle jump tables.
1002 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1003 // First emit a ldr pc, [] instruction.
1004 emitDataProcessingInstruction(MI, ARM::PC);
1006 // Then emit the inline jump table.
1007 unsigned JTIndex = (TID.Opcode == ARM::BR_JTr)
1008 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1009 emitInlineJumpTable(JTIndex);
1011 } else if (TID.Opcode == ARM::BR_JTm) {
1012 // First emit a ldr pc, [] instruction.
1013 emitLoadStoreInstruction(MI, ARM::PC);
1015 // Then emit the inline jump table.
1016 emitInlineJumpTable(MI.getOperand(3).getIndex());
1020 // Part of binary is determined by TableGn.
1021 unsigned Binary = getBinaryCodeForInstr(MI);
1023 // Set the conditional execution predicate
1024 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1026 if (TID.Opcode == ARM::BX_RET)
1027 // The return register is LR.
1028 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1030 // otherwise, set the return register
1031 Binary |= getMachineOpValue(MI, 0);
1036 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1037 const TargetInstrDesc &TID = MI.getDesc();
1039 // Part of binary is determined by TableGn.
1040 unsigned Binary = getBinaryCodeForInstr(MI);
1042 // Set the conditional execution predicate
1043 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1046 assert((Binary & ARMII::D_BitShift) == 0 &&
1047 (Binary & ARMII::N_BitShift) == 0 &&
1048 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1051 unsigned RegD = getMachineOpValue(MI, OpIdx++);
1052 Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
1053 Binary |= (RegD & 0x10) << ARMII::D_BitShift;
1055 // If this is a two-address operand, skip it, e.g. FMACD.
1056 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1060 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) {
1061 unsigned RegN = getMachineOpValue(MI, OpIdx++);
1062 Binary |= (RegN & 0x0f) << ARMII::RegRnShift;
1063 Binary |= (RegN & 0x10) << ARMII::N_BitShift;
1067 unsigned RegM = getMachineOpValue(MI, OpIdx++);
1068 Binary |= (RegM & 0x0f);
1069 Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1074 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1075 const TargetInstrDesc &TID = MI.getDesc();
1077 // Part of binary is determined by TableGn.
1078 unsigned Binary = getBinaryCodeForInstr(MI);
1080 // Set the conditional execution predicate
1081 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1086 unsigned RegD = getMachineOpValue(MI, OpIdx++);
1087 Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
1088 Binary |= (RegD & 0x10) << ARMII::D_BitShift;
1091 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPConv1Frm) {
1092 unsigned RegN = getMachineOpValue(MI, OpIdx++);
1093 Binary |= (RegN & 0x0f) << ARMII::RegRnShift;
1094 Binary |= (RegN & 0x10) << ARMII::N_BitShift;
1096 // FMRS / FMSR do not have Rm.
1097 if (!TID.OpInfo[2].isPredicate()) {
1098 unsigned RegM = getMachineOpValue(MI, OpIdx++);
1099 Binary |= (RegM & 0x0f);
1100 Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1103 unsigned RegM = getMachineOpValue(MI, OpIdx++);
1104 Binary |= (RegM & 0x0f);
1105 Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1111 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1112 // Part of binary is determined by TableGn.
1113 unsigned Binary = getBinaryCodeForInstr(MI);
1115 // Set the conditional execution predicate
1116 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1121 unsigned RegD = getMachineOpValue(MI, OpIdx++);
1122 Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
1123 Binary |= (RegD & 0x10) << ARMII::D_BitShift;
1125 // Encode address base.
1126 const MachineOperand &Base = MI.getOperand(OpIdx++);
1127 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1129 // If there is a non-zero immediate offset, encode it.
1131 const MachineOperand &Offset = MI.getOperand(OpIdx);
1132 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1133 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1134 Binary |= 1 << ARMII::U_BitShift;
1135 // Immediate offset is multiplied by 4.
1136 Binary |= ImmOffs >> 2;
1142 // If immediate offset is omitted, default to +0.
1143 Binary |= 1 << ARMII::U_BitShift;
1149 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1150 // Part of binary is determined by TableGn.
1151 unsigned Binary = getBinaryCodeForInstr(MI);
1153 // Set the conditional execution predicate
1154 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1156 // Set base address operand
1157 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1159 // Set addressing mode by modifying bits U(23) and P(24)
1160 const MachineOperand &MO = MI.getOperand(1);
1161 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1164 if (ARM_AM::getAM5WBFlag(MO.getImm()))
1165 Binary |= 0x1 << ARMII::W_BitShift;
1167 // First register is encoded in Dd.
1168 unsigned FirstReg = MI.getOperand(4).getReg();
1169 Binary |= ARMRegisterInfo::getRegisterNumbering(FirstReg)<< ARMII::RegRdShift;
1171 // Number of registers are encoded in offset field.
1172 unsigned NumRegs = 1;
1173 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1174 const MachineOperand &MO = MI.getOperand(i);
1175 if (!MO.isReg() || MO.isImplicit())
1179 Binary |= NumRegs * 2;
1184 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1185 // Part of binary is determined by TableGn.
1186 unsigned Binary = getBinaryCodeForInstr(MI);
1188 // Set the conditional execution predicate
1189 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1194 #include "ARMGenCodeEmitter.inc"