1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
166 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
168 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
170 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
172 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
179 unsigned Op) const { return 0; }
180 uint32_t getAddrModeImmOpValue(const MachineInstr &MI, unsigned Op) const {
182 // {16} = (U)nsigned (add == '1', sub == '0')
184 const MachineOperand &MO = MI.getOperand(Op);
185 const MachineOperand &MO1 = MI.getOperand(Op + 1);
187 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
191 unsigned Reg = getARMRegisterNumbering(MO.getReg());
192 int32_t Imm = MO1.getImm();
194 Binary = Imm & 0xffff;
198 Binary |= (Reg << 17);
201 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
204 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
207 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
208 /// machine operand requires relocation, record the relocation and return
210 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
213 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
215 unsigned getShiftOp(unsigned Imm) const ;
217 /// Routines that handle operands which add machine relocations which are
218 /// fixed up by the relocation stage.
219 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
220 bool MayNeedFarStub, bool Indirect,
221 intptr_t ACPV = 0) const;
222 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
223 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
224 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
225 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
226 intptr_t JTBase = 0) const;
230 char ARMCodeEmitter::ID = 0;
232 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
233 /// code to the specified MCE object.
234 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
235 JITCodeEmitter &JCE) {
236 return new ARMCodeEmitter(TM, JCE);
239 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
240 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
241 MF.getTarget().getRelocationModel() != Reloc::Static) &&
242 "JIT relocation model must be set to static or default!");
243 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
244 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
245 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
246 Subtarget = &TM.getSubtarget<ARMSubtarget>();
247 MCPEs = &MF.getConstantPool()->getConstants();
249 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
250 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
251 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
252 JTI->Initialize(MF, IsPIC);
253 MMI = &getAnalysis<MachineModuleInfo>();
254 MCE.setModuleInfo(MMI);
257 DEBUG(errs() << "JITTing function '"
258 << MF.getFunction()->getName() << "'\n");
259 MCE.startFunction(MF);
260 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
262 MCE.StartMachineBasicBlock(MBB);
263 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
267 } while (MCE.finishFunction(MF));
272 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
274 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
275 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
276 default: llvm_unreachable("Unknown shift opc!");
277 case ARM_AM::asr: return 2;
278 case ARM_AM::lsl: return 0;
279 case ARM_AM::lsr: return 1;
281 case ARM_AM::rrx: return 3;
286 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
287 /// machine operand requires relocation, record the relocation and return zero.
288 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
289 const MachineOperand &MO,
291 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
292 && "Relocation to this function should be for movt or movw");
295 return static_cast<unsigned>(MO.getImm());
296 else if (MO.isGlobal())
297 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
298 else if (MO.isSymbol())
299 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
301 emitMachineBasicBlock(MO.getMBB(), Reloc);
306 llvm_unreachable("Unsupported operand type for movw/movt");
311 /// getMachineOpValue - Return binary encoding of operand. If the machine
312 /// operand requires relocation, record the relocation and return zero.
313 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
314 const MachineOperand &MO) const {
316 return getARMRegisterNumbering(MO.getReg());
318 return static_cast<unsigned>(MO.getImm());
319 else if (MO.isGlobal())
320 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
321 else if (MO.isSymbol())
322 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
323 else if (MO.isCPI()) {
324 const TargetInstrDesc &TID = MI.getDesc();
325 // For VFP load, the immediate offset is multiplied by 4.
326 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
327 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
328 emitConstPoolAddress(MO.getIndex(), Reloc);
329 } else if (MO.isJTI())
330 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
332 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
342 /// emitGlobalAddress - Emit the specified address to the code stream.
344 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
345 bool MayNeedFarStub, bool Indirect,
346 intptr_t ACPV) const {
347 MachineRelocation MR = Indirect
348 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
349 const_cast<GlobalValue *>(GV),
350 ACPV, MayNeedFarStub)
351 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
352 const_cast<GlobalValue *>(GV), ACPV,
354 MCE.addRelocation(MR);
357 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
358 /// be emitted to the current location in the function, and allow it to be PC
360 void ARMCodeEmitter::
361 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
362 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
366 /// emitConstPoolAddress - Arrange for the address of an constant pool
367 /// to be emitted to the current location in the function, and allow it to be PC
369 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
370 // Tell JIT emitter we'll resolve the address.
371 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
372 Reloc, CPI, 0, true));
375 /// emitJumpTableAddress - Arrange for the address of a jump table to
376 /// be emitted to the current location in the function, and allow it to be PC
378 void ARMCodeEmitter::
379 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
380 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
381 Reloc, JTIndex, 0, true));
384 /// emitMachineBasicBlock - Emit the specified address basic block.
385 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
387 intptr_t JTBase) const {
388 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
392 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
393 DEBUG(errs() << " 0x";
394 errs().write_hex(Binary) << "\n");
395 MCE.emitWordLE(Binary);
398 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
399 DEBUG(errs() << " 0x";
400 errs().write_hex(Binary) << "\n");
401 MCE.emitDWordLE(Binary);
404 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
405 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
407 MCE.processDebugLoc(MI.getDebugLoc(), true);
409 ++NumEmitted; // Keep track of the # of mi's emitted
410 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
412 llvm_unreachable("Unhandled instruction encoding format!");
416 emitPseudoInstruction(MI);
419 case ARMII::DPSoRegFrm:
420 emitDataProcessingInstruction(MI);
424 emitLoadStoreInstruction(MI);
426 case ARMII::LdMiscFrm:
427 case ARMII::StMiscFrm:
428 emitMiscLoadStoreInstruction(MI);
430 case ARMII::LdStMulFrm:
431 emitLoadStoreMultipleInstruction(MI);
434 emitMulFrmInstruction(MI);
437 emitExtendInstruction(MI);
439 case ARMII::ArithMiscFrm:
440 emitMiscArithInstruction(MI);
443 emitSaturateInstruction(MI);
446 emitBranchInstruction(MI);
448 case ARMII::BrMiscFrm:
449 emitMiscBranchInstruction(MI);
452 case ARMII::VFPUnaryFrm:
453 case ARMII::VFPBinaryFrm:
454 emitVFPArithInstruction(MI);
456 case ARMII::VFPConv1Frm:
457 case ARMII::VFPConv2Frm:
458 case ARMII::VFPConv3Frm:
459 case ARMII::VFPConv4Frm:
460 case ARMII::VFPConv5Frm:
461 emitVFPConversionInstruction(MI);
463 case ARMII::VFPLdStFrm:
464 emitVFPLoadStoreInstruction(MI);
466 case ARMII::VFPLdStMulFrm:
467 emitVFPLoadStoreMultipleInstruction(MI);
470 // NEON instructions.
471 case ARMII::NGetLnFrm:
472 case ARMII::NSetLnFrm:
473 emitNEONLaneInstruction(MI);
476 emitNEONDupInstruction(MI);
478 case ARMII::N1RegModImmFrm:
479 emitNEON1RegModImmInstruction(MI);
481 case ARMII::N2RegFrm:
482 emitNEON2RegInstruction(MI);
484 case ARMII::N3RegFrm:
485 emitNEON3RegInstruction(MI);
488 MCE.processDebugLoc(MI.getDebugLoc(), false);
491 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
492 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
493 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
494 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
496 // Remember the CONSTPOOL_ENTRY address for later relocation.
497 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
499 // Emit constpool island entry. In most cases, the actual values will be
500 // resolved and relocated after code emission.
501 if (MCPE.isMachineConstantPoolEntry()) {
502 ARMConstantPoolValue *ACPV =
503 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
505 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
506 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
508 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
509 const GlobalValue *GV = ACPV->getGV();
511 Reloc::Model RelocM = TM.getRelocationModel();
512 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
514 Subtarget->GVIsIndirectSymbol(GV, RelocM),
517 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
521 const Constant *CV = MCPE.Val.ConstVal;
524 errs() << " ** Constant pool #" << CPI << " @ "
525 << (void*)MCE.getCurrentPCValue() << " ";
526 if (const Function *F = dyn_cast<Function>(CV))
527 errs() << F->getName();
533 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
534 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
536 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
537 uint32_t Val = uint32_t(*CI->getValue().getRawData());
539 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
540 if (CFP->getType()->isFloatTy())
541 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
542 else if (CFP->getType()->isDoubleTy())
543 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
545 llvm_unreachable("Unable to handle this constantpool entry!");
548 llvm_unreachable("Unable to handle this constantpool entry!");
553 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
554 const MachineOperand &MO0 = MI.getOperand(0);
555 const MachineOperand &MO1 = MI.getOperand(1);
557 // Emit the 'movw' instruction.
558 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
560 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
562 // Set the conditional execution predicate.
563 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
566 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
568 // Encode imm16 as imm4:imm12
569 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
570 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
573 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
574 // Emit the 'movt' instruction.
575 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
577 // Set the conditional execution predicate.
578 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
581 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
583 // Encode imm16 as imm4:imm1, same as movw above.
584 Binary |= Hi16 & 0xFFF;
585 Binary |= ((Hi16 >> 12) & 0xF) << 16;
589 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
590 const MachineOperand &MO0 = MI.getOperand(0);
591 const MachineOperand &MO1 = MI.getOperand(1);
592 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
593 "Not a valid so_imm value!");
594 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
595 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
597 // Emit the 'mov' instruction.
598 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
600 // Set the conditional execution predicate.
601 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
604 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
607 // Set bit I(25) to identify this is the immediate form of <shifter_op>
608 Binary |= 1 << ARMII::I_BitShift;
609 Binary |= getMachineSoImmOpValue(V1);
612 // Now the 'orr' instruction.
613 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
615 // Set the conditional execution predicate.
616 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
619 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
622 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
625 // Set bit I(25) to identify this is the immediate form of <shifter_op>
626 Binary |= 1 << ARMII::I_BitShift;
627 Binary |= getMachineSoImmOpValue(V2);
631 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
632 // It's basically add r, pc, (LJTI - $+8)
634 const TargetInstrDesc &TID = MI.getDesc();
636 // Emit the 'add' instruction.
637 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
639 // Set the conditional execution predicate
640 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
642 // Encode S bit if MI modifies CPSR.
643 Binary |= getAddrModeSBit(MI, TID);
646 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
648 // Encode Rn which is PC.
649 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
651 // Encode the displacement.
652 Binary |= 1 << ARMII::I_BitShift;
653 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
658 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
659 unsigned Opcode = MI.getDesc().Opcode;
661 // Part of binary is determined by TableGn.
662 unsigned Binary = getBinaryCodeForInstr(MI);
664 // Set the conditional execution predicate
665 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
667 // Encode S bit if MI modifies CPSR.
668 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
669 Binary |= 1 << ARMII::S_BitShift;
671 // Encode register def if there is one.
672 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
674 // Encode the shift operation.
681 case ARM::MOVsrl_flag:
683 Binary |= (0x2 << 4) | (1 << 7);
685 case ARM::MOVsra_flag:
687 Binary |= (0x4 << 4) | (1 << 7);
691 // Encode register Rm.
692 Binary |= getMachineOpValue(MI, 1);
697 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
698 DEBUG(errs() << " ** LPC" << LabelID << " @ "
699 << (void*)MCE.getCurrentPCValue() << '\n');
700 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
703 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
704 unsigned Opcode = MI.getDesc().Opcode;
707 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
711 case ARM::BMOVPCRXr9: {
712 // First emit mov lr, pc
713 unsigned Binary = 0x01a0e00f;
714 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
717 // and then emit the branch.
718 emitMiscBranchInstruction(MI);
721 case TargetOpcode::INLINEASM: {
722 // We allow inline assembler nodes with empty bodies - they can
723 // implicitly define registers, which is ok for JIT.
724 if (MI.getOperand(0).getSymbolName()[0]) {
725 report_fatal_error("JIT does not support inline asm!");
729 case TargetOpcode::PROLOG_LABEL:
730 case TargetOpcode::EH_LABEL:
731 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
733 case TargetOpcode::IMPLICIT_DEF:
734 case TargetOpcode::KILL:
737 case ARM::CONSTPOOL_ENTRY:
738 emitConstPoolInstruction(MI);
741 // Remember of the address of the PC label for relocation later.
742 addPCLabel(MI.getOperand(2).getImm());
743 // PICADD is just an add instruction that implicitly read pc.
744 emitDataProcessingInstruction(MI, 0, ARM::PC);
751 // Remember of the address of the PC label for relocation later.
752 addPCLabel(MI.getOperand(2).getImm());
753 // These are just load / store instructions that implicitly read pc.
754 emitLoadStoreInstruction(MI, 0, ARM::PC);
761 // Remember of the address of the PC label for relocation later.
762 addPCLabel(MI.getOperand(2).getImm());
763 // These are just load / store instructions that implicitly read pc.
764 emitMiscLoadStoreInstruction(MI, ARM::PC);
769 emitMOVi32immInstruction(MI);
772 case ARM::MOVi2pieces:
773 // Two instructions to materialize a constant.
774 emitMOVi2piecesInstruction(MI);
776 case ARM::LEApcrelJT:
777 // Materialize jumptable address.
778 emitLEApcrelJTInstruction(MI);
781 case ARM::MOVsrl_flag:
782 case ARM::MOVsra_flag:
783 emitPseudoMoveInstruction(MI);
788 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
789 const TargetInstrDesc &TID,
790 const MachineOperand &MO,
792 unsigned Binary = getMachineOpValue(MI, MO);
794 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
795 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
796 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
798 // Encode the shift opcode.
800 unsigned Rs = MO1.getReg();
802 // Set shift operand (bit[7:4]).
807 // RRX - 0110 and bit[11:8] clear.
809 default: llvm_unreachable("Unknown shift opc!");
810 case ARM_AM::lsl: SBits = 0x1; break;
811 case ARM_AM::lsr: SBits = 0x3; break;
812 case ARM_AM::asr: SBits = 0x5; break;
813 case ARM_AM::ror: SBits = 0x7; break;
814 case ARM_AM::rrx: SBits = 0x6; break;
817 // Set shift operand (bit[6:4]).
823 default: llvm_unreachable("Unknown shift opc!");
824 case ARM_AM::lsl: SBits = 0x0; break;
825 case ARM_AM::lsr: SBits = 0x2; break;
826 case ARM_AM::asr: SBits = 0x4; break;
827 case ARM_AM::ror: SBits = 0x6; break;
830 Binary |= SBits << 4;
831 if (SOpc == ARM_AM::rrx)
834 // Encode the shift operation Rs or shift_imm (except rrx).
836 // Encode Rs bit[11:8].
837 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
838 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
841 // Encode shift_imm bit[11:7].
842 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
845 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
846 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
847 assert(SoImmVal != -1 && "Not a valid so_imm value!");
849 // Encode rotate_imm.
850 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
851 << ARMII::SoRotImmShift;
854 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
858 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
859 const TargetInstrDesc &TID) const {
860 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
861 const MachineOperand &MO = MI.getOperand(i-1);
862 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
863 return 1 << ARMII::S_BitShift;
868 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
870 unsigned ImplicitRn) {
871 const TargetInstrDesc &TID = MI.getDesc();
873 // Part of binary is determined by TableGn.
874 unsigned Binary = getBinaryCodeForInstr(MI);
876 // Set the conditional execution predicate
877 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
879 // Encode S bit if MI modifies CPSR.
880 Binary |= getAddrModeSBit(MI, TID);
882 // Encode register def if there is one.
883 unsigned NumDefs = TID.getNumDefs();
886 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
888 // Special handling for implicit use (e.g. PC).
889 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
891 if (TID.Opcode == ARM::MOVi16) {
892 // Get immediate from MI.
893 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
894 ARM::reloc_arm_movw);
895 // Encode imm which is the same as in emitMOVi32immInstruction().
896 Binary |= Lo16 & 0xFFF;
897 Binary |= ((Lo16 >> 12) & 0xF) << 16;
900 } else if(TID.Opcode == ARM::MOVTi16) {
901 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
902 ARM::reloc_arm_movt) >> 16);
903 Binary |= Hi16 & 0xFFF;
904 Binary |= ((Hi16 >> 12) & 0xF) << 16;
907 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
908 uint32_t v = ~MI.getOperand(2).getImm();
909 int32_t lsb = CountTrailingZeros_32(v);
910 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
911 // Instr{20-16} = msb, Instr{11-7} = lsb
912 Binary |= (msb & 0x1F) << 16;
913 Binary |= (lsb & 0x1F) << 7;
916 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
917 // Encode Rn in Instr{0-3}
918 Binary |= getMachineOpValue(MI, OpIdx++);
920 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
921 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
923 // Instr{20-16} = widthm1, Instr{11-7} = lsb
924 Binary |= (widthm1 & 0x1F) << 16;
925 Binary |= (lsb & 0x1F) << 7;
930 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
931 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
934 // Encode first non-shifter register operand if there is one.
935 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
938 // Special handling for implicit use (e.g. PC).
939 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
941 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
946 // Encode shifter operand.
947 const MachineOperand &MO = MI.getOperand(OpIdx);
948 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
950 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
955 // Encode register Rm.
956 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
961 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
966 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
968 unsigned ImplicitRn) {
969 const TargetInstrDesc &TID = MI.getDesc();
970 unsigned Form = TID.TSFlags & ARMII::FormMask;
971 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
973 // Part of binary is determined by TableGn.
974 unsigned Binary = getBinaryCodeForInstr(MI);
976 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
977 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
978 MI.getOpcode() == ARM::STRi12) {
983 // Set the conditional execution predicate
984 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
988 // Operand 0 of a pre- and post-indexed store is the address base
989 // writeback. Skip it.
990 bool Skipped = false;
991 if (IsPrePost && Form == ARMII::StFrm) {
998 // Special handling for implicit use (e.g. PC).
999 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1001 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1003 // Set second operand
1005 // Special handling for implicit use (e.g. PC).
1006 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1008 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1010 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1011 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1014 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1015 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1016 ? 0 : MI.getOperand(OpIdx+1).getImm();
1018 // Set bit U(23) according to sign of immed value (positive or negative).
1019 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1021 if (!MO2.getReg()) { // is immediate
1022 if (ARM_AM::getAM2Offset(AM2Opc))
1023 // Set the value of offset_12 field
1024 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1029 // Set bit I(25), because this is not in immediate encoding.
1030 Binary |= 1 << ARMII::I_BitShift;
1031 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1032 // Set bit[3:0] to the corresponding Rm register
1033 Binary |= getARMRegisterNumbering(MO2.getReg());
1035 // If this instr is in scaled register offset/index instruction, set
1036 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1037 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1038 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1039 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1045 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1046 unsigned ImplicitRn) {
1047 const TargetInstrDesc &TID = MI.getDesc();
1048 unsigned Form = TID.TSFlags & ARMII::FormMask;
1049 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1051 // Part of binary is determined by TableGn.
1052 unsigned Binary = getBinaryCodeForInstr(MI);
1054 // Set the conditional execution predicate
1055 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1059 // Operand 0 of a pre- and post-indexed store is the address base
1060 // writeback. Skip it.
1061 bool Skipped = false;
1062 if (IsPrePost && Form == ARMII::StMiscFrm) {
1067 // Set first operand
1068 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1070 // Skip LDRD and STRD's second operand.
1071 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1074 // Set second operand
1076 // Special handling for implicit use (e.g. PC).
1077 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1079 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1081 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1082 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1085 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1086 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1087 ? 0 : MI.getOperand(OpIdx+1).getImm();
1089 // Set bit U(23) according to sign of immed value (positive or negative)
1090 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1093 // If this instr is in register offset/index encoding, set bit[3:0]
1094 // to the corresponding Rm register.
1096 Binary |= getARMRegisterNumbering(MO2.getReg());
1101 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1102 Binary |= 1 << ARMII::AM3_I_BitShift;
1103 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1105 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1106 Binary |= (ImmOffs & 0xF); // immedL
1112 static unsigned getAddrModeUPBits(unsigned Mode) {
1113 unsigned Binary = 0;
1115 // Set addressing mode by modifying bits U(23) and P(24)
1116 // IA - Increment after - bit U = 1 and bit P = 0
1117 // IB - Increment before - bit U = 1 and bit P = 1
1118 // DA - Decrement after - bit U = 0 and bit P = 0
1119 // DB - Decrement before - bit U = 0 and bit P = 1
1121 default: llvm_unreachable("Unknown addressing sub-mode!");
1122 case ARM_AM::da: break;
1123 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1124 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1125 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1131 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1132 const TargetInstrDesc &TID = MI.getDesc();
1133 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1135 // Part of binary is determined by TableGn.
1136 unsigned Binary = getBinaryCodeForInstr(MI);
1138 // Set the conditional execution predicate
1139 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1141 // Skip operand 0 of an instruction with base register update.
1146 // Set base address operand
1147 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1149 // Set addressing mode by modifying bits U(23) and P(24)
1150 const MachineOperand &MO = MI.getOperand(OpIdx++);
1151 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1155 Binary |= 0x1 << ARMII::W_BitShift;
1158 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1159 const MachineOperand &MO = MI.getOperand(i);
1160 if (!MO.isReg() || MO.isImplicit())
1162 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1163 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1165 Binary |= 0x1 << RegNum;
1171 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1172 const TargetInstrDesc &TID = MI.getDesc();
1174 // Part of binary is determined by TableGn.
1175 unsigned Binary = getBinaryCodeForInstr(MI);
1177 // Set the conditional execution predicate
1178 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1180 // Encode S bit if MI modifies CPSR.
1181 Binary |= getAddrModeSBit(MI, TID);
1183 // 32x32->64bit operations have two destination registers. The number
1184 // of register definitions will tell us if that's what we're dealing with.
1186 if (TID.getNumDefs() == 2)
1187 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1190 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1193 Binary |= getMachineOpValue(MI, OpIdx++);
1196 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1198 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1199 // it as Rn (for multiply, that's in the same offset as RdLo.
1200 if (TID.getNumOperands() > OpIdx &&
1201 !TID.OpInfo[OpIdx].isPredicate() &&
1202 !TID.OpInfo[OpIdx].isOptionalDef())
1203 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1208 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1209 const TargetInstrDesc &TID = MI.getDesc();
1211 // Part of binary is determined by TableGn.
1212 unsigned Binary = getBinaryCodeForInstr(MI);
1214 // Set the conditional execution predicate
1215 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1220 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1222 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1223 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1225 // Two register operand form.
1227 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1230 Binary |= getMachineOpValue(MI, MO2);
1233 Binary |= getMachineOpValue(MI, MO1);
1236 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1237 if (MI.getOperand(OpIdx).isImm() &&
1238 !TID.OpInfo[OpIdx].isPredicate() &&
1239 !TID.OpInfo[OpIdx].isOptionalDef())
1240 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1245 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1246 const TargetInstrDesc &TID = MI.getDesc();
1248 // Part of binary is determined by TableGn.
1249 unsigned Binary = getBinaryCodeForInstr(MI);
1251 // Set the conditional execution predicate
1252 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1257 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1259 const MachineOperand &MO = MI.getOperand(OpIdx++);
1260 if (OpIdx == TID.getNumOperands() ||
1261 TID.OpInfo[OpIdx].isPredicate() ||
1262 TID.OpInfo[OpIdx].isOptionalDef()) {
1263 // Encode Rm and it's done.
1264 Binary |= getMachineOpValue(MI, MO);
1270 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1273 Binary |= getMachineOpValue(MI, OpIdx++);
1275 // Encode shift_imm.
1276 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1277 if (TID.Opcode == ARM::PKHTB) {
1278 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1282 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1283 Binary |= ShiftAmt << ARMII::ShiftShift;
1288 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1289 const TargetInstrDesc &TID = MI.getDesc();
1291 // Part of binary is determined by TableGen.
1292 unsigned Binary = getBinaryCodeForInstr(MI);
1294 // Set the conditional execution predicate
1295 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1298 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1300 // Encode saturate bit position.
1301 unsigned Pos = MI.getOperand(1).getImm();
1302 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1304 assert((Pos < 16 || (Pos < 32 &&
1305 TID.Opcode != ARM::SSAT16 &&
1306 TID.Opcode != ARM::USAT16)) &&
1307 "saturate bit position out of range");
1308 Binary |= Pos << 16;
1311 Binary |= getMachineOpValue(MI, 2);
1313 // Encode shift_imm.
1314 if (TID.getNumOperands() == 4) {
1315 unsigned ShiftOp = MI.getOperand(3).getImm();
1316 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1317 if (Opc == ARM_AM::asr)
1319 unsigned ShiftAmt = MI.getOperand(3).getImm();
1320 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1322 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1323 Binary |= ShiftAmt << ARMII::ShiftShift;
1329 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1330 const TargetInstrDesc &TID = MI.getDesc();
1332 if (TID.Opcode == ARM::TPsoft) {
1333 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1336 // Part of binary is determined by TableGn.
1337 unsigned Binary = getBinaryCodeForInstr(MI);
1339 // Set the conditional execution predicate
1340 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1342 // Set signed_immed_24 field
1343 Binary |= getMachineOpValue(MI, 0);
1348 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1349 // Remember the base address of the inline jump table.
1350 uintptr_t JTBase = MCE.getCurrentPCValue();
1351 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1352 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1355 // Now emit the jump table entries.
1356 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1357 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1359 // DestBB address - JT base.
1360 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1362 // Absolute DestBB address.
1363 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1368 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1369 const TargetInstrDesc &TID = MI.getDesc();
1371 // Handle jump tables.
1372 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1373 // First emit a ldr pc, [] instruction.
1374 emitDataProcessingInstruction(MI, ARM::PC);
1376 // Then emit the inline jump table.
1378 (TID.Opcode == ARM::BR_JTr)
1379 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1380 emitInlineJumpTable(JTIndex);
1382 } else if (TID.Opcode == ARM::BR_JTm) {
1383 // First emit a ldr pc, [] instruction.
1384 emitLoadStoreInstruction(MI, ARM::PC);
1386 // Then emit the inline jump table.
1387 emitInlineJumpTable(MI.getOperand(3).getIndex());
1391 // Part of binary is determined by TableGn.
1392 unsigned Binary = getBinaryCodeForInstr(MI);
1394 // Set the conditional execution predicate
1395 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1397 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1398 // The return register is LR.
1399 Binary |= getARMRegisterNumbering(ARM::LR);
1401 // otherwise, set the return register
1402 Binary |= getMachineOpValue(MI, 0);
1407 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1408 unsigned RegD = MI.getOperand(OpIdx).getReg();
1409 unsigned Binary = 0;
1410 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1411 RegD = getARMRegisterNumbering(RegD);
1413 Binary |= RegD << ARMII::RegRdShift;
1415 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1416 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1421 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1422 unsigned RegN = MI.getOperand(OpIdx).getReg();
1423 unsigned Binary = 0;
1424 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1425 RegN = getARMRegisterNumbering(RegN);
1427 Binary |= RegN << ARMII::RegRnShift;
1429 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1430 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1435 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1436 unsigned RegM = MI.getOperand(OpIdx).getReg();
1437 unsigned Binary = 0;
1438 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1439 RegM = getARMRegisterNumbering(RegM);
1443 Binary |= ((RegM & 0x1E) >> 1);
1444 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1449 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1450 const TargetInstrDesc &TID = MI.getDesc();
1452 // Part of binary is determined by TableGn.
1453 unsigned Binary = getBinaryCodeForInstr(MI);
1455 // Set the conditional execution predicate
1456 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1459 assert((Binary & ARMII::D_BitShift) == 0 &&
1460 (Binary & ARMII::N_BitShift) == 0 &&
1461 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1464 Binary |= encodeVFPRd(MI, OpIdx++);
1466 // If this is a two-address operand, skip it, e.g. FMACD.
1467 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1471 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1472 Binary |= encodeVFPRn(MI, OpIdx++);
1474 if (OpIdx == TID.getNumOperands() ||
1475 TID.OpInfo[OpIdx].isPredicate() ||
1476 TID.OpInfo[OpIdx].isOptionalDef()) {
1477 // FCMPEZD etc. has only one operand.
1483 Binary |= encodeVFPRm(MI, OpIdx);
1488 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1489 const TargetInstrDesc &TID = MI.getDesc();
1490 unsigned Form = TID.TSFlags & ARMII::FormMask;
1492 // Part of binary is determined by TableGn.
1493 unsigned Binary = getBinaryCodeForInstr(MI);
1495 // Set the conditional execution predicate
1496 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1500 case ARMII::VFPConv1Frm:
1501 case ARMII::VFPConv2Frm:
1502 case ARMII::VFPConv3Frm:
1504 Binary |= encodeVFPRd(MI, 0);
1506 case ARMII::VFPConv4Frm:
1508 Binary |= encodeVFPRn(MI, 0);
1510 case ARMII::VFPConv5Frm:
1512 Binary |= encodeVFPRm(MI, 0);
1518 case ARMII::VFPConv1Frm:
1520 Binary |= encodeVFPRm(MI, 1);
1522 case ARMII::VFPConv2Frm:
1523 case ARMII::VFPConv3Frm:
1525 Binary |= encodeVFPRn(MI, 1);
1527 case ARMII::VFPConv4Frm:
1528 case ARMII::VFPConv5Frm:
1530 Binary |= encodeVFPRd(MI, 1);
1534 if (Form == ARMII::VFPConv5Frm)
1536 Binary |= encodeVFPRn(MI, 2);
1537 else if (Form == ARMII::VFPConv3Frm)
1539 Binary |= encodeVFPRm(MI, 2);
1544 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1545 // Part of binary is determined by TableGn.
1546 unsigned Binary = getBinaryCodeForInstr(MI);
1548 // Set the conditional execution predicate
1549 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1554 Binary |= encodeVFPRd(MI, OpIdx++);
1556 // Encode address base.
1557 const MachineOperand &Base = MI.getOperand(OpIdx++);
1558 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1560 // If there is a non-zero immediate offset, encode it.
1562 const MachineOperand &Offset = MI.getOperand(OpIdx);
1563 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1564 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1565 Binary |= 1 << ARMII::U_BitShift;
1572 // If immediate offset is omitted, default to +0.
1573 Binary |= 1 << ARMII::U_BitShift;
1579 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1580 const TargetInstrDesc &TID = MI.getDesc();
1581 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1583 // Part of binary is determined by TableGn.
1584 unsigned Binary = getBinaryCodeForInstr(MI);
1586 // Set the conditional execution predicate
1587 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1589 // Skip operand 0 of an instruction with base register update.
1594 // Set base address operand
1595 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1597 // Set addressing mode by modifying bits U(23) and P(24)
1598 const MachineOperand &MO = MI.getOperand(OpIdx++);
1599 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1603 Binary |= 0x1 << ARMII::W_BitShift;
1605 // First register is encoded in Dd.
1606 Binary |= encodeVFPRd(MI, OpIdx+2);
1608 // Count the number of registers.
1609 unsigned NumRegs = 1;
1610 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1611 const MachineOperand &MO = MI.getOperand(i);
1612 if (!MO.isReg() || MO.isImplicit())
1616 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1617 // Otherwise, it will be 0, in the case of 32-bit registers.
1619 Binary |= NumRegs * 2;
1626 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1627 unsigned RegD = MI.getOperand(OpIdx).getReg();
1628 unsigned Binary = 0;
1629 RegD = getARMRegisterNumbering(RegD);
1630 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1631 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1635 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1636 unsigned RegN = MI.getOperand(OpIdx).getReg();
1637 unsigned Binary = 0;
1638 RegN = getARMRegisterNumbering(RegN);
1639 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1640 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1644 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1645 unsigned RegM = MI.getOperand(OpIdx).getReg();
1646 unsigned Binary = 0;
1647 RegM = getARMRegisterNumbering(RegM);
1648 Binary |= (RegM & 0xf);
1649 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1653 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1654 /// data-processing instruction to the corresponding Thumb encoding.
1655 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1656 assert((Binary & 0xfe000000) == 0xf2000000 &&
1657 "not an ARM NEON data-processing instruction");
1658 unsigned UBit = (Binary >> 24) & 1;
1659 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1662 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1663 unsigned Binary = getBinaryCodeForInstr(MI);
1665 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1666 const TargetInstrDesc &TID = MI.getDesc();
1667 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1671 } else { // ARMII::NSetLnFrm
1677 // Set the conditional execution predicate
1678 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1680 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1681 RegT = getARMRegisterNumbering(RegT);
1682 Binary |= (RegT << ARMII::RegRdShift);
1683 Binary |= encodeNEONRn(MI, RegNOpIdx);
1686 if ((Binary & (1 << 22)) != 0)
1687 LaneShift = 0; // 8-bit elements
1688 else if ((Binary & (1 << 5)) != 0)
1689 LaneShift = 1; // 16-bit elements
1691 LaneShift = 2; // 32-bit elements
1693 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1694 unsigned Opc1 = Lane >> 2;
1695 unsigned Opc2 = Lane & 3;
1696 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1697 Binary |= (Opc1 << 21);
1698 Binary |= (Opc2 << 5);
1703 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1704 unsigned Binary = getBinaryCodeForInstr(MI);
1706 // Set the conditional execution predicate
1707 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1709 unsigned RegT = MI.getOperand(1).getReg();
1710 RegT = getARMRegisterNumbering(RegT);
1711 Binary |= (RegT << ARMII::RegRdShift);
1712 Binary |= encodeNEONRn(MI, 0);
1716 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1717 unsigned Binary = getBinaryCodeForInstr(MI);
1718 // Destination register is encoded in Dd.
1719 Binary |= encodeNEONRd(MI, 0);
1720 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1721 unsigned Imm = MI.getOperand(1).getImm();
1722 unsigned Op = (Imm >> 12) & 1;
1723 unsigned Cmode = (Imm >> 8) & 0xf;
1724 unsigned I = (Imm >> 7) & 1;
1725 unsigned Imm3 = (Imm >> 4) & 0x7;
1726 unsigned Imm4 = Imm & 0xf;
1727 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1729 Binary = convertNEONDataProcToThumb(Binary);
1733 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1734 const TargetInstrDesc &TID = MI.getDesc();
1735 unsigned Binary = getBinaryCodeForInstr(MI);
1736 // Destination register is encoded in Dd; source register in Dm.
1738 Binary |= encodeNEONRd(MI, OpIdx++);
1739 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1741 Binary |= encodeNEONRm(MI, OpIdx);
1743 Binary = convertNEONDataProcToThumb(Binary);
1744 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1748 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1749 const TargetInstrDesc &TID = MI.getDesc();
1750 unsigned Binary = getBinaryCodeForInstr(MI);
1751 // Destination register is encoded in Dd; source registers in Dn and Dm.
1753 Binary |= encodeNEONRd(MI, OpIdx++);
1754 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1756 Binary |= encodeNEONRn(MI, OpIdx++);
1757 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1759 Binary |= encodeNEONRm(MI, OpIdx);
1761 Binary = convertNEONDataProcToThumb(Binary);
1762 // FIXME: This does not handle VMOVDneon or VMOVQ.
1766 #include "ARMGenCodeEmitter.inc"