1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45 cl::desc("Reuse repeated frame index values"));
48 ARMDynamicStackAlign("arm-dynamic-stack-alignment", cl::Hidden, cl::init(false),
49 cl::desc("Dynamically re-align the stack as needed"));
51 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
59 llvm_unreachable("Unknown ARM register!");
60 case R0: case D0: case Q0: return 0;
61 case R1: case D1: case Q1: return 1;
62 case R2: case D2: case Q2: return 2;
63 case R3: case D3: case Q3: return 3;
64 case R4: case D4: case Q4: return 4;
65 case R5: case D5: case Q5: return 5;
66 case R6: case D6: case Q6: return 6;
67 case R7: case D7: case Q7: return 7;
68 case R8: case D8: case Q8: return 8;
69 case R9: case D9: case Q9: return 9;
70 case R10: case D10: case Q10: return 10;
71 case R11: case D11: case Q11: return 11;
72 case R12: case D12: case Q12: return 12;
73 case SP: case D13: case Q13: return 13;
74 case LR: case D14: case Q14: return 14;
75 case PC: case D15: case Q15: return 15;
94 case S0: case S1: case S2: case S3:
95 case S4: case S5: case S6: case S7:
96 case S8: case S9: case S10: case S11:
97 case S12: case S13: case S14: case S15:
98 case S16: case S17: case S18: case S19:
99 case S20: case S21: case S22: case S23:
100 case S24: case S25: case S26: case S27:
101 case S28: case S29: case S30: case S31: {
105 default: return 0; // Avoid compile time warning.
143 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
144 const ARMSubtarget &sti)
145 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
147 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
151 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
152 static const unsigned CalleeSavedRegs[] = {
153 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
154 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
156 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
157 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
161 static const unsigned DarwinCalleeSavedRegs[] = {
162 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
164 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
165 ARM::R11, ARM::R10, ARM::R8,
167 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
168 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
171 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
174 const TargetRegisterClass* const *
175 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
176 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
177 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
179 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
181 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
186 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
187 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
188 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
189 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
191 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
196 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
197 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
198 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
199 &ARM::GPRRegClass, &ARM::GPRRegClass,
201 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
206 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
207 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass,
208 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
209 &ARM::GPRRegClass, &ARM::GPRRegClass,
211 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
212 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
216 if (STI.isThumb1Only()) {
217 return STI.isTargetDarwin()
218 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
220 return STI.isTargetDarwin()
221 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
224 BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
225 // FIXME: avoid re-calculating this everytime.
226 BitVector Reserved(getNumRegs());
227 Reserved.set(ARM::SP);
228 Reserved.set(ARM::PC);
229 if (STI.isTargetDarwin() || hasFP(MF))
230 Reserved.set(FramePtr);
231 // Some targets reserve R9.
232 if (STI.isR9Reserved())
233 Reserved.set(ARM::R9);
237 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
238 unsigned Reg) const {
246 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
250 return STI.isR9Reserved();
256 const TargetRegisterClass *
257 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
258 const TargetRegisterClass *B,
259 unsigned SubIdx) const {
268 if (A->getSize() == 8) {
269 if (A == &ARM::DPR_8RegClass)
271 return &ARM::DPR_VFP2RegClass;
274 assert(A->getSize() == 16 && "Expecting a Q register class!");
275 return &ARM::QPR_VFP2RegClass;
285 const TargetRegisterClass *
286 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
287 return ARM::GPRRegisterClass;
290 /// getAllocationOrder - Returns the register allocation order for a specified
291 /// register class in the form of a pair of TargetRegisterClass iterators.
292 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
293 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
294 unsigned HintType, unsigned HintReg,
295 const MachineFunction &MF) const {
296 // Alternative register allocation orders when favoring even / odd registers
297 // of register pairs.
299 // No FP, R9 is available.
300 static const unsigned GPREven1[] = {
301 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
302 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
305 static const unsigned GPROdd1[] = {
306 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
307 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
311 // FP is R7, R9 is available.
312 static const unsigned GPREven2[] = {
313 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
314 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
317 static const unsigned GPROdd2[] = {
318 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
319 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
323 // FP is R11, R9 is available.
324 static const unsigned GPREven3[] = {
325 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
326 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
329 static const unsigned GPROdd3[] = {
330 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
331 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
335 // No FP, R9 is not available.
336 static const unsigned GPREven4[] = {
337 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
338 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
341 static const unsigned GPROdd4[] = {
342 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
343 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
347 // FP is R7, R9 is not available.
348 static const unsigned GPREven5[] = {
349 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
350 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
353 static const unsigned GPROdd5[] = {
354 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
355 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
359 // FP is R11, R9 is not available.
360 static const unsigned GPREven6[] = {
361 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
362 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
364 static const unsigned GPROdd6[] = {
365 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
366 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
370 if (HintType == ARMRI::RegPairEven) {
371 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
372 // It's no longer possible to fulfill this hint. Return the default
374 return std::make_pair(RC->allocation_order_begin(MF),
375 RC->allocation_order_end(MF));
377 if (!STI.isTargetDarwin() && !hasFP(MF)) {
378 if (!STI.isR9Reserved())
379 return std::make_pair(GPREven1,
380 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
382 return std::make_pair(GPREven4,
383 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
384 } else if (FramePtr == ARM::R7) {
385 if (!STI.isR9Reserved())
386 return std::make_pair(GPREven2,
387 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
389 return std::make_pair(GPREven5,
390 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
391 } else { // FramePtr == ARM::R11
392 if (!STI.isR9Reserved())
393 return std::make_pair(GPREven3,
394 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
396 return std::make_pair(GPREven6,
397 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
399 } else if (HintType == ARMRI::RegPairOdd) {
400 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
401 // It's no longer possible to fulfill this hint. Return the default
403 return std::make_pair(RC->allocation_order_begin(MF),
404 RC->allocation_order_end(MF));
406 if (!STI.isTargetDarwin() && !hasFP(MF)) {
407 if (!STI.isR9Reserved())
408 return std::make_pair(GPROdd1,
409 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
411 return std::make_pair(GPROdd4,
412 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
413 } else if (FramePtr == ARM::R7) {
414 if (!STI.isR9Reserved())
415 return std::make_pair(GPROdd2,
416 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
418 return std::make_pair(GPROdd5,
419 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
420 } else { // FramePtr == ARM::R11
421 if (!STI.isR9Reserved())
422 return std::make_pair(GPROdd3,
423 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
425 return std::make_pair(GPROdd6,
426 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
429 return std::make_pair(RC->allocation_order_begin(MF),
430 RC->allocation_order_end(MF));
433 /// ResolveRegAllocHint - Resolves the specified register allocation hint
434 /// to a physical register. Returns the physical register if it is successful.
436 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
437 const MachineFunction &MF) const {
438 if (Reg == 0 || !isPhysicalRegister(Reg))
442 else if (Type == (unsigned)ARMRI::RegPairOdd)
444 return getRegisterPairOdd(Reg, MF);
445 else if (Type == (unsigned)ARMRI::RegPairEven)
447 return getRegisterPairEven(Reg, MF);
452 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
453 MachineFunction &MF) const {
454 MachineRegisterInfo *MRI = &MF.getRegInfo();
455 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
456 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
457 Hint.first == (unsigned)ARMRI::RegPairEven) &&
458 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
459 // If 'Reg' is one of the even / odd register pair and it's now changed
460 // (e.g. coalesced) into a different register. The other register of the
461 // pair allocation hint must be updated to reflect the relationship
463 unsigned OtherReg = Hint.second;
464 Hint = MRI->getRegAllocationHint(OtherReg);
465 if (Hint.second == Reg)
466 // Make sure the pair has not already divorced.
467 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
471 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
472 unsigned MaxAlign = 0;
474 for (int i = FFI->getObjectIndexBegin(),
475 e = FFI->getObjectIndexEnd(); i != e; ++i) {
476 if (FFI->isDeadObjectIndex(i))
479 unsigned Align = FFI->getObjectAlignment(i);
480 MaxAlign = std::max(MaxAlign, Align);
486 /// hasFP - Return true if the specified function should have a dedicated frame
487 /// pointer register. This is true if the function has variable sized allocas
488 /// or if frame pointer elimination is disabled.
490 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
491 const MachineFrameInfo *MFI = MF.getFrameInfo();
492 return (NoFramePointerElim ||
493 needsStackRealignment(MF) ||
494 MFI->hasVarSizedObjects() ||
495 MFI->isFrameAddressTaken());
498 bool ARMBaseRegisterInfo::
499 needsStackRealignment(const MachineFunction &MF) const {
500 // Only do this for ARM if explicitly enabled
501 // FIXME: Once it's passing all the tests, enable by default
502 if (!ARMDynamicStackAlign)
505 const MachineFrameInfo *MFI = MF.getFrameInfo();
506 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
507 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
508 return (RealignStack &&
509 !AFI->isThumb1OnlyFunction() &&
510 (MFI->getMaxAlignment() > StackAlign) &&
511 !MFI->hasVarSizedObjects());
514 bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
515 const MachineFrameInfo *MFI = MF.getFrameInfo();
516 if (NoFramePointerElim && MFI->hasCalls())
518 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
521 /// estimateStackSize - Estimate and return the size of the frame.
522 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
523 const MachineFrameInfo *FFI = MF.getFrameInfo();
525 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
526 int FixedOff = -FFI->getObjectOffset(i);
527 if (FixedOff > Offset) Offset = FixedOff;
529 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
530 if (FFI->isDeadObjectIndex(i))
532 Offset += FFI->getObjectSize(i);
533 unsigned Align = FFI->getObjectAlignment(i);
534 // Adjust to alignment boundary
535 Offset = (Offset+Align-1)/Align*Align;
537 return (unsigned)Offset;
540 /// estimateRSStackSizeLimit - Look at each instruction that references stack
541 /// frames and return the stack size limit beyond which some of these
542 /// instructions will require scratch register during their expansion later.
544 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
545 unsigned Limit = (1 << 12) - 1;
546 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
547 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
549 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
550 if (!I->getOperand(i).isFI()) continue;
552 const TargetInstrDesc &Desc = TII.get(I->getOpcode());
553 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
554 if (AddrMode == ARMII::AddrMode3 ||
555 AddrMode == ARMII::AddrModeT2_i8)
558 if (AddrMode == ARMII::AddrMode5 ||
559 AddrMode == ARMII::AddrModeT2_i8s4)
560 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
562 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
563 // When the stack offset is negative, we will end up using
564 // the i8 instructions instead.
566 break; // At most one FI per instruction
575 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
576 RegScavenger *RS) const {
577 // This tells PEI to spill the FP as if it is any other callee-save register
578 // to take advantage the eliminateFrameIndex machinery. This also ensures it
579 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
580 // to combine multiple loads / stores.
581 bool CanEliminateFrame = true;
582 bool CS1Spilled = false;
583 bool LRSpilled = false;
584 unsigned NumGPRSpills = 0;
585 SmallVector<unsigned, 4> UnspilledCS1GPRs;
586 SmallVector<unsigned, 4> UnspilledCS2GPRs;
587 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
589 MachineFrameInfo *MFI = MF.getFrameInfo();
591 // Calculate and set max stack object alignment early, so we can decide
592 // whether we will need stack realignment (and thus FP).
593 if (ARMDynamicStackAlign) {
594 unsigned MaxAlign = std::max(MFI->getMaxAlignment(),
595 calculateMaxStackAlignment(MFI));
596 MFI->setMaxAlignment(MaxAlign);
599 // Don't spill FP if the frame can be eliminated. This is determined
600 // by scanning the callee-save registers to see if any is used.
601 const unsigned *CSRegs = getCalleeSavedRegs();
602 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
603 for (unsigned i = 0; CSRegs[i]; ++i) {
604 unsigned Reg = CSRegs[i];
605 bool Spilled = false;
606 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
607 AFI->setCSRegisterIsSpilled(Reg);
609 CanEliminateFrame = false;
611 // Check alias registers too.
612 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
613 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
615 CanEliminateFrame = false;
620 if (CSRegClasses[i] == ARM::GPRRegisterClass ||
621 CSRegClasses[i] == ARM::tGPRRegisterClass) {
625 if (!STI.isTargetDarwin()) {
632 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
647 if (!STI.isTargetDarwin()) {
648 UnspilledCS1GPRs.push_back(Reg);
658 UnspilledCS1GPRs.push_back(Reg);
661 UnspilledCS2GPRs.push_back(Reg);
668 bool ForceLRSpill = false;
669 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
670 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
671 // Force LR to be spilled if the Thumb function size is > 2048. This enables
672 // use of BL to implement far jump. If it turns out that it's not needed
673 // then the branch fix up path will undo it.
674 if (FnSize >= (1 << 11)) {
675 CanEliminateFrame = false;
680 bool ExtraCSSpill = false;
681 if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
682 AFI->setHasStackFrame(true);
684 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
685 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
686 if (!LRSpilled && CS1Spilled) {
687 MF.getRegInfo().setPhysRegUsed(ARM::LR);
688 AFI->setCSRegisterIsSpilled(ARM::LR);
690 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
691 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
692 ForceLRSpill = false;
696 // Darwin ABI requires FP to point to the stack slot that contains the
698 if (STI.isTargetDarwin() || hasFP(MF)) {
699 MF.getRegInfo().setPhysRegUsed(FramePtr);
703 // If stack and double are 8-byte aligned and we are spilling an odd number
704 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
705 // the integer and double callee save areas.
706 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
707 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
708 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
709 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
710 unsigned Reg = UnspilledCS1GPRs[i];
711 // Don't spill high register if the function is thumb1
712 if (!AFI->isThumb1OnlyFunction() ||
713 isARMLowRegister(Reg) || Reg == ARM::LR) {
714 MF.getRegInfo().setPhysRegUsed(Reg);
715 AFI->setCSRegisterIsSpilled(Reg);
716 if (!isReservedReg(MF, Reg))
721 } else if (!UnspilledCS2GPRs.empty() &&
722 !AFI->isThumb1OnlyFunction()) {
723 unsigned Reg = UnspilledCS2GPRs.front();
724 MF.getRegInfo().setPhysRegUsed(Reg);
725 AFI->setCSRegisterIsSpilled(Reg);
726 if (!isReservedReg(MF, Reg))
731 // Estimate if we might need to scavenge a register at some point in order
732 // to materialize a stack offset. If so, either spill one additional
733 // callee-saved register or reserve a special spill slot to facilitate
734 // register scavenging. Thumb1 needs a spill slot for stack pointer
735 // adjustments also, even when the frame itself is small.
736 if (RS && !ExtraCSSpill) {
737 MachineFrameInfo *MFI = MF.getFrameInfo();
738 // If any of the stack slot references may be out of range of an
739 // immediate offset, make sure a register (or a spill slot) is
740 // available for the register scavenger. Note that if we're indexing
741 // off the frame pointer, the effective stack size is 4 bytes larger
742 // since the FP points to the stack slot of the previous FP.
743 if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
744 >= estimateRSStackSizeLimit(MF)) {
745 // If any non-reserved CS register isn't spilled, just spill one or two
746 // extra. That should take care of it!
747 unsigned NumExtras = TargetAlign / 4;
748 SmallVector<unsigned, 2> Extras;
749 while (NumExtras && !UnspilledCS1GPRs.empty()) {
750 unsigned Reg = UnspilledCS1GPRs.back();
751 UnspilledCS1GPRs.pop_back();
752 if (!isReservedReg(MF, Reg)) {
753 Extras.push_back(Reg);
757 // For non-Thumb1 functions, also check for hi-reg CS registers
758 if (!AFI->isThumb1OnlyFunction()) {
759 while (NumExtras && !UnspilledCS2GPRs.empty()) {
760 unsigned Reg = UnspilledCS2GPRs.back();
761 UnspilledCS2GPRs.pop_back();
762 if (!isReservedReg(MF, Reg)) {
763 Extras.push_back(Reg);
768 if (Extras.size() && NumExtras == 0) {
769 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
770 MF.getRegInfo().setPhysRegUsed(Extras[i]);
771 AFI->setCSRegisterIsSpilled(Extras[i]);
773 } else if (!AFI->isThumb1OnlyFunction()) {
774 // note: Thumb1 functions spill to R12, not the stack.
775 // Reserve a slot closest to SP or frame pointer.
776 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
777 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
778 RC->getAlignment()));
785 MF.getRegInfo().setPhysRegUsed(ARM::LR);
786 AFI->setCSRegisterIsSpilled(ARM::LR);
787 AFI->setLRIsSpilledForFarJump(true);
791 unsigned ARMBaseRegisterInfo::getRARegister() const {
795 unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
796 if (STI.isTargetDarwin() || hasFP(MF))
801 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
802 llvm_unreachable("What is the exception register");
806 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
807 llvm_unreachable("What is the exception handler register");
811 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
812 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
815 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
816 const MachineFunction &MF) const {
819 // Return 0 if either register of the pair is a special register.
828 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
830 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
832 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
904 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
905 const MachineFunction &MF) const {
908 // Return 0 if either register of the pair is a special register.
917 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
919 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
921 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
993 /// emitLoadConstPool - Emits a load from constpool to materialize the
994 /// specified immediate.
995 void ARMBaseRegisterInfo::
996 emitLoadConstPool(MachineBasicBlock &MBB,
997 MachineBasicBlock::iterator &MBBI,
999 unsigned DestReg, unsigned SubIdx, int Val,
1000 ARMCC::CondCodes Pred,
1001 unsigned PredReg) const {
1002 MachineFunction &MF = *MBB.getParent();
1003 MachineConstantPool *ConstantPool = MF.getConstantPool();
1005 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1006 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1008 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1009 .addReg(DestReg, getDefRegState(true), SubIdx)
1010 .addConstantPoolIndex(Idx)
1011 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1014 bool ARMBaseRegisterInfo::
1015 requiresRegisterScavenging(const MachineFunction &MF) const {
1019 bool ARMBaseRegisterInfo::
1020 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1024 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1025 // not required, we reserve argument space for call sites in the function
1026 // immediately on entry to the current function. This eliminates the need for
1027 // add/sub sp brackets around call sites. Returns true if the call frame is
1028 // included as part of the stack frame.
1029 bool ARMBaseRegisterInfo::
1030 hasReservedCallFrame(MachineFunction &MF) const {
1031 const MachineFrameInfo *FFI = MF.getFrameInfo();
1032 unsigned CFSize = FFI->getMaxCallFrameSize();
1033 // It's not always a good idea to include the call frame as part of the
1034 // stack frame. ARM (especially Thumb) has small immediate offset to
1035 // address the stack frame. So a large call frame can cause poor codegen
1036 // and may even makes it impossible to scavenge a register.
1037 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1040 return !MF.getFrameInfo()->hasVarSizedObjects();
1044 emitSPUpdate(bool isARM,
1045 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1046 DebugLoc dl, const ARMBaseInstrInfo &TII,
1048 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1050 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1051 Pred, PredReg, TII);
1053 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1054 Pred, PredReg, TII);
1058 void ARMBaseRegisterInfo::
1059 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1060 MachineBasicBlock::iterator I) const {
1061 if (!hasReservedCallFrame(MF)) {
1062 // If we have alloca, convert as follows:
1063 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1064 // ADJCALLSTACKUP -> add, sp, sp, amount
1065 MachineInstr *Old = I;
1066 DebugLoc dl = Old->getDebugLoc();
1067 unsigned Amount = Old->getOperand(0).getImm();
1069 // We need to keep the stack aligned properly. To do this, we round the
1070 // amount of space needed for the outgoing arguments up to the next
1071 // alignment boundary.
1072 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1073 Amount = (Amount+Align-1)/Align*Align;
1075 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1076 assert(!AFI->isThumb1OnlyFunction() &&
1077 "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
1078 bool isARM = !AFI->isThumbFunction();
1080 // Replace the pseudo instruction with a new instruction...
1081 unsigned Opc = Old->getOpcode();
1082 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
1083 // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1084 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1085 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1086 unsigned PredReg = Old->getOperand(2).getReg();
1087 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1089 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1090 unsigned PredReg = Old->getOperand(3).getReg();
1091 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1092 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1100 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1101 int SPAdj, int *Value,
1102 RegScavenger *RS) const {
1104 MachineInstr &MI = *II;
1105 MachineBasicBlock &MBB = *MI.getParent();
1106 MachineFunction &MF = *MBB.getParent();
1107 const MachineFrameInfo *MFI = MF.getFrameInfo();
1108 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1109 assert(!AFI->isThumb1OnlyFunction() &&
1110 "This eliminateFrameIndex does not support Thumb1!");
1112 while (!MI.getOperand(i).isFI()) {
1114 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1117 unsigned FrameReg = ARM::SP;
1118 int FrameIndex = MI.getOperand(i).getIndex();
1119 int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1120 bool isFixed = MFI->isFixedObjectIndex(FrameIndex);
1122 // When doing dynamic stack realignment, all of these need to change(?)
1123 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1124 Offset -= AFI->getGPRCalleeSavedArea1Offset();
1125 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1126 Offset -= AFI->getGPRCalleeSavedArea2Offset();
1127 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1128 Offset -= AFI->getDPRCalleeSavedAreaOffset();
1129 else if (needsStackRealignment(MF)) {
1130 // When dynamically realigning the stack, use the frame pointer for
1131 // parameters, and the stack pointer for locals.
1132 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
1134 FrameReg = getFrameRegister(MF);
1135 Offset -= AFI->getFramePtrSpillOffset();
1136 // When referencing from the frame pointer, stack pointer adjustments
1140 } else if (hasFP(MF) && AFI->hasStackFrame()) {
1141 assert(SPAdj == 0 && "Unexpected stack offset!");
1142 if (isFixed || MFI->hasVarSizedObjects()) {
1143 // Use frame pointer to reference fixed objects unless this is a
1144 // frameless function.
1145 FrameReg = getFrameRegister(MF);
1146 Offset -= AFI->getFramePtrSpillOffset();
1147 } else if (AFI->isThumb2Function()) {
1148 // In Thumb2 mode, the negative offset is very limited.
1149 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
1150 if (FPOffset >= -255 && FPOffset < 0) {
1151 FrameReg = getFrameRegister(MF);
1157 // Modify MI as necessary to handle as much of 'Offset' as possible
1159 if (!AFI->isThumbFunction())
1160 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1162 assert(AFI->isThumb2Function());
1163 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1168 // If we get here, the immediate doesn't fit into the instruction. We folded
1169 // as much as possible above, handle the rest, providing a register that is
1172 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) &&
1173 "This code isn't needed if offset already handled!");
1175 unsigned ScratchReg = 0;
1176 int PIdx = MI.findFirstPredOperandIdx();
1177 ARMCC::CondCodes Pred = (PIdx == -1)
1178 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1179 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1181 // Must be addrmode4.
1182 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1184 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1185 if (Value) *Value = Offset;
1186 if (!AFI->isThumbFunction())
1187 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1188 Offset, Pred, PredReg, TII);
1190 assert(AFI->isThumb2Function());
1191 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1192 Offset, Pred, PredReg, TII);
1194 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1195 if (!ReuseFrameIndexVals)
1201 /// Move iterator pass the next bunch of callee save load / store ops for
1202 /// the particular spill area (1: integer area 1, 2: integer area 2,
1203 /// 3: fp area, 0: don't care).
1204 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1205 MachineBasicBlock::iterator &MBBI,
1206 int Opc1, int Opc2, unsigned Area,
1207 const ARMSubtarget &STI) {
1208 while (MBBI != MBB.end() &&
1209 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1210 MBBI->getOperand(1).isFI()) {
1213 unsigned Category = 0;
1214 switch (MBBI->getOperand(0).getReg()) {
1215 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1219 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1220 Category = STI.isTargetDarwin() ? 2 : 1;
1222 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1223 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1230 if (Done || Category != Area)
1238 void ARMBaseRegisterInfo::
1239 emitPrologue(MachineFunction &MF) const {
1240 MachineBasicBlock &MBB = MF.front();
1241 MachineBasicBlock::iterator MBBI = MBB.begin();
1242 MachineFrameInfo *MFI = MF.getFrameInfo();
1243 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1244 assert(!AFI->isThumb1OnlyFunction() &&
1245 "This emitPrologue does not suppor Thumb1!");
1246 bool isARM = !AFI->isThumbFunction();
1247 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1248 unsigned NumBytes = MFI->getStackSize();
1249 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1250 DebugLoc dl = (MBBI != MBB.end() ?
1251 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1253 // Determine the sizes of each callee-save spill areas and record which frame
1254 // belongs to which callee-save spill areas.
1255 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1256 int FramePtrSpillFI = 0;
1258 // Allocate the vararg register save area. This is not counted in NumBytes.
1260 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1262 if (!AFI->hasStackFrame()) {
1264 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1268 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1269 unsigned Reg = CSI[i].getReg();
1270 int FI = CSI[i].getFrameIdx();
1277 if (Reg == FramePtr)
1278 FramePtrSpillFI = FI;
1279 AFI->addGPRCalleeSavedArea1Frame(FI);
1286 if (Reg == FramePtr)
1287 FramePtrSpillFI = FI;
1288 if (STI.isTargetDarwin()) {
1289 AFI->addGPRCalleeSavedArea2Frame(FI);
1292 AFI->addGPRCalleeSavedArea1Frame(FI);
1297 AFI->addDPRCalleeSavedAreaFrame(FI);
1302 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1303 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1304 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1306 // Set FP to point to the stack slot that contains the previous FP.
1307 // For Darwin, FP is R7, which has now been stored in spill area 1.
1308 // Otherwise, if this is not Darwin, all the callee-saved registers go
1309 // into spill area 1, including the FP in R11. In either case, it is
1310 // now safe to emit this assignment.
1311 if (STI.isTargetDarwin() || hasFP(MF)) {
1312 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1313 MachineInstrBuilder MIB =
1314 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1315 .addFrameIndex(FramePtrSpillFI).addImm(0);
1316 AddDefaultCC(AddDefaultPred(MIB));
1319 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1320 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1322 // Build the new SUBri to adjust SP for FP callee-save spill area.
1323 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1324 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1326 // Determine starting offsets of spill areas.
1327 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1328 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1329 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1330 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1331 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1332 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1333 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1335 NumBytes = DPRCSOffset;
1337 // Insert it after all the callee-save spills.
1338 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI);
1339 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1342 if (STI.isTargetELF() && hasFP(MF)) {
1343 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1344 AFI->getFramePtrSpillOffset());
1347 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1348 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1349 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1351 // If we need dynamic stack realignment, do it here.
1352 if (needsStackRealignment(MF)) {
1354 unsigned MaxAlign = MFI->getMaxAlignment();
1355 assert (!AFI->isThumb1OnlyFunction());
1356 Opc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri;
1358 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), ARM::SP)
1359 .addReg(ARM::SP, RegState::Kill)
1360 .addImm(MaxAlign-1)));
1364 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1365 for (unsigned i = 0; CSRegs[i]; ++i)
1366 if (Reg == CSRegs[i])
1371 static bool isCSRestore(MachineInstr *MI,
1372 const ARMBaseInstrInfo &TII,
1373 const unsigned *CSRegs) {
1374 return ((MI->getOpcode() == (int)ARM::FLDD ||
1375 MI->getOpcode() == (int)ARM::LDR ||
1376 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1377 MI->getOperand(1).isFI() &&
1378 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1381 void ARMBaseRegisterInfo::
1382 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1383 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1384 assert(MBBI->getDesc().isReturn() &&
1385 "Can only insert epilog into returning blocks");
1386 DebugLoc dl = MBBI->getDebugLoc();
1387 MachineFrameInfo *MFI = MF.getFrameInfo();
1388 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1389 assert(!AFI->isThumb1OnlyFunction() &&
1390 "This emitEpilogue does not suppor Thumb1!");
1391 bool isARM = !AFI->isThumbFunction();
1393 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1394 int NumBytes = (int)MFI->getStackSize();
1396 if (!AFI->hasStackFrame()) {
1398 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1400 // Unwind MBBI to point to first LDR / FLDD.
1401 const unsigned *CSRegs = getCalleeSavedRegs();
1402 if (MBBI != MBB.begin()) {
1405 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1406 if (!isCSRestore(MBBI, TII, CSRegs))
1410 // Move SP to start of FP callee save spill area.
1411 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1412 AFI->getGPRCalleeSavedArea2Size() +
1413 AFI->getDPRCalleeSavedAreaSize());
1415 // Darwin ABI requires FP to point to the stack slot that contains the
1417 bool HasFP = hasFP(MF);
1418 if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1419 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1420 // Reset SP based on frame pointer only if the stack frame extends beyond
1421 // frame pointer stack slot or target is ELF and the function has FP.
1423 AFI->getGPRCalleeSavedArea2Size() ||
1424 AFI->getDPRCalleeSavedAreaSize() ||
1425 AFI->getDPRCalleeSavedAreaOffset()) {
1428 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1431 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1436 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1438 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1440 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1444 } else if (NumBytes)
1445 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1447 // Move SP to start of integer callee save spill area 2.
1448 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI);
1449 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1451 // Move SP to start of integer callee save spill area 1.
1452 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1453 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1455 // Move SP to SP upon entry to the function.
1456 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1457 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1461 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1464 #include "ARMGenRegisterInfo.inc"