1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45 cl::desc("Reuse repeated frame index values"));
47 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
55 llvm_unreachable("Unknown ARM register!");
56 case R0: case D0: case Q0: return 0;
57 case R1: case D1: case Q1: return 1;
58 case R2: case D2: case Q2: return 2;
59 case R3: case D3: case Q3: return 3;
60 case R4: case D4: case Q4: return 4;
61 case R5: case D5: case Q5: return 5;
62 case R6: case D6: case Q6: return 6;
63 case R7: case D7: case Q7: return 7;
64 case R8: case D8: case Q8: return 8;
65 case R9: case D9: case Q9: return 9;
66 case R10: case D10: case Q10: return 10;
67 case R11: case D11: case Q11: return 11;
68 case R12: case D12: case Q12: return 12;
69 case SP: case D13: case Q13: return 13;
70 case LR: case D14: case Q14: return 14;
71 case PC: case D15: case Q15: return 15;
90 case S0: case S1: case S2: case S3:
91 case S4: case S5: case S6: case S7:
92 case S8: case S9: case S10: case S11:
93 case S12: case S13: case S14: case S15:
94 case S16: case S17: case S18: case S19:
95 case S20: case S21: case S22: case S23:
96 case S24: case S25: case S26: case S27:
97 case S28: case S29: case S30: case S31: {
101 default: return 0; // Avoid compile time warning.
139 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
140 const ARMSubtarget &sti)
141 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
143 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
147 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
148 static const unsigned CalleeSavedRegs[] = {
149 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
150 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
152 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
153 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
157 static const unsigned DarwinCalleeSavedRegs[] = {
158 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
160 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
161 ARM::R11, ARM::R10, ARM::R8,
163 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
164 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
167 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
170 const TargetRegisterClass* const *
171 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
172 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
173 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
174 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
175 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
177 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
178 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
183 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
184 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
185 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
187 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
188 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
193 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
194 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
195 &ARM::GPRRegClass, &ARM::GPRRegClass,
197 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
198 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
203 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass,
204 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
205 &ARM::GPRRegClass, &ARM::GPRRegClass,
207 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
208 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
212 if (STI.isThumb1Only()) {
213 return STI.isTargetDarwin()
214 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
216 return STI.isTargetDarwin()
217 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
220 BitVector ARMBaseRegisterInfo::
221 getReservedRegs(const MachineFunction &MF) const {
222 // FIXME: avoid re-calculating this everytime.
223 BitVector Reserved(getNumRegs());
224 Reserved.set(ARM::SP);
225 Reserved.set(ARM::PC);
226 if (STI.isTargetDarwin() || hasFP(MF))
227 Reserved.set(FramePtr);
228 // Some targets reserve R9.
229 if (STI.isR9Reserved())
230 Reserved.set(ARM::R9);
234 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
235 unsigned Reg) const {
243 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
247 return STI.isR9Reserved();
253 const TargetRegisterClass *
254 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
255 const TargetRegisterClass *B,
256 unsigned SubIdx) const {
264 if (A->getSize() == 8) {
265 if (B == &ARM::SPR_8RegClass)
266 return &ARM::DPR_8RegClass;
267 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
268 if (A == &ARM::DPR_8RegClass)
270 return &ARM::DPR_VFP2RegClass;
273 assert(A->getSize() == 16 && "Expecting a Q register class!");
274 if (B == &ARM::SPR_8RegClass)
275 return &ARM::QPR_8RegClass;
276 return &ARM::QPR_VFP2RegClass;
280 if (B == &ARM::DPR_VFP2RegClass)
281 return &ARM::QPR_VFP2RegClass;
282 if (B == &ARM::DPR_8RegClass)
283 return &ARM::QPR_8RegClass;
289 const TargetRegisterClass *
290 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
291 return ARM::GPRRegisterClass;
294 /// getAllocationOrder - Returns the register allocation order for a specified
295 /// register class in the form of a pair of TargetRegisterClass iterators.
296 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
297 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
298 unsigned HintType, unsigned HintReg,
299 const MachineFunction &MF) const {
300 // Alternative register allocation orders when favoring even / odd registers
301 // of register pairs.
303 // No FP, R9 is available.
304 static const unsigned GPREven1[] = {
305 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
306 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
309 static const unsigned GPROdd1[] = {
310 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
311 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
315 // FP is R7, R9 is available.
316 static const unsigned GPREven2[] = {
317 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
318 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
321 static const unsigned GPROdd2[] = {
322 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
323 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
327 // FP is R11, R9 is available.
328 static const unsigned GPREven3[] = {
329 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
330 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
333 static const unsigned GPROdd3[] = {
334 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
335 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
339 // No FP, R9 is not available.
340 static const unsigned GPREven4[] = {
341 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
342 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
345 static const unsigned GPROdd4[] = {
346 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
347 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
351 // FP is R7, R9 is not available.
352 static const unsigned GPREven5[] = {
353 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
354 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
357 static const unsigned GPROdd5[] = {
358 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
359 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
363 // FP is R11, R9 is not available.
364 static const unsigned GPREven6[] = {
365 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
366 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
368 static const unsigned GPROdd6[] = {
369 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
370 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
374 if (HintType == ARMRI::RegPairEven) {
375 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
376 // It's no longer possible to fulfill this hint. Return the default
378 return std::make_pair(RC->allocation_order_begin(MF),
379 RC->allocation_order_end(MF));
381 if (!STI.isTargetDarwin() && !hasFP(MF)) {
382 if (!STI.isR9Reserved())
383 return std::make_pair(GPREven1,
384 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
386 return std::make_pair(GPREven4,
387 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
388 } else if (FramePtr == ARM::R7) {
389 if (!STI.isR9Reserved())
390 return std::make_pair(GPREven2,
391 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
393 return std::make_pair(GPREven5,
394 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
395 } else { // FramePtr == ARM::R11
396 if (!STI.isR9Reserved())
397 return std::make_pair(GPREven3,
398 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
400 return std::make_pair(GPREven6,
401 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
403 } else if (HintType == ARMRI::RegPairOdd) {
404 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
405 // It's no longer possible to fulfill this hint. Return the default
407 return std::make_pair(RC->allocation_order_begin(MF),
408 RC->allocation_order_end(MF));
410 if (!STI.isTargetDarwin() && !hasFP(MF)) {
411 if (!STI.isR9Reserved())
412 return std::make_pair(GPROdd1,
413 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
415 return std::make_pair(GPROdd4,
416 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
417 } else if (FramePtr == ARM::R7) {
418 if (!STI.isR9Reserved())
419 return std::make_pair(GPROdd2,
420 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
422 return std::make_pair(GPROdd5,
423 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
424 } else { // FramePtr == ARM::R11
425 if (!STI.isR9Reserved())
426 return std::make_pair(GPROdd3,
427 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
429 return std::make_pair(GPROdd6,
430 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
433 return std::make_pair(RC->allocation_order_begin(MF),
434 RC->allocation_order_end(MF));
437 /// ResolveRegAllocHint - Resolves the specified register allocation hint
438 /// to a physical register. Returns the physical register if it is successful.
440 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
441 const MachineFunction &MF) const {
442 if (Reg == 0 || !isPhysicalRegister(Reg))
446 else if (Type == (unsigned)ARMRI::RegPairOdd)
448 return getRegisterPairOdd(Reg, MF);
449 else if (Type == (unsigned)ARMRI::RegPairEven)
451 return getRegisterPairEven(Reg, MF);
456 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
457 MachineFunction &MF) const {
458 MachineRegisterInfo *MRI = &MF.getRegInfo();
459 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
460 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
461 Hint.first == (unsigned)ARMRI::RegPairEven) &&
462 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
463 // If 'Reg' is one of the even / odd register pair and it's now changed
464 // (e.g. coalesced) into a different register. The other register of the
465 // pair allocation hint must be updated to reflect the relationship
467 unsigned OtherReg = Hint.second;
468 Hint = MRI->getRegAllocationHint(OtherReg);
469 if (Hint.second == Reg)
470 // Make sure the pair has not already divorced.
471 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
475 /// hasFP - Return true if the specified function should have a dedicated frame
476 /// pointer register. This is true if the function has variable sized allocas
477 /// or if frame pointer elimination is disabled.
479 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
480 const MachineFrameInfo *MFI = MF.getFrameInfo();
481 return (NoFramePointerElim ||
482 needsStackRealignment(MF) ||
483 MFI->hasVarSizedObjects() ||
484 MFI->isFrameAddressTaken());
487 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
488 const MachineFrameInfo *MFI = MF.getFrameInfo();
489 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
490 return (RealignStack &&
491 !AFI->isThumb1OnlyFunction() &&
492 !MFI->hasVarSizedObjects());
495 bool ARMBaseRegisterInfo::
496 needsStackRealignment(const MachineFunction &MF) const {
497 const MachineFrameInfo *MFI = MF.getFrameInfo();
498 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
499 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
500 return (RealignStack &&
501 !AFI->isThumb1OnlyFunction() &&
502 (MFI->getMaxAlignment() > StackAlign) &&
503 !MFI->hasVarSizedObjects());
506 bool ARMBaseRegisterInfo::
507 cannotEliminateFrame(const MachineFunction &MF) const {
508 const MachineFrameInfo *MFI = MF.getFrameInfo();
509 if (NoFramePointerElim && MFI->hasCalls())
511 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
512 || needsStackRealignment(MF);
515 /// estimateStackSize - Estimate and return the size of the frame.
516 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
517 const MachineFrameInfo *FFI = MF.getFrameInfo();
519 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
520 int FixedOff = -FFI->getObjectOffset(i);
521 if (FixedOff > Offset) Offset = FixedOff;
523 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
524 if (FFI->isDeadObjectIndex(i))
526 Offset += FFI->getObjectSize(i);
527 unsigned Align = FFI->getObjectAlignment(i);
528 // Adjust to alignment boundary
529 Offset = (Offset+Align-1)/Align*Align;
531 return (unsigned)Offset;
534 /// estimateRSStackSizeLimit - Look at each instruction that references stack
535 /// frames and return the stack size limit beyond which some of these
536 /// instructions will require a scratch register during their expansion later.
538 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
539 unsigned Limit = (1 << 12) - 1;
540 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
541 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
543 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
544 if (!I->getOperand(i).isFI()) continue;
546 const TargetInstrDesc &Desc = TII.get(I->getOpcode());
547 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
548 if (AddrMode == ARMII::AddrMode3 ||
549 AddrMode == ARMII::AddrModeT2_i8)
552 if (AddrMode == ARMII::AddrMode5 ||
553 AddrMode == ARMII::AddrModeT2_i8s4)
554 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
556 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
557 // When the stack offset is negative, we will end up using
558 // the i8 instructions instead.
561 if (AddrMode == ARMII::AddrMode6)
563 break; // At most one FI per instruction
572 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
573 RegScavenger *RS) const {
574 // This tells PEI to spill the FP as if it is any other callee-save register
575 // to take advantage the eliminateFrameIndex machinery. This also ensures it
576 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
577 // to combine multiple loads / stores.
578 bool CanEliminateFrame = true;
579 bool CS1Spilled = false;
580 bool LRSpilled = false;
581 unsigned NumGPRSpills = 0;
582 SmallVector<unsigned, 4> UnspilledCS1GPRs;
583 SmallVector<unsigned, 4> UnspilledCS2GPRs;
584 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
587 // Calculate and set max stack object alignment early, so we can decide
588 // whether we will need stack realignment (and thus FP).
590 MachineFrameInfo *MFI = MF.getFrameInfo();
591 MFI->calculateMaxStackAlignment();
594 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
596 // FIXME: It will be better just to find spare register here.
597 if (needsStackRealignment(MF) &&
598 AFI->isThumb2Function())
599 MF.getRegInfo().setPhysRegUsed(ARM::R4);
601 // Don't spill FP if the frame can be eliminated. This is determined
602 // by scanning the callee-save registers to see if any is used.
603 const unsigned *CSRegs = getCalleeSavedRegs();
604 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
605 for (unsigned i = 0; CSRegs[i]; ++i) {
606 unsigned Reg = CSRegs[i];
607 bool Spilled = false;
608 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
609 AFI->setCSRegisterIsSpilled(Reg);
611 CanEliminateFrame = false;
613 // Check alias registers too.
614 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
615 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
617 CanEliminateFrame = false;
622 if (CSRegClasses[i] == ARM::GPRRegisterClass ||
623 CSRegClasses[i] == ARM::tGPRRegisterClass) {
627 if (!STI.isTargetDarwin()) {
634 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
649 if (!STI.isTargetDarwin()) {
650 UnspilledCS1GPRs.push_back(Reg);
660 UnspilledCS1GPRs.push_back(Reg);
663 UnspilledCS2GPRs.push_back(Reg);
670 bool ForceLRSpill = false;
671 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
672 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
673 // Force LR to be spilled if the Thumb function size is > 2048. This enables
674 // use of BL to implement far jump. If it turns out that it's not needed
675 // then the branch fix up path will undo it.
676 if (FnSize >= (1 << 11)) {
677 CanEliminateFrame = false;
682 bool ExtraCSSpill = false;
683 if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
684 AFI->setHasStackFrame(true);
686 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
687 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
688 if (!LRSpilled && CS1Spilled) {
689 MF.getRegInfo().setPhysRegUsed(ARM::LR);
690 AFI->setCSRegisterIsSpilled(ARM::LR);
692 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
693 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
694 ForceLRSpill = false;
698 // Darwin ABI requires FP to point to the stack slot that contains the
700 if (STI.isTargetDarwin() || hasFP(MF)) {
701 MF.getRegInfo().setPhysRegUsed(FramePtr);
705 // If stack and double are 8-byte aligned and we are spilling an odd number
706 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
707 // the integer and double callee save areas.
708 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
709 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
710 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
711 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
712 unsigned Reg = UnspilledCS1GPRs[i];
713 // Don't spill high register if the function is thumb1
714 if (!AFI->isThumb1OnlyFunction() ||
715 isARMLowRegister(Reg) || Reg == ARM::LR) {
716 MF.getRegInfo().setPhysRegUsed(Reg);
717 AFI->setCSRegisterIsSpilled(Reg);
718 if (!isReservedReg(MF, Reg))
723 } else if (!UnspilledCS2GPRs.empty() &&
724 !AFI->isThumb1OnlyFunction()) {
725 unsigned Reg = UnspilledCS2GPRs.front();
726 MF.getRegInfo().setPhysRegUsed(Reg);
727 AFI->setCSRegisterIsSpilled(Reg);
728 if (!isReservedReg(MF, Reg))
733 // Estimate if we might need to scavenge a register at some point in order
734 // to materialize a stack offset. If so, either spill one additional
735 // callee-saved register or reserve a special spill slot to facilitate
736 // register scavenging. Thumb1 needs a spill slot for stack pointer
737 // adjustments also, even when the frame itself is small.
738 if (RS && !ExtraCSSpill) {
739 MachineFrameInfo *MFI = MF.getFrameInfo();
740 // If any of the stack slot references may be out of range of an
741 // immediate offset, make sure a register (or a spill slot) is
742 // available for the register scavenger. Note that if we're indexing
743 // off the frame pointer, the effective stack size is 4 bytes larger
744 // since the FP points to the stack slot of the previous FP.
745 if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
746 >= estimateRSStackSizeLimit(MF)) {
747 // If any non-reserved CS register isn't spilled, just spill one or two
748 // extra. That should take care of it!
749 unsigned NumExtras = TargetAlign / 4;
750 SmallVector<unsigned, 2> Extras;
751 while (NumExtras && !UnspilledCS1GPRs.empty()) {
752 unsigned Reg = UnspilledCS1GPRs.back();
753 UnspilledCS1GPRs.pop_back();
754 if (!isReservedReg(MF, Reg)) {
755 Extras.push_back(Reg);
759 // For non-Thumb1 functions, also check for hi-reg CS registers
760 if (!AFI->isThumb1OnlyFunction()) {
761 while (NumExtras && !UnspilledCS2GPRs.empty()) {
762 unsigned Reg = UnspilledCS2GPRs.back();
763 UnspilledCS2GPRs.pop_back();
764 if (!isReservedReg(MF, Reg)) {
765 Extras.push_back(Reg);
770 if (Extras.size() && NumExtras == 0) {
771 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
772 MF.getRegInfo().setPhysRegUsed(Extras[i]);
773 AFI->setCSRegisterIsSpilled(Extras[i]);
775 } else if (!AFI->isThumb1OnlyFunction()) {
776 // note: Thumb1 functions spill to R12, not the stack.
777 // Reserve a slot closest to SP or frame pointer.
778 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
779 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
788 MF.getRegInfo().setPhysRegUsed(ARM::LR);
789 AFI->setCSRegisterIsSpilled(ARM::LR);
790 AFI->setLRIsSpilledForFarJump(true);
794 unsigned ARMBaseRegisterInfo::getRARegister() const {
799 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
800 if (STI.isTargetDarwin() || hasFP(MF))
806 ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
807 unsigned &FrameReg) const {
808 const MachineFrameInfo *MFI = MF.getFrameInfo();
809 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
810 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
811 bool isFixed = MFI->isFixedObjectIndex(FI);
814 if (AFI->isGPRCalleeSavedArea1Frame(FI))
815 Offset -= AFI->getGPRCalleeSavedArea1Offset();
816 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
817 Offset -= AFI->getGPRCalleeSavedArea2Offset();
818 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
819 Offset -= AFI->getDPRCalleeSavedAreaOffset();
820 else if (needsStackRealignment(MF)) {
821 // When dynamically realigning the stack, use the frame pointer for
822 // parameters, and the stack pointer for locals.
823 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
825 FrameReg = getFrameRegister(MF);
826 Offset -= AFI->getFramePtrSpillOffset();
828 } else if (hasFP(MF) && AFI->hasStackFrame()) {
829 if (isFixed || MFI->hasVarSizedObjects()) {
830 // Use frame pointer to reference fixed objects unless this is a
831 // frameless function.
832 FrameReg = getFrameRegister(MF);
833 Offset -= AFI->getFramePtrSpillOffset();
834 } else if (AFI->isThumb2Function()) {
835 // In Thumb2 mode, the negative offset is very limited.
836 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
837 if (FPOffset >= -255 && FPOffset < 0) {
838 FrameReg = getFrameRegister(MF);
848 ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
851 return getFrameIndexReference(MF, FI, FrameReg);
854 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
855 llvm_unreachable("What is the exception register");
859 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
860 llvm_unreachable("What is the exception handler register");
864 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
865 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
868 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
869 const MachineFunction &MF) const {
872 // Return 0 if either register of the pair is a special register.
881 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
883 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
885 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
957 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
958 const MachineFunction &MF) const {
961 // Return 0 if either register of the pair is a special register.
970 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
972 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
974 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1046 /// emitLoadConstPool - Emits a load from constpool to materialize the
1047 /// specified immediate.
1048 void ARMBaseRegisterInfo::
1049 emitLoadConstPool(MachineBasicBlock &MBB,
1050 MachineBasicBlock::iterator &MBBI,
1052 unsigned DestReg, unsigned SubIdx, int Val,
1053 ARMCC::CondCodes Pred,
1054 unsigned PredReg) const {
1055 MachineFunction &MF = *MBB.getParent();
1056 MachineConstantPool *ConstantPool = MF.getConstantPool();
1058 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1059 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1061 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1062 .addReg(DestReg, getDefRegState(true), SubIdx)
1063 .addConstantPoolIndex(Idx)
1064 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1067 bool ARMBaseRegisterInfo::
1068 requiresRegisterScavenging(const MachineFunction &MF) const {
1072 bool ARMBaseRegisterInfo::
1073 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1077 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1078 // not required, we reserve argument space for call sites in the function
1079 // immediately on entry to the current function. This eliminates the need for
1080 // add/sub sp brackets around call sites. Returns true if the call frame is
1081 // included as part of the stack frame.
1082 bool ARMBaseRegisterInfo::
1083 hasReservedCallFrame(MachineFunction &MF) const {
1084 const MachineFrameInfo *FFI = MF.getFrameInfo();
1085 unsigned CFSize = FFI->getMaxCallFrameSize();
1086 // It's not always a good idea to include the call frame as part of the
1087 // stack frame. ARM (especially Thumb) has small immediate offset to
1088 // address the stack frame. So a large call frame can cause poor codegen
1089 // and may even makes it impossible to scavenge a register.
1090 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1093 return !MF.getFrameInfo()->hasVarSizedObjects();
1097 emitSPUpdate(bool isARM,
1098 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1099 DebugLoc dl, const ARMBaseInstrInfo &TII,
1101 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1103 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1104 Pred, PredReg, TII);
1106 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1107 Pred, PredReg, TII);
1111 void ARMBaseRegisterInfo::
1112 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1113 MachineBasicBlock::iterator I) const {
1114 if (!hasReservedCallFrame(MF)) {
1115 // If we have alloca, convert as follows:
1116 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1117 // ADJCALLSTACKUP -> add, sp, sp, amount
1118 MachineInstr *Old = I;
1119 DebugLoc dl = Old->getDebugLoc();
1120 unsigned Amount = Old->getOperand(0).getImm();
1122 // We need to keep the stack aligned properly. To do this, we round the
1123 // amount of space needed for the outgoing arguments up to the next
1124 // alignment boundary.
1125 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1126 Amount = (Amount+Align-1)/Align*Align;
1128 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1129 assert(!AFI->isThumb1OnlyFunction() &&
1130 "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
1131 bool isARM = !AFI->isThumbFunction();
1133 // Replace the pseudo instruction with a new instruction...
1134 unsigned Opc = Old->getOpcode();
1135 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
1136 // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1137 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1138 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1139 unsigned PredReg = Old->getOperand(2).getReg();
1140 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1142 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1143 unsigned PredReg = Old->getOperand(3).getReg();
1144 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1145 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1153 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1154 int SPAdj, int *Value,
1155 RegScavenger *RS) const {
1157 MachineInstr &MI = *II;
1158 MachineBasicBlock &MBB = *MI.getParent();
1159 MachineFunction &MF = *MBB.getParent();
1160 const MachineFrameInfo *MFI = MF.getFrameInfo();
1161 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1162 assert(!AFI->isThumb1OnlyFunction() &&
1163 "This eliminateFrameIndex does not support Thumb1!");
1165 while (!MI.getOperand(i).isFI()) {
1167 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1170 int FrameIndex = MI.getOperand(i).getIndex();
1171 int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1174 Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1175 if (FrameReg != ARM::SP)
1178 // Modify MI as necessary to handle as much of 'Offset' as possible
1180 if (!AFI->isThumbFunction())
1181 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1183 assert(AFI->isThumb2Function());
1184 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1189 // If we get here, the immediate doesn't fit into the instruction. We folded
1190 // as much as possible above, handle the rest, providing a register that is
1193 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1194 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1195 "This code isn't needed if offset already handled!");
1197 unsigned ScratchReg = 0;
1198 int PIdx = MI.findFirstPredOperandIdx();
1199 ARMCC::CondCodes Pred = (PIdx == -1)
1200 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1201 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1203 // Must be addrmode4/6.
1204 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1206 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1207 if (Value) *Value = Offset;
1208 if (!AFI->isThumbFunction())
1209 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1210 Offset, Pred, PredReg, TII);
1212 assert(AFI->isThumb2Function());
1213 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1214 Offset, Pred, PredReg, TII);
1216 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1217 if (!ReuseFrameIndexVals)
1223 /// Move iterator past the next bunch of callee save load / store ops for
1224 /// the particular spill area (1: integer area 1, 2: integer area 2,
1225 /// 3: fp area, 0: don't care).
1226 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1227 MachineBasicBlock::iterator &MBBI,
1228 int Opc1, int Opc2, unsigned Area,
1229 const ARMSubtarget &STI) {
1230 while (MBBI != MBB.end() &&
1231 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1232 MBBI->getOperand(1).isFI()) {
1235 unsigned Category = 0;
1236 switch (MBBI->getOperand(0).getReg()) {
1237 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1241 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1242 Category = STI.isTargetDarwin() ? 2 : 1;
1244 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1245 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1252 if (Done || Category != Area)
1260 void ARMBaseRegisterInfo::
1261 emitPrologue(MachineFunction &MF) const {
1262 MachineBasicBlock &MBB = MF.front();
1263 MachineBasicBlock::iterator MBBI = MBB.begin();
1264 MachineFrameInfo *MFI = MF.getFrameInfo();
1265 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1266 assert(!AFI->isThumb1OnlyFunction() &&
1267 "This emitPrologue does not suppor Thumb1!");
1268 bool isARM = !AFI->isThumbFunction();
1269 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1270 unsigned NumBytes = MFI->getStackSize();
1271 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1272 DebugLoc dl = (MBBI != MBB.end() ?
1273 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1275 // Determine the sizes of each callee-save spill areas and record which frame
1276 // belongs to which callee-save spill areas.
1277 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1278 int FramePtrSpillFI = 0;
1280 // Allocate the vararg register save area. This is not counted in NumBytes.
1282 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1284 if (!AFI->hasStackFrame()) {
1286 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1290 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1291 unsigned Reg = CSI[i].getReg();
1292 int FI = CSI[i].getFrameIdx();
1299 if (Reg == FramePtr)
1300 FramePtrSpillFI = FI;
1301 AFI->addGPRCalleeSavedArea1Frame(FI);
1308 if (Reg == FramePtr)
1309 FramePtrSpillFI = FI;
1310 if (STI.isTargetDarwin()) {
1311 AFI->addGPRCalleeSavedArea2Frame(FI);
1314 AFI->addGPRCalleeSavedArea1Frame(FI);
1319 AFI->addDPRCalleeSavedAreaFrame(FI);
1324 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1325 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1326 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1328 // Set FP to point to the stack slot that contains the previous FP.
1329 // For Darwin, FP is R7, which has now been stored in spill area 1.
1330 // Otherwise, if this is not Darwin, all the callee-saved registers go
1331 // into spill area 1, including the FP in R11. In either case, it is
1332 // now safe to emit this assignment.
1333 if (STI.isTargetDarwin() || hasFP(MF)) {
1334 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1335 MachineInstrBuilder MIB =
1336 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1337 .addFrameIndex(FramePtrSpillFI).addImm(0);
1338 AddDefaultCC(AddDefaultPred(MIB));
1341 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1342 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1344 // Build the new SUBri to adjust SP for FP callee-save spill area.
1345 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1346 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1348 // Determine starting offsets of spill areas.
1349 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1350 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1351 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1352 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1353 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1354 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1355 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1357 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1358 NumBytes = DPRCSOffset;
1360 // Adjust SP after all the callee-save spills.
1361 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1364 if (STI.isTargetELF() && hasFP(MF)) {
1365 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1366 AFI->getFramePtrSpillOffset());
1369 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1370 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1371 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1373 // If we need dynamic stack realignment, do it here.
1374 if (needsStackRealignment(MF)) {
1375 unsigned MaxAlign = MFI->getMaxAlignment();
1376 assert (!AFI->isThumb1OnlyFunction());
1377 if (!AFI->isThumbFunction()) {
1378 // Emit bic sp, sp, MaxAlign
1379 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1380 TII.get(ARM::BICri), ARM::SP)
1381 .addReg(ARM::SP, RegState::Kill)
1382 .addImm(MaxAlign-1)));
1384 // We cannot use sp as source/dest register here, thus we're emitting the
1385 // following sequence:
1387 // bic r4, r4, MaxAlign
1389 // FIXME: It will be better just to find spare register here.
1390 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1391 .addReg(ARM::SP, RegState::Kill);
1392 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1393 TII.get(ARM::t2BICri), ARM::R4)
1394 .addReg(ARM::R4, RegState::Kill)
1395 .addImm(MaxAlign-1)));
1396 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1397 .addReg(ARM::R4, RegState::Kill);
1402 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1403 for (unsigned i = 0; CSRegs[i]; ++i)
1404 if (Reg == CSRegs[i])
1409 static bool isCSRestore(MachineInstr *MI,
1410 const ARMBaseInstrInfo &TII,
1411 const unsigned *CSRegs) {
1412 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1413 MI->getOpcode() == (int)ARM::LDR ||
1414 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1415 MI->getOperand(1).isFI() &&
1416 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1419 void ARMBaseRegisterInfo::
1420 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1421 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1422 assert(MBBI->getDesc().isReturn() &&
1423 "Can only insert epilog into returning blocks");
1424 DebugLoc dl = MBBI->getDebugLoc();
1425 MachineFrameInfo *MFI = MF.getFrameInfo();
1426 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1427 assert(!AFI->isThumb1OnlyFunction() &&
1428 "This emitEpilogue does not suppor Thumb1!");
1429 bool isARM = !AFI->isThumbFunction();
1431 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1432 int NumBytes = (int)MFI->getStackSize();
1434 if (!AFI->hasStackFrame()) {
1436 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1438 // Unwind MBBI to point to first LDR / VLDRD.
1439 const unsigned *CSRegs = getCalleeSavedRegs();
1440 if (MBBI != MBB.begin()) {
1443 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1444 if (!isCSRestore(MBBI, TII, CSRegs))
1448 // Move SP to start of FP callee save spill area.
1449 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1450 AFI->getGPRCalleeSavedArea2Size() +
1451 AFI->getDPRCalleeSavedAreaSize());
1453 // Darwin ABI requires FP to point to the stack slot that contains the
1455 bool HasFP = hasFP(MF);
1456 if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1457 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1458 // Reset SP based on frame pointer only if the stack frame extends beyond
1459 // frame pointer stack slot or target is ELF and the function has FP.
1461 AFI->getGPRCalleeSavedArea2Size() ||
1462 AFI->getDPRCalleeSavedAreaSize() ||
1463 AFI->getDPRCalleeSavedAreaOffset()) {
1466 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1469 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1474 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1476 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1478 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1482 } else if (NumBytes)
1483 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1485 // Move SP to start of integer callee save spill area 2.
1486 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1487 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1489 // Move SP to start of integer callee save spill area 1.
1490 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1491 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1493 // Move SP to SP upon entry to the function.
1494 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1495 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1499 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1502 #include "ARMGenRegisterInfo.inc"