1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMFrameLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/BitVector.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/Support/CommandLine.h"
43 #define GET_REGINFO_MC_DESC
44 #define GET_REGINFO_TARGET_DESC
45 #include "ARMGenRegisterInfo.inc"
50 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
51 cl::desc("Force use of virtual base registers for stack load/store"));
53 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
54 cl::desc("Enable pre-regalloc stack frame index allocation"));
56 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
57 cl::desc("Enable use of a base pointer for complex stack frames"));
59 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
60 const ARMSubtarget &sti)
61 : ARMGenRegisterInfo(ARMRegDesc, ARMRegInfoDesc,
62 ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
64 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
69 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
70 static const unsigned CalleeSavedRegs[] = {
71 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
72 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
74 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
75 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
79 static const unsigned DarwinCalleeSavedRegs[] = {
80 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
82 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
83 ARM::R11, ARM::R10, ARM::R8,
85 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
86 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
89 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
92 BitVector ARMBaseRegisterInfo::
93 getReservedRegs(const MachineFunction &MF) const {
94 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
96 // FIXME: avoid re-calculating this every time.
97 BitVector Reserved(getNumRegs());
98 Reserved.set(ARM::SP);
99 Reserved.set(ARM::PC);
100 Reserved.set(ARM::FPSCR);
102 Reserved.set(FramePtr);
103 if (hasBasePointer(MF))
104 Reserved.set(BasePtr);
105 // Some targets reserve R9.
106 if (STI.isR9Reserved())
107 Reserved.set(ARM::R9);
108 // Reserve D16-D31 if the subtarget doesn't support them.
109 if (!STI.hasVFP3() || STI.hasD16()) {
110 assert(ARM::D31 == ARM::D16 + 15);
111 for (unsigned i = 0; i != 16; ++i)
112 Reserved.set(ARM::D16 + i);
117 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
118 unsigned Reg) const {
119 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
127 if (hasBasePointer(MF))
132 if (FramePtr == Reg && TFI->hasFP(MF))
136 return STI.isR9Reserved();
142 const TargetRegisterClass *
143 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
144 const TargetRegisterClass *B,
145 unsigned SubIdx) const {
153 if (A->getSize() == 8) {
154 if (B == &ARM::SPR_8RegClass)
155 return &ARM::DPR_8RegClass;
156 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
157 if (A == &ARM::DPR_8RegClass)
159 return &ARM::DPR_VFP2RegClass;
162 if (A->getSize() == 16) {
163 if (B == &ARM::SPR_8RegClass)
164 return &ARM::QPR_8RegClass;
165 return &ARM::QPR_VFP2RegClass;
168 if (A->getSize() == 32) {
169 if (B == &ARM::SPR_8RegClass)
170 return 0; // Do not allow coalescing!
171 return &ARM::QQPR_VFP2RegClass;
174 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
175 return 0; // Do not allow coalescing!
182 if (A->getSize() == 16) {
183 if (B == &ARM::DPR_VFP2RegClass)
184 return &ARM::QPR_VFP2RegClass;
185 if (B == &ARM::DPR_8RegClass)
186 return 0; // Do not allow coalescing!
190 if (A->getSize() == 32) {
191 if (B == &ARM::DPR_VFP2RegClass)
192 return &ARM::QQPR_VFP2RegClass;
193 if (B == &ARM::DPR_8RegClass)
194 return 0; // Do not allow coalescing!
198 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
199 if (B != &ARM::DPRRegClass)
200 return 0; // Do not allow coalescing!
207 // D sub-registers of QQQQ registers.
208 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
210 return 0; // Do not allow coalescing!
216 if (A->getSize() == 32) {
217 if (B == &ARM::QPR_VFP2RegClass)
218 return &ARM::QQPR_VFP2RegClass;
219 if (B == &ARM::QPR_8RegClass)
220 return 0; // Do not allow coalescing!
224 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
225 if (B == &ARM::QPRRegClass)
227 return 0; // Do not allow coalescing!
231 // Q sub-registers of QQQQ registers.
232 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
234 return 0; // Do not allow coalescing!
241 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
242 SmallVectorImpl<unsigned> &SubIndices,
243 unsigned &NewSubIdx) const {
245 unsigned Size = RC->getSize() * 8;
249 NewSubIdx = 0; // Whole register.
250 unsigned NumRegs = SubIndices.size();
252 // 8 D registers -> 1 QQQQ register.
253 return (Size == 512 &&
254 SubIndices[0] == ARM::dsub_0 &&
255 SubIndices[1] == ARM::dsub_1 &&
256 SubIndices[2] == ARM::dsub_2 &&
257 SubIndices[3] == ARM::dsub_3 &&
258 SubIndices[4] == ARM::dsub_4 &&
259 SubIndices[5] == ARM::dsub_5 &&
260 SubIndices[6] == ARM::dsub_6 &&
261 SubIndices[7] == ARM::dsub_7);
262 } else if (NumRegs == 4) {
263 if (SubIndices[0] == ARM::qsub_0) {
264 // 4 Q registers -> 1 QQQQ register.
265 return (Size == 512 &&
266 SubIndices[1] == ARM::qsub_1 &&
267 SubIndices[2] == ARM::qsub_2 &&
268 SubIndices[3] == ARM::qsub_3);
269 } else if (SubIndices[0] == ARM::dsub_0) {
270 // 4 D registers -> 1 QQ register.
272 SubIndices[1] == ARM::dsub_1 &&
273 SubIndices[2] == ARM::dsub_2 &&
274 SubIndices[3] == ARM::dsub_3) {
276 NewSubIdx = ARM::qqsub_0;
279 } else if (SubIndices[0] == ARM::dsub_4) {
280 // 4 D registers -> 1 QQ register (2nd).
282 SubIndices[1] == ARM::dsub_5 &&
283 SubIndices[2] == ARM::dsub_6 &&
284 SubIndices[3] == ARM::dsub_7) {
285 NewSubIdx = ARM::qqsub_1;
288 } else if (SubIndices[0] == ARM::ssub_0) {
289 // 4 S registers -> 1 Q register.
291 SubIndices[1] == ARM::ssub_1 &&
292 SubIndices[2] == ARM::ssub_2 &&
293 SubIndices[3] == ARM::ssub_3) {
295 NewSubIdx = ARM::qsub_0;
299 } else if (NumRegs == 2) {
300 if (SubIndices[0] == ARM::qsub_0) {
301 // 2 Q registers -> 1 QQ register.
302 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
304 NewSubIdx = ARM::qqsub_0;
307 } else if (SubIndices[0] == ARM::qsub_2) {
308 // 2 Q registers -> 1 QQ register (2nd).
309 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
310 NewSubIdx = ARM::qqsub_1;
313 } else if (SubIndices[0] == ARM::dsub_0) {
314 // 2 D registers -> 1 Q register.
315 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
317 NewSubIdx = ARM::qsub_0;
320 } else if (SubIndices[0] == ARM::dsub_2) {
321 // 2 D registers -> 1 Q register (2nd).
322 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
323 NewSubIdx = ARM::qsub_1;
326 } else if (SubIndices[0] == ARM::dsub_4) {
327 // 2 D registers -> 1 Q register (3rd).
328 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
329 NewSubIdx = ARM::qsub_2;
332 } else if (SubIndices[0] == ARM::dsub_6) {
333 // 2 D registers -> 1 Q register (3rd).
334 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
335 NewSubIdx = ARM::qsub_3;
338 } else if (SubIndices[0] == ARM::ssub_0) {
339 // 2 S registers -> 1 D register.
340 if (SubIndices[1] == ARM::ssub_1) {
342 NewSubIdx = ARM::dsub_0;
345 } else if (SubIndices[0] == ARM::ssub_2) {
346 // 2 S registers -> 1 D register (2nd).
347 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
348 NewSubIdx = ARM::dsub_1;
356 const TargetRegisterClass*
357 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
359 const TargetRegisterClass *Super = RC;
360 TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
362 switch (Super->getID()) {
363 case ARM::GPRRegClassID:
364 case ARM::SPRRegClassID:
365 case ARM::DPRRegClassID:
366 case ARM::QPRRegClassID:
367 case ARM::QQPRRegClassID:
368 case ARM::QQQQPRRegClassID:
376 const TargetRegisterClass *
377 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
378 return ARM::GPRRegisterClass;
382 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
383 MachineFunction &MF) const {
384 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
386 switch (RC->getID()) {
389 case ARM::tGPRRegClassID:
390 return TFI->hasFP(MF) ? 4 : 5;
391 case ARM::GPRRegClassID: {
392 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
393 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
395 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
396 case ARM::DPRRegClassID:
401 /// getRawAllocationOrder - Returns the register allocation order for a
402 /// specified register class with a target-dependent hint.
404 ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
405 unsigned HintType, unsigned HintReg,
406 const MachineFunction &MF) const {
407 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
408 // Alternative register allocation orders when favoring even / odd registers
409 // of register pairs.
411 // No FP, R9 is available.
412 static const unsigned GPREven1[] = {
413 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
414 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
417 static const unsigned GPROdd1[] = {
418 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
419 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
423 // FP is R7, R9 is available.
424 static const unsigned GPREven2[] = {
425 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
426 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
429 static const unsigned GPROdd2[] = {
430 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
431 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
435 // FP is R11, R9 is available.
436 static const unsigned GPREven3[] = {
437 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
438 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
441 static const unsigned GPROdd3[] = {
442 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
443 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
447 // No FP, R9 is not available.
448 static const unsigned GPREven4[] = {
449 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
450 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
453 static const unsigned GPROdd4[] = {
454 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
455 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
459 // FP is R7, R9 is not available.
460 static const unsigned GPREven5[] = {
461 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
462 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
465 static const unsigned GPROdd5[] = {
466 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
467 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
471 // FP is R11, R9 is not available.
472 static const unsigned GPREven6[] = {
473 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
474 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
476 static const unsigned GPROdd6[] = {
477 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
478 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
481 // We only support even/odd hints for GPR and rGPR.
482 if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
483 return RC->getRawAllocationOrder(MF);
485 if (HintType == ARMRI::RegPairEven) {
486 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
487 // It's no longer possible to fulfill this hint. Return the default
489 return RC->getRawAllocationOrder(MF);
491 if (!TFI->hasFP(MF)) {
492 if (!STI.isR9Reserved())
493 return ArrayRef<unsigned>(GPREven1);
495 return ArrayRef<unsigned>(GPREven4);
496 } else if (FramePtr == ARM::R7) {
497 if (!STI.isR9Reserved())
498 return ArrayRef<unsigned>(GPREven2);
500 return ArrayRef<unsigned>(GPREven5);
501 } else { // FramePtr == ARM::R11
502 if (!STI.isR9Reserved())
503 return ArrayRef<unsigned>(GPREven3);
505 return ArrayRef<unsigned>(GPREven6);
507 } else if (HintType == ARMRI::RegPairOdd) {
508 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
509 // It's no longer possible to fulfill this hint. Return the default
511 return RC->getRawAllocationOrder(MF);
513 if (!TFI->hasFP(MF)) {
514 if (!STI.isR9Reserved())
515 return ArrayRef<unsigned>(GPROdd1);
517 return ArrayRef<unsigned>(GPROdd4);
518 } else if (FramePtr == ARM::R7) {
519 if (!STI.isR9Reserved())
520 return ArrayRef<unsigned>(GPROdd2);
522 return ArrayRef<unsigned>(GPROdd5);
523 } else { // FramePtr == ARM::R11
524 if (!STI.isR9Reserved())
525 return ArrayRef<unsigned>(GPROdd3);
527 return ArrayRef<unsigned>(GPROdd6);
530 return RC->getRawAllocationOrder(MF);
533 /// ResolveRegAllocHint - Resolves the specified register allocation hint
534 /// to a physical register. Returns the physical register if it is successful.
536 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
537 const MachineFunction &MF) const {
538 if (Reg == 0 || !isPhysicalRegister(Reg))
542 else if (Type == (unsigned)ARMRI::RegPairOdd)
544 return getRegisterPairOdd(Reg, MF);
545 else if (Type == (unsigned)ARMRI::RegPairEven)
547 return getRegisterPairEven(Reg, MF);
552 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
553 MachineFunction &MF) const {
554 MachineRegisterInfo *MRI = &MF.getRegInfo();
555 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
556 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
557 Hint.first == (unsigned)ARMRI::RegPairEven) &&
558 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
559 // If 'Reg' is one of the even / odd register pair and it's now changed
560 // (e.g. coalesced) into a different register. The other register of the
561 // pair allocation hint must be updated to reflect the relationship
563 unsigned OtherReg = Hint.second;
564 Hint = MRI->getRegAllocationHint(OtherReg);
565 if (Hint.second == Reg)
566 // Make sure the pair has not already divorced.
567 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
572 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
573 // CortexA9 has a Write-after-write hazard for NEON registers.
574 if (!STI.isCortexA9())
577 switch (RC->getID()) {
578 case ARM::DPRRegClassID:
579 case ARM::DPR_8RegClassID:
580 case ARM::DPR_VFP2RegClassID:
581 case ARM::QPRRegClassID:
582 case ARM::QPR_8RegClassID:
583 case ARM::QPR_VFP2RegClassID:
584 case ARM::SPRRegClassID:
585 case ARM::SPR_8RegClassID:
586 // Avoid reusing S, D, and Q registers.
587 // Don't increase register pressure for QQ and QQQQ.
594 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
595 const MachineFrameInfo *MFI = MF.getFrameInfo();
596 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
598 if (!EnableBasePointer)
601 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
604 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
605 // negative range for ldr/str (255), and thumb1 is positive offsets only.
606 // It's going to be better to use the SP or Base Pointer instead. When there
607 // are variable sized objects, we can't reference off of the SP, so we
608 // reserve a Base Pointer.
609 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
610 // Conservatively estimate whether the negative offset from the frame
611 // pointer will be sufficient to reach. If a function has a smallish
612 // frame, it's less likely to have lots of spills and callee saved
613 // space, so it's all more likely to be within range of the frame pointer.
614 // If it's wrong, the scavenger will still enable access to work, it just
616 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
624 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
625 const MachineFrameInfo *MFI = MF.getFrameInfo();
626 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
627 // We can't realign the stack if:
628 // 1. Dynamic stack realignment is explicitly disabled,
629 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
630 // 3. There are VLAs in the function and the base pointer is disabled.
631 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
632 (!MFI->hasVarSizedObjects() || EnableBasePointer));
635 bool ARMBaseRegisterInfo::
636 needsStackRealignment(const MachineFunction &MF) const {
637 const MachineFrameInfo *MFI = MF.getFrameInfo();
638 const Function *F = MF.getFunction();
639 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
640 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
641 F->hasFnAttr(Attribute::StackAlignment));
643 return requiresRealignment && canRealignStack(MF);
646 bool ARMBaseRegisterInfo::
647 cannotEliminateFrame(const MachineFunction &MF) const {
648 const MachineFrameInfo *MFI = MF.getFrameInfo();
649 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
651 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
652 || needsStackRealignment(MF);
655 unsigned ARMBaseRegisterInfo::getRARegister() const {
660 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
661 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
668 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
669 llvm_unreachable("What is the exception register");
673 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
674 llvm_unreachable("What is the exception handler register");
678 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
679 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
682 int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
683 return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
686 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
687 const MachineFunction &MF) const {
690 // Return 0 if either register of the pair is a special register.
699 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
702 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
704 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
776 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
777 const MachineFunction &MF) const {
780 // Return 0 if either register of the pair is a special register.
789 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
792 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
794 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
866 /// emitLoadConstPool - Emits a load from constpool to materialize the
867 /// specified immediate.
868 void ARMBaseRegisterInfo::
869 emitLoadConstPool(MachineBasicBlock &MBB,
870 MachineBasicBlock::iterator &MBBI,
872 unsigned DestReg, unsigned SubIdx, int Val,
873 ARMCC::CondCodes Pred,
874 unsigned PredReg, unsigned MIFlags) const {
875 MachineFunction &MF = *MBB.getParent();
876 MachineConstantPool *ConstantPool = MF.getConstantPool();
878 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
879 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
881 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
882 .addReg(DestReg, getDefRegState(true), SubIdx)
883 .addConstantPoolIndex(Idx)
884 .addImm(0).addImm(Pred).addReg(PredReg)
885 .setMIFlags(MIFlags);
888 bool ARMBaseRegisterInfo::
889 requiresRegisterScavenging(const MachineFunction &MF) const {
893 bool ARMBaseRegisterInfo::
894 requiresFrameIndexScavenging(const MachineFunction &MF) const {
898 bool ARMBaseRegisterInfo::
899 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
900 return EnableLocalStackAlloc;
904 emitSPUpdate(bool isARM,
905 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
906 DebugLoc dl, const ARMBaseInstrInfo &TII,
908 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
910 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
913 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
918 void ARMBaseRegisterInfo::
919 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
920 MachineBasicBlock::iterator I) const {
921 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
922 if (!TFI->hasReservedCallFrame(MF)) {
923 // If we have alloca, convert as follows:
924 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
925 // ADJCALLSTACKUP -> add, sp, sp, amount
926 MachineInstr *Old = I;
927 DebugLoc dl = Old->getDebugLoc();
928 unsigned Amount = Old->getOperand(0).getImm();
930 // We need to keep the stack aligned properly. To do this, we round the
931 // amount of space needed for the outgoing arguments up to the next
932 // alignment boundary.
933 unsigned Align = TFI->getStackAlignment();
934 Amount = (Amount+Align-1)/Align*Align;
936 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
937 assert(!AFI->isThumb1OnlyFunction() &&
938 "This eliminateCallFramePseudoInstr does not support Thumb1!");
939 bool isARM = !AFI->isThumbFunction();
941 // Replace the pseudo instruction with a new instruction...
942 unsigned Opc = Old->getOpcode();
943 int PIdx = Old->findFirstPredOperandIdx();
944 ARMCC::CondCodes Pred = (PIdx == -1)
945 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
946 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
947 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
948 unsigned PredReg = Old->getOperand(2).getReg();
949 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
951 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
952 unsigned PredReg = Old->getOperand(3).getReg();
953 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
954 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
961 int64_t ARMBaseRegisterInfo::
962 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
963 const TargetInstrDesc &Desc = MI->getDesc();
964 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
965 int64_t InstrOffs = 0;;
969 case ARMII::AddrModeT2_i8:
970 case ARMII::AddrModeT2_i12:
971 case ARMII::AddrMode_i12:
972 InstrOffs = MI->getOperand(Idx+1).getImm();
975 case ARMII::AddrMode5: {
977 const MachineOperand &OffOp = MI->getOperand(Idx+1);
978 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
979 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
980 InstrOffs = -InstrOffs;
984 case ARMII::AddrMode2: {
986 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
987 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
988 InstrOffs = -InstrOffs;
991 case ARMII::AddrMode3: {
993 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
994 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
995 InstrOffs = -InstrOffs;
998 case ARMII::AddrModeT1_s: {
1000 InstrOffs = MI->getOperand(ImmIdx).getImm();
1005 llvm_unreachable("Unsupported addressing mode!");
1009 return InstrOffs * Scale;
1012 /// needsFrameBaseReg - Returns true if the instruction's frame index
1013 /// reference would be better served by a base register other than FP
1014 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1015 /// references it should create new base registers for.
1016 bool ARMBaseRegisterInfo::
1017 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1018 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1019 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1022 // It's the load/store FI references that cause issues, as it can be difficult
1023 // to materialize the offset if it won't fit in the literal field. Estimate
1024 // based on the size of the local frame and some conservative assumptions
1025 // about the rest of the stack frame (note, this is pre-regalloc, so
1026 // we don't know everything for certain yet) whether this offset is likely
1027 // to be out of range of the immediate. Return true if so.
1029 // We only generate virtual base registers for loads and stores, so
1030 // return false for everything else.
1031 unsigned Opc = MI->getOpcode();
1033 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
1034 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
1035 case ARM::t2LDRi12: case ARM::t2LDRi8:
1036 case ARM::t2STRi12: case ARM::t2STRi8:
1037 case ARM::VLDRS: case ARM::VLDRD:
1038 case ARM::VSTRS: case ARM::VSTRD:
1039 case ARM::tSTRspi: case ARM::tLDRspi:
1040 if (ForceAllBaseRegAlloc)
1047 // Without a virtual base register, if the function has variable sized
1048 // objects, all fixed-size local references will be via the frame pointer,
1049 // Approximate the offset and see if it's legal for the instruction.
1050 // Note that the incoming offset is based on the SP value at function entry,
1051 // so it'll be negative.
1052 MachineFunction &MF = *MI->getParent()->getParent();
1053 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
1054 MachineFrameInfo *MFI = MF.getFrameInfo();
1055 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1057 // Estimate an offset from the frame pointer.
1058 // Conservatively assume all callee-saved registers get pushed. R4-R6
1059 // will be earlier than the FP, so we ignore those.
1061 int64_t FPOffset = Offset - 8;
1062 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1063 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1065 // Estimate an offset from the stack pointer.
1066 // The incoming offset is relating to the SP at the start of the function,
1067 // but when we access the local it'll be relative to the SP after local
1068 // allocation, so adjust our SP-relative offset by that allocation size.
1070 Offset += MFI->getLocalFrameSize();
1071 // Assume that we'll have at least some spill slots allocated.
1072 // FIXME: This is a total SWAG number. We should run some statistics
1073 // and pick a real one.
1074 Offset += 128; // 128 bytes of spill slots
1076 // If there is a frame pointer, try using it.
1077 // The FP is only available if there is no dynamic realignment. We
1078 // don't know for sure yet whether we'll need that, so we guess based
1079 // on whether there are any local variables that would trigger it.
1080 unsigned StackAlign = TFI->getStackAlignment();
1081 if (TFI->hasFP(MF) &&
1082 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1083 if (isFrameOffsetLegal(MI, FPOffset))
1086 // If we can reference via the stack pointer, try that.
1087 // FIXME: This (and the code that resolves the references) can be improved
1088 // to only disallow SP relative references in the live range of
1089 // the VLA(s). In practice, it's unclear how much difference that
1090 // would make, but it may be worth doing.
1091 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1094 // The offset likely isn't legal, we want to allocate a virtual base register.
1098 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
1099 /// be a pointer to FrameIdx at the beginning of the basic block.
1100 void ARMBaseRegisterInfo::
1101 materializeFrameBaseRegister(MachineBasicBlock *MBB,
1102 unsigned BaseReg, int FrameIdx,
1103 int64_t Offset) const {
1104 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
1105 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1106 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1108 MachineBasicBlock::iterator Ins = MBB->begin();
1109 DebugLoc DL; // Defaults to "unknown"
1110 if (Ins != MBB->end())
1111 DL = Ins->getDebugLoc();
1113 const TargetInstrDesc &TID = TII.get(ADDriOpc);
1114 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1115 MRI.constrainRegClass(BaseReg, TII.getRegClass(TID, 0, this));
1117 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, TID, BaseReg)
1118 .addFrameIndex(FrameIdx).addImm(Offset);
1120 if (!AFI->isThumb1OnlyFunction())
1121 AddDefaultCC(AddDefaultPred(MIB));
1125 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1126 unsigned BaseReg, int64_t Offset) const {
1127 MachineInstr &MI = *I;
1128 MachineBasicBlock &MBB = *MI.getParent();
1129 MachineFunction &MF = *MBB.getParent();
1130 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1131 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1134 assert(!AFI->isThumb1OnlyFunction() &&
1135 "This resolveFrameIndex does not support Thumb1!");
1137 while (!MI.getOperand(i).isFI()) {
1139 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1142 if (!AFI->isThumbFunction())
1143 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1145 assert(AFI->isThumb2Function());
1146 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1148 assert (Done && "Unable to resolve frame index!");
1151 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1152 int64_t Offset) const {
1153 const TargetInstrDesc &Desc = MI->getDesc();
1154 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1157 while (!MI->getOperand(i).isFI()) {
1159 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1162 // AddrMode4 and AddrMode6 cannot handle any offset.
1163 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1166 unsigned NumBits = 0;
1168 bool isSigned = true;
1170 case ARMII::AddrModeT2_i8:
1171 case ARMII::AddrModeT2_i12:
1172 // i8 supports only negative, and i12 supports only positive, so
1173 // based on Offset sign, consider the appropriate instruction
1182 case ARMII::AddrMode5:
1183 // VFP address mode.
1187 case ARMII::AddrMode_i12:
1188 case ARMII::AddrMode2:
1191 case ARMII::AddrMode3:
1194 case ARMII::AddrModeT1_s:
1200 llvm_unreachable("Unsupported addressing mode!");
1204 Offset += getFrameIndexInstrOffset(MI, i);
1205 // Make sure the offset is encodable for instructions that scale the
1207 if ((Offset & (Scale-1)) != 0)
1210 if (isSigned && Offset < 0)
1213 unsigned Mask = (1 << NumBits) - 1;
1214 if ((unsigned)Offset <= Mask * Scale)
1221 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1222 int SPAdj, RegScavenger *RS) const {
1224 MachineInstr &MI = *II;
1225 MachineBasicBlock &MBB = *MI.getParent();
1226 MachineFunction &MF = *MBB.getParent();
1227 const ARMFrameLowering *TFI =
1228 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1229 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1230 assert(!AFI->isThumb1OnlyFunction() &&
1231 "This eliminateFrameIndex does not support Thumb1!");
1233 while (!MI.getOperand(i).isFI()) {
1235 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1238 int FrameIndex = MI.getOperand(i).getIndex();
1241 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1243 // Special handling of dbg_value instructions.
1244 if (MI.isDebugValue()) {
1245 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1246 MI.getOperand(i+1).ChangeToImmediate(Offset);
1250 // Modify MI as necessary to handle as much of 'Offset' as possible
1252 if (!AFI->isThumbFunction())
1253 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1255 assert(AFI->isThumb2Function());
1256 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1261 // If we get here, the immediate doesn't fit into the instruction. We folded
1262 // as much as possible above, handle the rest, providing a register that is
1265 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1266 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1267 "This code isn't needed if offset already handled!");
1269 unsigned ScratchReg = 0;
1270 int PIdx = MI.findFirstPredOperandIdx();
1271 ARMCC::CondCodes Pred = (PIdx == -1)
1272 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1273 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1275 // Must be addrmode4/6.
1276 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1278 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1279 if (!AFI->isThumbFunction())
1280 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1281 Offset, Pred, PredReg, TII);
1283 assert(AFI->isThumb2Function());
1284 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1285 Offset, Pred, PredReg, TII);
1287 // Update the original instruction to use the scratch register.
1288 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1289 if (MI.getOpcode() == ARM::t2ADDrSPi)
1290 MI.setDesc(TII.get(ARM::t2ADDri));
1291 else if (MI.getOpcode() == ARM::t2SUBrSPi)
1292 MI.setDesc(TII.get(ARM::t2SUBri));