1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
45 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
46 cl::desc("Force use of virtual base registers for stack load/store"));
48 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
49 cl::desc("Enable pre-regalloc stack frame index allocation"));
51 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
52 cl::desc("Enable use of a base pointer for complex stack frames"));
54 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
55 const ARMSubtarget &sti)
56 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
58 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
63 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
64 static const unsigned CalleeSavedRegs[] = {
65 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
66 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
68 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
69 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
73 static const unsigned DarwinCalleeSavedRegs[] = {
74 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
76 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
77 ARM::R11, ARM::R10, ARM::R8,
79 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
80 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
83 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
86 BitVector ARMBaseRegisterInfo::
87 getReservedRegs(const MachineFunction &MF) const {
88 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
90 // FIXME: avoid re-calculating this everytime.
91 BitVector Reserved(getNumRegs());
92 Reserved.set(ARM::SP);
93 Reserved.set(ARM::PC);
94 Reserved.set(ARM::FPSCR);
96 Reserved.set(FramePtr);
97 if (hasBasePointer(MF))
98 Reserved.set(BasePtr);
99 // Some targets reserve R9.
100 if (STI.isR9Reserved())
101 Reserved.set(ARM::R9);
105 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
106 unsigned Reg) const {
107 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
115 if (hasBasePointer(MF))
120 if (FramePtr == Reg && TFI->hasFP(MF))
124 return STI.isR9Reserved();
130 const TargetRegisterClass *
131 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
132 const TargetRegisterClass *B,
133 unsigned SubIdx) const {
141 if (A->getSize() == 8) {
142 if (B == &ARM::SPR_8RegClass)
143 return &ARM::DPR_8RegClass;
144 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
145 if (A == &ARM::DPR_8RegClass)
147 return &ARM::DPR_VFP2RegClass;
150 if (A->getSize() == 16) {
151 if (B == &ARM::SPR_8RegClass)
152 return &ARM::QPR_8RegClass;
153 return &ARM::QPR_VFP2RegClass;
156 if (A->getSize() == 32) {
157 if (B == &ARM::SPR_8RegClass)
158 return 0; // Do not allow coalescing!
159 return &ARM::QQPR_VFP2RegClass;
162 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
163 return 0; // Do not allow coalescing!
170 if (A->getSize() == 16) {
171 if (B == &ARM::DPR_VFP2RegClass)
172 return &ARM::QPR_VFP2RegClass;
173 if (B == &ARM::DPR_8RegClass)
174 return 0; // Do not allow coalescing!
178 if (A->getSize() == 32) {
179 if (B == &ARM::DPR_VFP2RegClass)
180 return &ARM::QQPR_VFP2RegClass;
181 if (B == &ARM::DPR_8RegClass)
182 return 0; // Do not allow coalescing!
186 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
187 if (B != &ARM::DPRRegClass)
188 return 0; // Do not allow coalescing!
195 // D sub-registers of QQQQ registers.
196 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
198 return 0; // Do not allow coalescing!
204 if (A->getSize() == 32) {
205 if (B == &ARM::QPR_VFP2RegClass)
206 return &ARM::QQPR_VFP2RegClass;
207 if (B == &ARM::QPR_8RegClass)
208 return 0; // Do not allow coalescing!
212 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
213 if (B == &ARM::QPRRegClass)
215 return 0; // Do not allow coalescing!
219 // Q sub-registers of QQQQ registers.
220 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
222 return 0; // Do not allow coalescing!
229 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
230 SmallVectorImpl<unsigned> &SubIndices,
231 unsigned &NewSubIdx) const {
233 unsigned Size = RC->getSize() * 8;
237 NewSubIdx = 0; // Whole register.
238 unsigned NumRegs = SubIndices.size();
240 // 8 D registers -> 1 QQQQ register.
241 return (Size == 512 &&
242 SubIndices[0] == ARM::dsub_0 &&
243 SubIndices[1] == ARM::dsub_1 &&
244 SubIndices[2] == ARM::dsub_2 &&
245 SubIndices[3] == ARM::dsub_3 &&
246 SubIndices[4] == ARM::dsub_4 &&
247 SubIndices[5] == ARM::dsub_5 &&
248 SubIndices[6] == ARM::dsub_6 &&
249 SubIndices[7] == ARM::dsub_7);
250 } else if (NumRegs == 4) {
251 if (SubIndices[0] == ARM::qsub_0) {
252 // 4 Q registers -> 1 QQQQ register.
253 return (Size == 512 &&
254 SubIndices[1] == ARM::qsub_1 &&
255 SubIndices[2] == ARM::qsub_2 &&
256 SubIndices[3] == ARM::qsub_3);
257 } else if (SubIndices[0] == ARM::dsub_0) {
258 // 4 D registers -> 1 QQ register.
260 SubIndices[1] == ARM::dsub_1 &&
261 SubIndices[2] == ARM::dsub_2 &&
262 SubIndices[3] == ARM::dsub_3) {
264 NewSubIdx = ARM::qqsub_0;
267 } else if (SubIndices[0] == ARM::dsub_4) {
268 // 4 D registers -> 1 QQ register (2nd).
270 SubIndices[1] == ARM::dsub_5 &&
271 SubIndices[2] == ARM::dsub_6 &&
272 SubIndices[3] == ARM::dsub_7) {
273 NewSubIdx = ARM::qqsub_1;
276 } else if (SubIndices[0] == ARM::ssub_0) {
277 // 4 S registers -> 1 Q register.
279 SubIndices[1] == ARM::ssub_1 &&
280 SubIndices[2] == ARM::ssub_2 &&
281 SubIndices[3] == ARM::ssub_3) {
283 NewSubIdx = ARM::qsub_0;
287 } else if (NumRegs == 2) {
288 if (SubIndices[0] == ARM::qsub_0) {
289 // 2 Q registers -> 1 QQ register.
290 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
292 NewSubIdx = ARM::qqsub_0;
295 } else if (SubIndices[0] == ARM::qsub_2) {
296 // 2 Q registers -> 1 QQ register (2nd).
297 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
298 NewSubIdx = ARM::qqsub_1;
301 } else if (SubIndices[0] == ARM::dsub_0) {
302 // 2 D registers -> 1 Q register.
303 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
305 NewSubIdx = ARM::qsub_0;
308 } else if (SubIndices[0] == ARM::dsub_2) {
309 // 2 D registers -> 1 Q register (2nd).
310 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
311 NewSubIdx = ARM::qsub_1;
314 } else if (SubIndices[0] == ARM::dsub_4) {
315 // 2 D registers -> 1 Q register (3rd).
316 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
317 NewSubIdx = ARM::qsub_2;
320 } else if (SubIndices[0] == ARM::dsub_6) {
321 // 2 D registers -> 1 Q register (3rd).
322 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
323 NewSubIdx = ARM::qsub_3;
326 } else if (SubIndices[0] == ARM::ssub_0) {
327 // 2 S registers -> 1 D register.
328 if (SubIndices[1] == ARM::ssub_1) {
330 NewSubIdx = ARM::dsub_0;
333 } else if (SubIndices[0] == ARM::ssub_2) {
334 // 2 S registers -> 1 D register (2nd).
335 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
336 NewSubIdx = ARM::dsub_1;
345 const TargetRegisterClass *
346 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
347 return ARM::GPRRegisterClass;
350 /// getAllocationOrder - Returns the register allocation order for a specified
351 /// register class in the form of a pair of TargetRegisterClass iterators.
352 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
353 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
354 unsigned HintType, unsigned HintReg,
355 const MachineFunction &MF) const {
356 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
357 // Alternative register allocation orders when favoring even / odd registers
358 // of register pairs.
360 // No FP, R9 is available.
361 static const unsigned GPREven1[] = {
362 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
363 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
366 static const unsigned GPROdd1[] = {
367 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
368 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
372 // FP is R7, R9 is available.
373 static const unsigned GPREven2[] = {
374 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
375 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
378 static const unsigned GPROdd2[] = {
379 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
380 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
384 // FP is R11, R9 is available.
385 static const unsigned GPREven3[] = {
386 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
387 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
390 static const unsigned GPROdd3[] = {
391 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
392 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
396 // No FP, R9 is not available.
397 static const unsigned GPREven4[] = {
398 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
399 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
402 static const unsigned GPROdd4[] = {
403 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
404 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
408 // FP is R7, R9 is not available.
409 static const unsigned GPREven5[] = {
410 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
411 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
414 static const unsigned GPROdd5[] = {
415 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
416 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
420 // FP is R11, R9 is not available.
421 static const unsigned GPREven6[] = {
422 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
423 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
425 static const unsigned GPROdd6[] = {
426 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
427 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
431 if (HintType == ARMRI::RegPairEven) {
432 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
433 // It's no longer possible to fulfill this hint. Return the default
435 return std::make_pair(RC->allocation_order_begin(MF),
436 RC->allocation_order_end(MF));
438 if (!TFI->hasFP(MF)) {
439 if (!STI.isR9Reserved())
440 return std::make_pair(GPREven1,
441 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
443 return std::make_pair(GPREven4,
444 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
445 } else if (FramePtr == ARM::R7) {
446 if (!STI.isR9Reserved())
447 return std::make_pair(GPREven2,
448 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
450 return std::make_pair(GPREven5,
451 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
452 } else { // FramePtr == ARM::R11
453 if (!STI.isR9Reserved())
454 return std::make_pair(GPREven3,
455 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
457 return std::make_pair(GPREven6,
458 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
460 } else if (HintType == ARMRI::RegPairOdd) {
461 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
462 // It's no longer possible to fulfill this hint. Return the default
464 return std::make_pair(RC->allocation_order_begin(MF),
465 RC->allocation_order_end(MF));
467 if (!TFI->hasFP(MF)) {
468 if (!STI.isR9Reserved())
469 return std::make_pair(GPROdd1,
470 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
472 return std::make_pair(GPROdd4,
473 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
474 } else if (FramePtr == ARM::R7) {
475 if (!STI.isR9Reserved())
476 return std::make_pair(GPROdd2,
477 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
479 return std::make_pair(GPROdd5,
480 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
481 } else { // FramePtr == ARM::R11
482 if (!STI.isR9Reserved())
483 return std::make_pair(GPROdd3,
484 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
486 return std::make_pair(GPROdd6,
487 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
490 return std::make_pair(RC->allocation_order_begin(MF),
491 RC->allocation_order_end(MF));
494 /// ResolveRegAllocHint - Resolves the specified register allocation hint
495 /// to a physical register. Returns the physical register if it is successful.
497 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
498 const MachineFunction &MF) const {
499 if (Reg == 0 || !isPhysicalRegister(Reg))
503 else if (Type == (unsigned)ARMRI::RegPairOdd)
505 return getRegisterPairOdd(Reg, MF);
506 else if (Type == (unsigned)ARMRI::RegPairEven)
508 return getRegisterPairEven(Reg, MF);
513 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
514 MachineFunction &MF) const {
515 MachineRegisterInfo *MRI = &MF.getRegInfo();
516 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
517 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
518 Hint.first == (unsigned)ARMRI::RegPairEven) &&
519 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
520 // If 'Reg' is one of the even / odd register pair and it's now changed
521 // (e.g. coalesced) into a different register. The other register of the
522 // pair allocation hint must be updated to reflect the relationship
524 unsigned OtherReg = Hint.second;
525 Hint = MRI->getRegAllocationHint(OtherReg);
526 if (Hint.second == Reg)
527 // Make sure the pair has not already divorced.
528 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
532 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
533 const MachineFrameInfo *MFI = MF.getFrameInfo();
534 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
536 if (!EnableBasePointer)
539 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
542 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
543 // negative range for ldr/str (255), and thumb1 is positive offsets only.
544 // It's going to be better to use the SP or Base Pointer instead. When there
545 // are variable sized objects, we can't reference off of the SP, so we
546 // reserve a Base Pointer.
547 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
548 // Conservatively estimate whether the negative offset from the frame
549 // pointer will be sufficient to reach. If a function has a smallish
550 // frame, it's less likely to have lots of spills and callee saved
551 // space, so it's all more likely to be within range of the frame pointer.
552 // If it's wrong, the scavenger will still enable access to work, it just
554 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
562 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
563 const MachineFrameInfo *MFI = MF.getFrameInfo();
564 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
565 // We can't realign the stack if:
566 // 1. Dynamic stack realignment is explicitly disabled,
567 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
568 // 3. There are VLAs in the function and the base pointer is disabled.
569 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
570 (!MFI->hasVarSizedObjects() || EnableBasePointer));
573 bool ARMBaseRegisterInfo::
574 needsStackRealignment(const MachineFunction &MF) const {
575 const MachineFrameInfo *MFI = MF.getFrameInfo();
576 const Function *F = MF.getFunction();
577 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
578 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
579 F->hasFnAttr(Attribute::StackAlignment));
581 return requiresRealignment && canRealignStack(MF);
584 bool ARMBaseRegisterInfo::
585 cannotEliminateFrame(const MachineFunction &MF) const {
586 const MachineFrameInfo *MFI = MF.getFrameInfo();
587 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
589 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
590 || needsStackRealignment(MF);
593 /// estimateStackSize - Estimate and return the size of the frame.
594 static unsigned estimateStackSize(MachineFunction &MF) {
595 const MachineFrameInfo *FFI = MF.getFrameInfo();
597 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
598 int FixedOff = -FFI->getObjectOffset(i);
599 if (FixedOff > Offset) Offset = FixedOff;
601 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
602 if (FFI->isDeadObjectIndex(i))
604 Offset += FFI->getObjectSize(i);
605 unsigned Align = FFI->getObjectAlignment(i);
606 // Adjust to alignment boundary
607 Offset = (Offset+Align-1)/Align*Align;
609 return (unsigned)Offset;
612 /// estimateRSStackSizeLimit - Look at each instruction that references stack
613 /// frames and return the stack size limit beyond which some of these
614 /// instructions will require a scratch register during their expansion later.
616 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
617 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
618 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
619 unsigned Limit = (1 << 12) - 1;
620 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
621 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
623 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
624 if (!I->getOperand(i).isFI()) continue;
626 // When using ADDri to get the address of a stack object, 255 is the
627 // largest offset guaranteed to fit in the immediate offset.
628 if (I->getOpcode() == ARM::ADDri) {
629 Limit = std::min(Limit, (1U << 8) - 1);
633 // Otherwise check the addressing mode.
634 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
635 case ARMII::AddrMode3:
636 case ARMII::AddrModeT2_i8:
637 Limit = std::min(Limit, (1U << 8) - 1);
639 case ARMII::AddrMode5:
640 case ARMII::AddrModeT2_i8s4:
641 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
643 case ARMII::AddrModeT2_i12:
644 // i12 supports only positive offset so these will be converted to
645 // i8 opcodes. See llvm::rewriteT2FrameIndex.
646 if (TFI->hasFP(MF) && AFI->hasStackFrame())
647 Limit = std::min(Limit, (1U << 8) - 1);
649 case ARMII::AddrMode4:
650 case ARMII::AddrMode6:
651 // Addressing modes 4 & 6 (load/store) instructions can't encode an
652 // immediate offset for stack references.
657 break; // At most one FI per instruction
665 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
666 const ARMBaseInstrInfo &TII) {
668 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
670 const MachineBasicBlock &MBB = *MBBI;
671 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
673 FnSize += TII.GetInstSizeInBytes(I);
679 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
680 RegScavenger *RS) const {
681 // This tells PEI to spill the FP as if it is any other callee-save register
682 // to take advantage the eliminateFrameIndex machinery. This also ensures it
683 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
684 // to combine multiple loads / stores.
685 bool CanEliminateFrame = true;
686 bool CS1Spilled = false;
687 bool LRSpilled = false;
688 unsigned NumGPRSpills = 0;
689 SmallVector<unsigned, 4> UnspilledCS1GPRs;
690 SmallVector<unsigned, 4> UnspilledCS2GPRs;
691 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
692 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
693 MachineFrameInfo *MFI = MF.getFrameInfo();
695 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
697 // FIXME: It will be better just to find spare register here.
698 if (needsStackRealignment(MF) &&
699 AFI->isThumb2Function())
700 MF.getRegInfo().setPhysRegUsed(ARM::R4);
702 // Spill LR if Thumb1 function uses variable length argument lists.
703 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
704 MF.getRegInfo().setPhysRegUsed(ARM::LR);
706 // Spill the BasePtr if it's used.
707 if (hasBasePointer(MF))
708 MF.getRegInfo().setPhysRegUsed(BasePtr);
710 // Don't spill FP if the frame can be eliminated. This is determined
711 // by scanning the callee-save registers to see if any is used.
712 const unsigned *CSRegs = getCalleeSavedRegs();
713 for (unsigned i = 0; CSRegs[i]; ++i) {
714 unsigned Reg = CSRegs[i];
715 bool Spilled = false;
716 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
717 AFI->setCSRegisterIsSpilled(Reg);
719 CanEliminateFrame = false;
721 // Check alias registers too.
722 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
723 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
725 CanEliminateFrame = false;
730 if (!ARM::GPRRegisterClass->contains(Reg))
736 if (!STI.isTargetDarwin()) {
743 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
758 if (!STI.isTargetDarwin()) {
759 UnspilledCS1GPRs.push_back(Reg);
769 UnspilledCS1GPRs.push_back(Reg);
772 UnspilledCS2GPRs.push_back(Reg);
778 bool ForceLRSpill = false;
779 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
780 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
781 // Force LR to be spilled if the Thumb function size is > 2048. This enables
782 // use of BL to implement far jump. If it turns out that it's not needed
783 // then the branch fix up path will undo it.
784 if (FnSize >= (1 << 11)) {
785 CanEliminateFrame = false;
790 // If any of the stack slot references may be out of range of an immediate
791 // offset, make sure a register (or a spill slot) is available for the
792 // register scavenger. Note that if we're indexing off the frame pointer, the
793 // effective stack size is 4 bytes larger since the FP points to the stack
794 // slot of the previous FP. Also, if we have variable sized objects in the
795 // function, stack slot references will often be negative, and some of
796 // our instructions are positive-offset only, so conservatively consider
797 // that case to want a spill slot (or register) as well. Similarly, if
798 // the function adjusts the stack pointer during execution and the
799 // adjustments aren't already part of our stack size estimate, our offset
800 // calculations may be off, so be conservative.
801 // FIXME: We could add logic to be more precise about negative offsets
802 // and which instructions will need a scratch register for them. Is it
803 // worth the effort and added fragility?
806 (estimateStackSize(MF) + ((TFI->hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
807 estimateRSStackSizeLimit(MF)))
808 || MFI->hasVarSizedObjects()
809 || (MFI->adjustsStack() && !TFI->canSimplifyCallFramePseudos(MF));
811 bool ExtraCSSpill = false;
812 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
813 AFI->setHasStackFrame(true);
815 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
816 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
817 if (!LRSpilled && CS1Spilled) {
818 MF.getRegInfo().setPhysRegUsed(ARM::LR);
819 AFI->setCSRegisterIsSpilled(ARM::LR);
821 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
822 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
823 ForceLRSpill = false;
827 if (TFI->hasFP(MF)) {
828 MF.getRegInfo().setPhysRegUsed(FramePtr);
832 // If stack and double are 8-byte aligned and we are spilling an odd number
833 // of GPRs, spill one extra callee save GPR so we won't have to pad between
834 // the integer and double callee save areas.
835 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
836 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
837 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
838 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
839 unsigned Reg = UnspilledCS1GPRs[i];
840 // Don't spill high register if the function is thumb1
841 if (!AFI->isThumb1OnlyFunction() ||
842 isARMLowRegister(Reg) || Reg == ARM::LR) {
843 MF.getRegInfo().setPhysRegUsed(Reg);
844 AFI->setCSRegisterIsSpilled(Reg);
845 if (!isReservedReg(MF, Reg))
850 } else if (!UnspilledCS2GPRs.empty() &&
851 !AFI->isThumb1OnlyFunction()) {
852 unsigned Reg = UnspilledCS2GPRs.front();
853 MF.getRegInfo().setPhysRegUsed(Reg);
854 AFI->setCSRegisterIsSpilled(Reg);
855 if (!isReservedReg(MF, Reg))
860 // Estimate if we might need to scavenge a register at some point in order
861 // to materialize a stack offset. If so, either spill one additional
862 // callee-saved register or reserve a special spill slot to facilitate
863 // register scavenging. Thumb1 needs a spill slot for stack pointer
864 // adjustments also, even when the frame itself is small.
865 if (BigStack && !ExtraCSSpill) {
866 // If any non-reserved CS register isn't spilled, just spill one or two
867 // extra. That should take care of it!
868 unsigned NumExtras = TargetAlign / 4;
869 SmallVector<unsigned, 2> Extras;
870 while (NumExtras && !UnspilledCS1GPRs.empty()) {
871 unsigned Reg = UnspilledCS1GPRs.back();
872 UnspilledCS1GPRs.pop_back();
873 if (!isReservedReg(MF, Reg) &&
874 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
876 Extras.push_back(Reg);
880 // For non-Thumb1 functions, also check for hi-reg CS registers
881 if (!AFI->isThumb1OnlyFunction()) {
882 while (NumExtras && !UnspilledCS2GPRs.empty()) {
883 unsigned Reg = UnspilledCS2GPRs.back();
884 UnspilledCS2GPRs.pop_back();
885 if (!isReservedReg(MF, Reg)) {
886 Extras.push_back(Reg);
891 if (Extras.size() && NumExtras == 0) {
892 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
893 MF.getRegInfo().setPhysRegUsed(Extras[i]);
894 AFI->setCSRegisterIsSpilled(Extras[i]);
896 } else if (!AFI->isThumb1OnlyFunction()) {
897 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
898 // closest to SP or frame pointer.
899 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
900 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
908 MF.getRegInfo().setPhysRegUsed(ARM::LR);
909 AFI->setCSRegisterIsSpilled(ARM::LR);
910 AFI->setLRIsSpilledForFarJump(true);
914 unsigned ARMBaseRegisterInfo::getRARegister() const {
919 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
920 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
927 // Provide a base+offset reference to an FI slot for debug info. It's the
928 // same as what we use for resolving the code-gen references for now.
929 // FIXME: This can go wrong when references are SP-relative and simple call
930 // frames aren't used.
932 ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
933 unsigned &FrameReg) const {
934 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
938 ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
942 const MachineFrameInfo *MFI = MF.getFrameInfo();
943 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
944 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
945 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
946 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
947 bool isFixed = MFI->isFixedObjectIndex(FI);
951 if (AFI->isGPRCalleeSavedArea1Frame(FI))
952 return Offset - AFI->getGPRCalleeSavedArea1Offset();
953 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
954 return Offset - AFI->getGPRCalleeSavedArea2Offset();
955 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
956 return Offset - AFI->getDPRCalleeSavedAreaOffset();
958 // When dynamically realigning the stack, use the frame pointer for
959 // parameters, and the stack/base pointer for locals.
960 if (needsStackRealignment(MF)) {
961 assert (TFI->hasFP(MF) && "dynamic stack realignment without a FP!");
963 FrameReg = getFrameRegister(MF);
965 } else if (MFI->hasVarSizedObjects()) {
966 assert(hasBasePointer(MF) &&
967 "VLAs and dynamic stack alignment, but missing base pointer!");
973 // If there is a frame pointer, use it when we can.
974 if (TFI->hasFP(MF) && AFI->hasStackFrame()) {
975 // Use frame pointer to reference fixed objects. Use it for locals if
976 // there are VLAs (and thus the SP isn't reliable as a base).
977 if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
978 FrameReg = getFrameRegister(MF);
980 } else if (MFI->hasVarSizedObjects()) {
981 assert(hasBasePointer(MF) && "missing base pointer!");
982 // Try to use the frame pointer if we can, else use the base pointer
983 // since it's available. This is handy for the emergency spill slot, in
985 if (AFI->isThumb2Function()) {
986 if (FPOffset >= -255 && FPOffset < 0) {
987 FrameReg = getFrameRegister(MF);
992 } else if (AFI->isThumb2Function()) {
993 // In Thumb2 mode, the negative offset is very limited. Try to avoid
994 // out of range references.
995 if (FPOffset >= -255 && FPOffset < 0) {
996 FrameReg = getFrameRegister(MF);
999 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1000 // Otherwise, use SP or FP, whichever is closer to the stack slot.
1001 FrameReg = getFrameRegister(MF);
1005 // Use the base pointer if we have one.
1006 if (hasBasePointer(MF))
1012 ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1015 return getFrameIndexReference(MF, FI, FrameReg);
1018 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1019 llvm_unreachable("What is the exception register");
1023 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1024 llvm_unreachable("What is the exception handler register");
1028 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1029 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1032 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1033 const MachineFunction &MF) const {
1036 // Return 0 if either register of the pair is a special register.
1045 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1048 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
1050 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1122 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1123 const MachineFunction &MF) const {
1126 // Return 0 if either register of the pair is a special register.
1135 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1138 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1140 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1212 /// emitLoadConstPool - Emits a load from constpool to materialize the
1213 /// specified immediate.
1214 void ARMBaseRegisterInfo::
1215 emitLoadConstPool(MachineBasicBlock &MBB,
1216 MachineBasicBlock::iterator &MBBI,
1218 unsigned DestReg, unsigned SubIdx, int Val,
1219 ARMCC::CondCodes Pred,
1220 unsigned PredReg) const {
1221 MachineFunction &MF = *MBB.getParent();
1222 MachineConstantPool *ConstantPool = MF.getConstantPool();
1224 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1225 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1227 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1228 .addReg(DestReg, getDefRegState(true), SubIdx)
1229 .addConstantPoolIndex(Idx)
1230 .addImm(0).addImm(Pred).addReg(PredReg);
1233 bool ARMBaseRegisterInfo::
1234 requiresRegisterScavenging(const MachineFunction &MF) const {
1238 bool ARMBaseRegisterInfo::
1239 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1243 bool ARMBaseRegisterInfo::
1244 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1245 return EnableLocalStackAlloc;
1249 emitSPUpdate(bool isARM,
1250 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1251 DebugLoc dl, const ARMBaseInstrInfo &TII,
1253 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1255 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1256 Pred, PredReg, TII);
1258 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1259 Pred, PredReg, TII);
1263 void ARMBaseRegisterInfo::
1264 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1265 MachineBasicBlock::iterator I) const {
1266 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1267 if (!TFI->hasReservedCallFrame(MF)) {
1268 // If we have alloca, convert as follows:
1269 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1270 // ADJCALLSTACKUP -> add, sp, sp, amount
1271 MachineInstr *Old = I;
1272 DebugLoc dl = Old->getDebugLoc();
1273 unsigned Amount = Old->getOperand(0).getImm();
1275 // We need to keep the stack aligned properly. To do this, we round the
1276 // amount of space needed for the outgoing arguments up to the next
1277 // alignment boundary.
1278 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1279 Amount = (Amount+Align-1)/Align*Align;
1281 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1282 assert(!AFI->isThumb1OnlyFunction() &&
1283 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1284 bool isARM = !AFI->isThumbFunction();
1286 // Replace the pseudo instruction with a new instruction...
1287 unsigned Opc = Old->getOpcode();
1288 int PIdx = Old->findFirstPredOperandIdx();
1289 ARMCC::CondCodes Pred = (PIdx == -1)
1290 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1291 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1292 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1293 unsigned PredReg = Old->getOperand(2).getReg();
1294 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1296 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1297 unsigned PredReg = Old->getOperand(3).getReg();
1298 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1299 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1306 int64_t ARMBaseRegisterInfo::
1307 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
1308 const TargetInstrDesc &Desc = MI->getDesc();
1309 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1310 int64_t InstrOffs = 0;;
1312 unsigned ImmIdx = 0;
1314 case ARMII::AddrModeT2_i8:
1315 case ARMII::AddrModeT2_i12:
1316 case ARMII::AddrMode_i12:
1317 InstrOffs = MI->getOperand(Idx+1).getImm();
1320 case ARMII::AddrMode5: {
1321 // VFP address mode.
1322 const MachineOperand &OffOp = MI->getOperand(Idx+1);
1323 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1324 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1325 InstrOffs = -InstrOffs;
1329 case ARMII::AddrMode2: {
1331 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1332 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1333 InstrOffs = -InstrOffs;
1336 case ARMII::AddrMode3: {
1338 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1339 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1340 InstrOffs = -InstrOffs;
1343 case ARMII::AddrModeT1_s: {
1345 InstrOffs = MI->getOperand(ImmIdx).getImm();
1350 llvm_unreachable("Unsupported addressing mode!");
1354 return InstrOffs * Scale;
1357 /// needsFrameBaseReg - Returns true if the instruction's frame index
1358 /// reference would be better served by a base register other than FP
1359 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1360 /// references it should create new base registers for.
1361 bool ARMBaseRegisterInfo::
1362 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1363 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1364 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1367 // It's the load/store FI references that cause issues, as it can be difficult
1368 // to materialize the offset if it won't fit in the literal field. Estimate
1369 // based on the size of the local frame and some conservative assumptions
1370 // about the rest of the stack frame (note, this is pre-regalloc, so
1371 // we don't know everything for certain yet) whether this offset is likely
1372 // to be out of range of the immediate. Return true if so.
1374 // We only generate virtual base registers for loads and stores, so
1375 // return false for everything else.
1376 unsigned Opc = MI->getOpcode();
1378 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
1379 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
1380 case ARM::t2LDRi12: case ARM::t2LDRi8:
1381 case ARM::t2STRi12: case ARM::t2STRi8:
1382 case ARM::VLDRS: case ARM::VLDRD:
1383 case ARM::VSTRS: case ARM::VSTRD:
1384 case ARM::tSTRspi: case ARM::tLDRspi:
1385 if (ForceAllBaseRegAlloc)
1392 // Without a virtual base register, if the function has variable sized
1393 // objects, all fixed-size local references will be via the frame pointer,
1394 // Approximate the offset and see if it's legal for the instruction.
1395 // Note that the incoming offset is based on the SP value at function entry,
1396 // so it'll be negative.
1397 MachineFunction &MF = *MI->getParent()->getParent();
1398 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1399 MachineFrameInfo *MFI = MF.getFrameInfo();
1400 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1402 // Estimate an offset from the frame pointer.
1403 // Conservatively assume all callee-saved registers get pushed. R4-R6
1404 // will be earlier than the FP, so we ignore those.
1406 int64_t FPOffset = Offset - 8;
1407 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1408 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1410 // Estimate an offset from the stack pointer.
1411 // The incoming offset is relating to the SP at the start of the function,
1412 // but when we access the local it'll be relative to the SP after local
1413 // allocation, so adjust our SP-relative offset by that allocation size.
1415 Offset += MFI->getLocalFrameSize();
1416 // Assume that we'll have at least some spill slots allocated.
1417 // FIXME: This is a total SWAG number. We should run some statistics
1418 // and pick a real one.
1419 Offset += 128; // 128 bytes of spill slots
1421 // If there is a frame pointer, try using it.
1422 // The FP is only available if there is no dynamic realignment. We
1423 // don't know for sure yet whether we'll need that, so we guess based
1424 // on whether there are any local variables that would trigger it.
1425 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1426 if (TFI->hasFP(MF) &&
1427 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1428 if (isFrameOffsetLegal(MI, FPOffset))
1431 // If we can reference via the stack pointer, try that.
1432 // FIXME: This (and the code that resolves the references) can be improved
1433 // to only disallow SP relative references in the live range of
1434 // the VLA(s). In practice, it's unclear how much difference that
1435 // would make, but it may be worth doing.
1436 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1439 // The offset likely isn't legal, we want to allocate a virtual base register.
1443 /// materializeFrameBaseRegister - Insert defining instruction(s) for
1444 /// BaseReg to be a pointer to FrameIdx before insertion point I.
1445 void ARMBaseRegisterInfo::
1446 materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1447 int FrameIdx, int64_t Offset) const {
1448 ARMFunctionInfo *AFI =
1449 I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1450 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1451 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1453 MachineInstrBuilder MIB =
1454 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1455 .addFrameIndex(FrameIdx).addImm(Offset);
1456 if (!AFI->isThumb1OnlyFunction())
1457 AddDefaultCC(AddDefaultPred(MIB));
1461 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1462 unsigned BaseReg, int64_t Offset) const {
1463 MachineInstr &MI = *I;
1464 MachineBasicBlock &MBB = *MI.getParent();
1465 MachineFunction &MF = *MBB.getParent();
1466 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1467 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1470 assert(!AFI->isThumb1OnlyFunction() &&
1471 "This resolveFrameIndex does not support Thumb1!");
1473 while (!MI.getOperand(i).isFI()) {
1475 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1478 if (!AFI->isThumbFunction())
1479 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1481 assert(AFI->isThumb2Function());
1482 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1484 assert (Done && "Unable to resolve frame index!");
1487 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1488 int64_t Offset) const {
1489 const TargetInstrDesc &Desc = MI->getDesc();
1490 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1493 while (!MI->getOperand(i).isFI()) {
1495 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1498 // AddrMode4 and AddrMode6 cannot handle any offset.
1499 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1502 unsigned NumBits = 0;
1504 bool isSigned = true;
1506 case ARMII::AddrModeT2_i8:
1507 case ARMII::AddrModeT2_i12:
1508 // i8 supports only negative, and i12 supports only positive, so
1509 // based on Offset sign, consider the appropriate instruction
1518 case ARMII::AddrMode5:
1519 // VFP address mode.
1523 case ARMII::AddrMode_i12:
1524 case ARMII::AddrMode2:
1527 case ARMII::AddrMode3:
1530 case ARMII::AddrModeT1_s:
1536 llvm_unreachable("Unsupported addressing mode!");
1540 Offset += getFrameIndexInstrOffset(MI, i);
1541 // Make sure the offset is encodable for instructions that scale the
1543 if ((Offset & (Scale-1)) != 0)
1546 if (isSigned && Offset < 0)
1549 unsigned Mask = (1 << NumBits) - 1;
1550 if ((unsigned)Offset <= Mask * Scale)
1557 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1558 int SPAdj, RegScavenger *RS) const {
1560 MachineInstr &MI = *II;
1561 MachineBasicBlock &MBB = *MI.getParent();
1562 MachineFunction &MF = *MBB.getParent();
1563 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1564 assert(!AFI->isThumb1OnlyFunction() &&
1565 "This eliminateFrameIndex does not support Thumb1!");
1567 while (!MI.getOperand(i).isFI()) {
1569 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1572 int FrameIndex = MI.getOperand(i).getIndex();
1575 int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1577 // Special handling of dbg_value instructions.
1578 if (MI.isDebugValue()) {
1579 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1580 MI.getOperand(i+1).ChangeToImmediate(Offset);
1584 // Modify MI as necessary to handle as much of 'Offset' as possible
1586 if (!AFI->isThumbFunction())
1587 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1589 assert(AFI->isThumb2Function());
1590 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1595 // If we get here, the immediate doesn't fit into the instruction. We folded
1596 // as much as possible above, handle the rest, providing a register that is
1599 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1600 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1601 "This code isn't needed if offset already handled!");
1603 unsigned ScratchReg = 0;
1604 int PIdx = MI.findFirstPredOperandIdx();
1605 ARMCC::CondCodes Pred = (PIdx == -1)
1606 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1607 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1609 // Must be addrmode4/6.
1610 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1612 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1613 if (!AFI->isThumbFunction())
1614 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1615 Offset, Pred, PredReg, TII);
1617 assert(AFI->isThumb2Function());
1618 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1619 Offset, Pred, PredReg, TII);
1621 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1625 #include "ARMGenRegisterInfo.inc"