1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/SmallVector.h"
41 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
44 case R0: case S0: case D0: return 0;
45 case R1: case S1: case D1: return 1;
46 case R2: case S2: case D2: return 2;
47 case R3: case S3: case D3: return 3;
48 case R4: case S4: case D4: return 4;
49 case R5: case S5: case D5: return 5;
50 case R6: case S6: case D6: return 6;
51 case R7: case S7: case D7: return 7;
52 case R8: case S8: case D8: return 8;
53 case R9: case S9: case D9: return 9;
54 case R10: case S10: case D10: return 10;
55 case R11: case S11: case D11: return 11;
56 case R12: case S12: case D12: return 12;
57 case SP: case S13: case D13: return 13;
58 case LR: case S14: case D14: return 14;
59 case PC: case S15: case D15: return 15;
77 llvm_unreachable("Unknown ARM register!");
81 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
88 llvm_unreachable("Unknown ARM register!");
89 case R0: case D0: return 0;
90 case R1: case D1: return 1;
91 case R2: case D2: return 2;
92 case R3: case D3: return 3;
93 case R4: case D4: return 4;
94 case R5: case D5: return 5;
95 case R6: case D6: return 6;
96 case R7: case D7: return 7;
97 case R8: case D8: return 8;
98 case R9: case D9: return 9;
99 case R10: case D10: return 10;
100 case R11: case D11: return 11;
101 case R12: case D12: return 12;
102 case SP: case D13: return 13;
103 case LR: case D14: return 14;
104 case PC: case D15: return 15;
106 case S0: case S1: case S2: case S3:
107 case S4: case S5: case S6: case S7:
108 case S8: case S9: case S10: case S11:
109 case S12: case S13: case S14: case S15:
110 case S16: case S17: case S18: case S19:
111 case S20: case S21: case S22: case S23:
112 case S24: case S25: case S26: case S27:
113 case S28: case S29: case S30: case S31: {
116 default: return 0; // Avoid compile time warning.
154 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
155 const ARMSubtarget &sti)
156 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
158 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
161 unsigned ARMBaseRegisterInfo::
162 getOpcode(int Op) const {
163 return TII.getOpcode((ARMII::Op)Op);
167 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
168 static const unsigned CalleeSavedRegs[] = {
169 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
170 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
172 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
173 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
177 static const unsigned DarwinCalleeSavedRegs[] = {
178 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
180 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
181 ARM::R11, ARM::R10, ARM::R8,
183 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
184 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
187 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
190 const TargetRegisterClass* const *
191 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
192 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
193 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
194 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
195 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
197 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
198 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
203 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
204 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
205 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
207 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
208 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
212 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
213 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
214 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
215 &ARM::GPRRegClass, &ARM::GPRRegClass,
217 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
218 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
222 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
223 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass,
224 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
225 &ARM::GPRRegClass, &ARM::GPRRegClass,
227 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
228 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
232 if (STI.isThumb1Only()) {
233 return STI.isTargetDarwin()
234 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
236 return STI.isTargetDarwin()
237 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
240 BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
241 // FIXME: avoid re-calculating this everytime.
242 BitVector Reserved(getNumRegs());
243 Reserved.set(ARM::SP);
244 Reserved.set(ARM::PC);
245 if (STI.isTargetDarwin() || hasFP(MF))
246 Reserved.set(FramePtr);
247 // Some targets reserve R9.
248 if (STI.isR9Reserved())
249 Reserved.set(ARM::R9);
254 ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
262 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
266 return STI.isR9Reserved();
272 const TargetRegisterClass *ARMBaseRegisterInfo::getPointerRegClass() const {
273 return &ARM::GPRRegClass;
276 /// getAllocationOrder - Returns the register allocation order for a specified
277 /// register class in the form of a pair of TargetRegisterClass iterators.
278 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
279 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
280 unsigned HintType, unsigned HintReg,
281 const MachineFunction &MF) const {
282 // Alternative register allocation orders when favoring even / odd registers
283 // of register pairs.
285 // No FP, R9 is available.
286 static const unsigned GPREven1[] = {
287 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
288 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
291 static const unsigned GPROdd1[] = {
292 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
293 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
297 // FP is R7, R9 is available.
298 static const unsigned GPREven2[] = {
299 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
300 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
303 static const unsigned GPROdd2[] = {
304 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
305 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
309 // FP is R11, R9 is available.
310 static const unsigned GPREven3[] = {
311 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
312 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
315 static const unsigned GPROdd3[] = {
316 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
317 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
321 // No FP, R9 is not available.
322 static const unsigned GPREven4[] = {
323 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
324 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
327 static const unsigned GPROdd4[] = {
328 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
329 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
333 // FP is R7, R9 is not available.
334 static const unsigned GPREven5[] = {
335 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
336 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
339 static const unsigned GPROdd5[] = {
340 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
341 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
345 // FP is R11, R9 is not available.
346 static const unsigned GPREven6[] = {
347 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
348 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
350 static const unsigned GPROdd6[] = {
351 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
352 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
356 if (HintType == ARMRI::RegPairEven) {
357 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
358 // It's no longer possible to fulfill this hint. Return the default
360 return std::make_pair(RC->allocation_order_begin(MF),
361 RC->allocation_order_end(MF));
363 if (!STI.isTargetDarwin() && !hasFP(MF)) {
364 if (!STI.isR9Reserved())
365 return std::make_pair(GPREven1,
366 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
368 return std::make_pair(GPREven4,
369 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
370 } else if (FramePtr == ARM::R7) {
371 if (!STI.isR9Reserved())
372 return std::make_pair(GPREven2,
373 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
375 return std::make_pair(GPREven5,
376 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
377 } else { // FramePtr == ARM::R11
378 if (!STI.isR9Reserved())
379 return std::make_pair(GPREven3,
380 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
382 return std::make_pair(GPREven6,
383 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
385 } else if (HintType == ARMRI::RegPairOdd) {
386 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
387 // It's no longer possible to fulfill this hint. Return the default
389 return std::make_pair(RC->allocation_order_begin(MF),
390 RC->allocation_order_end(MF));
392 if (!STI.isTargetDarwin() && !hasFP(MF)) {
393 if (!STI.isR9Reserved())
394 return std::make_pair(GPROdd1,
395 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
397 return std::make_pair(GPROdd4,
398 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
399 } else if (FramePtr == ARM::R7) {
400 if (!STI.isR9Reserved())
401 return std::make_pair(GPROdd2,
402 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
404 return std::make_pair(GPROdd5,
405 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
406 } else { // FramePtr == ARM::R11
407 if (!STI.isR9Reserved())
408 return std::make_pair(GPROdd3,
409 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
411 return std::make_pair(GPROdd6,
412 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
415 return std::make_pair(RC->allocation_order_begin(MF),
416 RC->allocation_order_end(MF));
419 /// ResolveRegAllocHint - Resolves the specified register allocation hint
420 /// to a physical register. Returns the physical register if it is successful.
422 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
423 const MachineFunction &MF) const {
424 if (Reg == 0 || !isPhysicalRegister(Reg))
428 else if (Type == (unsigned)ARMRI::RegPairOdd)
430 return getRegisterPairOdd(Reg, MF);
431 else if (Type == (unsigned)ARMRI::RegPairEven)
433 return getRegisterPairEven(Reg, MF);
438 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
439 MachineFunction &MF) const {
440 MachineRegisterInfo *MRI = &MF.getRegInfo();
441 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
442 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
443 Hint.first == (unsigned)ARMRI::RegPairEven) &&
444 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
445 // If 'Reg' is one of the even / odd register pair and it's now changed
446 // (e.g. coalesced) into a different register. The other register of the
447 // pair allocation hint must be updated to reflect the relationship
449 unsigned OtherReg = Hint.second;
450 Hint = MRI->getRegAllocationHint(OtherReg);
451 if (Hint.second == Reg)
452 // Make sure the pair has not already divorced.
453 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
457 /// hasFP - Return true if the specified function should have a dedicated frame
458 /// pointer register. This is true if the function has variable sized allocas
459 /// or if frame pointer elimination is disabled.
461 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
462 const MachineFrameInfo *MFI = MF.getFrameInfo();
463 return (NoFramePointerElim ||
464 MFI->hasVarSizedObjects() ||
465 MFI->isFrameAddressTaken());
468 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
469 const MachineFrameInfo *FFI = MF.getFrameInfo();
471 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
472 int FixedOff = -FFI->getObjectOffset(i);
473 if (FixedOff > Offset) Offset = FixedOff;
475 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
476 if (FFI->isDeadObjectIndex(i))
478 Offset += FFI->getObjectSize(i);
479 unsigned Align = FFI->getObjectAlignment(i);
480 // Adjust to alignment boundary
481 Offset = (Offset+Align-1)/Align*Align;
483 return (unsigned)Offset;
487 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
488 RegScavenger *RS) const {
489 // This tells PEI to spill the FP as if it is any other callee-save register
490 // to take advantage the eliminateFrameIndex machinery. This also ensures it
491 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
492 // to combine multiple loads / stores.
493 bool CanEliminateFrame = true;
494 bool CS1Spilled = false;
495 bool LRSpilled = false;
496 unsigned NumGPRSpills = 0;
497 SmallVector<unsigned, 4> UnspilledCS1GPRs;
498 SmallVector<unsigned, 4> UnspilledCS2GPRs;
499 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
501 // Don't spill FP if the frame can be eliminated. This is determined
502 // by scanning the callee-save registers to see if any is used.
503 const unsigned *CSRegs = getCalleeSavedRegs();
504 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
505 for (unsigned i = 0; CSRegs[i]; ++i) {
506 unsigned Reg = CSRegs[i];
507 bool Spilled = false;
508 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
509 AFI->setCSRegisterIsSpilled(Reg);
511 CanEliminateFrame = false;
513 // Check alias registers too.
514 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
515 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
517 CanEliminateFrame = false;
522 if (CSRegClasses[i] == &ARM::GPRRegClass) {
526 if (!STI.isTargetDarwin()) {
533 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
548 if (!STI.isTargetDarwin()) {
549 UnspilledCS1GPRs.push_back(Reg);
559 UnspilledCS1GPRs.push_back(Reg);
562 UnspilledCS2GPRs.push_back(Reg);
569 bool ForceLRSpill = false;
570 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
571 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
572 // Force LR to be spilled if the Thumb function size is > 2048. This enables
573 // use of BL to implement far jump. If it turns out that it's not needed
574 // then the branch fix up path will undo it.
575 if (FnSize >= (1 << 11)) {
576 CanEliminateFrame = false;
581 bool ExtraCSSpill = false;
582 if (!CanEliminateFrame || hasFP(MF)) {
583 AFI->setHasStackFrame(true);
585 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
586 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
587 if (!LRSpilled && CS1Spilled) {
588 MF.getRegInfo().setPhysRegUsed(ARM::LR);
589 AFI->setCSRegisterIsSpilled(ARM::LR);
591 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
592 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
593 ForceLRSpill = false;
597 // Darwin ABI requires FP to point to the stack slot that contains the
599 if (STI.isTargetDarwin() || hasFP(MF)) {
600 MF.getRegInfo().setPhysRegUsed(FramePtr);
604 // If stack and double are 8-byte aligned and we are spilling an odd number
605 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
606 // the integer and double callee save areas.
607 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
608 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
609 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
610 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
611 unsigned Reg = UnspilledCS1GPRs[i];
612 // Don't spill high register if the function is thumb1
613 if (!AFI->isThumb1OnlyFunction() ||
614 isARMLowRegister(Reg) || Reg == ARM::LR) {
615 MF.getRegInfo().setPhysRegUsed(Reg);
616 AFI->setCSRegisterIsSpilled(Reg);
617 if (!isReservedReg(MF, Reg))
622 } else if (!UnspilledCS2GPRs.empty() &&
623 !AFI->isThumb1OnlyFunction()) {
624 unsigned Reg = UnspilledCS2GPRs.front();
625 MF.getRegInfo().setPhysRegUsed(Reg);
626 AFI->setCSRegisterIsSpilled(Reg);
627 if (!isReservedReg(MF, Reg))
632 // Estimate if we might need to scavenge a register at some point in order
633 // to materialize a stack offset. If so, either spill one additional
634 // callee-saved register or reserve a special spill slot to facilitate
635 // register scavenging.
636 if (RS && !ExtraCSSpill && !AFI->isThumb1OnlyFunction()) {
637 MachineFrameInfo *MFI = MF.getFrameInfo();
638 unsigned Size = estimateStackSize(MF, MFI);
639 unsigned Limit = (1 << 12) - 1;
640 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
641 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
642 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
643 if (I->getOperand(i).isFI()) {
644 unsigned Opcode = I->getOpcode();
645 const TargetInstrDesc &Desc = TII.get(Opcode);
646 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
647 if (AddrMode == ARMII::AddrMode3) {
648 Limit = (1 << 8) - 1;
650 } else if (AddrMode == ARMII::AddrMode5) {
651 unsigned ThisLimit = ((1 << 8) - 1) * 4;
652 if (ThisLimit < Limit)
659 // If any non-reserved CS register isn't spilled, just spill one or two
660 // extra. That should take care of it!
661 unsigned NumExtras = TargetAlign / 4;
662 SmallVector<unsigned, 2> Extras;
663 while (NumExtras && !UnspilledCS1GPRs.empty()) {
664 unsigned Reg = UnspilledCS1GPRs.back();
665 UnspilledCS1GPRs.pop_back();
666 if (!isReservedReg(MF, Reg)) {
667 Extras.push_back(Reg);
671 while (NumExtras && !UnspilledCS2GPRs.empty()) {
672 unsigned Reg = UnspilledCS2GPRs.back();
673 UnspilledCS2GPRs.pop_back();
674 if (!isReservedReg(MF, Reg)) {
675 Extras.push_back(Reg);
679 if (Extras.size() && NumExtras == 0) {
680 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
681 MF.getRegInfo().setPhysRegUsed(Extras[i]);
682 AFI->setCSRegisterIsSpilled(Extras[i]);
685 // Reserve a slot closest to SP or frame pointer.
686 const TargetRegisterClass *RC = &ARM::GPRRegClass;
687 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
688 RC->getAlignment()));
695 MF.getRegInfo().setPhysRegUsed(ARM::LR);
696 AFI->setCSRegisterIsSpilled(ARM::LR);
697 AFI->setLRIsSpilledForFarJump(true);
701 unsigned ARMBaseRegisterInfo::getRARegister() const {
705 unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
706 if (STI.isTargetDarwin() || hasFP(MF))
711 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
712 llvm_unreachable("What is the exception register");
716 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
717 llvm_unreachable("What is the exception handler register");
721 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
722 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
725 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
726 const MachineFunction &MF) const {
729 // Return 0 if either register of the pair is a special register.
735 return STI.isThumb1Only() ? 0 : ARM::R2;
739 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
741 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
743 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
799 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
800 const MachineFunction &MF) const {
803 // Return 0 if either register of the pair is a special register.
809 return STI.isThumb1Only() ? 0 : ARM::R3;
813 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
815 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
817 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
873 // FIXME: Dup in ARMBaseInstrInfo.cpp
875 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
876 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
880 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
881 return MIB.addReg(0);
884 /// emitLoadConstPool - Emits a load from constpool to materialize the
885 /// specified immediate.
886 void ARMBaseRegisterInfo::
887 emitLoadConstPool(MachineBasicBlock &MBB,
888 MachineBasicBlock::iterator &MBBI,
890 unsigned DestReg, unsigned SubIdx, int Val,
891 ARMCC::CondCodes Pred,
892 unsigned PredReg) const {
893 MachineFunction &MF = *MBB.getParent();
894 MachineConstantPool *ConstantPool = MF.getConstantPool();
896 MF.getFunction()->getContext()->getConstantInt(Type::Int32Ty, Val);
897 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
899 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
900 .addReg(DestReg, getDefRegState(true), SubIdx)
901 .addConstantPoolIndex(Idx)
902 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
905 bool ARMBaseRegisterInfo::
906 requiresRegisterScavenging(const MachineFunction &MF) const {
910 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
911 // not required, we reserve argument space for call sites in the function
912 // immediately on entry to the current function. This eliminates the need for
913 // add/sub sp brackets around call sites. Returns true if the call frame is
914 // included as part of the stack frame.
915 bool ARMBaseRegisterInfo::
916 hasReservedCallFrame(MachineFunction &MF) const {
917 const MachineFrameInfo *FFI = MF.getFrameInfo();
918 unsigned CFSize = FFI->getMaxCallFrameSize();
919 // It's not always a good idea to include the call frame as part of the
920 // stack frame. ARM (especially Thumb) has small immediate offset to
921 // address the stack frame. So a large call frame can cause poor codegen
922 // and may even makes it impossible to scavenge a register.
923 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
926 return !MF.getFrameInfo()->hasVarSizedObjects();
929 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
930 /// a destreg = basereg + immediate in ARM code.
932 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
933 MachineBasicBlock::iterator &MBBI,
934 unsigned DestReg, unsigned BaseReg, int NumBytes,
935 ARMCC::CondCodes Pred, unsigned PredReg,
936 const ARMBaseInstrInfo &TII,
938 bool isSub = NumBytes < 0;
939 if (isSub) NumBytes = -NumBytes;
942 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
943 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
944 assert(ThisVal && "Didn't extract field correctly");
946 // We will handle these bits from offset, clear them.
947 NumBytes &= ~ThisVal;
949 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
951 // Build the new ADD / SUB.
952 BuildMI(MBB, MBBI, dl, TII.get(TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri)), DestReg)
953 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
954 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
960 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
961 const ARMBaseInstrInfo &TII, DebugLoc dl,
963 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
964 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
965 Pred, PredReg, TII, dl);
968 void ARMBaseRegisterInfo::
969 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
970 MachineBasicBlock::iterator I) const {
971 if (!hasReservedCallFrame(MF)) {
972 // If we have alloca, convert as follows:
973 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
974 // ADJCALLSTACKUP -> add, sp, sp, amount
975 MachineInstr *Old = I;
976 DebugLoc dl = Old->getDebugLoc();
977 unsigned Amount = Old->getOperand(0).getImm();
979 // We need to keep the stack aligned properly. To do this, we round the
980 // amount of space needed for the outgoing arguments up to the next
981 // alignment boundary.
982 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
983 Amount = (Amount+Align-1)/Align*Align;
985 // Replace the pseudo instruction with a new instruction...
986 unsigned Opc = Old->getOpcode();
987 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
988 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
989 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
990 unsigned PredReg = Old->getOperand(2).getReg();
991 emitSPUpdate(MBB, I, TII, dl, -Amount, Pred, PredReg);
993 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
994 unsigned PredReg = Old->getOperand(3).getReg();
995 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
996 emitSPUpdate(MBB, I, TII, dl, Amount, Pred, PredReg);
1003 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
1004 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
1005 /// register first and then a spilled callee-saved register if that fails.
1007 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
1008 ARMFunctionInfo *AFI) {
1009 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
1010 assert (!AFI->isThumb1OnlyFunction());
1012 // Try a already spilled CS register.
1013 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
1018 void ARMBaseRegisterInfo::
1019 eliminateFrameIndex(MachineBasicBlock::iterator II,
1020 int SPAdj, RegScavenger *RS) const{
1022 MachineInstr &MI = *II;
1023 MachineBasicBlock &MBB = *MI.getParent();
1024 MachineFunction &MF = *MBB.getParent();
1025 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1026 DebugLoc dl = MI.getDebugLoc();
1028 while (!MI.getOperand(i).isFI()) {
1030 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1033 unsigned FrameReg = ARM::SP;
1034 int FrameIndex = MI.getOperand(i).getIndex();
1035 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
1036 MF.getFrameInfo()->getStackSize() + SPAdj;
1038 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1039 Offset -= AFI->getGPRCalleeSavedArea1Offset();
1040 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1041 Offset -= AFI->getGPRCalleeSavedArea2Offset();
1042 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1043 Offset -= AFI->getDPRCalleeSavedAreaOffset();
1044 else if (hasFP(MF)) {
1045 assert(SPAdj == 0 && "Unexpected");
1046 // There is alloca()'s in this function, must reference off the frame
1048 FrameReg = getFrameRegister(MF);
1049 Offset -= AFI->getFramePtrSpillOffset();
1052 unsigned Opcode = MI.getOpcode();
1053 const TargetInstrDesc &Desc = MI.getDesc();
1054 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1057 // Memory operands in inline assembly always use AddrMode2.
1058 if (Opcode == ARM::INLINEASM)
1059 AddrMode = ARMII::AddrMode2;
1061 if (Opcode == getOpcode(ARMII::ADDri)) {
1062 Offset += MI.getOperand(i+1).getImm();
1064 // Turn it into a move.
1065 MI.setDesc(TII.get(getOpcode(ARMII::MOVr)));
1066 MI.getOperand(i).ChangeToRegister(FrameReg, false);
1067 MI.RemoveOperand(i+1);
1069 } else if (Offset < 0) {
1072 MI.setDesc(TII.get(getOpcode(ARMII::SUBri)));
1075 // Common case: small offset, fits into instruction.
1076 if (ARM_AM::getSOImmVal(Offset) != -1) {
1077 // Replace the FrameIndex with sp / fp
1078 MI.getOperand(i).ChangeToRegister(FrameReg, false);
1079 MI.getOperand(i+1).ChangeToImmediate(Offset);
1083 // Otherwise, we fallback to common code below to form the imm offset with
1084 // a sequence of ADDri instructions. First though, pull as much of the imm
1085 // into this ADDri as possible.
1086 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1087 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1089 // We will handle these bits from offset, clear them.
1090 Offset &= ~ThisImmVal;
1092 // Get the properly encoded SOImmVal field.
1093 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1094 "Bit extraction didn't work?");
1095 MI.getOperand(i+1).ChangeToImmediate(ThisImmVal);
1097 unsigned ImmIdx = 0;
1099 unsigned NumBits = 0;
1102 case ARMII::AddrMode2: {
1104 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1105 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1110 case ARMII::AddrMode3: {
1112 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1113 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1118 case ARMII::AddrMode5: {
1120 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1121 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1127 case ARMII::AddrModeT2_i12: {
1129 InstrOffs = MI.getOperand(ImmIdx).getImm();
1133 case ARMII::AddrModeT2_i8: {
1135 InstrOffs = MI.getOperand(ImmIdx).getImm();
1139 case ARMII::AddrModeT2_so: {
1141 InstrOffs = MI.getOperand(ImmIdx).getImm();
1145 llvm_unreachable("Unsupported addressing mode!");
1149 Offset += InstrOffs * Scale;
1150 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1156 // Common case: small offset, fits into instruction.
1157 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1158 int ImmedOffset = Offset / Scale;
1159 unsigned Mask = (1 << NumBits) - 1;
1160 if ((unsigned)Offset <= Mask * Scale) {
1161 // Replace the FrameIndex with sp
1162 MI.getOperand(i).ChangeToRegister(FrameReg, false);
1164 ImmedOffset |= 1 << NumBits;
1165 ImmOp.ChangeToImmediate(ImmedOffset);
1169 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1170 ImmedOffset = ImmedOffset & Mask;
1172 ImmedOffset |= 1 << NumBits;
1173 ImmOp.ChangeToImmediate(ImmedOffset);
1174 Offset &= ~(Mask*Scale);
1177 // If we get here, the immediate doesn't fit into the instruction. We folded
1178 // as much as possible above, handle the rest, providing a register that is
1180 assert(Offset && "This code isn't needed if offset already handled!");
1182 // Insert a set of r12 with the full address: r12 = sp + offset
1183 // If the offset we have is too large to fit into the instruction, we need
1184 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
1186 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
1187 if (ScratchReg == 0)
1188 // No register is "free". Scavenge a register.
1189 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
1190 int PIdx = MI.findFirstPredOperandIdx();
1191 ARMCC::CondCodes Pred = (PIdx == -1)
1192 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1193 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1194 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
1195 isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
1196 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1199 /// Move iterator pass the next bunch of callee save load / store ops for
1200 /// the particular spill area (1: integer area 1, 2: integer area 2,
1201 /// 3: fp area, 0: don't care).
1202 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1203 MachineBasicBlock::iterator &MBBI,
1204 int Opc, unsigned Area,
1205 const ARMSubtarget &STI) {
1206 while (MBBI != MBB.end() &&
1207 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
1210 unsigned Category = 0;
1211 switch (MBBI->getOperand(0).getReg()) {
1212 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1216 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1217 Category = STI.isTargetDarwin() ? 2 : 1;
1219 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1220 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1227 if (Done || Category != Area)
1235 void ARMBaseRegisterInfo::
1236 emitPrologue(MachineFunction &MF) const {
1237 MachineBasicBlock &MBB = MF.front();
1238 MachineBasicBlock::iterator MBBI = MBB.begin();
1239 MachineFrameInfo *MFI = MF.getFrameInfo();
1240 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1241 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1242 unsigned NumBytes = MFI->getStackSize();
1243 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1244 DebugLoc dl = (MBBI != MBB.end() ?
1245 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1247 // Determine the sizes of each callee-save spill areas and record which frame
1248 // belongs to which callee-save spill areas.
1249 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1250 int FramePtrSpillFI = 0;
1253 emitSPUpdate(MBB, MBBI, TII, dl, -VARegSaveSize);
1255 if (!AFI->hasStackFrame()) {
1257 emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
1261 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1262 unsigned Reg = CSI[i].getReg();
1263 int FI = CSI[i].getFrameIdx();
1270 if (Reg == FramePtr)
1271 FramePtrSpillFI = FI;
1272 AFI->addGPRCalleeSavedArea1Frame(FI);
1279 if (Reg == FramePtr)
1280 FramePtrSpillFI = FI;
1281 if (STI.isTargetDarwin()) {
1282 AFI->addGPRCalleeSavedArea2Frame(FI);
1285 AFI->addGPRCalleeSavedArea1Frame(FI);
1290 AFI->addDPRCalleeSavedAreaFrame(FI);
1295 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1296 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
1297 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 1, STI);
1299 // Darwin ABI requires FP to point to the stack slot that contains the
1301 if (STI.isTargetDarwin() || hasFP(MF)) {
1302 MachineInstrBuilder MIB =
1303 BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::ADDri)), FramePtr)
1304 .addFrameIndex(FramePtrSpillFI).addImm(0);
1305 AddDefaultCC(AddDefaultPred(MIB));
1308 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1309 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
1311 // Build the new SUBri to adjust SP for FP callee-save spill area.
1312 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 2, STI);
1313 emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
1315 // Determine starting offsets of spill areas.
1316 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1317 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1318 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1319 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1320 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1321 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1322 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1324 NumBytes = DPRCSOffset;
1326 // Insert it after all the callee-save spills.
1327 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FSTD), 3, STI);
1328 emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
1331 if (STI.isTargetELF() && hasFP(MF)) {
1332 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1333 AFI->getFramePtrSpillOffset());
1336 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1337 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1338 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1341 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1342 for (unsigned i = 0; CSRegs[i]; ++i)
1343 if (Reg == CSRegs[i])
1348 static bool isCSRestore(MachineInstr *MI,
1349 const ARMBaseInstrInfo &TII,
1350 const unsigned *CSRegs) {
1351 return ((MI->getOpcode() == (int)TII.getOpcode(ARMII::FLDD) ||
1352 MI->getOpcode() == (int)TII.getOpcode(ARMII::LDR)) &&
1353 MI->getOperand(1).isFI() &&
1354 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1357 void ARMBaseRegisterInfo::
1358 emitEpilogue(MachineFunction &MF,
1359 MachineBasicBlock &MBB) const {
1360 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1361 assert(MBBI->getOpcode() == (int)getOpcode(ARMII::BX_RET) &&
1362 "Can only insert epilog into returning blocks");
1363 DebugLoc dl = MBBI->getDebugLoc();
1364 MachineFrameInfo *MFI = MF.getFrameInfo();
1365 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1366 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1367 int NumBytes = (int)MFI->getStackSize();
1369 if (!AFI->hasStackFrame()) {
1371 emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
1373 // Unwind MBBI to point to first LDR / FLDD.
1374 const unsigned *CSRegs = getCalleeSavedRegs();
1375 if (MBBI != MBB.begin()) {
1378 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1379 if (!isCSRestore(MBBI, TII, CSRegs))
1383 // Move SP to start of FP callee save spill area.
1384 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1385 AFI->getGPRCalleeSavedArea2Size() +
1386 AFI->getDPRCalleeSavedAreaSize());
1388 // Darwin ABI requires FP to point to the stack slot that contains the
1390 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1391 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1392 // Reset SP based on frame pointer only if the stack frame extends beyond
1393 // frame pointer stack slot or target is ELF and the function has FP.
1394 if (AFI->getGPRCalleeSavedArea2Size() ||
1395 AFI->getDPRCalleeSavedAreaSize() ||
1396 AFI->getDPRCalleeSavedAreaOffset()||
1399 BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::SUBri)), ARM::SP).addReg(FramePtr)
1401 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1403 BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::MOVr)), ARM::SP).addReg(FramePtr)
1404 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1406 } else if (NumBytes) {
1407 emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
1410 // Move SP to start of integer callee save spill area 2.
1411 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FLDD), 3, STI);
1412 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
1414 // Move SP to start of integer callee save spill area 1.
1415 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 2, STI);
1416 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
1418 // Move SP to SP upon entry to the function.
1419 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 1, STI);
1420 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
1424 emitSPUpdate(MBB, MBBI, TII, dl, VARegSaveSize);
1428 #include "ARMGenRegisterInfo.inc"