1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/Support/CommandLine.h"
43 ScavengeFrameIndexVals("arm-virtual-frame-index-vals", cl::Hidden,
45 cl::desc("Resolve frame index values via scavenging in PEI"));
48 ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(false),
49 cl::desc("Reuse repeated frame index values"));
51 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
59 llvm_unreachable("Unknown ARM register!");
60 case R0: case D0: case Q0: return 0;
61 case R1: case D1: case Q1: return 1;
62 case R2: case D2: case Q2: return 2;
63 case R3: case D3: case Q3: return 3;
64 case R4: case D4: case Q4: return 4;
65 case R5: case D5: case Q5: return 5;
66 case R6: case D6: case Q6: return 6;
67 case R7: case D7: case Q7: return 7;
68 case R8: case D8: case Q8: return 8;
69 case R9: case D9: case Q9: return 9;
70 case R10: case D10: case Q10: return 10;
71 case R11: case D11: case Q11: return 11;
72 case R12: case D12: case Q12: return 12;
73 case SP: case D13: case Q13: return 13;
74 case LR: case D14: case Q14: return 14;
75 case PC: case D15: case Q15: return 15;
94 case S0: case S1: case S2: case S3:
95 case S4: case S5: case S6: case S7:
96 case S8: case S9: case S10: case S11:
97 case S12: case S13: case S14: case S15:
98 case S16: case S17: case S18: case S19:
99 case S20: case S21: case S22: case S23:
100 case S24: case S25: case S26: case S27:
101 case S28: case S29: case S30: case S31: {
105 default: return 0; // Avoid compile time warning.
143 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
144 const ARMSubtarget &sti)
145 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
147 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
151 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
152 static const unsigned CalleeSavedRegs[] = {
153 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
154 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
156 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
157 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
161 static const unsigned DarwinCalleeSavedRegs[] = {
162 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
164 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
165 ARM::R11, ARM::R10, ARM::R8,
167 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
168 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
171 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
174 const TargetRegisterClass* const *
175 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
176 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
177 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
179 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
181 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
186 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
187 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
188 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
189 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
191 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
196 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
197 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
198 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
199 &ARM::GPRRegClass, &ARM::GPRRegClass,
201 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
206 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
207 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass,
208 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
209 &ARM::GPRRegClass, &ARM::GPRRegClass,
211 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
212 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
216 if (STI.isThumb1Only()) {
217 return STI.isTargetDarwin()
218 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
220 return STI.isTargetDarwin()
221 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
224 BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
225 // FIXME: avoid re-calculating this everytime.
226 BitVector Reserved(getNumRegs());
227 Reserved.set(ARM::SP);
228 Reserved.set(ARM::PC);
229 if (STI.isTargetDarwin() || hasFP(MF))
230 Reserved.set(FramePtr);
231 // Some targets reserve R9.
232 if (STI.isR9Reserved())
233 Reserved.set(ARM::R9);
237 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
238 unsigned Reg) const {
246 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
250 return STI.isR9Reserved();
256 const TargetRegisterClass *
257 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
258 const TargetRegisterClass *B,
259 unsigned SubIdx) const {
267 if (A->getSize() == 8) {
268 if (A == &ARM::DPR_8RegClass)
270 return &ARM::DPR_VFP2RegClass;
273 assert(A->getSize() == 16 && "Expecting a Q register class!");
274 return &ARM::QPR_VFP2RegClass;
283 const TargetRegisterClass *
284 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
285 return ARM::GPRRegisterClass;
288 /// getAllocationOrder - Returns the register allocation order for a specified
289 /// register class in the form of a pair of TargetRegisterClass iterators.
290 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
291 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
292 unsigned HintType, unsigned HintReg,
293 const MachineFunction &MF) const {
294 // Alternative register allocation orders when favoring even / odd registers
295 // of register pairs.
297 // No FP, R9 is available.
298 static const unsigned GPREven1[] = {
299 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
300 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
303 static const unsigned GPROdd1[] = {
304 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
305 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
309 // FP is R7, R9 is available.
310 static const unsigned GPREven2[] = {
311 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
312 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
315 static const unsigned GPROdd2[] = {
316 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
317 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
321 // FP is R11, R9 is available.
322 static const unsigned GPREven3[] = {
323 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
324 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
327 static const unsigned GPROdd3[] = {
328 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
329 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
333 // No FP, R9 is not available.
334 static const unsigned GPREven4[] = {
335 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
336 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
339 static const unsigned GPROdd4[] = {
340 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
341 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
345 // FP is R7, R9 is not available.
346 static const unsigned GPREven5[] = {
347 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
348 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
351 static const unsigned GPROdd5[] = {
352 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
353 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
357 // FP is R11, R9 is not available.
358 static const unsigned GPREven6[] = {
359 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
360 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
362 static const unsigned GPROdd6[] = {
363 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
364 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
368 if (HintType == ARMRI::RegPairEven) {
369 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
370 // It's no longer possible to fulfill this hint. Return the default
372 return std::make_pair(RC->allocation_order_begin(MF),
373 RC->allocation_order_end(MF));
375 if (!STI.isTargetDarwin() && !hasFP(MF)) {
376 if (!STI.isR9Reserved())
377 return std::make_pair(GPREven1,
378 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
380 return std::make_pair(GPREven4,
381 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
382 } else if (FramePtr == ARM::R7) {
383 if (!STI.isR9Reserved())
384 return std::make_pair(GPREven2,
385 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
387 return std::make_pair(GPREven5,
388 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
389 } else { // FramePtr == ARM::R11
390 if (!STI.isR9Reserved())
391 return std::make_pair(GPREven3,
392 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
394 return std::make_pair(GPREven6,
395 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
397 } else if (HintType == ARMRI::RegPairOdd) {
398 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
399 // It's no longer possible to fulfill this hint. Return the default
401 return std::make_pair(RC->allocation_order_begin(MF),
402 RC->allocation_order_end(MF));
404 if (!STI.isTargetDarwin() && !hasFP(MF)) {
405 if (!STI.isR9Reserved())
406 return std::make_pair(GPROdd1,
407 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
409 return std::make_pair(GPROdd4,
410 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
411 } else if (FramePtr == ARM::R7) {
412 if (!STI.isR9Reserved())
413 return std::make_pair(GPROdd2,
414 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
416 return std::make_pair(GPROdd5,
417 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
418 } else { // FramePtr == ARM::R11
419 if (!STI.isR9Reserved())
420 return std::make_pair(GPROdd3,
421 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
423 return std::make_pair(GPROdd6,
424 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
427 return std::make_pair(RC->allocation_order_begin(MF),
428 RC->allocation_order_end(MF));
431 /// ResolveRegAllocHint - Resolves the specified register allocation hint
432 /// to a physical register. Returns the physical register if it is successful.
434 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
435 const MachineFunction &MF) const {
436 if (Reg == 0 || !isPhysicalRegister(Reg))
440 else if (Type == (unsigned)ARMRI::RegPairOdd)
442 return getRegisterPairOdd(Reg, MF);
443 else if (Type == (unsigned)ARMRI::RegPairEven)
445 return getRegisterPairEven(Reg, MF);
450 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
451 MachineFunction &MF) const {
452 MachineRegisterInfo *MRI = &MF.getRegInfo();
453 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
454 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
455 Hint.first == (unsigned)ARMRI::RegPairEven) &&
456 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
457 // If 'Reg' is one of the even / odd register pair and it's now changed
458 // (e.g. coalesced) into a different register. The other register of the
459 // pair allocation hint must be updated to reflect the relationship
461 unsigned OtherReg = Hint.second;
462 Hint = MRI->getRegAllocationHint(OtherReg);
463 if (Hint.second == Reg)
464 // Make sure the pair has not already divorced.
465 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
469 /// hasFP - Return true if the specified function should have a dedicated frame
470 /// pointer register. This is true if the function has variable sized allocas
471 /// or if frame pointer elimination is disabled.
473 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
474 const MachineFrameInfo *MFI = MF.getFrameInfo();
475 return (NoFramePointerElim ||
476 MFI->hasVarSizedObjects() ||
477 MFI->isFrameAddressTaken());
480 bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
481 const MachineFrameInfo *MFI = MF.getFrameInfo();
482 if (NoFramePointerElim && MFI->hasCalls())
484 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
487 /// estimateStackSize - Estimate and return the size of the frame.
488 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
489 const MachineFrameInfo *FFI = MF.getFrameInfo();
491 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
492 int FixedOff = -FFI->getObjectOffset(i);
493 if (FixedOff > Offset) Offset = FixedOff;
495 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
496 if (FFI->isDeadObjectIndex(i))
498 Offset += FFI->getObjectSize(i);
499 unsigned Align = FFI->getObjectAlignment(i);
500 // Adjust to alignment boundary
501 Offset = (Offset+Align-1)/Align*Align;
503 return (unsigned)Offset;
506 /// estimateRSStackSizeLimit - Look at each instruction that references stack
507 /// frames and return the stack size limit beyond which some of these
508 /// instructions will require scratch register during their expansion later.
510 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
511 unsigned Limit = (1 << 12) - 1;
512 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
513 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
515 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
516 if (!I->getOperand(i).isFI()) continue;
518 const TargetInstrDesc &Desc = TII.get(I->getOpcode());
519 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
520 if (AddrMode == ARMII::AddrMode3 ||
521 AddrMode == ARMII::AddrModeT2_i8)
524 if (AddrMode == ARMII::AddrMode5 ||
525 AddrMode == ARMII::AddrModeT2_i8s4)
526 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
528 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
529 // When the stack offset is negative, we will end up using
530 // the i8 instructions instead.
532 break; // At most one FI per instruction
541 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
542 RegScavenger *RS) const {
543 // This tells PEI to spill the FP as if it is any other callee-save register
544 // to take advantage the eliminateFrameIndex machinery. This also ensures it
545 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
546 // to combine multiple loads / stores.
547 bool CanEliminateFrame = true;
548 bool CS1Spilled = false;
549 bool LRSpilled = false;
550 unsigned NumGPRSpills = 0;
551 SmallVector<unsigned, 4> UnspilledCS1GPRs;
552 SmallVector<unsigned, 4> UnspilledCS2GPRs;
553 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
555 // Don't spill FP if the frame can be eliminated. This is determined
556 // by scanning the callee-save registers to see if any is used.
557 const unsigned *CSRegs = getCalleeSavedRegs();
558 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
559 for (unsigned i = 0; CSRegs[i]; ++i) {
560 unsigned Reg = CSRegs[i];
561 bool Spilled = false;
562 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
563 AFI->setCSRegisterIsSpilled(Reg);
565 CanEliminateFrame = false;
567 // Check alias registers too.
568 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
569 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
571 CanEliminateFrame = false;
576 if (CSRegClasses[i] == ARM::GPRRegisterClass ||
577 CSRegClasses[i] == ARM::tGPRRegisterClass) {
581 if (!STI.isTargetDarwin()) {
588 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
603 if (!STI.isTargetDarwin()) {
604 UnspilledCS1GPRs.push_back(Reg);
614 UnspilledCS1GPRs.push_back(Reg);
617 UnspilledCS2GPRs.push_back(Reg);
624 bool ForceLRSpill = false;
625 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
626 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
627 // Force LR to be spilled if the Thumb function size is > 2048. This enables
628 // use of BL to implement far jump. If it turns out that it's not needed
629 // then the branch fix up path will undo it.
630 if (FnSize >= (1 << 11)) {
631 CanEliminateFrame = false;
636 bool ExtraCSSpill = false;
637 if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
638 AFI->setHasStackFrame(true);
640 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
641 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
642 if (!LRSpilled && CS1Spilled) {
643 MF.getRegInfo().setPhysRegUsed(ARM::LR);
644 AFI->setCSRegisterIsSpilled(ARM::LR);
646 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
647 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
648 ForceLRSpill = false;
652 // Darwin ABI requires FP to point to the stack slot that contains the
654 if (STI.isTargetDarwin() || hasFP(MF)) {
655 MF.getRegInfo().setPhysRegUsed(FramePtr);
659 // If stack and double are 8-byte aligned and we are spilling an odd number
660 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
661 // the integer and double callee save areas.
662 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
663 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
664 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
665 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
666 unsigned Reg = UnspilledCS1GPRs[i];
667 // Don't spill high register if the function is thumb1
668 if (!AFI->isThumb1OnlyFunction() ||
669 isARMLowRegister(Reg) || Reg == ARM::LR) {
670 MF.getRegInfo().setPhysRegUsed(Reg);
671 AFI->setCSRegisterIsSpilled(Reg);
672 if (!isReservedReg(MF, Reg))
677 } else if (!UnspilledCS2GPRs.empty() &&
678 !AFI->isThumb1OnlyFunction()) {
679 unsigned Reg = UnspilledCS2GPRs.front();
680 MF.getRegInfo().setPhysRegUsed(Reg);
681 AFI->setCSRegisterIsSpilled(Reg);
682 if (!isReservedReg(MF, Reg))
687 // Estimate if we might need to scavenge a register at some point in order
688 // to materialize a stack offset. If so, either spill one additional
689 // callee-saved register or reserve a special spill slot to facilitate
690 // register scavenging. Thumb1 needs a spill slot for stack pointer
691 // adjustments also, even when the frame itself is small.
692 if (RS && !ExtraCSSpill) {
693 MachineFrameInfo *MFI = MF.getFrameInfo();
694 // If any of the stack slot references may be out of range of an
695 // immediate offset, make sure a register (or a spill slot) is
696 // available for the register scavenger. Note that if we're indexing
697 // off the frame pointer, the effective stack size is 4 bytes larger
698 // since the FP points to the stack slot of the previous FP.
699 if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
700 >= estimateRSStackSizeLimit(MF)) {
701 // If any non-reserved CS register isn't spilled, just spill one or two
702 // extra. That should take care of it!
703 unsigned NumExtras = TargetAlign / 4;
704 SmallVector<unsigned, 2> Extras;
705 while (NumExtras && !UnspilledCS1GPRs.empty()) {
706 unsigned Reg = UnspilledCS1GPRs.back();
707 UnspilledCS1GPRs.pop_back();
708 if (!isReservedReg(MF, Reg)) {
709 Extras.push_back(Reg);
713 // For non-Thumb1 functions, also check for hi-reg CS registers
714 if (!AFI->isThumb1OnlyFunction()) {
715 while (NumExtras && !UnspilledCS2GPRs.empty()) {
716 unsigned Reg = UnspilledCS2GPRs.back();
717 UnspilledCS2GPRs.pop_back();
718 if (!isReservedReg(MF, Reg)) {
719 Extras.push_back(Reg);
724 if (Extras.size() && NumExtras == 0) {
725 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
726 MF.getRegInfo().setPhysRegUsed(Extras[i]);
727 AFI->setCSRegisterIsSpilled(Extras[i]);
729 } else if (!AFI->isThumb1OnlyFunction()) {
730 // note: Thumb1 functions spill to R12, not the stack.
731 // Reserve a slot closest to SP or frame pointer.
732 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
733 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
734 RC->getAlignment()));
741 MF.getRegInfo().setPhysRegUsed(ARM::LR);
742 AFI->setCSRegisterIsSpilled(ARM::LR);
743 AFI->setLRIsSpilledForFarJump(true);
747 unsigned ARMBaseRegisterInfo::getRARegister() const {
751 unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
752 if (STI.isTargetDarwin() || hasFP(MF))
757 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
758 llvm_unreachable("What is the exception register");
762 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
763 llvm_unreachable("What is the exception handler register");
767 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
768 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
771 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
772 const MachineFunction &MF) const {
775 // Return 0 if either register of the pair is a special register.
784 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
786 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
788 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
860 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
861 const MachineFunction &MF) const {
864 // Return 0 if either register of the pair is a special register.
873 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
875 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
877 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
949 /// emitLoadConstPool - Emits a load from constpool to materialize the
950 /// specified immediate.
951 void ARMBaseRegisterInfo::
952 emitLoadConstPool(MachineBasicBlock &MBB,
953 MachineBasicBlock::iterator &MBBI,
955 unsigned DestReg, unsigned SubIdx, int Val,
956 ARMCC::CondCodes Pred,
957 unsigned PredReg) const {
958 MachineFunction &MF = *MBB.getParent();
959 MachineConstantPool *ConstantPool = MF.getConstantPool();
961 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
962 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
964 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
965 .addReg(DestReg, getDefRegState(true), SubIdx)
966 .addConstantPoolIndex(Idx)
967 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
970 bool ARMBaseRegisterInfo::
971 requiresRegisterScavenging(const MachineFunction &MF) const {
975 bool ARMBaseRegisterInfo::
976 requiresFrameIndexScavenging(const MachineFunction &MF) const {
977 return ScavengeFrameIndexVals;
980 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
981 // not required, we reserve argument space for call sites in the function
982 // immediately on entry to the current function. This eliminates the need for
983 // add/sub sp brackets around call sites. Returns true if the call frame is
984 // included as part of the stack frame.
985 bool ARMBaseRegisterInfo::
986 hasReservedCallFrame(MachineFunction &MF) const {
987 const MachineFrameInfo *FFI = MF.getFrameInfo();
988 unsigned CFSize = FFI->getMaxCallFrameSize();
989 // It's not always a good idea to include the call frame as part of the
990 // stack frame. ARM (especially Thumb) has small immediate offset to
991 // address the stack frame. So a large call frame can cause poor codegen
992 // and may even makes it impossible to scavenge a register.
993 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
996 return !MF.getFrameInfo()->hasVarSizedObjects();
1000 emitSPUpdate(bool isARM,
1001 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1002 DebugLoc dl, const ARMBaseInstrInfo &TII,
1004 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1006 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1007 Pred, PredReg, TII);
1009 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1010 Pred, PredReg, TII);
1014 void ARMBaseRegisterInfo::
1015 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1016 MachineBasicBlock::iterator I) const {
1017 if (!hasReservedCallFrame(MF)) {
1018 // If we have alloca, convert as follows:
1019 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1020 // ADJCALLSTACKUP -> add, sp, sp, amount
1021 MachineInstr *Old = I;
1022 DebugLoc dl = Old->getDebugLoc();
1023 unsigned Amount = Old->getOperand(0).getImm();
1025 // We need to keep the stack aligned properly. To do this, we round the
1026 // amount of space needed for the outgoing arguments up to the next
1027 // alignment boundary.
1028 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1029 Amount = (Amount+Align-1)/Align*Align;
1031 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1032 assert(!AFI->isThumb1OnlyFunction() &&
1033 "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
1034 bool isARM = !AFI->isThumbFunction();
1036 // Replace the pseudo instruction with a new instruction...
1037 unsigned Opc = Old->getOpcode();
1038 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
1039 // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1040 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1041 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1042 unsigned PredReg = Old->getOperand(2).getReg();
1043 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1045 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1046 unsigned PredReg = Old->getOperand(3).getReg();
1047 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1048 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1055 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
1056 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
1057 /// register first and then a spilled callee-saved register if that fails.
1059 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
1060 ARMFunctionInfo *AFI) {
1061 unsigned Reg = RS ? RS->FindUnusedReg(RC) : (unsigned) ARM::R12;
1062 assert(!AFI->isThumb1OnlyFunction());
1067 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1068 int SPAdj, int *Value,
1069 RegScavenger *RS) const {
1071 MachineInstr &MI = *II;
1072 MachineBasicBlock &MBB = *MI.getParent();
1073 MachineFunction &MF = *MBB.getParent();
1074 const MachineFrameInfo *MFI = MF.getFrameInfo();
1075 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1076 assert(!AFI->isThumb1OnlyFunction() &&
1077 "This eliminateFrameIndex does not support Thumb1!");
1079 while (!MI.getOperand(i).isFI()) {
1081 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1084 unsigned FrameReg = ARM::SP;
1085 int FrameIndex = MI.getOperand(i).getIndex();
1086 int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1088 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1089 Offset -= AFI->getGPRCalleeSavedArea1Offset();
1090 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1091 Offset -= AFI->getGPRCalleeSavedArea2Offset();
1092 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1093 Offset -= AFI->getDPRCalleeSavedAreaOffset();
1094 else if (hasFP(MF) && AFI->hasStackFrame()) {
1095 assert(SPAdj == 0 && "Unexpected stack offset!");
1096 // Use frame pointer to reference fixed objects unless this is a
1097 // frameless function,
1098 FrameReg = getFrameRegister(MF);
1099 Offset -= AFI->getFramePtrSpillOffset();
1102 // modify MI as necessary to handle as much of 'Offset' as possible
1104 if (!AFI->isThumbFunction())
1105 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1107 assert(AFI->isThumb2Function());
1108 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1113 // If we get here, the immediate doesn't fit into the instruction. We folded
1114 // as much as possible above, handle the rest, providing a register that is
1117 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) &&
1118 "This code isn't needed if offset already handled!");
1120 unsigned ScratchReg = 0;
1121 int PIdx = MI.findFirstPredOperandIdx();
1122 ARMCC::CondCodes Pred = (PIdx == -1)
1123 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1124 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1126 // Must be addrmode4.
1127 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1129 if (!ScavengeFrameIndexVals) {
1130 // Insert a set of r12 with the full address: r12 = sp + offset
1131 // If the offset we have is too large to fit into the instruction, we need
1132 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
1134 ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI);
1135 if (ScratchReg == 0)
1136 // No register is "free". Scavenge a register.
1137 ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj);
1139 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1142 if (!AFI->isThumbFunction())
1143 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1144 Offset, Pred, PredReg, TII);
1146 assert(AFI->isThumb2Function());
1147 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1148 Offset, Pred, PredReg, TII);
1150 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1151 if (!ReuseFrameIndexVals || !ScavengeFrameIndexVals)
1157 /// Move iterator pass the next bunch of callee save load / store ops for
1158 /// the particular spill area (1: integer area 1, 2: integer area 2,
1159 /// 3: fp area, 0: don't care).
1160 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1161 MachineBasicBlock::iterator &MBBI,
1162 int Opc1, int Opc2, unsigned Area,
1163 const ARMSubtarget &STI) {
1164 while (MBBI != MBB.end() &&
1165 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1166 MBBI->getOperand(1).isFI()) {
1169 unsigned Category = 0;
1170 switch (MBBI->getOperand(0).getReg()) {
1171 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1175 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1176 Category = STI.isTargetDarwin() ? 2 : 1;
1178 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1179 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1186 if (Done || Category != Area)
1194 void ARMBaseRegisterInfo::
1195 emitPrologue(MachineFunction &MF) const {
1196 MachineBasicBlock &MBB = MF.front();
1197 MachineBasicBlock::iterator MBBI = MBB.begin();
1198 MachineFrameInfo *MFI = MF.getFrameInfo();
1199 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1200 assert(!AFI->isThumb1OnlyFunction() &&
1201 "This emitPrologue does not suppor Thumb1!");
1202 bool isARM = !AFI->isThumbFunction();
1203 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1204 unsigned NumBytes = MFI->getStackSize();
1205 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1206 DebugLoc dl = (MBBI != MBB.end() ?
1207 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1209 // Determine the sizes of each callee-save spill areas and record which frame
1210 // belongs to which callee-save spill areas.
1211 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1212 int FramePtrSpillFI = 0;
1214 // Allocate the vararg register save area. This is not counted in NumBytes.
1216 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1218 if (!AFI->hasStackFrame()) {
1220 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1224 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1225 unsigned Reg = CSI[i].getReg();
1226 int FI = CSI[i].getFrameIdx();
1233 if (Reg == FramePtr)
1234 FramePtrSpillFI = FI;
1235 AFI->addGPRCalleeSavedArea1Frame(FI);
1242 if (Reg == FramePtr)
1243 FramePtrSpillFI = FI;
1244 if (STI.isTargetDarwin()) {
1245 AFI->addGPRCalleeSavedArea2Frame(FI);
1248 AFI->addGPRCalleeSavedArea1Frame(FI);
1253 AFI->addDPRCalleeSavedAreaFrame(FI);
1258 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1259 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1260 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1262 // Set FP to point to the stack slot that contains the previous FP.
1263 // For Darwin, FP is R7, which has now been stored in spill area 1.
1264 // Otherwise, if this is not Darwin, all the callee-saved registers go
1265 // into spill area 1, including the FP in R11. In either case, it is
1266 // now safe to emit this assignment.
1267 if (STI.isTargetDarwin() || hasFP(MF)) {
1268 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1269 MachineInstrBuilder MIB =
1270 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1271 .addFrameIndex(FramePtrSpillFI).addImm(0);
1272 AddDefaultCC(AddDefaultPred(MIB));
1275 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1276 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1278 // Build the new SUBri to adjust SP for FP callee-save spill area.
1279 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1280 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1282 // Determine starting offsets of spill areas.
1283 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1284 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1285 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1286 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1287 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1288 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1289 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1291 NumBytes = DPRCSOffset;
1293 // Insert it after all the callee-save spills.
1294 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI);
1295 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1298 if (STI.isTargetELF() && hasFP(MF)) {
1299 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1300 AFI->getFramePtrSpillOffset());
1303 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1304 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1305 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1308 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1309 for (unsigned i = 0; CSRegs[i]; ++i)
1310 if (Reg == CSRegs[i])
1315 static bool isCSRestore(MachineInstr *MI,
1316 const ARMBaseInstrInfo &TII,
1317 const unsigned *CSRegs) {
1318 return ((MI->getOpcode() == (int)ARM::FLDD ||
1319 MI->getOpcode() == (int)ARM::LDR ||
1320 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1321 MI->getOperand(1).isFI() &&
1322 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1325 void ARMBaseRegisterInfo::
1326 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1327 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1328 assert(MBBI->getDesc().isReturn() &&
1329 "Can only insert epilog into returning blocks");
1330 DebugLoc dl = MBBI->getDebugLoc();
1331 MachineFrameInfo *MFI = MF.getFrameInfo();
1332 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1333 assert(!AFI->isThumb1OnlyFunction() &&
1334 "This emitEpilogue does not suppor Thumb1!");
1335 bool isARM = !AFI->isThumbFunction();
1337 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1338 int NumBytes = (int)MFI->getStackSize();
1340 if (!AFI->hasStackFrame()) {
1342 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1344 // Unwind MBBI to point to first LDR / FLDD.
1345 const unsigned *CSRegs = getCalleeSavedRegs();
1346 if (MBBI != MBB.begin()) {
1349 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1350 if (!isCSRestore(MBBI, TII, CSRegs))
1354 // Move SP to start of FP callee save spill area.
1355 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1356 AFI->getGPRCalleeSavedArea2Size() +
1357 AFI->getDPRCalleeSavedAreaSize());
1359 // Darwin ABI requires FP to point to the stack slot that contains the
1361 bool HasFP = hasFP(MF);
1362 if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1363 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1364 // Reset SP based on frame pointer only if the stack frame extends beyond
1365 // frame pointer stack slot or target is ELF and the function has FP.
1367 AFI->getGPRCalleeSavedArea2Size() ||
1368 AFI->getDPRCalleeSavedAreaSize() ||
1369 AFI->getDPRCalleeSavedAreaOffset()) {
1372 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1375 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1380 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1382 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1384 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1388 } else if (NumBytes)
1389 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1391 // Move SP to start of integer callee save spill area 2.
1392 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI);
1393 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1395 // Move SP to start of integer callee save spill area 1.
1396 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1397 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1399 // Move SP to SP upon entry to the function.
1400 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1401 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1405 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1408 #include "ARMGenRegisterInfo.inc"