1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Target/TargetInstrInfo.h"
23 class ARMBaseRegisterInfo;
25 /// ARMII - This namespace holds all of the target specific flags that
26 /// instruction info tracks.
30 //===------------------------------------------------------------------===//
33 //===------------------------------------------------------------------===//
34 // This four-bit field describes the addressing mode used.
47 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
51 AddrModeT2_pc = 14, // +/- i12 for pc relative data
52 AddrModeT2_i8s4 = 15, // i8 * 4
54 // Size* - Flags to keep track of the size of an instruction.
56 SizeMask = 7 << SizeShift,
57 SizeSpecial = 1, // 0 byte pseudo or special case.
62 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
63 // and store ops only. Generic "updating" flag is used for ld/st multiple.
65 IndexModeMask = 3 << IndexModeShift,
70 //===------------------------------------------------------------------===//
71 // Instruction encoding formats.
74 FormMask = 0x3f << FormShift,
76 // Pseudo instructions
77 Pseudo = 0 << FormShift,
79 // Multiply instructions
80 MulFrm = 1 << FormShift,
82 // Branch instructions
83 BrFrm = 2 << FormShift,
84 BrMiscFrm = 3 << FormShift,
86 // Data Processing instructions
87 DPFrm = 4 << FormShift,
88 DPSoRegFrm = 5 << FormShift,
91 LdFrm = 6 << FormShift,
92 StFrm = 7 << FormShift,
93 LdMiscFrm = 8 << FormShift,
94 StMiscFrm = 9 << FormShift,
95 LdStMulFrm = 10 << FormShift,
97 LdStExFrm = 11 << FormShift,
99 // Miscellaneous arithmetic instructions
100 ArithMiscFrm = 12 << FormShift,
101 SatFrm = 13 << FormShift,
103 // Extend instructions
104 ExtFrm = 14 << FormShift,
107 VFPUnaryFrm = 15 << FormShift,
108 VFPBinaryFrm = 16 << FormShift,
109 VFPConv1Frm = 17 << FormShift,
110 VFPConv2Frm = 18 << FormShift,
111 VFPConv3Frm = 19 << FormShift,
112 VFPConv4Frm = 20 << FormShift,
113 VFPConv5Frm = 21 << FormShift,
114 VFPLdStFrm = 22 << FormShift,
115 VFPLdStMulFrm = 23 << FormShift,
116 VFPMiscFrm = 24 << FormShift,
119 ThumbFrm = 25 << FormShift,
121 // Miscelleaneous format
122 MiscFrm = 26 << FormShift,
125 NGetLnFrm = 27 << FormShift,
126 NSetLnFrm = 28 << FormShift,
127 NDupFrm = 29 << FormShift,
128 NLdStFrm = 30 << FormShift,
129 N1RegModImmFrm= 31 << FormShift,
130 N2RegFrm = 32 << FormShift,
131 NVCVTFrm = 33 << FormShift,
132 NVDupLnFrm = 34 << FormShift,
133 N2RegVShLFrm = 35 << FormShift,
134 N2RegVShRFrm = 36 << FormShift,
135 N3RegFrm = 37 << FormShift,
136 N3RegVShFrm = 38 << FormShift,
137 NVExtFrm = 39 << FormShift,
138 NVMulSLFrm = 40 << FormShift,
139 NVTBLFrm = 41 << FormShift,
141 //===------------------------------------------------------------------===//
144 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
145 // it doesn't have a Rn operand.
148 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
149 // a 16-bit Thumb instruction if certain conditions are met.
150 Xform16Bit = 1 << 17,
152 //===------------------------------------------------------------------===//
155 DomainMask = 3 << DomainShift,
156 DomainGeneral = 0 << DomainShift,
157 DomainVFP = 1 << DomainShift,
158 DomainNEON = 2 << DomainShift,
160 //===------------------------------------------------------------------===//
161 // Field shifts - such shifts are used to set field while generating
162 // machine instructions.
164 // FIXME: This list will need adjusting/fixing as the MC code emitter
165 // takes shape and the ARMCodeEmitter.cpp bits go away.
191 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
192 const ARMSubtarget &Subtarget;
194 // Can be only subclassed.
195 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
197 // Return the non-pre/post incrementing version of 'Opc'. Return 0
198 // if there is not such an opcode.
199 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
201 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
202 MachineBasicBlock::iterator &MBBI,
203 LiveVariables *LV) const;
205 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
206 const ARMSubtarget &getSubtarget() const { return Subtarget; }
208 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
209 MachineBasicBlock::iterator MI,
210 const std::vector<CalleeSavedInfo> &CSI,
211 const TargetRegisterInfo *TRI) const;
214 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
215 MachineBasicBlock *&FBB,
216 SmallVectorImpl<MachineOperand> &Cond,
217 bool AllowModify = false) const;
218 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
219 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
220 MachineBasicBlock *FBB,
221 const SmallVectorImpl<MachineOperand> &Cond,
225 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
227 // Predication support.
228 bool isPredicated(const MachineInstr *MI) const {
229 int PIdx = MI->findFirstPredOperandIdx();
230 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
233 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
234 int PIdx = MI->findFirstPredOperandIdx();
235 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
240 bool PredicateInstruction(MachineInstr *MI,
241 const SmallVectorImpl<MachineOperand> &Pred) const;
244 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
245 const SmallVectorImpl<MachineOperand> &Pred2) const;
247 virtual bool DefinesPredicate(MachineInstr *MI,
248 std::vector<MachineOperand> &Pred) const;
250 virtual bool isPredicable(MachineInstr *MI) const;
252 /// GetInstSize - Returns the size of the specified MachineInstr.
254 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
256 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
257 int &FrameIndex) const;
258 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
259 int &FrameIndex) const;
261 virtual void copyPhysReg(MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator I, DebugLoc DL,
263 unsigned DestReg, unsigned SrcReg,
266 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
267 MachineBasicBlock::iterator MBBI,
268 unsigned SrcReg, bool isKill, int FrameIndex,
269 const TargetRegisterClass *RC,
270 const TargetRegisterInfo *TRI) const;
272 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
273 MachineBasicBlock::iterator MBBI,
274 unsigned DestReg, int FrameIndex,
275 const TargetRegisterClass *RC,
276 const TargetRegisterInfo *TRI) const;
278 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
284 virtual void reMaterialize(MachineBasicBlock &MBB,
285 MachineBasicBlock::iterator MI,
286 unsigned DestReg, unsigned SubIdx,
287 const MachineInstr *Orig,
288 const TargetRegisterInfo &TRI) const;
290 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
292 virtual bool produceSameValue(const MachineInstr *MI0,
293 const MachineInstr *MI1) const;
295 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
296 /// determine if two loads are loading from the same base address. It should
297 /// only return true if the base pointers are the same and the only
298 /// differences between the two addresses is the offset. It also returns the
299 /// offsets by reference.
300 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
301 int64_t &Offset1, int64_t &Offset2)const;
303 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
304 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
305 /// be scheduled togther. On some targets if two loads are loading from
306 /// addresses in the same cache line, it's better if they are scheduled
307 /// together. This function takes two integers that represent the load offsets
308 /// from the common base address. It returns true if it decides it's desirable
309 /// to schedule the two loads together. "NumLoads" is the number of loads that
310 /// have already been scheduled after Load1.
311 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
312 int64_t Offset1, int64_t Offset2,
313 unsigned NumLoads) const;
315 virtual bool isSchedulingBoundary(const MachineInstr *MI,
316 const MachineBasicBlock *MBB,
317 const MachineFunction &MF) const;
319 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
321 float Prob, float Confidence) const;
323 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT,
324 MachineBasicBlock &FMBB,unsigned NumF,
325 float Probability, float Confidence) const;
327 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
330 float Confidence) const {
331 return NumInstrs && NumInstrs == 1;
334 /// AnalyzeCompare - For a comparison instruction, return the source register
335 /// in SrcReg and the value it compares against in CmpValue. Return true if
336 /// the comparison instruction can be analyzed.
337 virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
338 int &CmpMask, int &CmpValue) const;
340 /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
341 /// that we can remove a "comparison with zero".
342 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
343 int CmpMask, int CmpValue,
344 MachineBasicBlock::iterator &MII) const;
346 virtual unsigned getNumMicroOps(const MachineInstr *MI,
347 const InstrItineraryData *ItinData) const;
350 int getOperandLatency(const InstrItineraryData *ItinData,
351 const MachineInstr *DefMI, unsigned DefIdx,
352 const MachineInstr *UseMI, unsigned UseIdx) const;
354 int getOperandLatency(const InstrItineraryData *ItinData,
355 SDNode *DefNode, unsigned DefIdx,
356 SDNode *UseNode, unsigned UseIdx) const;
358 int getVLDMDefCycle(const InstrItineraryData *ItinData,
359 const TargetInstrDesc &DefTID,
361 unsigned DefIdx, unsigned DefAlign) const;
362 int getLDMDefCycle(const InstrItineraryData *ItinData,
363 const TargetInstrDesc &DefTID,
365 unsigned DefIdx, unsigned DefAlign) const;
366 int getVSTMUseCycle(const InstrItineraryData *ItinData,
367 const TargetInstrDesc &UseTID,
369 unsigned UseIdx, unsigned UseAlign) const;
370 int getSTMUseCycle(const InstrItineraryData *ItinData,
371 const TargetInstrDesc &UseTID,
373 unsigned UseIdx, unsigned UseAlign) const;
374 int getOperandLatency(const InstrItineraryData *ItinData,
375 const TargetInstrDesc &DefTID,
376 unsigned DefIdx, unsigned DefAlign,
377 const TargetInstrDesc &UseTID,
378 unsigned UseIdx, unsigned UseAlign) const;
382 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
383 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
387 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
388 return MIB.addReg(0);
392 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
393 bool isDead = false) {
394 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
398 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
399 return MIB.addReg(0);
403 bool isUncondBranchOpcode(int Opc) {
404 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
408 bool isCondBranchOpcode(int Opc) {
409 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
413 bool isJumpTableBranchOpcode(int Opc) {
414 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
415 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
419 bool isIndirectBranchOpcode(int Opc) {
420 return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
423 /// getInstrPredicate - If instruction is predicated, returns its predicate
424 /// condition, otherwise returns AL. It also returns the condition code
425 /// register by reference.
426 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
428 int getMatchingCondBranchOpcode(int Opc);
430 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
431 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
433 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
434 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
435 unsigned DestReg, unsigned BaseReg, int NumBytes,
436 ARMCC::CondCodes Pred, unsigned PredReg,
437 const ARMBaseInstrInfo &TII);
439 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
440 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
441 unsigned DestReg, unsigned BaseReg, int NumBytes,
442 ARMCC::CondCodes Pred, unsigned PredReg,
443 const ARMBaseInstrInfo &TII);
446 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
447 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
448 /// offset could not be handled directly in MI, and return the left-over
449 /// portion by reference.
450 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
451 unsigned FrameReg, int &Offset,
452 const ARMBaseInstrInfo &TII);
454 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
455 unsigned FrameReg, int &Offset,
456 const ARMBaseInstrInfo &TII);
458 } // End llvm namespace