1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMHazardRecognizer.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
54 unsigned MLxOpc; // MLA / MLS opcode
55 unsigned MulOpc; // Expanded multiplication opcode
56 unsigned AddSubOpc; // Expanded add / sub opcode
57 bool NegAcc; // True if the acc is negated before the add / sub.
58 bool HasLane; // True if instruction has an extra "lane" operand.
61 static const ARM_MLxEntry ARM_MLxTable[] = {
62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
84 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
89 assert(false && "Duplicated entries?");
90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
95 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
96 // currently defaults to no prepass hazard recognizer.
97 ScheduleHazardRecognizer *ARMBaseInstrInfo::
98 CreateTargetHazardRecognizer(const TargetMachine *TM,
99 const ScheduleDAG *DAG) const {
100 if (usePreRAHazardRecognizer()) {
101 const InstrItineraryData *II = TM->getInstrItineraryData();
102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
107 ScheduleHazardRecognizer *ARMBaseInstrInfo::
108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
109 const ScheduleDAG *DAG) const {
110 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
111 return (ScheduleHazardRecognizer *)
112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
117 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
118 MachineBasicBlock::iterator &MBBI,
119 LiveVariables *LV) const {
120 // FIXME: Thumb2 support.
125 MachineInstr *MI = MBBI;
126 MachineFunction &MF = *MI->getParent()->getParent();
127 uint64_t TSFlags = MI->getDesc().TSFlags;
129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
130 default: return NULL;
131 case ARMII::IndexModePre:
134 case ARMII::IndexModePost:
138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
144 MachineInstr *UpdateMI = NULL;
145 MachineInstr *MemMI = NULL;
146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
147 const MCInstrDesc &MCID = MI->getDesc();
148 unsigned NumOps = MCID.getNumOperands();
149 bool isLoad = !MI->mayStore();
150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
151 const MachineOperand &Base = MI->getOperand(2);
152 const MachineOperand &Offset = MI->getOperand(NumOps-3);
153 unsigned WBReg = WB.getReg();
154 unsigned BaseReg = Base.getReg();
155 unsigned OffReg = Offset.getReg();
156 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
160 assert(false && "Unknown indexed op!");
162 case ARMII::AddrMode2: {
163 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
164 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
166 if (ARM_AM::getSOImmVal(Amt) == -1)
167 // Can't encode it in a so_imm operand. This transformation will
168 // add more than 1 instruction. Abandon!
170 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
171 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
172 .addReg(BaseReg).addImm(Amt)
173 .addImm(Pred).addReg(0).addReg(0);
174 } else if (Amt != 0) {
175 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
176 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
177 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
178 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
179 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
180 .addImm(Pred).addReg(0).addReg(0);
182 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
183 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
184 .addReg(BaseReg).addReg(OffReg)
185 .addImm(Pred).addReg(0).addReg(0);
188 case ARMII::AddrMode3 : {
189 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
190 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
192 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
193 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
194 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
195 .addReg(BaseReg).addImm(Amt)
196 .addImm(Pred).addReg(0).addReg(0);
198 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
199 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
200 .addReg(BaseReg).addReg(OffReg)
201 .addImm(Pred).addReg(0).addReg(0);
206 std::vector<MachineInstr*> NewMIs;
209 MemMI = BuildMI(MF, MI->getDebugLoc(),
210 get(MemOpc), MI->getOperand(0).getReg())
211 .addReg(WBReg).addImm(0).addImm(Pred);
213 MemMI = BuildMI(MF, MI->getDebugLoc(),
214 get(MemOpc)).addReg(MI->getOperand(1).getReg())
215 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
216 NewMIs.push_back(MemMI);
217 NewMIs.push_back(UpdateMI);
220 MemMI = BuildMI(MF, MI->getDebugLoc(),
221 get(MemOpc), MI->getOperand(0).getReg())
222 .addReg(BaseReg).addImm(0).addImm(Pred);
224 MemMI = BuildMI(MF, MI->getDebugLoc(),
225 get(MemOpc)).addReg(MI->getOperand(1).getReg())
226 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
228 UpdateMI->getOperand(0).setIsDead();
229 NewMIs.push_back(UpdateMI);
230 NewMIs.push_back(MemMI);
233 // Transfer LiveVariables states, kill / dead info.
235 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236 MachineOperand &MO = MI->getOperand(i);
237 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
238 unsigned Reg = MO.getReg();
240 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
242 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
244 LV->addVirtualRegisterDead(Reg, NewMI);
246 if (MO.isUse() && MO.isKill()) {
247 for (unsigned j = 0; j < 2; ++j) {
248 // Look at the two new MI's in reverse order.
249 MachineInstr *NewMI = NewMIs[j];
250 if (!NewMI->readsRegister(Reg))
252 LV->addVirtualRegisterKilled(Reg, NewMI);
253 if (VI.removeKill(MI))
254 VI.Kills.push_back(NewMI);
262 MFI->insert(MBBI, NewMIs[1]);
263 MFI->insert(MBBI, NewMIs[0]);
269 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
270 MachineBasicBlock *&FBB,
271 SmallVectorImpl<MachineOperand> &Cond,
272 bool AllowModify) const {
273 // If the block has no terminators, it just falls into the block after it.
274 MachineBasicBlock::iterator I = MBB.end();
275 if (I == MBB.begin())
278 while (I->isDebugValue()) {
279 if (I == MBB.begin())
283 if (!isUnpredicatedTerminator(I))
286 // Get the last instruction in the block.
287 MachineInstr *LastInst = I;
289 // If there is only one terminator instruction, process it.
290 unsigned LastOpc = LastInst->getOpcode();
291 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
292 if (isUncondBranchOpcode(LastOpc)) {
293 TBB = LastInst->getOperand(0).getMBB();
296 if (isCondBranchOpcode(LastOpc)) {
297 // Block ends with fall-through condbranch.
298 TBB = LastInst->getOperand(0).getMBB();
299 Cond.push_back(LastInst->getOperand(1));
300 Cond.push_back(LastInst->getOperand(2));
303 return true; // Can't handle indirect branch.
306 // Get the instruction before it if it is a terminator.
307 MachineInstr *SecondLastInst = I;
308 unsigned SecondLastOpc = SecondLastInst->getOpcode();
310 // If AllowModify is true and the block ends with two or more unconditional
311 // branches, delete all but the first unconditional branch.
312 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
313 while (isUncondBranchOpcode(SecondLastOpc)) {
314 LastInst->eraseFromParent();
315 LastInst = SecondLastInst;
316 LastOpc = LastInst->getOpcode();
317 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
318 // Return now the only terminator is an unconditional branch.
319 TBB = LastInst->getOperand(0).getMBB();
323 SecondLastOpc = SecondLastInst->getOpcode();
328 // If there are three terminators, we don't know what sort of block this is.
329 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
332 // If the block ends with a B and a Bcc, handle it.
333 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
334 TBB = SecondLastInst->getOperand(0).getMBB();
335 Cond.push_back(SecondLastInst->getOperand(1));
336 Cond.push_back(SecondLastInst->getOperand(2));
337 FBB = LastInst->getOperand(0).getMBB();
341 // If the block ends with two unconditional branches, handle it. The second
342 // one is not executed, so remove it.
343 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
344 TBB = SecondLastInst->getOperand(0).getMBB();
347 I->eraseFromParent();
351 // ...likewise if it ends with a branch table followed by an unconditional
352 // branch. The branch folder can create these, and we must get rid of them for
353 // correctness of Thumb constant islands.
354 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
355 isIndirectBranchOpcode(SecondLastOpc)) &&
356 isUncondBranchOpcode(LastOpc)) {
359 I->eraseFromParent();
363 // Otherwise, can't handle this.
368 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
369 MachineBasicBlock::iterator I = MBB.end();
370 if (I == MBB.begin()) return 0;
372 while (I->isDebugValue()) {
373 if (I == MBB.begin())
377 if (!isUncondBranchOpcode(I->getOpcode()) &&
378 !isCondBranchOpcode(I->getOpcode()))
381 // Remove the branch.
382 I->eraseFromParent();
386 if (I == MBB.begin()) return 1;
388 if (!isCondBranchOpcode(I->getOpcode()))
391 // Remove the branch.
392 I->eraseFromParent();
397 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
398 MachineBasicBlock *FBB,
399 const SmallVectorImpl<MachineOperand> &Cond,
401 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
402 int BOpc = !AFI->isThumbFunction()
403 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
404 int BccOpc = !AFI->isThumbFunction()
405 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
406 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
408 // Shouldn't be a fall through.
409 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
410 assert((Cond.size() == 2 || Cond.size() == 0) &&
411 "ARM branch conditions have two components!");
414 if (Cond.empty()) { // Unconditional branch?
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
418 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
420 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
421 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
425 // Two-way conditional branch.
426 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
427 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
431 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
435 bool ARMBaseInstrInfo::
436 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
437 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
438 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
442 bool ARMBaseInstrInfo::
443 PredicateInstruction(MachineInstr *MI,
444 const SmallVectorImpl<MachineOperand> &Pred) const {
445 unsigned Opc = MI->getOpcode();
446 if (isUncondBranchOpcode(Opc)) {
447 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
448 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
449 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
453 int PIdx = MI->findFirstPredOperandIdx();
455 MachineOperand &PMO = MI->getOperand(PIdx);
456 PMO.setImm(Pred[0].getImm());
457 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
463 bool ARMBaseInstrInfo::
464 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
465 const SmallVectorImpl<MachineOperand> &Pred2) const {
466 if (Pred1.size() > 2 || Pred2.size() > 2)
469 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
470 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
480 return CC2 == ARMCC::HI;
482 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
484 return CC2 == ARMCC::GT;
486 return CC2 == ARMCC::LT;
490 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
491 std::vector<MachineOperand> &Pred) const {
492 // FIXME: This confuses implicit_def with optional CPSR def.
493 const MCInstrDesc &MCID = MI->getDesc();
494 if (!MCID.getImplicitDefs() && !MI->hasOptionalDef())
498 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
499 const MachineOperand &MO = MI->getOperand(i);
500 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
509 /// isPredicable - Return true if the specified instruction can be predicated.
510 /// By default, this returns true for every instruction with a
511 /// PredicateOperand.
512 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
513 if (!MI->isPredicable())
516 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
517 ARMFunctionInfo *AFI =
518 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
519 return AFI->isThumb2Function();
524 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
525 LLVM_ATTRIBUTE_NOINLINE
526 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
528 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
530 assert(JTI < JT.size());
531 return JT[JTI].MBBs.size();
534 /// GetInstSize - Return the size of the specified MachineInstr.
536 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
537 const MachineBasicBlock &MBB = *MI->getParent();
538 const MachineFunction *MF = MBB.getParent();
539 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
541 const MCInstrDesc &MCID = MI->getDesc();
543 return MCID.getSize();
545 // If this machine instr is an inline asm, measure it.
546 if (MI->getOpcode() == ARM::INLINEASM)
547 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
550 unsigned Opc = MI->getOpcode();
552 case TargetOpcode::IMPLICIT_DEF:
553 case TargetOpcode::KILL:
554 case TargetOpcode::PROLOG_LABEL:
555 case TargetOpcode::EH_LABEL:
556 case TargetOpcode::DBG_VALUE:
558 case ARM::MOVi16_ga_pcrel:
559 case ARM::MOVTi16_ga_pcrel:
560 case ARM::t2MOVi16_ga_pcrel:
561 case ARM::t2MOVTi16_ga_pcrel:
564 case ARM::t2MOVi32imm:
566 case ARM::CONSTPOOL_ENTRY:
567 // If this machine instr is a constant pool entry, its size is recorded as
569 return MI->getOperand(2).getImm();
570 case ARM::Int_eh_sjlj_longjmp:
572 case ARM::tInt_eh_sjlj_longjmp:
574 case ARM::Int_eh_sjlj_setjmp:
575 case ARM::Int_eh_sjlj_setjmp_nofp:
577 case ARM::tInt_eh_sjlj_setjmp:
578 case ARM::t2Int_eh_sjlj_setjmp:
579 case ARM::t2Int_eh_sjlj_setjmp_nofp:
587 case ARM::t2TBH_JT: {
588 // These are jumptable branches, i.e. a branch followed by an inlined
589 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
590 // entry is one byte; TBH two byte each.
591 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
592 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
593 unsigned NumOps = MCID.getNumOperands();
594 MachineOperand JTOP =
595 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
596 unsigned JTI = JTOP.getIndex();
597 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
599 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
600 assert(JTI < JT.size());
601 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
602 // 4 aligned. The assembler / linker may add 2 byte padding just before
603 // the JT entries. The size does not include this padding; the
604 // constant islands pass does separate bookkeeping for it.
605 // FIXME: If we know the size of the function is less than (1 << 16) *2
606 // bytes, we can use 16-bit entries instead. Then there won't be an
608 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
609 unsigned NumEntries = getNumJTEntries(JT, JTI);
610 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
611 // Make sure the instruction that follows TBB is 2-byte aligned.
612 // FIXME: Constant island pass should insert an "ALIGN" instruction
615 return NumEntries * EntrySize + InstSize;
618 // Otherwise, pseudo-instruction sizes are zero.
621 return 0; // Not reached
624 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
625 MachineBasicBlock::iterator I, DebugLoc DL,
626 unsigned DestReg, unsigned SrcReg,
627 bool KillSrc) const {
628 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
629 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
631 if (GPRDest && GPRSrc) {
632 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
633 .addReg(SrcReg, getKillRegState(KillSrc))));
637 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
638 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
641 if (SPRDest && SPRSrc)
643 else if (GPRDest && SPRSrc)
645 else if (SPRDest && GPRSrc)
647 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
649 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
653 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
654 MIB.addReg(SrcReg, getKillRegState(KillSrc));
655 if (Opc == ARM::VORRq)
656 MIB.addReg(SrcReg, getKillRegState(KillSrc));
661 // Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place.
662 if (ARM::QQPRRegClass.contains(DestReg, SrcReg) ||
663 ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
664 const TargetRegisterInfo *TRI = &getRegisterInfo();
665 assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
666 unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ?
667 ARM::qsub_1 : ARM::qsub_3;
668 for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) {
669 unsigned Dst = TRI->getSubReg(DestReg, i);
670 unsigned Src = TRI->getSubReg(SrcReg, i);
671 MachineInstrBuilder Mov =
672 AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
673 .addReg(Dst, RegState::Define)
674 .addReg(Src, getKillRegState(KillSrc))
675 .addReg(Src, getKillRegState(KillSrc)));
676 if (i == EndSubReg) {
677 Mov->addRegisterDefined(DestReg, TRI);
679 Mov->addRegisterKilled(SrcReg, TRI);
684 llvm_unreachable("Impossible reg-to-reg copy");
688 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
689 unsigned Reg, unsigned SubIdx, unsigned State,
690 const TargetRegisterInfo *TRI) {
692 return MIB.addReg(Reg, State);
694 if (TargetRegisterInfo::isPhysicalRegister(Reg))
695 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
696 return MIB.addReg(Reg, State, SubIdx);
699 void ARMBaseInstrInfo::
700 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
701 unsigned SrcReg, bool isKill, int FI,
702 const TargetRegisterClass *RC,
703 const TargetRegisterInfo *TRI) const {
705 if (I != MBB.end()) DL = I->getDebugLoc();
706 MachineFunction &MF = *MBB.getParent();
707 MachineFrameInfo &MFI = *MF.getFrameInfo();
708 unsigned Align = MFI.getObjectAlignment(FI);
710 MachineMemOperand *MMO =
711 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
712 MachineMemOperand::MOStore,
713 MFI.getObjectSize(FI),
716 switch (RC->getSize()) {
718 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
719 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
720 .addReg(SrcReg, getKillRegState(isKill))
721 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
722 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
723 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
724 .addReg(SrcReg, getKillRegState(isKill))
725 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
727 llvm_unreachable("Unknown reg class!");
730 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
731 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
732 .addReg(SrcReg, getKillRegState(isKill))
733 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
735 llvm_unreachable("Unknown reg class!");
738 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
739 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
740 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
741 .addFrameIndex(FI).addImm(16)
742 .addReg(SrcReg, getKillRegState(isKill))
743 .addMemOperand(MMO));
745 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
746 .addReg(SrcReg, getKillRegState(isKill))
748 .addMemOperand(MMO));
751 llvm_unreachable("Unknown reg class!");
754 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
755 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
756 // FIXME: It's possible to only store part of the QQ register if the
757 // spilled def has a sub-register index.
758 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
759 .addFrameIndex(FI).addImm(16)
760 .addReg(SrcReg, getKillRegState(isKill))
761 .addMemOperand(MMO));
763 MachineInstrBuilder MIB =
764 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
767 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
768 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
769 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
770 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
773 llvm_unreachable("Unknown reg class!");
776 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
777 MachineInstrBuilder MIB =
778 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
781 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
782 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
783 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
784 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
785 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
786 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
787 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
788 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
790 llvm_unreachable("Unknown reg class!");
793 llvm_unreachable("Unknown reg class!");
798 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
799 int &FrameIndex) const {
800 switch (MI->getOpcode()) {
803 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
804 if (MI->getOperand(1).isFI() &&
805 MI->getOperand(2).isReg() &&
806 MI->getOperand(3).isImm() &&
807 MI->getOperand(2).getReg() == 0 &&
808 MI->getOperand(3).getImm() == 0) {
809 FrameIndex = MI->getOperand(1).getIndex();
810 return MI->getOperand(0).getReg();
818 if (MI->getOperand(1).isFI() &&
819 MI->getOperand(2).isImm() &&
820 MI->getOperand(2).getImm() == 0) {
821 FrameIndex = MI->getOperand(1).getIndex();
822 return MI->getOperand(0).getReg();
825 case ARM::VST1q64Pseudo:
826 if (MI->getOperand(0).isFI() &&
827 MI->getOperand(2).getSubReg() == 0) {
828 FrameIndex = MI->getOperand(0).getIndex();
829 return MI->getOperand(2).getReg();
833 if (MI->getOperand(1).isFI() &&
834 MI->getOperand(0).getSubReg() == 0) {
835 FrameIndex = MI->getOperand(1).getIndex();
836 return MI->getOperand(0).getReg();
844 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
845 int &FrameIndex) const {
846 const MachineMemOperand *Dummy;
847 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
850 void ARMBaseInstrInfo::
851 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
852 unsigned DestReg, int FI,
853 const TargetRegisterClass *RC,
854 const TargetRegisterInfo *TRI) const {
856 if (I != MBB.end()) DL = I->getDebugLoc();
857 MachineFunction &MF = *MBB.getParent();
858 MachineFrameInfo &MFI = *MF.getFrameInfo();
859 unsigned Align = MFI.getObjectAlignment(FI);
860 MachineMemOperand *MMO =
861 MF.getMachineMemOperand(
862 MachinePointerInfo::getFixedStack(FI),
863 MachineMemOperand::MOLoad,
864 MFI.getObjectSize(FI),
867 switch (RC->getSize()) {
869 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
870 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
871 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
873 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
874 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
875 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
877 llvm_unreachable("Unknown reg class!");
880 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
881 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
882 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
884 llvm_unreachable("Unknown reg class!");
887 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
888 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
889 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
890 .addFrameIndex(FI).addImm(16)
891 .addMemOperand(MMO));
893 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
895 .addMemOperand(MMO));
898 llvm_unreachable("Unknown reg class!");
901 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
902 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
903 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
904 .addFrameIndex(FI).addImm(16)
905 .addMemOperand(MMO));
907 MachineInstrBuilder MIB =
908 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
911 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
912 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
913 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
914 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
915 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
918 llvm_unreachable("Unknown reg class!");
921 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
922 MachineInstrBuilder MIB =
923 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
926 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
927 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
928 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
929 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
930 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
931 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
932 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
933 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
934 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
936 llvm_unreachable("Unknown reg class!");
939 llvm_unreachable("Unknown regclass!");
944 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
945 int &FrameIndex) const {
946 switch (MI->getOpcode()) {
949 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
950 if (MI->getOperand(1).isFI() &&
951 MI->getOperand(2).isReg() &&
952 MI->getOperand(3).isImm() &&
953 MI->getOperand(2).getReg() == 0 &&
954 MI->getOperand(3).getImm() == 0) {
955 FrameIndex = MI->getOperand(1).getIndex();
956 return MI->getOperand(0).getReg();
964 if (MI->getOperand(1).isFI() &&
965 MI->getOperand(2).isImm() &&
966 MI->getOperand(2).getImm() == 0) {
967 FrameIndex = MI->getOperand(1).getIndex();
968 return MI->getOperand(0).getReg();
971 case ARM::VLD1q64Pseudo:
972 if (MI->getOperand(1).isFI() &&
973 MI->getOperand(0).getSubReg() == 0) {
974 FrameIndex = MI->getOperand(1).getIndex();
975 return MI->getOperand(0).getReg();
979 if (MI->getOperand(1).isFI() &&
980 MI->getOperand(0).getSubReg() == 0) {
981 FrameIndex = MI->getOperand(1).getIndex();
982 return MI->getOperand(0).getReg();
990 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
991 int &FrameIndex) const {
992 const MachineMemOperand *Dummy;
993 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
996 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
997 // This hook gets to expand COPY instructions before they become
998 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
999 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1000 // changed into a VORR that can go down the NEON pipeline.
1001 if (!WidenVMOVS || !MI->isCopy())
1004 // Look for a copy between even S-registers. That is where we keep floats
1005 // when using NEON v2f32 instructions for f32 arithmetic.
1006 unsigned DstRegS = MI->getOperand(0).getReg();
1007 unsigned SrcRegS = MI->getOperand(1).getReg();
1008 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1011 const TargetRegisterInfo *TRI = &getRegisterInfo();
1012 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1014 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1016 if (!DstRegD || !SrcRegD)
1019 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1020 // legal if the COPY already defines the full DstRegD, and it isn't a
1021 // sub-register insertion.
1022 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1025 // A dead copy shouldn't show up here, but reject it just in case.
1026 if (MI->getOperand(0).isDead())
1029 // All clear, widen the COPY.
1030 DEBUG(dbgs() << "widening: " << *MI);
1032 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1033 // or some other super-register.
1034 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1035 if (ImpDefIdx != -1)
1036 MI->RemoveOperand(ImpDefIdx);
1038 // Change the opcode and operands.
1039 MI->setDesc(get(ARM::VMOVD));
1040 MI->getOperand(0).setReg(DstRegD);
1041 MI->getOperand(1).setReg(SrcRegD);
1042 AddDefaultPred(MachineInstrBuilder(MI));
1044 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1045 // register scavenger and machine verifier, so we need to indicate that we
1046 // are reading an undefined value from SrcRegD, but a proper value from
1048 MI->getOperand(1).setIsUndef();
1049 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1051 // SrcRegD may actually contain an unrelated value in the ssub_1
1052 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1053 if (MI->getOperand(1).isKill()) {
1054 MI->getOperand(1).setIsKill(false);
1055 MI->addRegisterKilled(SrcRegS, TRI, true);
1058 DEBUG(dbgs() << "replaced by: " << *MI);
1063 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1064 int FrameIx, uint64_t Offset,
1065 const MDNode *MDPtr,
1066 DebugLoc DL) const {
1067 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1068 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1072 /// Create a copy of a const pool value. Update CPI to the new index and return
1074 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1075 MachineConstantPool *MCP = MF.getConstantPool();
1076 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1078 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1079 assert(MCPE.isMachineConstantPoolEntry() &&
1080 "Expecting a machine constantpool entry!");
1081 ARMConstantPoolValue *ACPV =
1082 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1084 unsigned PCLabelId = AFI->createPICLabelUId();
1085 ARMConstantPoolValue *NewCPV = 0;
1086 // FIXME: The below assumes PIC relocation model and that the function
1087 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1088 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1089 // instructions, so that's probably OK, but is PIC always correct when
1091 if (ACPV->isGlobalValue())
1092 NewCPV = ARMConstantPoolConstant::
1093 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1095 else if (ACPV->isExtSymbol())
1096 NewCPV = ARMConstantPoolSymbol::
1097 Create(MF.getFunction()->getContext(),
1098 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1099 else if (ACPV->isBlockAddress())
1100 NewCPV = ARMConstantPoolConstant::
1101 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1102 ARMCP::CPBlockAddress, 4);
1103 else if (ACPV->isLSDA())
1104 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1106 else if (ACPV->isMachineBasicBlock())
1107 NewCPV = ARMConstantPoolMBB::
1108 Create(MF.getFunction()->getContext(),
1109 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1111 llvm_unreachable("Unexpected ARM constantpool value type!!");
1112 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1116 void ARMBaseInstrInfo::
1117 reMaterialize(MachineBasicBlock &MBB,
1118 MachineBasicBlock::iterator I,
1119 unsigned DestReg, unsigned SubIdx,
1120 const MachineInstr *Orig,
1121 const TargetRegisterInfo &TRI) const {
1122 unsigned Opcode = Orig->getOpcode();
1125 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1126 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1130 case ARM::tLDRpci_pic:
1131 case ARM::t2LDRpci_pic: {
1132 MachineFunction &MF = *MBB.getParent();
1133 unsigned CPI = Orig->getOperand(1).getIndex();
1134 unsigned PCLabelId = duplicateCPV(MF, CPI);
1135 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1137 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1138 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1145 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1146 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1147 switch(Orig->getOpcode()) {
1148 case ARM::tLDRpci_pic:
1149 case ARM::t2LDRpci_pic: {
1150 unsigned CPI = Orig->getOperand(1).getIndex();
1151 unsigned PCLabelId = duplicateCPV(MF, CPI);
1152 Orig->getOperand(1).setIndex(CPI);
1153 Orig->getOperand(2).setImm(PCLabelId);
1160 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1161 const MachineInstr *MI1,
1162 const MachineRegisterInfo *MRI) const {
1163 int Opcode = MI0->getOpcode();
1164 if (Opcode == ARM::t2LDRpci ||
1165 Opcode == ARM::t2LDRpci_pic ||
1166 Opcode == ARM::tLDRpci ||
1167 Opcode == ARM::tLDRpci_pic ||
1168 Opcode == ARM::MOV_ga_dyn ||
1169 Opcode == ARM::MOV_ga_pcrel ||
1170 Opcode == ARM::MOV_ga_pcrel_ldr ||
1171 Opcode == ARM::t2MOV_ga_dyn ||
1172 Opcode == ARM::t2MOV_ga_pcrel) {
1173 if (MI1->getOpcode() != Opcode)
1175 if (MI0->getNumOperands() != MI1->getNumOperands())
1178 const MachineOperand &MO0 = MI0->getOperand(1);
1179 const MachineOperand &MO1 = MI1->getOperand(1);
1180 if (MO0.getOffset() != MO1.getOffset())
1183 if (Opcode == ARM::MOV_ga_dyn ||
1184 Opcode == ARM::MOV_ga_pcrel ||
1185 Opcode == ARM::MOV_ga_pcrel_ldr ||
1186 Opcode == ARM::t2MOV_ga_dyn ||
1187 Opcode == ARM::t2MOV_ga_pcrel)
1188 // Ignore the PC labels.
1189 return MO0.getGlobal() == MO1.getGlobal();
1191 const MachineFunction *MF = MI0->getParent()->getParent();
1192 const MachineConstantPool *MCP = MF->getConstantPool();
1193 int CPI0 = MO0.getIndex();
1194 int CPI1 = MO1.getIndex();
1195 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1196 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1197 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1198 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1199 if (isARMCP0 && isARMCP1) {
1200 ARMConstantPoolValue *ACPV0 =
1201 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1202 ARMConstantPoolValue *ACPV1 =
1203 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1204 return ACPV0->hasSameValue(ACPV1);
1205 } else if (!isARMCP0 && !isARMCP1) {
1206 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1209 } else if (Opcode == ARM::PICLDR) {
1210 if (MI1->getOpcode() != Opcode)
1212 if (MI0->getNumOperands() != MI1->getNumOperands())
1215 unsigned Addr0 = MI0->getOperand(1).getReg();
1216 unsigned Addr1 = MI1->getOperand(1).getReg();
1217 if (Addr0 != Addr1) {
1219 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1220 !TargetRegisterInfo::isVirtualRegister(Addr1))
1223 // This assumes SSA form.
1224 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1225 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1226 // Check if the loaded value, e.g. a constantpool of a global address, are
1228 if (!produceSameValue(Def0, Def1, MRI))
1232 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1233 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1234 const MachineOperand &MO0 = MI0->getOperand(i);
1235 const MachineOperand &MO1 = MI1->getOperand(i);
1236 if (!MO0.isIdenticalTo(MO1))
1242 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1245 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1246 /// determine if two loads are loading from the same base address. It should
1247 /// only return true if the base pointers are the same and the only differences
1248 /// between the two addresses is the offset. It also returns the offsets by
1250 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1252 int64_t &Offset2) const {
1253 // Don't worry about Thumb: just ARM and Thumb2.
1254 if (Subtarget.isThumb1Only()) return false;
1256 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1259 switch (Load1->getMachineOpcode()) {
1272 case ARM::t2LDRSHi8:
1274 case ARM::t2LDRSHi12:
1278 switch (Load2->getMachineOpcode()) {
1291 case ARM::t2LDRSHi8:
1293 case ARM::t2LDRSHi12:
1297 // Check if base addresses and chain operands match.
1298 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1299 Load1->getOperand(4) != Load2->getOperand(4))
1302 // Index should be Reg0.
1303 if (Load1->getOperand(3) != Load2->getOperand(3))
1306 // Determine the offsets.
1307 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1308 isa<ConstantSDNode>(Load2->getOperand(1))) {
1309 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1310 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1317 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1318 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1319 /// be scheduled togther. On some targets if two loads are loading from
1320 /// addresses in the same cache line, it's better if they are scheduled
1321 /// together. This function takes two integers that represent the load offsets
1322 /// from the common base address. It returns true if it decides it's desirable
1323 /// to schedule the two loads together. "NumLoads" is the number of loads that
1324 /// have already been scheduled after Load1.
1325 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1326 int64_t Offset1, int64_t Offset2,
1327 unsigned NumLoads) const {
1328 // Don't worry about Thumb: just ARM and Thumb2.
1329 if (Subtarget.isThumb1Only()) return false;
1331 assert(Offset2 > Offset1);
1333 if ((Offset2 - Offset1) / 8 > 64)
1336 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1337 return false; // FIXME: overly conservative?
1339 // Four loads in a row should be sufficient.
1346 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1347 const MachineBasicBlock *MBB,
1348 const MachineFunction &MF) const {
1349 // Debug info is never a scheduling boundary. It's necessary to be explicit
1350 // due to the special treatment of IT instructions below, otherwise a
1351 // dbg_value followed by an IT will result in the IT instruction being
1352 // considered a scheduling hazard, which is wrong. It should be the actual
1353 // instruction preceding the dbg_value instruction(s), just like it is
1354 // when debug info is not present.
1355 if (MI->isDebugValue())
1358 // Terminators and labels can't be scheduled around.
1359 if (MI->isTerminator() || MI->isLabel())
1362 // Treat the start of the IT block as a scheduling boundary, but schedule
1363 // t2IT along with all instructions following it.
1364 // FIXME: This is a big hammer. But the alternative is to add all potential
1365 // true and anti dependencies to IT block instructions as implicit operands
1366 // to the t2IT instruction. The added compile time and complexity does not
1368 MachineBasicBlock::const_iterator I = MI;
1369 // Make sure to skip any dbg_value instructions
1370 while (++I != MBB->end() && I->isDebugValue())
1372 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1375 // Don't attempt to schedule around any instruction that defines
1376 // a stack-oriented pointer, as it's unlikely to be profitable. This
1377 // saves compile time, because it doesn't require every single
1378 // stack slot reference to depend on the instruction that does the
1380 if (MI->definesRegister(ARM::SP))
1386 bool ARMBaseInstrInfo::
1387 isProfitableToIfCvt(MachineBasicBlock &MBB,
1388 unsigned NumCycles, unsigned ExtraPredCycles,
1389 const BranchProbability &Probability) const {
1393 // Attempt to estimate the relative costs of predication versus branching.
1394 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1395 UnpredCost /= Probability.getDenominator();
1396 UnpredCost += 1; // The branch itself
1397 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1399 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1402 bool ARMBaseInstrInfo::
1403 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1404 unsigned TCycles, unsigned TExtra,
1405 MachineBasicBlock &FMBB,
1406 unsigned FCycles, unsigned FExtra,
1407 const BranchProbability &Probability) const {
1408 if (!TCycles || !FCycles)
1411 // Attempt to estimate the relative costs of predication versus branching.
1412 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1413 TUnpredCost /= Probability.getDenominator();
1415 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1416 unsigned FUnpredCost = Comp * FCycles;
1417 FUnpredCost /= Probability.getDenominator();
1419 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1420 UnpredCost += 1; // The branch itself
1421 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1423 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1426 /// getInstrPredicate - If instruction is predicated, returns its predicate
1427 /// condition, otherwise returns AL. It also returns the condition code
1428 /// register by reference.
1430 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1431 int PIdx = MI->findFirstPredOperandIdx();
1437 PredReg = MI->getOperand(PIdx+1).getReg();
1438 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1442 int llvm::getMatchingCondBranchOpcode(int Opc) {
1445 else if (Opc == ARM::tB)
1447 else if (Opc == ARM::t2B)
1450 llvm_unreachable("Unknown unconditional branch opcode!");
1455 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1456 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1459 /// This will go away once we can teach tblgen how to set the optional CPSR def
1461 struct AddSubFlagsOpcodePair {
1463 unsigned MachineOpc;
1466 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1467 {ARM::ADDSri, ARM::ADDri},
1468 {ARM::ADDSrr, ARM::ADDrr},
1469 {ARM::ADDSrsi, ARM::ADDrsi},
1470 {ARM::ADDSrsr, ARM::ADDrsr},
1472 {ARM::SUBSri, ARM::SUBri},
1473 {ARM::SUBSrr, ARM::SUBrr},
1474 {ARM::SUBSrsi, ARM::SUBrsi},
1475 {ARM::SUBSrsr, ARM::SUBrsr},
1477 {ARM::RSBSri, ARM::RSBri},
1478 {ARM::RSBSrsi, ARM::RSBrsi},
1479 {ARM::RSBSrsr, ARM::RSBrsr},
1481 {ARM::t2ADDSri, ARM::t2ADDri},
1482 {ARM::t2ADDSrr, ARM::t2ADDrr},
1483 {ARM::t2ADDSrs, ARM::t2ADDrs},
1485 {ARM::t2SUBSri, ARM::t2SUBri},
1486 {ARM::t2SUBSrr, ARM::t2SUBrr},
1487 {ARM::t2SUBSrs, ARM::t2SUBrs},
1489 {ARM::t2RSBSri, ARM::t2RSBri},
1490 {ARM::t2RSBSrs, ARM::t2RSBrs},
1493 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1494 static const int NPairs =
1495 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
1496 for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0],
1497 *End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) {
1498 if (OldOpc == OpcPair->PseudoOpc) {
1499 return OpcPair->MachineOpc;
1505 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1506 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1507 unsigned DestReg, unsigned BaseReg, int NumBytes,
1508 ARMCC::CondCodes Pred, unsigned PredReg,
1509 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1510 bool isSub = NumBytes < 0;
1511 if (isSub) NumBytes = -NumBytes;
1514 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1515 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1516 assert(ThisVal && "Didn't extract field correctly");
1518 // We will handle these bits from offset, clear them.
1519 NumBytes &= ~ThisVal;
1521 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1523 // Build the new ADD / SUB.
1524 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1525 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1526 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1527 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1528 .setMIFlags(MIFlags);
1533 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1534 unsigned FrameReg, int &Offset,
1535 const ARMBaseInstrInfo &TII) {
1536 unsigned Opcode = MI.getOpcode();
1537 const MCInstrDesc &Desc = MI.getDesc();
1538 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1541 // Memory operands in inline assembly always use AddrMode2.
1542 if (Opcode == ARM::INLINEASM)
1543 AddrMode = ARMII::AddrMode2;
1545 if (Opcode == ARM::ADDri) {
1546 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1548 // Turn it into a move.
1549 MI.setDesc(TII.get(ARM::MOVr));
1550 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1551 MI.RemoveOperand(FrameRegIdx+1);
1554 } else if (Offset < 0) {
1557 MI.setDesc(TII.get(ARM::SUBri));
1560 // Common case: small offset, fits into instruction.
1561 if (ARM_AM::getSOImmVal(Offset) != -1) {
1562 // Replace the FrameIndex with sp / fp
1563 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1564 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1569 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1571 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1572 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1574 // We will handle these bits from offset, clear them.
1575 Offset &= ~ThisImmVal;
1577 // Get the properly encoded SOImmVal field.
1578 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1579 "Bit extraction didn't work?");
1580 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1582 unsigned ImmIdx = 0;
1584 unsigned NumBits = 0;
1587 case ARMII::AddrMode_i12: {
1588 ImmIdx = FrameRegIdx + 1;
1589 InstrOffs = MI.getOperand(ImmIdx).getImm();
1593 case ARMII::AddrMode2: {
1594 ImmIdx = FrameRegIdx+2;
1595 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1596 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1601 case ARMII::AddrMode3: {
1602 ImmIdx = FrameRegIdx+2;
1603 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1604 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1609 case ARMII::AddrMode4:
1610 case ARMII::AddrMode6:
1611 // Can't fold any offset even if it's zero.
1613 case ARMII::AddrMode5: {
1614 ImmIdx = FrameRegIdx+1;
1615 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1616 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1623 llvm_unreachable("Unsupported addressing mode!");
1627 Offset += InstrOffs * Scale;
1628 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1634 // Attempt to fold address comp. if opcode has offset bits
1636 // Common case: small offset, fits into instruction.
1637 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1638 int ImmedOffset = Offset / Scale;
1639 unsigned Mask = (1 << NumBits) - 1;
1640 if ((unsigned)Offset <= Mask * Scale) {
1641 // Replace the FrameIndex with sp
1642 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1643 // FIXME: When addrmode2 goes away, this will simplify (like the
1644 // T2 version), as the LDR.i12 versions don't need the encoding
1645 // tricks for the offset value.
1647 if (AddrMode == ARMII::AddrMode_i12)
1648 ImmedOffset = -ImmedOffset;
1650 ImmedOffset |= 1 << NumBits;
1652 ImmOp.ChangeToImmediate(ImmedOffset);
1657 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1658 ImmedOffset = ImmedOffset & Mask;
1660 if (AddrMode == ARMII::AddrMode_i12)
1661 ImmedOffset = -ImmedOffset;
1663 ImmedOffset |= 1 << NumBits;
1665 ImmOp.ChangeToImmediate(ImmedOffset);
1666 Offset &= ~(Mask*Scale);
1670 Offset = (isSub) ? -Offset : Offset;
1674 bool ARMBaseInstrInfo::
1675 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1676 int &CmpValue) const {
1677 switch (MI->getOpcode()) {
1681 SrcReg = MI->getOperand(0).getReg();
1683 CmpValue = MI->getOperand(1).getImm();
1687 SrcReg = MI->getOperand(0).getReg();
1688 CmpMask = MI->getOperand(1).getImm();
1696 /// isSuitableForMask - Identify a suitable 'and' instruction that
1697 /// operates on the given source register and applies the same mask
1698 /// as a 'tst' instruction. Provide a limited look-through for copies.
1699 /// When successful, MI will hold the found instruction.
1700 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1701 int CmpMask, bool CommonUse) {
1702 switch (MI->getOpcode()) {
1705 if (CmpMask != MI->getOperand(2).getImm())
1707 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1711 // Walk down one instruction which is potentially an 'and'.
1712 const MachineInstr &Copy = *MI;
1713 MachineBasicBlock::iterator AND(
1714 llvm::next(MachineBasicBlock::iterator(MI)));
1715 if (AND == MI->getParent()->end()) return false;
1717 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1725 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1726 /// comparison into one that sets the zero bit in the flags register.
1727 bool ARMBaseInstrInfo::
1728 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1729 int CmpValue, const MachineRegisterInfo *MRI) const {
1733 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1734 if (llvm::next(DI) != MRI->def_end())
1735 // Only support one definition.
1738 MachineInstr *MI = &*DI;
1740 // Masked compares sometimes use the same register as the corresponding 'and'.
1741 if (CmpMask != ~0) {
1742 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1744 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1745 UE = MRI->use_end(); UI != UE; ++UI) {
1746 if (UI->getParent() != CmpInstr->getParent()) continue;
1747 MachineInstr *PotentialAND = &*UI;
1748 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1753 if (!MI) return false;
1757 // Conservatively refuse to convert an instruction which isn't in the same BB
1758 // as the comparison.
1759 if (MI->getParent() != CmpInstr->getParent())
1762 // Check that CPSR isn't set between the comparison instruction and the one we
1764 MachineBasicBlock::iterator I = CmpInstr,E = MI, B = MI->getParent()->begin();
1766 // Early exit if CmpInstr is at the beginning of the BB.
1767 if (I == B) return false;
1770 for (; I != E; --I) {
1771 const MachineInstr &Instr = *I;
1773 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1774 const MachineOperand &MO = Instr.getOperand(IO);
1775 if (!MO.isReg()) continue;
1777 // This instruction modifies or uses CPSR after the one we want to
1778 // change. We can't do this transformation.
1779 if (MO.getReg() == ARM::CPSR)
1784 // The 'and' is below the comparison instruction.
1788 // Set the "zero" bit in CPSR.
1789 switch (MI->getOpcode()) {
1823 case ARM::t2EORri: {
1824 // Scan forward for the use of CPSR, if it's a conditional code requires
1825 // checking of V bit, then this is not safe to do. If we can't find the
1826 // CPSR use (i.e. used in another block), then it's not safe to perform
1827 // the optimization.
1828 bool isSafe = false;
1830 E = MI->getParent()->end();
1831 while (!isSafe && ++I != E) {
1832 const MachineInstr &Instr = *I;
1833 for (unsigned IO = 0, EO = Instr.getNumOperands();
1834 !isSafe && IO != EO; ++IO) {
1835 const MachineOperand &MO = Instr.getOperand(IO);
1836 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1842 // Condition code is after the operand before CPSR.
1843 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1862 // Toggle the optional operand to CPSR.
1863 MI->getOperand(5).setReg(ARM::CPSR);
1864 MI->getOperand(5).setIsDef(true);
1865 CmpInstr->eraseFromParent();
1873 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1874 MachineInstr *DefMI, unsigned Reg,
1875 MachineRegisterInfo *MRI) const {
1876 // Fold large immediates into add, sub, or, xor.
1877 unsigned DefOpc = DefMI->getOpcode();
1878 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1880 if (!DefMI->getOperand(1).isImm())
1881 // Could be t2MOVi32imm <ga:xx>
1884 if (!MRI->hasOneNonDBGUse(Reg))
1887 unsigned UseOpc = UseMI->getOpcode();
1888 unsigned NewUseOpc = 0;
1889 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1890 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1891 bool Commute = false;
1893 default: return false;
1901 case ARM::t2EORrr: {
1902 Commute = UseMI->getOperand(2).getReg() != Reg;
1909 NewUseOpc = ARM::SUBri;
1915 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1917 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1918 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1921 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1922 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1923 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1927 case ARM::t2SUBrr: {
1931 NewUseOpc = ARM::t2SUBri;
1936 case ARM::t2EORrr: {
1937 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1939 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1940 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1943 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1944 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1945 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1953 unsigned OpIdx = Commute ? 2 : 1;
1954 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1955 bool isKill = UseMI->getOperand(OpIdx).isKill();
1956 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1957 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1958 *UseMI, UseMI->getDebugLoc(),
1959 get(NewUseOpc), NewReg)
1960 .addReg(Reg1, getKillRegState(isKill))
1961 .addImm(SOImmValV1)));
1962 UseMI->setDesc(get(NewUseOpc));
1963 UseMI->getOperand(1).setReg(NewReg);
1964 UseMI->getOperand(1).setIsKill();
1965 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1966 DefMI->eraseFromParent();
1971 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1972 const MachineInstr *MI) const {
1973 if (!ItinData || ItinData->isEmpty())
1976 const MCInstrDesc &Desc = MI->getDesc();
1977 unsigned Class = Desc.getSchedClass();
1978 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1982 unsigned Opc = MI->getOpcode();
1985 llvm_unreachable("Unexpected multi-uops instruction!");
1991 // The number of uOps for load / store multiple are determined by the number
1994 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1995 // same cycle. The scheduling for the first load / store must be done
1996 // separately by assuming the the address is not 64-bit aligned.
1998 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1999 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2000 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2002 case ARM::VLDMDIA_UPD:
2003 case ARM::VLDMDDB_UPD:
2005 case ARM::VLDMSIA_UPD:
2006 case ARM::VLDMSDB_UPD:
2008 case ARM::VSTMDIA_UPD:
2009 case ARM::VSTMDDB_UPD:
2011 case ARM::VSTMSIA_UPD:
2012 case ARM::VSTMSDB_UPD: {
2013 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2014 return (NumRegs / 2) + (NumRegs % 2) + 1;
2017 case ARM::LDMIA_RET:
2022 case ARM::LDMIA_UPD:
2023 case ARM::LDMDA_UPD:
2024 case ARM::LDMDB_UPD:
2025 case ARM::LDMIB_UPD:
2030 case ARM::STMIA_UPD:
2031 case ARM::STMDA_UPD:
2032 case ARM::STMDB_UPD:
2033 case ARM::STMIB_UPD:
2035 case ARM::tLDMIA_UPD:
2036 case ARM::tSTMIA_UPD:
2040 case ARM::t2LDMIA_RET:
2043 case ARM::t2LDMIA_UPD:
2044 case ARM::t2LDMDB_UPD:
2047 case ARM::t2STMIA_UPD:
2048 case ARM::t2STMDB_UPD: {
2049 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2050 if (Subtarget.isCortexA8()) {
2053 // 4 registers would be issued: 2, 2.
2054 // 5 registers would be issued: 2, 2, 1.
2055 UOps = (NumRegs / 2);
2059 } else if (Subtarget.isCortexA9()) {
2060 UOps = (NumRegs / 2);
2061 // If there are odd number of registers or if it's not 64-bit aligned,
2062 // then it takes an extra AGU (Address Generation Unit) cycle.
2063 if ((NumRegs % 2) ||
2064 !MI->hasOneMemOperand() ||
2065 (*MI->memoperands_begin())->getAlignment() < 8)
2069 // Assume the worst.
2077 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2078 const MCInstrDesc &DefMCID,
2080 unsigned DefIdx, unsigned DefAlign) const {
2081 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2083 // Def is the address writeback.
2084 return ItinData->getOperandCycle(DefClass, DefIdx);
2087 if (Subtarget.isCortexA8()) {
2088 // (regno / 2) + (regno % 2) + 1
2089 DefCycle = RegNo / 2 + 1;
2092 } else if (Subtarget.isCortexA9()) {
2094 bool isSLoad = false;
2096 switch (DefMCID.getOpcode()) {
2099 case ARM::VLDMSIA_UPD:
2100 case ARM::VLDMSDB_UPD:
2105 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2106 // then it takes an extra cycle.
2107 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2110 // Assume the worst.
2111 DefCycle = RegNo + 2;
2118 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2119 const MCInstrDesc &DefMCID,
2121 unsigned DefIdx, unsigned DefAlign) const {
2122 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2124 // Def is the address writeback.
2125 return ItinData->getOperandCycle(DefClass, DefIdx);
2128 if (Subtarget.isCortexA8()) {
2129 // 4 registers would be issued: 1, 2, 1.
2130 // 5 registers would be issued: 1, 2, 2.
2131 DefCycle = RegNo / 2;
2134 // Result latency is issue cycle + 2: E2.
2136 } else if (Subtarget.isCortexA9()) {
2137 DefCycle = (RegNo / 2);
2138 // If there are odd number of registers or if it's not 64-bit aligned,
2139 // then it takes an extra AGU (Address Generation Unit) cycle.
2140 if ((RegNo % 2) || DefAlign < 8)
2142 // Result latency is AGU cycles + 2.
2145 // Assume the worst.
2146 DefCycle = RegNo + 2;
2153 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2154 const MCInstrDesc &UseMCID,
2156 unsigned UseIdx, unsigned UseAlign) const {
2157 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2159 return ItinData->getOperandCycle(UseClass, UseIdx);
2162 if (Subtarget.isCortexA8()) {
2163 // (regno / 2) + (regno % 2) + 1
2164 UseCycle = RegNo / 2 + 1;
2167 } else if (Subtarget.isCortexA9()) {
2169 bool isSStore = false;
2171 switch (UseMCID.getOpcode()) {
2174 case ARM::VSTMSIA_UPD:
2175 case ARM::VSTMSDB_UPD:
2180 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2181 // then it takes an extra cycle.
2182 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2185 // Assume the worst.
2186 UseCycle = RegNo + 2;
2193 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2194 const MCInstrDesc &UseMCID,
2196 unsigned UseIdx, unsigned UseAlign) const {
2197 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2199 return ItinData->getOperandCycle(UseClass, UseIdx);
2202 if (Subtarget.isCortexA8()) {
2203 UseCycle = RegNo / 2;
2208 } else if (Subtarget.isCortexA9()) {
2209 UseCycle = (RegNo / 2);
2210 // If there are odd number of registers or if it's not 64-bit aligned,
2211 // then it takes an extra AGU (Address Generation Unit) cycle.
2212 if ((RegNo % 2) || UseAlign < 8)
2215 // Assume the worst.
2222 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2223 const MCInstrDesc &DefMCID,
2224 unsigned DefIdx, unsigned DefAlign,
2225 const MCInstrDesc &UseMCID,
2226 unsigned UseIdx, unsigned UseAlign) const {
2227 unsigned DefClass = DefMCID.getSchedClass();
2228 unsigned UseClass = UseMCID.getSchedClass();
2230 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2231 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2233 // This may be a def / use of a variable_ops instruction, the operand
2234 // latency might be determinable dynamically. Let the target try to
2237 bool LdmBypass = false;
2238 switch (DefMCID.getOpcode()) {
2240 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2244 case ARM::VLDMDIA_UPD:
2245 case ARM::VLDMDDB_UPD:
2247 case ARM::VLDMSIA_UPD:
2248 case ARM::VLDMSDB_UPD:
2249 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2252 case ARM::LDMIA_RET:
2257 case ARM::LDMIA_UPD:
2258 case ARM::LDMDA_UPD:
2259 case ARM::LDMDB_UPD:
2260 case ARM::LDMIB_UPD:
2262 case ARM::tLDMIA_UPD:
2264 case ARM::t2LDMIA_RET:
2267 case ARM::t2LDMIA_UPD:
2268 case ARM::t2LDMDB_UPD:
2270 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2275 // We can't seem to determine the result latency of the def, assume it's 2.
2279 switch (UseMCID.getOpcode()) {
2281 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2285 case ARM::VSTMDIA_UPD:
2286 case ARM::VSTMDDB_UPD:
2288 case ARM::VSTMSIA_UPD:
2289 case ARM::VSTMSDB_UPD:
2290 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2297 case ARM::STMIA_UPD:
2298 case ARM::STMDA_UPD:
2299 case ARM::STMDB_UPD:
2300 case ARM::STMIB_UPD:
2301 case ARM::tSTMIA_UPD:
2306 case ARM::t2STMIA_UPD:
2307 case ARM::t2STMDB_UPD:
2308 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2313 // Assume it's read in the first stage.
2316 UseCycle = DefCycle - UseCycle + 1;
2319 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2320 // first def operand.
2321 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2324 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2325 UseClass, UseIdx)) {
2334 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2335 const MachineInstr *DefMI, unsigned DefIdx,
2336 const MachineInstr *UseMI, unsigned UseIdx) const {
2337 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2338 DefMI->isRegSequence() || DefMI->isImplicitDef())
2341 if (!ItinData || ItinData->isEmpty())
2342 return DefMI->mayLoad() ? 3 : 1;
2344 const MCInstrDesc &DefMCID = DefMI->getDesc();
2345 const MCInstrDesc &UseMCID = UseMI->getDesc();
2346 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2347 if (DefMO.getReg() == ARM::CPSR) {
2348 if (DefMI->getOpcode() == ARM::FMSTAT) {
2349 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2350 return Subtarget.isCortexA9() ? 1 : 20;
2353 // CPSR set and branch can be paired in the same cycle.
2354 if (UseMI->isBranch())
2358 unsigned DefAlign = DefMI->hasOneMemOperand()
2359 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2360 unsigned UseAlign = UseMI->hasOneMemOperand()
2361 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2362 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2363 UseMCID, UseIdx, UseAlign);
2366 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2367 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2368 // variants are one cycle cheaper.
2369 switch (DefMCID.getOpcode()) {
2373 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2374 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2376 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2383 case ARM::t2LDRSHs: {
2384 // Thumb2 mode: lsl only.
2385 unsigned ShAmt = DefMI->getOperand(3).getImm();
2386 if (ShAmt == 0 || ShAmt == 2)
2393 if (DefAlign < 8 && Subtarget.isCortexA9())
2394 switch (DefMCID.getOpcode()) {
2400 case ARM::VLD1q8wb_fixed:
2401 case ARM::VLD1q16wb_fixed:
2402 case ARM::VLD1q32wb_fixed:
2403 case ARM::VLD1q64wb_fixed:
2404 case ARM::VLD1q8wb_register:
2405 case ARM::VLD1q16wb_register:
2406 case ARM::VLD1q32wb_register:
2407 case ARM::VLD1q64wb_register:
2414 case ARM::VLD2d8wb_fixed:
2415 case ARM::VLD2d16wb_fixed:
2416 case ARM::VLD2d32wb_fixed:
2417 case ARM::VLD2q8wb_fixed:
2418 case ARM::VLD2q16wb_fixed:
2419 case ARM::VLD2q32wb_fixed:
2420 case ARM::VLD2d8wb_register:
2421 case ARM::VLD2d16wb_register:
2422 case ARM::VLD2d32wb_register:
2423 case ARM::VLD2q8wb_register:
2424 case ARM::VLD2q16wb_register:
2425 case ARM::VLD2q32wb_register:
2430 case ARM::VLD3d8_UPD:
2431 case ARM::VLD3d16_UPD:
2432 case ARM::VLD3d32_UPD:
2433 case ARM::VLD1d64Twb_fixed:
2434 case ARM::VLD1d64Twb_register:
2435 case ARM::VLD3q8_UPD:
2436 case ARM::VLD3q16_UPD:
2437 case ARM::VLD3q32_UPD:
2442 case ARM::VLD4d8_UPD:
2443 case ARM::VLD4d16_UPD:
2444 case ARM::VLD4d32_UPD:
2445 case ARM::VLD1d64Qwb_fixed:
2446 case ARM::VLD1d64Qwb_register:
2447 case ARM::VLD4q8_UPD:
2448 case ARM::VLD4q16_UPD:
2449 case ARM::VLD4q32_UPD:
2450 case ARM::VLD1DUPq8:
2451 case ARM::VLD1DUPq16:
2452 case ARM::VLD1DUPq32:
2453 case ARM::VLD1DUPq8wb_fixed:
2454 case ARM::VLD1DUPq16wb_fixed:
2455 case ARM::VLD1DUPq32wb_fixed:
2456 case ARM::VLD1DUPq8wb_register:
2457 case ARM::VLD1DUPq16wb_register:
2458 case ARM::VLD1DUPq32wb_register:
2459 case ARM::VLD2DUPd8:
2460 case ARM::VLD2DUPd16:
2461 case ARM::VLD2DUPd32:
2462 case ARM::VLD2DUPd8_UPD:
2463 case ARM::VLD2DUPd16_UPD:
2464 case ARM::VLD2DUPd32_UPD:
2465 case ARM::VLD4DUPd8:
2466 case ARM::VLD4DUPd16:
2467 case ARM::VLD4DUPd32:
2468 case ARM::VLD4DUPd8_UPD:
2469 case ARM::VLD4DUPd16_UPD:
2470 case ARM::VLD4DUPd32_UPD:
2472 case ARM::VLD1LNd16:
2473 case ARM::VLD1LNd32:
2474 case ARM::VLD1LNd8_UPD:
2475 case ARM::VLD1LNd16_UPD:
2476 case ARM::VLD1LNd32_UPD:
2478 case ARM::VLD2LNd16:
2479 case ARM::VLD2LNd32:
2480 case ARM::VLD2LNq16:
2481 case ARM::VLD2LNq32:
2482 case ARM::VLD2LNd8_UPD:
2483 case ARM::VLD2LNd16_UPD:
2484 case ARM::VLD2LNd32_UPD:
2485 case ARM::VLD2LNq16_UPD:
2486 case ARM::VLD2LNq32_UPD:
2488 case ARM::VLD4LNd16:
2489 case ARM::VLD4LNd32:
2490 case ARM::VLD4LNq16:
2491 case ARM::VLD4LNq32:
2492 case ARM::VLD4LNd8_UPD:
2493 case ARM::VLD4LNd16_UPD:
2494 case ARM::VLD4LNd32_UPD:
2495 case ARM::VLD4LNq16_UPD:
2496 case ARM::VLD4LNq32_UPD:
2497 // If the address is not 64-bit aligned, the latencies of these
2498 // instructions increases by one.
2507 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2508 SDNode *DefNode, unsigned DefIdx,
2509 SDNode *UseNode, unsigned UseIdx) const {
2510 if (!DefNode->isMachineOpcode())
2513 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2515 if (isZeroCost(DefMCID.Opcode))
2518 if (!ItinData || ItinData->isEmpty())
2519 return DefMCID.mayLoad() ? 3 : 1;
2521 if (!UseNode->isMachineOpcode()) {
2522 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2523 if (Subtarget.isCortexA9())
2524 return Latency <= 2 ? 1 : Latency - 1;
2526 return Latency <= 3 ? 1 : Latency - 2;
2529 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
2530 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2531 unsigned DefAlign = !DefMN->memoperands_empty()
2532 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2533 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2534 unsigned UseAlign = !UseMN->memoperands_empty()
2535 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2536 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2537 UseMCID, UseIdx, UseAlign);
2540 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2541 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2542 // variants are one cycle cheaper.
2543 switch (DefMCID.getOpcode()) {
2548 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2549 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2551 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2558 case ARM::t2LDRSHs: {
2559 // Thumb2 mode: lsl only.
2561 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2562 if (ShAmt == 0 || ShAmt == 2)
2569 if (DefAlign < 8 && Subtarget.isCortexA9())
2570 switch (DefMCID.getOpcode()) {
2572 case ARM::VLD1q8Pseudo:
2573 case ARM::VLD1q16Pseudo:
2574 case ARM::VLD1q32Pseudo:
2575 case ARM::VLD1q64Pseudo:
2576 case ARM::VLD1q8PseudoWB_register:
2577 case ARM::VLD1q16PseudoWB_register:
2578 case ARM::VLD1q32PseudoWB_register:
2579 case ARM::VLD1q64PseudoWB_register:
2580 case ARM::VLD1q8PseudoWB_fixed:
2581 case ARM::VLD1q16PseudoWB_fixed:
2582 case ARM::VLD1q32PseudoWB_fixed:
2583 case ARM::VLD1q64PseudoWB_fixed:
2584 case ARM::VLD2d8Pseudo:
2585 case ARM::VLD2d16Pseudo:
2586 case ARM::VLD2d32Pseudo:
2587 case ARM::VLD2q8Pseudo:
2588 case ARM::VLD2q16Pseudo:
2589 case ARM::VLD2q32Pseudo:
2590 case ARM::VLD2d8PseudoWB_fixed:
2591 case ARM::VLD2d16PseudoWB_fixed:
2592 case ARM::VLD2d32PseudoWB_fixed:
2593 case ARM::VLD2q8PseudoWB_fixed:
2594 case ARM::VLD2q16PseudoWB_fixed:
2595 case ARM::VLD2q32PseudoWB_fixed:
2596 case ARM::VLD2d8PseudoWB_register:
2597 case ARM::VLD2d16PseudoWB_register:
2598 case ARM::VLD2d32PseudoWB_register:
2599 case ARM::VLD2q8PseudoWB_register:
2600 case ARM::VLD2q16PseudoWB_register:
2601 case ARM::VLD2q32PseudoWB_register:
2602 case ARM::VLD3d8Pseudo:
2603 case ARM::VLD3d16Pseudo:
2604 case ARM::VLD3d32Pseudo:
2605 case ARM::VLD1d64TPseudo:
2606 case ARM::VLD3d8Pseudo_UPD:
2607 case ARM::VLD3d16Pseudo_UPD:
2608 case ARM::VLD3d32Pseudo_UPD:
2609 case ARM::VLD3q8Pseudo_UPD:
2610 case ARM::VLD3q16Pseudo_UPD:
2611 case ARM::VLD3q32Pseudo_UPD:
2612 case ARM::VLD3q8oddPseudo:
2613 case ARM::VLD3q16oddPseudo:
2614 case ARM::VLD3q32oddPseudo:
2615 case ARM::VLD3q8oddPseudo_UPD:
2616 case ARM::VLD3q16oddPseudo_UPD:
2617 case ARM::VLD3q32oddPseudo_UPD:
2618 case ARM::VLD4d8Pseudo:
2619 case ARM::VLD4d16Pseudo:
2620 case ARM::VLD4d32Pseudo:
2621 case ARM::VLD1d64QPseudo:
2622 case ARM::VLD4d8Pseudo_UPD:
2623 case ARM::VLD4d16Pseudo_UPD:
2624 case ARM::VLD4d32Pseudo_UPD:
2625 case ARM::VLD4q8Pseudo_UPD:
2626 case ARM::VLD4q16Pseudo_UPD:
2627 case ARM::VLD4q32Pseudo_UPD:
2628 case ARM::VLD4q8oddPseudo:
2629 case ARM::VLD4q16oddPseudo:
2630 case ARM::VLD4q32oddPseudo:
2631 case ARM::VLD4q8oddPseudo_UPD:
2632 case ARM::VLD4q16oddPseudo_UPD:
2633 case ARM::VLD4q32oddPseudo_UPD:
2634 case ARM::VLD1DUPq8Pseudo:
2635 case ARM::VLD1DUPq16Pseudo:
2636 case ARM::VLD1DUPq32Pseudo:
2637 case ARM::VLD1DUPq8PseudoWB_fixed:
2638 case ARM::VLD1DUPq16PseudoWB_fixed:
2639 case ARM::VLD1DUPq32PseudoWB_fixed:
2640 case ARM::VLD1DUPq8PseudoWB_register:
2641 case ARM::VLD1DUPq16PseudoWB_register:
2642 case ARM::VLD1DUPq32PseudoWB_register:
2643 case ARM::VLD2DUPd8Pseudo:
2644 case ARM::VLD2DUPd16Pseudo:
2645 case ARM::VLD2DUPd32Pseudo:
2646 case ARM::VLD2DUPd8Pseudo_UPD:
2647 case ARM::VLD2DUPd16Pseudo_UPD:
2648 case ARM::VLD2DUPd32Pseudo_UPD:
2649 case ARM::VLD4DUPd8Pseudo:
2650 case ARM::VLD4DUPd16Pseudo:
2651 case ARM::VLD4DUPd32Pseudo:
2652 case ARM::VLD4DUPd8Pseudo_UPD:
2653 case ARM::VLD4DUPd16Pseudo_UPD:
2654 case ARM::VLD4DUPd32Pseudo_UPD:
2655 case ARM::VLD1LNq8Pseudo:
2656 case ARM::VLD1LNq16Pseudo:
2657 case ARM::VLD1LNq32Pseudo:
2658 case ARM::VLD1LNq8Pseudo_UPD:
2659 case ARM::VLD1LNq16Pseudo_UPD:
2660 case ARM::VLD1LNq32Pseudo_UPD:
2661 case ARM::VLD2LNd8Pseudo:
2662 case ARM::VLD2LNd16Pseudo:
2663 case ARM::VLD2LNd32Pseudo:
2664 case ARM::VLD2LNq16Pseudo:
2665 case ARM::VLD2LNq32Pseudo:
2666 case ARM::VLD2LNd8Pseudo_UPD:
2667 case ARM::VLD2LNd16Pseudo_UPD:
2668 case ARM::VLD2LNd32Pseudo_UPD:
2669 case ARM::VLD2LNq16Pseudo_UPD:
2670 case ARM::VLD2LNq32Pseudo_UPD:
2671 case ARM::VLD4LNd8Pseudo:
2672 case ARM::VLD4LNd16Pseudo:
2673 case ARM::VLD4LNd32Pseudo:
2674 case ARM::VLD4LNq16Pseudo:
2675 case ARM::VLD4LNq32Pseudo:
2676 case ARM::VLD4LNd8Pseudo_UPD:
2677 case ARM::VLD4LNd16Pseudo_UPD:
2678 case ARM::VLD4LNd32Pseudo_UPD:
2679 case ARM::VLD4LNq16Pseudo_UPD:
2680 case ARM::VLD4LNq32Pseudo_UPD:
2681 // If the address is not 64-bit aligned, the latencies of these
2682 // instructions increases by one.
2690 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2691 const MachineInstr *MI,
2692 unsigned *PredCost) const {
2693 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2694 MI->isRegSequence() || MI->isImplicitDef())
2697 if (!ItinData || ItinData->isEmpty())
2700 const MCInstrDesc &MCID = MI->getDesc();
2701 unsigned Class = MCID.getSchedClass();
2702 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2703 if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR))
2704 // When predicated, CPSR is an additional source operand for CPSR updating
2705 // instructions, this apparently increases their latencies.
2708 return ItinData->getStageLatency(Class);
2709 return getNumMicroOps(ItinData, MI);
2712 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2713 SDNode *Node) const {
2714 if (!Node->isMachineOpcode())
2717 if (!ItinData || ItinData->isEmpty())
2720 unsigned Opcode = Node->getMachineOpcode();
2723 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2730 bool ARMBaseInstrInfo::
2731 hasHighOperandLatency(const InstrItineraryData *ItinData,
2732 const MachineRegisterInfo *MRI,
2733 const MachineInstr *DefMI, unsigned DefIdx,
2734 const MachineInstr *UseMI, unsigned UseIdx) const {
2735 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2736 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2737 if (Subtarget.isCortexA8() &&
2738 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2739 // CortexA8 VFP instructions are not pipelined.
2742 // Hoist VFP / NEON instructions with 4 or higher latency.
2743 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2746 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2747 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2750 bool ARMBaseInstrInfo::
2751 hasLowDefLatency(const InstrItineraryData *ItinData,
2752 const MachineInstr *DefMI, unsigned DefIdx) const {
2753 if (!ItinData || ItinData->isEmpty())
2756 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2757 if (DDomain == ARMII::DomainGeneral) {
2758 unsigned DefClass = DefMI->getDesc().getSchedClass();
2759 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2760 return (DefCycle != -1 && DefCycle <= 2);
2765 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
2766 StringRef &ErrInfo) const {
2767 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
2768 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
2775 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2776 unsigned &AddSubOpc,
2777 bool &NegAcc, bool &HasLane) const {
2778 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2779 if (I == MLxEntryMap.end())
2782 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2783 MulOpc = Entry.MulOpc;
2784 AddSubOpc = Entry.AddSubOpc;
2785 NegAcc = Entry.NegAcc;
2786 HasLane = Entry.HasLane;
2790 //===----------------------------------------------------------------------===//
2791 // Execution domains.
2792 //===----------------------------------------------------------------------===//
2794 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
2795 // and some can go down both. The vmov instructions go down the VFP pipeline,
2796 // but they can be changed to vorr equivalents that are executed by the NEON
2799 // We use the following execution domain numbering:
2807 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
2809 std::pair<uint16_t, uint16_t>
2810 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
2811 // VMOVD is a VFP instruction, but can be changed to NEON if it isn't
2813 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
2814 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
2816 // No other instructions can be swizzled, so just determine their domain.
2817 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
2819 if (Domain & ARMII::DomainNEON)
2820 return std::make_pair(ExeNEON, 0);
2822 // Certain instructions can go either way on Cortex-A8.
2823 // Treat them as NEON instructions.
2824 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
2825 return std::make_pair(ExeNEON, 0);
2827 if (Domain & ARMII::DomainVFP)
2828 return std::make_pair(ExeVFP, 0);
2830 return std::make_pair(ExeGeneric, 0);
2834 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
2835 // We only know how to change VMOVD into VORR.
2836 assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD");
2837 if (Domain != ExeNEON)
2840 // Zap the predicate operands.
2841 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
2842 MI->RemoveOperand(3);
2843 MI->RemoveOperand(2);
2845 // Change to a VORRd which requires two identical use operands.
2846 MI->setDesc(get(ARM::VORRd));
2848 // Add the extra source operand and new predicates.
2849 // This will go before any implicit ops.
2850 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));