1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMBuildAttrs.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMConstantPoolValue.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMMCExpr.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "InstPrinter/ARMInstPrinter.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Target/TargetRegistry.h"
49 #include "llvm/ADT/SmallPtrSet.h"
50 #include "llvm/ADT/SmallString.h"
51 #include "llvm/ADT/StringExtras.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 MCObjectStreamer &Streamer;
104 StringRef CurrentVendor;
105 SmallString<64> Contents;
108 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
109 Streamer(Streamer_), CurrentVendor("") { }
111 void MaybeSwitchVendor(StringRef Vendor) {
112 assert(!Vendor.empty() && "Vendor cannot be empty.");
114 if (CurrentVendor.empty())
115 CurrentVendor = Vendor;
116 else if (CurrentVendor == Vendor)
121 CurrentVendor = Vendor;
123 assert(Contents.size() == 0);
126 void EmitAttribute(unsigned Attribute, unsigned Value) {
127 // FIXME: should be ULEB
128 Contents += Attribute;
132 void EmitTextAttribute(unsigned Attribute, StringRef String) {
133 Contents += Attribute;
134 Contents += UppercaseString(String);
139 const size_t ContentsSize = Contents.size();
141 // Vendor size + Vendor name + '\0'
142 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
145 const size_t TagHeaderSize = 1 + 4;
147 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
148 Streamer.EmitBytes(CurrentVendor, 0);
149 Streamer.EmitIntValue(0, 1); // '\0'
151 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
152 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
154 Streamer.EmitBytes(Contents, 0);
160 } // end of anonymous namespace
162 MachineLocation ARMAsmPrinter::
163 getDebugValueLocation(const MachineInstr *MI) const {
164 MachineLocation Location;
165 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
166 // Frame address. Currently handles register +- offset only.
167 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
168 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
170 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
175 void ARMAsmPrinter::EmitFunctionEntryLabel() {
176 if (AFI->isThumbFunction()) {
177 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
178 OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0);
181 OutStreamer.EmitLabel(CurrentFnSym);
184 /// runOnMachineFunction - This uses the EmitInstruction()
185 /// method to print assembly for each instruction.
187 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
188 AFI = MF.getInfo<ARMFunctionInfo>();
189 MCP = MF.getConstantPool();
191 return AsmPrinter::runOnMachineFunction(MF);
194 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
195 raw_ostream &O, const char *Modifier) {
196 const MachineOperand &MO = MI->getOperand(OpNum);
197 unsigned TF = MO.getTargetFlags();
199 switch (MO.getType()) {
201 assert(0 && "<unknown operand type>");
202 case MachineOperand::MO_Register: {
203 unsigned Reg = MO.getReg();
204 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
205 assert(!MO.getSubReg() && "Subregs should be eliminated!");
206 O << ARMInstPrinter::getRegisterName(Reg);
209 case MachineOperand::MO_Immediate: {
210 int64_t Imm = MO.getImm();
212 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
213 (TF == ARMII::MO_LO16))
215 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
216 (TF == ARMII::MO_HI16))
221 case MachineOperand::MO_MachineBasicBlock:
222 O << *MO.getMBB()->getSymbol();
224 case MachineOperand::MO_GlobalAddress: {
225 const GlobalValue *GV = MO.getGlobal();
226 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
227 (TF & ARMII::MO_LO16))
229 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
230 (TF & ARMII::MO_HI16))
232 O << *Mang->getSymbol(GV);
234 printOffset(MO.getOffset(), O);
235 if (TF == ARMII::MO_PLT)
239 case MachineOperand::MO_ExternalSymbol: {
240 O << *GetExternalSymbolSymbol(MO.getSymbolName());
241 if (TF == ARMII::MO_PLT)
245 case MachineOperand::MO_ConstantPoolIndex:
246 O << *GetCPISymbol(MO.getIndex());
248 case MachineOperand::MO_JumpTableIndex:
249 O << *GetJTISymbol(MO.getIndex());
254 //===--------------------------------------------------------------------===//
256 MCSymbol *ARMAsmPrinter::
257 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
258 const MachineBasicBlock *MBB) const {
259 SmallString<60> Name;
260 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
261 << getFunctionNumber() << '_' << uid << '_' << uid2
262 << "_set_" << MBB->getNumber();
263 return OutContext.GetOrCreateSymbol(Name.str());
266 MCSymbol *ARMAsmPrinter::
267 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
268 SmallString<60> Name;
269 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
270 << getFunctionNumber() << '_' << uid << '_' << uid2;
271 return OutContext.GetOrCreateSymbol(Name.str());
275 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
276 SmallString<60> Name;
277 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
278 << getFunctionNumber();
279 return OutContext.GetOrCreateSymbol(Name.str());
282 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
283 unsigned AsmVariant, const char *ExtraCode,
285 // Does this asm operand have a single letter operand modifier?
286 if (ExtraCode && ExtraCode[0]) {
287 if (ExtraCode[1] != 0) return true; // Unknown modifier.
289 switch (ExtraCode[0]) {
290 default: return true; // Unknown modifier.
291 case 'a': // Print as a memory address.
292 if (MI->getOperand(OpNum).isReg()) {
294 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
299 case 'c': // Don't print "#" before an immediate operand.
300 if (!MI->getOperand(OpNum).isImm())
302 O << MI->getOperand(OpNum).getImm();
304 case 'P': // Print a VFP double precision register.
305 case 'q': // Print a NEON quad precision register.
306 printOperand(MI, OpNum, O);
311 // These modifiers are not yet supported.
316 printOperand(MI, OpNum, O);
320 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
321 unsigned OpNum, unsigned AsmVariant,
322 const char *ExtraCode,
324 if (ExtraCode && ExtraCode[0])
325 return true; // Unknown modifier.
327 const MachineOperand &MO = MI->getOperand(OpNum);
328 assert(MO.isReg() && "unexpected inline asm memory operand");
329 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
333 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
334 if (Subtarget->isTargetDarwin()) {
335 Reloc::Model RelocM = TM.getRelocationModel();
336 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
337 // Declare all the text sections up front (before the DWARF sections
338 // emitted by AsmPrinter::doInitialization) so the assembler will keep
339 // them together at the beginning of the object file. This helps
340 // avoid out-of-range branches that are due a fundamental limitation of
341 // the way symbol offsets are encoded with the current Darwin ARM
343 const TargetLoweringObjectFileMachO &TLOFMacho =
344 static_cast<const TargetLoweringObjectFileMachO &>(
345 getObjFileLowering());
346 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
347 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
348 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
349 if (RelocM == Reloc::DynamicNoPIC) {
350 const MCSection *sect =
351 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
352 MCSectionMachO::S_SYMBOL_STUBS,
353 12, SectionKind::getText());
354 OutStreamer.SwitchSection(sect);
356 const MCSection *sect =
357 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
358 MCSectionMachO::S_SYMBOL_STUBS,
359 16, SectionKind::getText());
360 OutStreamer.SwitchSection(sect);
362 const MCSection *StaticInitSect =
363 OutContext.getMachOSection("__TEXT", "__StaticInit",
364 MCSectionMachO::S_REGULAR |
365 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
366 SectionKind::getText());
367 OutStreamer.SwitchSection(StaticInitSect);
371 // Use unified assembler syntax.
372 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
374 // Emit ARM Build Attributes
375 if (Subtarget->isTargetELF()) {
382 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
383 if (Subtarget->isTargetDarwin()) {
384 // All darwin targets use mach-o.
385 const TargetLoweringObjectFileMachO &TLOFMacho =
386 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
387 MachineModuleInfoMachO &MMIMacho =
388 MMI->getObjFileInfo<MachineModuleInfoMachO>();
390 // Output non-lazy-pointers for external and common global variables.
391 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
393 if (!Stubs.empty()) {
394 // Switch with ".non_lazy_symbol_pointer" directive.
395 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
397 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
399 OutStreamer.EmitLabel(Stubs[i].first);
400 // .indirect_symbol _foo
401 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
402 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
405 // External to current translation unit.
406 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
408 // Internal to current translation unit.
410 // When we place the LSDA into the TEXT section, the type info
411 // pointers need to be indirect and pc-rel. We accomplish this by
412 // using NLPs; however, sometimes the types are local to the file.
413 // We need to fill in the value for the NLP in those cases.
414 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
416 4/*size*/, 0/*addrspace*/);
420 OutStreamer.AddBlankLine();
423 Stubs = MMIMacho.GetHiddenGVStubList();
424 if (!Stubs.empty()) {
425 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
427 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
429 OutStreamer.EmitLabel(Stubs[i].first);
431 OutStreamer.EmitValue(MCSymbolRefExpr::
432 Create(Stubs[i].second.getPointer(),
434 4/*size*/, 0/*addrspace*/);
438 OutStreamer.AddBlankLine();
441 // Funny Darwin hack: This flag tells the linker that no global symbols
442 // contain code that falls through to other global symbols (e.g. the obvious
443 // implementation of multiple entry points). If this doesn't occur, the
444 // linker can safely perform dead code stripping. Since LLVM never
445 // generates code that does this, it is always safe to set.
446 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
450 //===----------------------------------------------------------------------===//
451 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
453 // The following seem like one-off assembler flags, but they actually need
454 // to appear in the .ARM.attributes section in ELF.
455 // Instead of subclassing the MCELFStreamer, we do the work here.
457 void ARMAsmPrinter::emitAttributes() {
459 emitARMAttributeSection();
461 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
462 bool emitFPU = false;
463 AttributeEmitter *AttrEmitter;
464 if (OutStreamer.hasRawTextSupport()) {
465 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
468 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
469 AttrEmitter = new ObjectAttributeEmitter(O);
472 AttrEmitter->MaybeSwitchVendor("aeabi");
474 std::string CPUString = Subtarget->getCPUString();
476 if (CPUString == "cortex-a8" ||
477 Subtarget->isCortexA8()) {
478 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
479 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
480 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
481 ARMBuildAttrs::ApplicationProfile);
482 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
483 ARMBuildAttrs::Allowed);
484 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
485 ARMBuildAttrs::AllowThumb32);
486 // Fixme: figure out when this is emitted.
487 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
488 // ARMBuildAttrs::AllowWMMXv1);
491 /// ADD additional Else-cases here!
492 } else if (CPUString == "generic") {
493 // FIXME: Why these defaults?
494 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
495 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
496 ARMBuildAttrs::Allowed);
497 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
498 ARMBuildAttrs::Allowed);
501 if (Subtarget->hasNEON() && emitFPU) {
502 /* NEON is not exactly a VFP architecture, but GAS emit one of
503 * neon/vfpv3/vfpv2 for .fpu parameters */
504 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
505 /* If emitted for NEON, omit from VFP below, since you can have both
506 * NEON and VFP in build attributes but only one .fpu */
511 if (Subtarget->hasVFP3()) {
512 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
513 ARMBuildAttrs::AllowFPv3A);
515 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
518 } else if (Subtarget->hasVFP2()) {
519 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
520 ARMBuildAttrs::AllowFPv2);
522 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
525 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
526 * since NEON can have 1 (allowed) or 2 (fused MAC operations) */
527 if (Subtarget->hasNEON()) {
528 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
529 ARMBuildAttrs::Allowed);
532 // Signal various FP modes.
534 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
535 ARMBuildAttrs::Allowed);
536 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
537 ARMBuildAttrs::Allowed);
540 if (NoInfsFPMath && NoNaNsFPMath)
541 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
542 ARMBuildAttrs::Allowed);
544 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
545 ARMBuildAttrs::AllowIEE754);
547 // FIXME: add more flags to ARMBuildAttrs.h
548 // 8-bytes alignment stuff.
549 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
550 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
552 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
553 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
554 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
555 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
557 // FIXME: Should we signal R9 usage?
559 if (Subtarget->hasDivide())
560 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
562 AttrEmitter->Finish();
566 void ARMAsmPrinter::emitARMAttributeSection() {
568 // [ <section-length> "vendor-name"
569 // [ <file-tag> <size> <attribute>*
570 // | <section-tag> <size> <section-number>* 0 <attribute>*
571 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
575 if (OutStreamer.hasRawTextSupport())
578 const ARMElfTargetObjectFile &TLOFELF =
579 static_cast<const ARMElfTargetObjectFile &>
580 (getObjFileLowering());
582 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
585 OutStreamer.EmitIntValue(0x41, 1);
588 //===----------------------------------------------------------------------===//
590 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
591 unsigned LabelId, MCContext &Ctx) {
593 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
594 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
598 static MCSymbolRefExpr::VariantKind
599 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
601 default: llvm_unreachable("Unknown modifier!");
602 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
603 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
604 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
605 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
606 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
607 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
609 return MCSymbolRefExpr::VK_None;
612 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
613 bool isIndirect = Subtarget->isTargetDarwin() &&
614 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
616 return Mang->getSymbol(GV);
618 // FIXME: Remove this when Darwin transition to @GOT like syntax.
619 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
620 MachineModuleInfoMachO &MMIMachO =
621 MMI->getObjFileInfo<MachineModuleInfoMachO>();
622 MachineModuleInfoImpl::StubValueTy &StubSym =
623 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
624 MMIMachO.getGVStubEntry(MCSym);
625 if (StubSym.getPointer() == 0)
626 StubSym = MachineModuleInfoImpl::
627 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
632 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
633 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
635 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
638 if (ACPV->isLSDA()) {
639 SmallString<128> Str;
640 raw_svector_ostream OS(Str);
641 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
642 MCSym = OutContext.GetOrCreateSymbol(OS.str());
643 } else if (ACPV->isBlockAddress()) {
644 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
645 } else if (ACPV->isGlobalValue()) {
646 const GlobalValue *GV = ACPV->getGV();
647 MCSym = GetARMGVSymbol(GV);
649 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
650 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
653 // Create an MCSymbol for the reference.
655 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
658 if (ACPV->getPCAdjustment()) {
659 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
663 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
665 MCBinaryExpr::CreateAdd(PCRelExpr,
666 MCConstantExpr::Create(ACPV->getPCAdjustment(),
669 if (ACPV->mustAddCurrentAddress()) {
670 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
671 // label, so just emit a local label end reference that instead.
672 MCSymbol *DotSym = OutContext.CreateTempSymbol();
673 OutStreamer.EmitLabel(DotSym);
674 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
675 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
677 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
679 OutStreamer.EmitValue(Expr, Size);
682 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
683 unsigned Opcode = MI->getOpcode();
685 if (Opcode == ARM::BR_JTadd)
687 else if (Opcode == ARM::BR_JTm)
690 const MachineOperand &MO1 = MI->getOperand(OpNum);
691 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
692 unsigned JTI = MO1.getIndex();
694 // Emit a label for the jump table.
695 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
696 OutStreamer.EmitLabel(JTISymbol);
698 // Emit each entry of the table.
699 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
700 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
701 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
703 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
704 MachineBasicBlock *MBB = JTBBs[i];
705 // Construct an MCExpr for the entry. We want a value of the form:
706 // (BasicBlockAddr - TableBeginAddr)
708 // For example, a table with entries jumping to basic blocks BB0 and BB1
711 // .word (LBB0 - LJTI_0_0)
712 // .word (LBB1 - LJTI_0_0)
713 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
715 if (TM.getRelocationModel() == Reloc::PIC_)
716 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
719 OutStreamer.EmitValue(Expr, 4);
723 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
724 unsigned Opcode = MI->getOpcode();
725 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
726 const MachineOperand &MO1 = MI->getOperand(OpNum);
727 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
728 unsigned JTI = MO1.getIndex();
730 // Emit a label for the jump table.
731 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
732 OutStreamer.EmitLabel(JTISymbol);
734 // Emit each entry of the table.
735 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
736 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
737 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
738 unsigned OffsetWidth = 4;
739 if (MI->getOpcode() == ARM::t2TBB_JT)
741 else if (MI->getOpcode() == ARM::t2TBH_JT)
744 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
745 MachineBasicBlock *MBB = JTBBs[i];
746 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
748 // If this isn't a TBB or TBH, the entries are direct branch instructions.
749 if (OffsetWidth == 4) {
751 BrInst.setOpcode(ARM::t2B);
752 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
753 OutStreamer.EmitInstruction(BrInst);
756 // Otherwise it's an offset from the dispatch instruction. Construct an
757 // MCExpr for the entry. We want a value of the form:
758 // (BasicBlockAddr - TableBeginAddr) / 2
760 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
763 // .byte (LBB0 - LJTI_0_0) / 2
764 // .byte (LBB1 - LJTI_0_0) / 2
766 MCBinaryExpr::CreateSub(MBBSymbolExpr,
767 MCSymbolRefExpr::Create(JTISymbol, OutContext),
769 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
771 OutStreamer.EmitValue(Expr, OffsetWidth);
775 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
777 unsigned NOps = MI->getNumOperands();
779 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
780 // cast away const; DIetc do not take const operands for some reason.
781 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
784 // Frame address. Currently handles register +- offset only.
785 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
786 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
789 printOperand(MI, NOps-2, OS);
792 static void populateADROperands(MCInst &Inst, unsigned Dest,
793 const MCSymbol *Label,
794 unsigned pred, unsigned ccreg,
796 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
797 Inst.addOperand(MCOperand::CreateReg(Dest));
798 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
799 // Add predicate operands.
800 Inst.addOperand(MCOperand::CreateImm(pred));
801 Inst.addOperand(MCOperand::CreateReg(ccreg));
804 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
808 // Emit the instruction as usual, just patch the opcode.
809 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
810 TmpInst.setOpcode(Opcode);
811 OutStreamer.EmitInstruction(TmpInst);
814 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
815 assert(MI->getFlag(MachineInstr::FrameSetup) &&
816 "Only instruction which are involved into frame setup code are allowed");
818 const MachineFunction &MF = *MI->getParent()->getParent();
819 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
820 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
822 unsigned FramePtr = RegInfo->getFrameRegister(MF);
823 unsigned Opc = MI->getOpcode();
824 unsigned SrcReg, DstReg;
826 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
827 // Two special cases:
828 // 1) tPUSH does not have src/dst regs.
829 // 2) for Thumb1 code we sometimes materialize the constant via constpool
830 // load. Yes, this is pretty fragile, but for now I don't see better
832 SrcReg = DstReg = ARM::SP;
834 SrcReg = MI->getOperand(1).getReg();
835 DstReg = MI->getOperand(0).getReg();
838 // Try to figure out the unwinding opcode out of src / dst regs.
839 if (MI->getDesc().mayStore()) {
841 assert(DstReg == ARM::SP &&
842 "Only stack pointer as a destination reg is supported");
844 SmallVector<unsigned, 4> RegList;
845 // Skip src & dst reg, and pred ops.
846 unsigned StartOp = 2 + 2;
847 // Use all the operands.
848 unsigned NumOffset = 0;
853 assert(0 && "Unsupported opcode for unwinding information");
855 // Special case here: no src & dst reg, but two extra imp ops.
856 StartOp = 2; NumOffset = 2;
858 case ARM::t2STMDB_UPD:
859 case ARM::VSTMDDB_UPD:
860 assert(SrcReg == ARM::SP &&
861 "Only stack pointer as a source reg is supported");
862 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
864 RegList.push_back(MI->getOperand(i).getReg());
867 assert(MI->getOperand(2).getReg() == ARM::SP &&
868 "Only stack pointer as a source reg is supported");
869 RegList.push_back(SrcReg);
872 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
874 // Changes of stack / frame pointer.
875 if (SrcReg == ARM::SP) {
880 assert(0 && "Unsupported opcode for unwinding information");
882 case ARM::tMOVgpr2gpr:
883 case ARM::tMOVgpr2tgpr:
887 Offset = -MI->getOperand(2).getImm();
891 Offset = MI->getOperand(2).getImm();
894 Offset = MI->getOperand(2).getImm()*4;
898 Offset = -MI->getOperand(2).getImm()*4;
901 // Grab the constpool index and check, whether it corresponds to
902 // original or cloned constpool entry.
903 unsigned CPI = MI->getOperand(1).getIndex();
904 const MachineConstantPool *MCP = MF.getConstantPool();
905 if (CPI >= MCP->getConstants().size())
906 CPI = AFI.getOriginalCPIdx(CPI);
907 assert(CPI != -1U && "Invalid constpool index");
909 // Derive the actual offset.
910 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
911 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
912 // FIXME: Check for user, it should be "add" instruction!
913 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
918 if (DstReg == FramePtr && FramePtr != ARM::SP)
919 // Set-up of the frame pointer. Positive values correspond to "add"
921 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
922 else if (DstReg == ARM::SP) {
923 // Change of SP by an offset. Positive values correspond to "sub"
925 OutStreamer.EmitPad(Offset);
928 assert(0 && "Unsupported opcode for unwinding information");
930 } else if (DstReg == ARM::SP) {
931 // FIXME: .movsp goes here
933 assert(0 && "Unsupported opcode for unwinding information");
937 assert(0 && "Unsupported opcode for unwinding information");
942 extern cl::opt<bool> EnableARMEHABI;
944 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
945 unsigned Opc = MI->getOpcode();
949 // B is just a Bcc with an 'always' predicate.
951 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
952 TmpInst.setOpcode(ARM::Bcc);
953 // Add predicate operands.
954 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
955 TmpInst.addOperand(MCOperand::CreateReg(0));
956 OutStreamer.EmitInstruction(TmpInst);
959 case ARM::LDMIA_RET: {
960 // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
961 // such has additional code-gen properties and scheduling information.
962 // To emit it, we just construct as normal and set the opcode to LDMIA_UPD.
964 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
965 TmpInst.setOpcode(ARM::LDMIA_UPD);
966 OutStreamer.EmitInstruction(TmpInst);
970 case ARM::t2ADDrSPi12:
972 case ARM::t2SUBrSPi12:
973 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
974 "Unexpected source register!");
977 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
978 case ARM::DBG_VALUE: {
979 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
980 SmallString<128> TmpStr;
981 raw_svector_ostream OS(TmpStr);
982 PrintDebugValueComment(MI, OS);
983 OutStreamer.EmitRawText(StringRef(OS.str()));
989 TmpInst.setOpcode(ARM::tBL);
990 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
991 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
992 OutStreamer.EmitInstruction(TmpInst);
997 case ARM::t2LEApcrel: {
998 // FIXME: Need to also handle globals and externals
1000 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1001 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1003 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1004 GetCPISymbol(MI->getOperand(1).getIndex()),
1005 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1007 OutStreamer.EmitInstruction(TmpInst);
1010 case ARM::LEApcrelJT:
1011 case ARM::tLEApcrelJT:
1012 case ARM::t2LEApcrelJT: {
1014 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1015 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1017 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1018 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1019 MI->getOperand(2).getImm()),
1020 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1022 OutStreamer.EmitInstruction(TmpInst);
1025 case ARM::MOVPCRX: {
1027 TmpInst.setOpcode(ARM::MOVr);
1028 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1029 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1030 // Add predicate operands.
1031 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1032 TmpInst.addOperand(MCOperand::CreateReg(0));
1033 // Add 's' bit operand (always reg0 for this)
1034 TmpInst.addOperand(MCOperand::CreateReg(0));
1035 OutStreamer.EmitInstruction(TmpInst);
1038 case ARM::BXr9_CALL:
1039 case ARM::BX_CALL: {
1042 TmpInst.setOpcode(ARM::MOVr);
1043 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1044 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1045 // Add predicate operands.
1046 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1047 TmpInst.addOperand(MCOperand::CreateReg(0));
1048 // Add 's' bit operand (always reg0 for this)
1049 TmpInst.addOperand(MCOperand::CreateReg(0));
1050 OutStreamer.EmitInstruction(TmpInst);
1054 TmpInst.setOpcode(ARM::BX);
1055 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1056 OutStreamer.EmitInstruction(TmpInst);
1060 case ARM::BMOVPCRXr9_CALL:
1061 case ARM::BMOVPCRX_CALL: {
1064 TmpInst.setOpcode(ARM::MOVr);
1065 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1066 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1067 // Add predicate operands.
1068 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1069 TmpInst.addOperand(MCOperand::CreateReg(0));
1070 // Add 's' bit operand (always reg0 for this)
1071 TmpInst.addOperand(MCOperand::CreateReg(0));
1072 OutStreamer.EmitInstruction(TmpInst);
1076 TmpInst.setOpcode(ARM::MOVr);
1077 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1078 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1079 // Add predicate operands.
1080 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1081 TmpInst.addOperand(MCOperand::CreateReg(0));
1082 // Add 's' bit operand (always reg0 for this)
1083 TmpInst.addOperand(MCOperand::CreateReg(0));
1084 OutStreamer.EmitInstruction(TmpInst);
1088 case ARM::MOVi16_ga_pcrel:
1089 case ARM::t2MOVi16_ga_pcrel: {
1091 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1092 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1094 unsigned TF = MI->getOperand(1).getTargetFlags();
1095 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1096 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1097 MCSymbol *GVSym = GetARMGVSymbol(GV);
1098 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1100 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1101 getFunctionNumber(),
1102 MI->getOperand(2).getImm(), OutContext);
1103 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1104 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1105 const MCExpr *PCRelExpr =
1106 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1107 MCBinaryExpr::CreateAdd(LabelSymExpr,
1108 MCConstantExpr::Create(PCAdj, OutContext),
1109 OutContext), OutContext), OutContext);
1110 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1112 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1113 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1116 // Add predicate operands.
1117 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1118 TmpInst.addOperand(MCOperand::CreateReg(0));
1119 // Add 's' bit operand (always reg0 for this)
1120 TmpInst.addOperand(MCOperand::CreateReg(0));
1121 OutStreamer.EmitInstruction(TmpInst);
1124 case ARM::MOVTi16_ga_pcrel:
1125 case ARM::t2MOVTi16_ga_pcrel: {
1127 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1128 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1129 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1130 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1132 unsigned TF = MI->getOperand(2).getTargetFlags();
1133 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1134 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1135 MCSymbol *GVSym = GetARMGVSymbol(GV);
1136 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1138 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1139 getFunctionNumber(),
1140 MI->getOperand(3).getImm(), OutContext);
1141 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1142 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1143 const MCExpr *PCRelExpr =
1144 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1145 MCBinaryExpr::CreateAdd(LabelSymExpr,
1146 MCConstantExpr::Create(PCAdj, OutContext),
1147 OutContext), OutContext), OutContext);
1148 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1150 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1151 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1153 // Add predicate operands.
1154 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1155 TmpInst.addOperand(MCOperand::CreateReg(0));
1156 // Add 's' bit operand (always reg0 for this)
1157 TmpInst.addOperand(MCOperand::CreateReg(0));
1158 OutStreamer.EmitInstruction(TmpInst);
1161 case ARM::tPICADD: {
1162 // This is a pseudo op for a label + instruction sequence, which looks like:
1165 // This adds the address of LPC0 to r0.
1168 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1169 getFunctionNumber(), MI->getOperand(2).getImm(),
1172 // Form and emit the add.
1174 AddInst.setOpcode(ARM::tADDhirr);
1175 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1176 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1177 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1178 // Add predicate operands.
1179 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1180 AddInst.addOperand(MCOperand::CreateReg(0));
1181 OutStreamer.EmitInstruction(AddInst);
1185 // This is a pseudo op for a label + instruction sequence, which looks like:
1188 // This adds the address of LPC0 to r0.
1191 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1192 getFunctionNumber(), MI->getOperand(2).getImm(),
1195 // Form and emit the add.
1197 AddInst.setOpcode(ARM::ADDrr);
1198 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1199 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1200 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1201 // Add predicate operands.
1202 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1203 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1204 // Add 's' bit operand (always reg0 for this)
1205 AddInst.addOperand(MCOperand::CreateReg(0));
1206 OutStreamer.EmitInstruction(AddInst);
1216 case ARM::PICLDRSH: {
1217 // This is a pseudo op for a label + instruction sequence, which looks like:
1220 // The LCP0 label is referenced by a constant pool entry in order to get
1221 // a PC-relative address at the ldr instruction.
1224 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1225 getFunctionNumber(), MI->getOperand(2).getImm(),
1228 // Form and emit the load
1230 switch (MI->getOpcode()) {
1232 llvm_unreachable("Unexpected opcode!");
1233 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1234 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1235 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1236 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1237 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1238 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1239 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1240 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1243 LdStInst.setOpcode(Opcode);
1244 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1245 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1246 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1247 LdStInst.addOperand(MCOperand::CreateImm(0));
1248 // Add predicate operands.
1249 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1250 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1251 OutStreamer.EmitInstruction(LdStInst);
1255 case ARM::CONSTPOOL_ENTRY: {
1256 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1257 /// in the function. The first operand is the ID# for this instruction, the
1258 /// second is the index into the MachineConstantPool that this is, the third
1259 /// is the size in bytes of this constant pool entry.
1260 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1261 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1264 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1266 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1267 if (MCPE.isMachineConstantPoolEntry())
1268 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1270 EmitGlobalConstant(MCPE.Val.ConstVal);
1274 case ARM::t2BR_JT: {
1275 // Lower and emit the instruction itself, then the jump table following it.
1277 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1278 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1279 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1280 // Add predicate operands.
1281 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1282 TmpInst.addOperand(MCOperand::CreateReg(0));
1283 OutStreamer.EmitInstruction(TmpInst);
1284 // Output the data for the jump table itself
1288 case ARM::t2TBB_JT: {
1289 // Lower and emit the instruction itself, then the jump table following it.
1292 TmpInst.setOpcode(ARM::t2TBB);
1293 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1294 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1295 // Add predicate operands.
1296 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1297 TmpInst.addOperand(MCOperand::CreateReg(0));
1298 OutStreamer.EmitInstruction(TmpInst);
1299 // Output the data for the jump table itself
1301 // Make sure the next instruction is 2-byte aligned.
1305 case ARM::t2TBH_JT: {
1306 // Lower and emit the instruction itself, then the jump table following it.
1309 TmpInst.setOpcode(ARM::t2TBH);
1310 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1311 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1312 // Add predicate operands.
1313 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1314 TmpInst.addOperand(MCOperand::CreateReg(0));
1315 OutStreamer.EmitInstruction(TmpInst);
1316 // Output the data for the jump table itself
1322 // Lower and emit the instruction itself, then the jump table following it.
1325 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1326 ARM::MOVr : ARM::tMOVgpr2gpr;
1327 TmpInst.setOpcode(Opc);
1328 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1329 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1330 // Add predicate operands.
1331 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1332 TmpInst.addOperand(MCOperand::CreateReg(0));
1333 // Add 's' bit operand (always reg0 for this)
1334 if (Opc == ARM::MOVr)
1335 TmpInst.addOperand(MCOperand::CreateReg(0));
1336 OutStreamer.EmitInstruction(TmpInst);
1338 // Make sure the Thumb jump table is 4-byte aligned.
1339 if (Opc == ARM::tMOVgpr2gpr)
1342 // Output the data for the jump table itself
1347 // Lower and emit the instruction itself, then the jump table following it.
1350 if (MI->getOperand(1).getReg() == 0) {
1352 TmpInst.setOpcode(ARM::LDRi12);
1353 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1354 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1355 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1357 TmpInst.setOpcode(ARM::LDRrs);
1358 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1359 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1360 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1361 TmpInst.addOperand(MCOperand::CreateImm(0));
1363 // Add predicate operands.
1364 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1365 TmpInst.addOperand(MCOperand::CreateReg(0));
1366 OutStreamer.EmitInstruction(TmpInst);
1368 // Output the data for the jump table itself
1372 case ARM::BR_JTadd: {
1373 // Lower and emit the instruction itself, then the jump table following it.
1374 // add pc, target, idx
1376 TmpInst.setOpcode(ARM::ADDrr);
1377 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1378 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1379 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1380 // Add predicate operands.
1381 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1382 TmpInst.addOperand(MCOperand::CreateReg(0));
1383 // Add 's' bit operand (always reg0 for this)
1384 TmpInst.addOperand(MCOperand::CreateReg(0));
1385 OutStreamer.EmitInstruction(TmpInst);
1387 // Output the data for the jump table itself
1392 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1393 // FIXME: Remove this special case when they do.
1394 if (!Subtarget->isTargetDarwin()) {
1395 //.long 0xe7ffdefe @ trap
1396 uint32_t Val = 0xe7ffdefeUL;
1397 OutStreamer.AddComment("trap");
1398 OutStreamer.EmitIntValue(Val, 4);
1404 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1405 // FIXME: Remove this special case when they do.
1406 if (!Subtarget->isTargetDarwin()) {
1407 //.short 57086 @ trap
1408 uint16_t Val = 0xdefe;
1409 OutStreamer.AddComment("trap");
1410 OutStreamer.EmitIntValue(Val, 2);
1415 case ARM::t2Int_eh_sjlj_setjmp:
1416 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1417 case ARM::tInt_eh_sjlj_setjmp: {
1418 // Two incoming args: GPR:$src, GPR:$val
1421 // str $val, [$src, #4]
1426 unsigned SrcReg = MI->getOperand(0).getReg();
1427 unsigned ValReg = MI->getOperand(1).getReg();
1428 MCSymbol *Label = GetARMSJLJEHLabel();
1431 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1432 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1433 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1435 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1436 OutStreamer.AddComment("eh_setjmp begin");
1437 OutStreamer.EmitInstruction(TmpInst);
1441 TmpInst.setOpcode(ARM::tADDi3);
1442 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1444 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1445 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1446 TmpInst.addOperand(MCOperand::CreateImm(7));
1448 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1449 TmpInst.addOperand(MCOperand::CreateReg(0));
1450 OutStreamer.EmitInstruction(TmpInst);
1454 TmpInst.setOpcode(ARM::tSTRi);
1455 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1456 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1457 // The offset immediate is #4. The operand value is scaled by 4 for the
1458 // tSTR instruction.
1459 TmpInst.addOperand(MCOperand::CreateImm(1));
1461 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1462 TmpInst.addOperand(MCOperand::CreateReg(0));
1463 OutStreamer.EmitInstruction(TmpInst);
1467 TmpInst.setOpcode(ARM::tMOVi8);
1468 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1469 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1470 TmpInst.addOperand(MCOperand::CreateImm(0));
1472 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1473 TmpInst.addOperand(MCOperand::CreateReg(0));
1474 OutStreamer.EmitInstruction(TmpInst);
1477 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1479 TmpInst.setOpcode(ARM::tB);
1480 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1481 OutStreamer.EmitInstruction(TmpInst);
1485 TmpInst.setOpcode(ARM::tMOVi8);
1486 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1487 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1488 TmpInst.addOperand(MCOperand::CreateImm(1));
1490 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1491 TmpInst.addOperand(MCOperand::CreateReg(0));
1492 OutStreamer.AddComment("eh_setjmp end");
1493 OutStreamer.EmitInstruction(TmpInst);
1495 OutStreamer.EmitLabel(Label);
1499 case ARM::Int_eh_sjlj_setjmp_nofp:
1500 case ARM::Int_eh_sjlj_setjmp: {
1501 // Two incoming args: GPR:$src, GPR:$val
1503 // str $val, [$src, #+4]
1507 unsigned SrcReg = MI->getOperand(0).getReg();
1508 unsigned ValReg = MI->getOperand(1).getReg();
1512 TmpInst.setOpcode(ARM::ADDri);
1513 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1514 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1515 TmpInst.addOperand(MCOperand::CreateImm(8));
1517 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1518 TmpInst.addOperand(MCOperand::CreateReg(0));
1519 // 's' bit operand (always reg0 for this).
1520 TmpInst.addOperand(MCOperand::CreateReg(0));
1521 OutStreamer.AddComment("eh_setjmp begin");
1522 OutStreamer.EmitInstruction(TmpInst);
1526 TmpInst.setOpcode(ARM::STRi12);
1527 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1528 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1529 TmpInst.addOperand(MCOperand::CreateImm(4));
1531 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1532 TmpInst.addOperand(MCOperand::CreateReg(0));
1533 OutStreamer.EmitInstruction(TmpInst);
1537 TmpInst.setOpcode(ARM::MOVi);
1538 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1539 TmpInst.addOperand(MCOperand::CreateImm(0));
1541 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1542 TmpInst.addOperand(MCOperand::CreateReg(0));
1543 // 's' bit operand (always reg0 for this).
1544 TmpInst.addOperand(MCOperand::CreateReg(0));
1545 OutStreamer.EmitInstruction(TmpInst);
1549 TmpInst.setOpcode(ARM::ADDri);
1550 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1551 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1552 TmpInst.addOperand(MCOperand::CreateImm(0));
1554 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1555 TmpInst.addOperand(MCOperand::CreateReg(0));
1556 // 's' bit operand (always reg0 for this).
1557 TmpInst.addOperand(MCOperand::CreateReg(0));
1558 OutStreamer.EmitInstruction(TmpInst);
1562 TmpInst.setOpcode(ARM::MOVi);
1563 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1564 TmpInst.addOperand(MCOperand::CreateImm(1));
1566 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1567 TmpInst.addOperand(MCOperand::CreateReg(0));
1568 // 's' bit operand (always reg0 for this).
1569 TmpInst.addOperand(MCOperand::CreateReg(0));
1570 OutStreamer.AddComment("eh_setjmp end");
1571 OutStreamer.EmitInstruction(TmpInst);
1575 case ARM::Int_eh_sjlj_longjmp: {
1576 // ldr sp, [$src, #8]
1577 // ldr $scratch, [$src, #4]
1580 unsigned SrcReg = MI->getOperand(0).getReg();
1581 unsigned ScratchReg = MI->getOperand(1).getReg();
1584 TmpInst.setOpcode(ARM::LDRi12);
1585 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1586 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1587 TmpInst.addOperand(MCOperand::CreateImm(8));
1589 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1590 TmpInst.addOperand(MCOperand::CreateReg(0));
1591 OutStreamer.EmitInstruction(TmpInst);
1595 TmpInst.setOpcode(ARM::LDRi12);
1596 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1597 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1598 TmpInst.addOperand(MCOperand::CreateImm(4));
1600 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1601 TmpInst.addOperand(MCOperand::CreateReg(0));
1602 OutStreamer.EmitInstruction(TmpInst);
1606 TmpInst.setOpcode(ARM::LDRi12);
1607 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1608 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1609 TmpInst.addOperand(MCOperand::CreateImm(0));
1611 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1612 TmpInst.addOperand(MCOperand::CreateReg(0));
1613 OutStreamer.EmitInstruction(TmpInst);
1617 TmpInst.setOpcode(ARM::BX);
1618 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1620 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1621 TmpInst.addOperand(MCOperand::CreateReg(0));
1622 OutStreamer.EmitInstruction(TmpInst);
1626 case ARM::tInt_eh_sjlj_longjmp: {
1627 // ldr $scratch, [$src, #8]
1629 // ldr $scratch, [$src, #4]
1632 unsigned SrcReg = MI->getOperand(0).getReg();
1633 unsigned ScratchReg = MI->getOperand(1).getReg();
1636 TmpInst.setOpcode(ARM::tLDRi);
1637 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1638 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1639 // The offset immediate is #8. The operand value is scaled by 4 for the
1640 // tLDR instruction.
1641 TmpInst.addOperand(MCOperand::CreateImm(2));
1643 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1644 TmpInst.addOperand(MCOperand::CreateReg(0));
1645 OutStreamer.EmitInstruction(TmpInst);
1649 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1650 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1651 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1653 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1654 TmpInst.addOperand(MCOperand::CreateReg(0));
1655 OutStreamer.EmitInstruction(TmpInst);
1659 TmpInst.setOpcode(ARM::tLDRi);
1660 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1661 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1662 TmpInst.addOperand(MCOperand::CreateImm(1));
1664 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1665 TmpInst.addOperand(MCOperand::CreateReg(0));
1666 OutStreamer.EmitInstruction(TmpInst);
1670 TmpInst.setOpcode(ARM::tLDRr);
1671 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1672 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1673 TmpInst.addOperand(MCOperand::CreateReg(0));
1675 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1676 TmpInst.addOperand(MCOperand::CreateReg(0));
1677 OutStreamer.EmitInstruction(TmpInst);
1681 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1682 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1684 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1685 TmpInst.addOperand(MCOperand::CreateReg(0));
1686 OutStreamer.EmitInstruction(TmpInst);
1690 // These are the pseudos created to comply with stricter operand restrictions
1691 // on ARMv5. Lower them now to "normal" instructions, since all the
1692 // restrictions are already satisfied.
1694 EmitPatchedInstruction(MI, ARM::MUL);
1697 EmitPatchedInstruction(MI, ARM::MLA);
1700 EmitPatchedInstruction(MI, ARM::SMULL);
1703 EmitPatchedInstruction(MI, ARM::UMULL);
1706 EmitPatchedInstruction(MI, ARM::SMLAL);
1709 EmitPatchedInstruction(MI, ARM::UMLAL);
1712 EmitPatchedInstruction(MI, ARM::UMAAL);
1717 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1719 // Emit unwinding stuff for frame-related instructions
1720 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1721 EmitUnwindingInstruction(MI);
1723 OutStreamer.EmitInstruction(TmpInst);
1726 //===----------------------------------------------------------------------===//
1727 // Target Registry Stuff
1728 //===----------------------------------------------------------------------===//
1730 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1731 unsigned SyntaxVariant,
1732 const MCAsmInfo &MAI) {
1733 if (SyntaxVariant == 0)
1734 return new ARMInstPrinter(MAI);
1738 // Force static initialization.
1739 extern "C" void LLVMInitializeARMAsmPrinter() {
1740 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1741 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1743 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1744 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);