1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMFPUName.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMBuildAttrs.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/ADT/SetVector.h"
28 #include "llvm/ADT/SmallString.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/DebugInfo.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/IR/Writer.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCAssembler.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCELFStreamer.h"
42 #include "llvm/MC/MCInst.h"
43 #include "llvm/MC/MCInstBuilder.h"
44 #include "llvm/MC/MCObjectStreamer.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/MC/MCStreamer.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/Mangler.h"
55 #include "llvm/Target/TargetMachine.h"
59 /// EmitDwarfRegOp - Emit dwarf register operation.
60 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
61 bool Indirect) const {
62 const TargetRegisterInfo *RI = TM.getRegisterInfo();
63 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
64 AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
67 assert(MLoc.isReg() && !Indirect &&
68 "This doesn't support offset/indirection - implement it if needed");
69 unsigned Reg = MLoc.getReg();
70 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
71 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
72 // S registers are described as bit-pieces of a register
73 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
74 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
76 unsigned SReg = Reg - ARM::S0;
77 bool odd = SReg & 0x1;
78 unsigned Rx = 256 + (SReg >> 1);
80 OutStreamer.AddComment("DW_OP_regx for S register");
81 EmitInt8(dwarf::DW_OP_regx);
83 OutStreamer.AddComment(Twine(SReg));
87 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
88 EmitInt8(dwarf::DW_OP_bit_piece);
92 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
93 EmitInt8(dwarf::DW_OP_bit_piece);
97 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
98 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
99 // Q registers Q0-Q15 are described by composing two D registers together.
100 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
103 unsigned QReg = Reg - ARM::Q0;
104 unsigned D1 = 256 + 2 * QReg;
105 unsigned D2 = D1 + 1;
107 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
108 EmitInt8(dwarf::DW_OP_regx);
110 OutStreamer.AddComment("DW_OP_piece 8");
111 EmitInt8(dwarf::DW_OP_piece);
114 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
115 EmitInt8(dwarf::DW_OP_regx);
117 OutStreamer.AddComment("DW_OP_piece 8");
118 EmitInt8(dwarf::DW_OP_piece);
123 void ARMAsmPrinter::EmitFunctionBodyEnd() {
124 // Make sure to terminate any constant pools that were at the end
128 InConstantPool = false;
129 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
132 void ARMAsmPrinter::EmitFunctionEntryLabel() {
133 if (AFI->isThumbFunction()) {
134 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
135 OutStreamer.EmitThumbFunc(CurrentFnSym);
138 OutStreamer.EmitLabel(CurrentFnSym);
141 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
142 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
143 assert(Size && "C++ constructor pointer had zero size!");
145 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
146 assert(GV && "C++ constructor pointer was not a GlobalValue!");
148 const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
149 (Subtarget->isTargetELF()
150 ? MCSymbolRefExpr::VK_ARM_TARGET1
151 : MCSymbolRefExpr::VK_None),
154 OutStreamer.EmitValue(E, Size);
157 /// runOnMachineFunction - This uses the EmitInstruction()
158 /// method to print assembly for each instruction.
160 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
161 AFI = MF.getInfo<ARMFunctionInfo>();
162 MCP = MF.getConstantPool();
164 return AsmPrinter::runOnMachineFunction(MF);
167 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
168 raw_ostream &O, const char *Modifier) {
169 const MachineOperand &MO = MI->getOperand(OpNum);
170 unsigned TF = MO.getTargetFlags();
172 switch (MO.getType()) {
173 default: llvm_unreachable("<unknown operand type>");
174 case MachineOperand::MO_Register: {
175 unsigned Reg = MO.getReg();
176 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
177 assert(!MO.getSubReg() && "Subregs should be eliminated!");
178 if(ARM::GPRPairRegClass.contains(Reg)) {
179 const MachineFunction &MF = *MI->getParent()->getParent();
180 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
181 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
183 O << ARMInstPrinter::getRegisterName(Reg);
186 case MachineOperand::MO_Immediate: {
187 int64_t Imm = MO.getImm();
189 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
190 (TF == ARMII::MO_LO16))
192 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
193 (TF == ARMII::MO_HI16))
198 case MachineOperand::MO_MachineBasicBlock:
199 O << *MO.getMBB()->getSymbol();
201 case MachineOperand::MO_GlobalAddress: {
202 const GlobalValue *GV = MO.getGlobal();
203 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
204 (TF & ARMII::MO_LO16))
206 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
207 (TF & ARMII::MO_HI16))
211 printOffset(MO.getOffset(), O);
212 if (TF == ARMII::MO_PLT)
216 case MachineOperand::MO_ConstantPoolIndex:
217 O << *GetCPISymbol(MO.getIndex());
222 //===--------------------------------------------------------------------===//
224 MCSymbol *ARMAsmPrinter::
225 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
226 const DataLayout *DL = TM.getDataLayout();
227 SmallString<60> Name;
228 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
229 << getFunctionNumber() << '_' << uid << '_' << uid2;
230 return OutContext.GetOrCreateSymbol(Name.str());
234 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
235 const DataLayout *DL = TM.getDataLayout();
236 SmallString<60> Name;
237 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
238 << getFunctionNumber();
239 return OutContext.GetOrCreateSymbol(Name.str());
242 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
243 unsigned AsmVariant, const char *ExtraCode,
245 // Does this asm operand have a single letter operand modifier?
246 if (ExtraCode && ExtraCode[0]) {
247 if (ExtraCode[1] != 0) return true; // Unknown modifier.
249 switch (ExtraCode[0]) {
251 // See if this is a generic print operand
252 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
253 case 'a': // Print as a memory address.
254 if (MI->getOperand(OpNum).isReg()) {
256 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
261 case 'c': // Don't print "#" before an immediate operand.
262 if (!MI->getOperand(OpNum).isImm())
264 O << MI->getOperand(OpNum).getImm();
266 case 'P': // Print a VFP double precision register.
267 case 'q': // Print a NEON quad precision register.
268 printOperand(MI, OpNum, O);
270 case 'y': // Print a VFP single precision register as indexed double.
271 if (MI->getOperand(OpNum).isReg()) {
272 unsigned Reg = MI->getOperand(OpNum).getReg();
273 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
274 // Find the 'd' register that has this 's' register as a sub-register,
275 // and determine the lane number.
276 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
277 if (!ARM::DPRRegClass.contains(*SR))
279 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
280 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
285 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
286 if (!MI->getOperand(OpNum).isImm())
288 O << ~(MI->getOperand(OpNum).getImm());
290 case 'L': // The low 16 bits of an immediate constant.
291 if (!MI->getOperand(OpNum).isImm())
293 O << (MI->getOperand(OpNum).getImm() & 0xffff);
295 case 'M': { // A register range suitable for LDM/STM.
296 if (!MI->getOperand(OpNum).isReg())
298 const MachineOperand &MO = MI->getOperand(OpNum);
299 unsigned RegBegin = MO.getReg();
300 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
301 // already got the operands in registers that are operands to the
302 // inline asm statement.
304 if (ARM::GPRPairRegClass.contains(RegBegin)) {
305 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
306 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
307 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
308 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
310 O << ARMInstPrinter::getRegisterName(RegBegin);
312 // FIXME: The register allocator not only may not have given us the
313 // registers in sequence, but may not be in ascending registers. This
314 // will require changes in the register allocator that'll need to be
315 // propagated down here if the operands change.
316 unsigned RegOps = OpNum + 1;
317 while (MI->getOperand(RegOps).isReg()) {
319 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
327 case 'R': // The most significant register of a pair.
328 case 'Q': { // The least significant register of a pair.
331 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
332 if (!FlagsOP.isImm())
334 unsigned Flags = FlagsOP.getImm();
336 // This operand may not be the one that actually provides the register. If
337 // it's tied to a previous one then we should refer instead to that one
338 // for registers and their classes.
340 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
341 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
342 unsigned OpFlags = MI->getOperand(OpNum).getImm();
343 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
345 Flags = MI->getOperand(OpNum).getImm();
347 // Later code expects OpNum to be pointing at the register rather than
352 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
354 InlineAsm::hasRegClassConstraint(Flags, RC);
355 if (RC == ARM::GPRPairRegClassID) {
358 const MachineOperand &MO = MI->getOperand(OpNum);
361 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
362 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
363 ARM::gsub_0 : ARM::gsub_1);
364 O << ARMInstPrinter::getRegisterName(Reg);
369 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
370 if (RegOp >= MI->getNumOperands())
372 const MachineOperand &MO = MI->getOperand(RegOp);
375 unsigned Reg = MO.getReg();
376 O << ARMInstPrinter::getRegisterName(Reg);
380 case 'e': // The low doubleword register of a NEON quad register.
381 case 'f': { // The high doubleword register of a NEON quad register.
382 if (!MI->getOperand(OpNum).isReg())
384 unsigned Reg = MI->getOperand(OpNum).getReg();
385 if (!ARM::QPRRegClass.contains(Reg))
387 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
388 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
389 ARM::dsub_0 : ARM::dsub_1);
390 O << ARMInstPrinter::getRegisterName(SubReg);
394 // This modifier is not yet supported.
395 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
397 case 'H': { // The highest-numbered register of a pair.
398 const MachineOperand &MO = MI->getOperand(OpNum);
401 const MachineFunction &MF = *MI->getParent()->getParent();
402 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
403 unsigned Reg = MO.getReg();
404 if(!ARM::GPRPairRegClass.contains(Reg))
406 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
407 O << ARMInstPrinter::getRegisterName(Reg);
413 printOperand(MI, OpNum, O);
417 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
418 unsigned OpNum, unsigned AsmVariant,
419 const char *ExtraCode,
421 // Does this asm operand have a single letter operand modifier?
422 if (ExtraCode && ExtraCode[0]) {
423 if (ExtraCode[1] != 0) return true; // Unknown modifier.
425 switch (ExtraCode[0]) {
426 case 'A': // A memory operand for a VLD1/VST1 instruction.
427 default: return true; // Unknown modifier.
428 case 'm': // The base register of a memory operand.
429 if (!MI->getOperand(OpNum).isReg())
431 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
436 const MachineOperand &MO = MI->getOperand(OpNum);
437 assert(MO.isReg() && "unexpected inline asm memory operand");
438 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
442 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
443 if (Subtarget->isTargetMachO()) {
444 Reloc::Model RelocM = TM.getRelocationModel();
445 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
446 // Declare all the text sections up front (before the DWARF sections
447 // emitted by AsmPrinter::doInitialization) so the assembler will keep
448 // them together at the beginning of the object file. This helps
449 // avoid out-of-range branches that are due a fundamental limitation of
450 // the way symbol offsets are encoded with the current Darwin ARM
452 const TargetLoweringObjectFileMachO &TLOFMacho =
453 static_cast<const TargetLoweringObjectFileMachO &>(
454 getObjFileLowering());
456 // Collect the set of sections our functions will go into.
457 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
458 SmallPtrSet<const MCSection *, 8> > TextSections;
459 // Default text section comes first.
460 TextSections.insert(TLOFMacho.getTextSection());
461 // Now any user defined text sections from function attributes.
462 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
463 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
464 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
465 // Now the coalescable sections.
466 TextSections.insert(TLOFMacho.getTextCoalSection());
467 TextSections.insert(TLOFMacho.getConstTextCoalSection());
469 // Emit the sections in the .s file header to fix the order.
470 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
471 OutStreamer.SwitchSection(TextSections[i]);
473 if (RelocM == Reloc::DynamicNoPIC) {
474 const MCSection *sect =
475 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
476 MCSectionMachO::S_SYMBOL_STUBS,
477 12, SectionKind::getText());
478 OutStreamer.SwitchSection(sect);
480 const MCSection *sect =
481 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
482 MCSectionMachO::S_SYMBOL_STUBS,
483 16, SectionKind::getText());
484 OutStreamer.SwitchSection(sect);
486 const MCSection *StaticInitSect =
487 OutContext.getMachOSection("__TEXT", "__StaticInit",
488 MCSectionMachO::S_REGULAR |
489 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
490 SectionKind::getText());
491 OutStreamer.SwitchSection(StaticInitSect);
494 // Compiling with debug info should not affect the code
495 // generation! Since some of the data sections are first switched
496 // to only in ASMPrinter::doFinalization(), the debug info
497 // sections would come before the data sections in the object
498 // file. This is problematic, since PC-relative loads have to use
499 // different instruction sequences in order to reach global data
500 // in the same object file.
501 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
502 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
503 OutStreamer.SwitchSection(getObjFileLowering().getDataCommonSection());
504 OutStreamer.SwitchSection(getObjFileLowering().getDataBSSSection());
505 OutStreamer.SwitchSection(getObjFileLowering().getNonLazySymbolPointerSection());
508 // Use unified assembler syntax.
509 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
511 // Emit ARM Build Attributes
512 if (Subtarget->isTargetELF())
517 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
518 if (Subtarget->isTargetMachO()) {
519 // All darwin targets use mach-o.
520 const TargetLoweringObjectFileMachO &TLOFMacho =
521 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
522 MachineModuleInfoMachO &MMIMacho =
523 MMI->getObjFileInfo<MachineModuleInfoMachO>();
525 // Output non-lazy-pointers for external and common global variables.
526 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
528 if (!Stubs.empty()) {
529 // Switch with ".non_lazy_symbol_pointer" directive.
530 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
532 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
534 OutStreamer.EmitLabel(Stubs[i].first);
535 // .indirect_symbol _foo
536 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
537 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
540 // External to current translation unit.
541 OutStreamer.EmitIntValue(0, 4/*size*/);
543 // Internal to current translation unit.
545 // When we place the LSDA into the TEXT section, the type info
546 // pointers need to be indirect and pc-rel. We accomplish this by
547 // using NLPs; however, sometimes the types are local to the file.
548 // We need to fill in the value for the NLP in those cases.
549 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
555 OutStreamer.AddBlankLine();
558 Stubs = MMIMacho.GetHiddenGVStubList();
559 if (!Stubs.empty()) {
560 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
562 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
564 OutStreamer.EmitLabel(Stubs[i].first);
566 OutStreamer.EmitValue(MCSymbolRefExpr::
567 Create(Stubs[i].second.getPointer(),
573 OutStreamer.AddBlankLine();
576 // Funny Darwin hack: This flag tells the linker that no global symbols
577 // contain code that falls through to other global symbols (e.g. the obvious
578 // implementation of multiple entry points). If this doesn't occur, the
579 // linker can safely perform dead code stripping. Since LLVM never
580 // generates code that does this, it is always safe to set.
581 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
585 //===----------------------------------------------------------------------===//
586 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
588 // The following seem like one-off assembler flags, but they actually need
589 // to appear in the .ARM.attributes section in ELF.
590 // Instead of subclassing the MCELFStreamer, we do the work here.
592 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
593 const ARMSubtarget *Subtarget) {
595 return ARMBuildAttrs::v5TEJ;
597 if (Subtarget->hasV8Ops())
598 return ARMBuildAttrs::v8;
599 else if (Subtarget->hasV7Ops()) {
600 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
601 return ARMBuildAttrs::v7E_M;
602 return ARMBuildAttrs::v7;
603 } else if (Subtarget->hasV6T2Ops())
604 return ARMBuildAttrs::v6T2;
605 else if (Subtarget->hasV6MOps())
606 return ARMBuildAttrs::v6S_M;
607 else if (Subtarget->hasV6Ops())
608 return ARMBuildAttrs::v6;
609 else if (Subtarget->hasV5TEOps())
610 return ARMBuildAttrs::v5TE;
611 else if (Subtarget->hasV5TOps())
612 return ARMBuildAttrs::v5T;
613 else if (Subtarget->hasV4TOps())
614 return ARMBuildAttrs::v4T;
616 return ARMBuildAttrs::v4;
619 void ARMAsmPrinter::emitAttributes() {
620 MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
621 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
623 ATS.switchVendor("aeabi");
625 std::string CPUString = Subtarget->getCPUString();
627 // FIXME: remove krait check when GNU tools support krait cpu
628 if (CPUString != "generic" && CPUString != "krait")
629 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
631 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
632 getArchForCPU(CPUString, Subtarget));
634 if (Subtarget->isAClass()) {
635 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
636 ARMBuildAttrs::ApplicationProfile);
637 } else if (Subtarget->isRClass()) {
638 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
639 ARMBuildAttrs::RealTimeProfile);
640 } else if (Subtarget->isMClass()){
641 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
642 ARMBuildAttrs::MicroControllerProfile);
645 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
646 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
647 if (Subtarget->isThumb1Only()) {
648 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
649 ARMBuildAttrs::Allowed);
650 } else if (Subtarget->hasThumb2()) {
651 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
652 ARMBuildAttrs::AllowThumb32);
655 if (Subtarget->hasNEON()) {
656 /* NEON is not exactly a VFP architecture, but GAS emit one of
657 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
658 if (Subtarget->hasFPARMv8()) {
659 if (Subtarget->hasCrypto())
660 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
662 ATS.emitFPU(ARM::NEON_FP_ARMV8);
664 else if (Subtarget->hasVFP4())
665 ATS.emitFPU(ARM::NEON_VFPV4);
667 ATS.emitFPU(ARM::NEON);
668 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
669 if (Subtarget->hasV8Ops())
670 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
671 ARMBuildAttrs::AllowNeonARMv8);
673 if (Subtarget->hasFPARMv8())
674 ATS.emitFPU(ARM::FP_ARMV8);
675 else if (Subtarget->hasVFP4())
676 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
677 else if (Subtarget->hasVFP3())
678 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
679 else if (Subtarget->hasVFP2())
680 ATS.emitFPU(ARM::VFPV2);
683 // Signal various FP modes.
684 if (!TM.Options.UnsafeFPMath) {
685 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
686 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
687 ARMBuildAttrs::Allowed);
690 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
691 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
692 ARMBuildAttrs::Allowed);
694 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
695 ARMBuildAttrs::AllowIEE754);
697 // FIXME: add more flags to ARMBuildAttrs.h
698 // 8-bytes alignment stuff.
699 ATS.emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
700 ATS.emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
702 // ABI_HardFP_use attribute to indicate single precision FP.
703 if (Subtarget->isFPOnlySP())
704 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
705 ARMBuildAttrs::HardFPSinglePrecision);
707 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
708 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
709 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
711 // FIXME: Should we signal R9 usage?
713 if (Subtarget->hasFP16())
714 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
716 if (Subtarget->hasMPExtension())
717 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
719 if (Subtarget->hasDivide()) {
720 // Check if hardware divide is only available in thumb2 or ARM as well.
721 ATS.emitAttribute(ARMBuildAttrs::DIV_use,
722 Subtarget->hasDivideInARMMode() ? ARMBuildAttrs::AllowDIVExt :
723 ARMBuildAttrs::AllowDIVIfExists);
726 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
727 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
728 ARMBuildAttrs::AllowTZVirtualization);
729 else if (Subtarget->hasTrustZone())
730 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
731 ARMBuildAttrs::AllowTZ);
732 else if (Subtarget->hasVirtualization())
733 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
734 ARMBuildAttrs::AllowVirtualization);
736 ATS.finishAttributeSection();
739 void ARMAsmPrinter::emitARMAttributeSection() {
741 // [ <section-length> "vendor-name"
742 // [ <file-tag> <size> <attribute>*
743 // | <section-tag> <size> <section-number>* 0 <attribute>*
744 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
748 if (OutStreamer.hasRawTextSupport())
751 const ARMElfTargetObjectFile &TLOFELF =
752 static_cast<const ARMElfTargetObjectFile &>
753 (getObjFileLowering());
755 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
758 OutStreamer.EmitIntValue(0x41, 1);
761 //===----------------------------------------------------------------------===//
763 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
764 unsigned LabelId, MCContext &Ctx) {
766 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
767 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
771 static MCSymbolRefExpr::VariantKind
772 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
774 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
775 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
776 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
777 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
778 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
779 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
781 llvm_unreachable("Invalid ARMCPModifier!");
784 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
785 unsigned char TargetFlags) {
786 bool isIndirect = Subtarget->isTargetMachO() &&
787 (TargetFlags & ARMII::MO_NONLAZY) &&
788 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
790 return getSymbol(GV);
792 // FIXME: Remove this when Darwin transition to @GOT like syntax.
793 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
794 MachineModuleInfoMachO &MMIMachO =
795 MMI->getObjFileInfo<MachineModuleInfoMachO>();
796 MachineModuleInfoImpl::StubValueTy &StubSym =
797 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
798 MMIMachO.getGVStubEntry(MCSym);
799 if (StubSym.getPointer() == 0)
800 StubSym = MachineModuleInfoImpl::
801 StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
806 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
807 const DataLayout *DL = TM.getDataLayout();
808 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
810 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
813 if (ACPV->isLSDA()) {
814 SmallString<128> Str;
815 raw_svector_ostream OS(Str);
816 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
817 MCSym = OutContext.GetOrCreateSymbol(OS.str());
818 } else if (ACPV->isBlockAddress()) {
819 const BlockAddress *BA =
820 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
821 MCSym = GetBlockAddressSymbol(BA);
822 } else if (ACPV->isGlobalValue()) {
823 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
825 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
826 // flag the global as MO_NONLAZY.
827 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
828 MCSym = GetARMGVSymbol(GV, TF);
829 } else if (ACPV->isMachineBasicBlock()) {
830 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
831 MCSym = MBB->getSymbol();
833 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
834 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
835 MCSym = GetExternalSymbolSymbol(Sym);
838 // Create an MCSymbol for the reference.
840 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
843 if (ACPV->getPCAdjustment()) {
844 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
848 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
850 MCBinaryExpr::CreateAdd(PCRelExpr,
851 MCConstantExpr::Create(ACPV->getPCAdjustment(),
854 if (ACPV->mustAddCurrentAddress()) {
855 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
856 // label, so just emit a local label end reference that instead.
857 MCSymbol *DotSym = OutContext.CreateTempSymbol();
858 OutStreamer.EmitLabel(DotSym);
859 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
860 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
862 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
864 OutStreamer.EmitValue(Expr, Size);
867 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
868 unsigned Opcode = MI->getOpcode();
870 if (Opcode == ARM::BR_JTadd)
872 else if (Opcode == ARM::BR_JTm)
875 const MachineOperand &MO1 = MI->getOperand(OpNum);
876 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
877 unsigned JTI = MO1.getIndex();
879 // Emit a label for the jump table.
880 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
881 OutStreamer.EmitLabel(JTISymbol);
883 // Mark the jump table as data-in-code.
884 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
886 // Emit each entry of the table.
887 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
888 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
889 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
891 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
892 MachineBasicBlock *MBB = JTBBs[i];
893 // Construct an MCExpr for the entry. We want a value of the form:
894 // (BasicBlockAddr - TableBeginAddr)
896 // For example, a table with entries jumping to basic blocks BB0 and BB1
899 // .word (LBB0 - LJTI_0_0)
900 // .word (LBB1 - LJTI_0_0)
901 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
903 if (TM.getRelocationModel() == Reloc::PIC_)
904 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
907 // If we're generating a table of Thumb addresses in static relocation
908 // model, we need to add one to keep interworking correctly.
909 else if (AFI->isThumbFunction())
910 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
912 OutStreamer.EmitValue(Expr, 4);
914 // Mark the end of jump table data-in-code region.
915 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
918 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
919 unsigned Opcode = MI->getOpcode();
920 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
921 const MachineOperand &MO1 = MI->getOperand(OpNum);
922 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
923 unsigned JTI = MO1.getIndex();
925 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
926 OutStreamer.EmitLabel(JTISymbol);
928 // Emit each entry of the table.
929 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
930 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
931 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
932 unsigned OffsetWidth = 4;
933 if (MI->getOpcode() == ARM::t2TBB_JT) {
935 // Mark the jump table as data-in-code.
936 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
937 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
939 // Mark the jump table as data-in-code.
940 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
943 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
944 MachineBasicBlock *MBB = JTBBs[i];
945 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
947 // If this isn't a TBB or TBH, the entries are direct branch instructions.
948 if (OffsetWidth == 4) {
949 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
950 .addExpr(MBBSymbolExpr)
955 // Otherwise it's an offset from the dispatch instruction. Construct an
956 // MCExpr for the entry. We want a value of the form:
957 // (BasicBlockAddr - TableBeginAddr) / 2
959 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
962 // .byte (LBB0 - LJTI_0_0) / 2
963 // .byte (LBB1 - LJTI_0_0) / 2
965 MCBinaryExpr::CreateSub(MBBSymbolExpr,
966 MCSymbolRefExpr::Create(JTISymbol, OutContext),
968 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
970 OutStreamer.EmitValue(Expr, OffsetWidth);
972 // Mark the end of jump table data-in-code region. 32-bit offsets use
973 // actual branch instructions here, so we don't mark those as a data-region
975 if (OffsetWidth != 4)
976 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
979 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
980 assert(MI->getFlag(MachineInstr::FrameSetup) &&
981 "Only instruction which are involved into frame setup code are allowed");
983 MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
984 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
985 const MachineFunction &MF = *MI->getParent()->getParent();
986 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
987 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
989 unsigned FramePtr = RegInfo->getFrameRegister(MF);
990 unsigned Opc = MI->getOpcode();
991 unsigned SrcReg, DstReg;
993 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
994 // Two special cases:
995 // 1) tPUSH does not have src/dst regs.
996 // 2) for Thumb1 code we sometimes materialize the constant via constpool
997 // load. Yes, this is pretty fragile, but for now I don't see better
999 SrcReg = DstReg = ARM::SP;
1001 SrcReg = MI->getOperand(1).getReg();
1002 DstReg = MI->getOperand(0).getReg();
1005 // Try to figure out the unwinding opcode out of src / dst regs.
1006 if (MI->mayStore()) {
1008 assert(DstReg == ARM::SP &&
1009 "Only stack pointer as a destination reg is supported");
1011 SmallVector<unsigned, 4> RegList;
1012 // Skip src & dst reg, and pred ops.
1013 unsigned StartOp = 2 + 2;
1014 // Use all the operands.
1015 unsigned NumOffset = 0;
1020 llvm_unreachable("Unsupported opcode for unwinding information");
1022 // Special case here: no src & dst reg, but two extra imp ops.
1023 StartOp = 2; NumOffset = 2;
1024 case ARM::STMDB_UPD:
1025 case ARM::t2STMDB_UPD:
1026 case ARM::VSTMDDB_UPD:
1027 assert(SrcReg == ARM::SP &&
1028 "Only stack pointer as a source reg is supported");
1029 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1031 const MachineOperand &MO = MI->getOperand(i);
1032 // Actually, there should never be any impdef stuff here. Skip it
1033 // temporary to workaround PR11902.
1034 if (MO.isImplicit())
1036 RegList.push_back(MO.getReg());
1039 case ARM::STR_PRE_IMM:
1040 case ARM::STR_PRE_REG:
1041 case ARM::t2STR_PRE:
1042 assert(MI->getOperand(2).getReg() == ARM::SP &&
1043 "Only stack pointer as a source reg is supported");
1044 RegList.push_back(SrcReg);
1047 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1049 // Changes of stack / frame pointer.
1050 if (SrcReg == ARM::SP) {
1055 llvm_unreachable("Unsupported opcode for unwinding information");
1061 Offset = -MI->getOperand(2).getImm();
1065 Offset = MI->getOperand(2).getImm();
1068 Offset = MI->getOperand(2).getImm()*4;
1072 Offset = -MI->getOperand(2).getImm()*4;
1074 case ARM::tLDRpci: {
1075 // Grab the constpool index and check, whether it corresponds to
1076 // original or cloned constpool entry.
1077 unsigned CPI = MI->getOperand(1).getIndex();
1078 const MachineConstantPool *MCP = MF.getConstantPool();
1079 if (CPI >= MCP->getConstants().size())
1080 CPI = AFI.getOriginalCPIdx(CPI);
1081 assert(CPI != -1U && "Invalid constpool index");
1083 // Derive the actual offset.
1084 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1085 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1086 // FIXME: Check for user, it should be "add" instruction!
1087 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1092 if (DstReg == FramePtr && FramePtr != ARM::SP)
1093 // Set-up of the frame pointer. Positive values correspond to "add"
1095 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1096 else if (DstReg == ARM::SP) {
1097 // Change of SP by an offset. Positive values correspond to "sub"
1099 ATS.emitPad(Offset);
1102 llvm_unreachable("Unsupported opcode for unwinding information");
1104 } else if (DstReg == ARM::SP) {
1105 // FIXME: .movsp goes here
1107 llvm_unreachable("Unsupported opcode for unwinding information");
1111 llvm_unreachable("Unsupported opcode for unwinding information");
1116 extern cl::opt<bool> EnableARMEHABI;
1118 // Simple pseudo-instructions have their lowering (with expansion to real
1119 // instructions) auto-generated.
1120 #include "ARMGenMCPseudoLowering.inc"
1122 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1123 const DataLayout *DL = TM.getDataLayout();
1125 // If we just ended a constant pool, mark it as such.
1126 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1127 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1128 InConstantPool = false;
1131 // Emit unwinding stuff for frame-related instructions
1132 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1133 EmitUnwindingInstruction(MI);
1135 // Do any auto-generated pseudo lowerings.
1136 if (emitPseudoExpansionLowering(OutStreamer, MI))
1139 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1140 "Pseudo flag setting opcode should be expanded early");
1142 // Check for manual lowerings.
1143 unsigned Opc = MI->getOpcode();
1145 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1146 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1148 case ARM::tLEApcrel:
1149 case ARM::t2LEApcrel: {
1150 // FIXME: Need to also handle globals and externals
1151 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1152 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1153 ARM::t2LEApcrel ? ARM::t2ADR
1154 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1156 .addReg(MI->getOperand(0).getReg())
1157 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1158 // Add predicate operands.
1159 .addImm(MI->getOperand(2).getImm())
1160 .addReg(MI->getOperand(3).getReg()));
1163 case ARM::LEApcrelJT:
1164 case ARM::tLEApcrelJT:
1165 case ARM::t2LEApcrelJT: {
1166 MCSymbol *JTIPICSymbol =
1167 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1168 MI->getOperand(2).getImm());
1169 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1170 ARM::t2LEApcrelJT ? ARM::t2ADR
1171 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1173 .addReg(MI->getOperand(0).getReg())
1174 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1175 // Add predicate operands.
1176 .addImm(MI->getOperand(3).getImm())
1177 .addReg(MI->getOperand(4).getReg()));
1180 // Darwin call instructions are just normal call instructions with different
1181 // clobber semantics (they clobber R9).
1182 case ARM::BX_CALL: {
1183 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1186 // Add predicate operands.
1189 // Add 's' bit operand (always reg0 for this)
1192 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1193 .addReg(MI->getOperand(0).getReg()));
1196 case ARM::tBX_CALL: {
1197 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1200 // Add predicate operands.
1204 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1205 .addReg(MI->getOperand(0).getReg())
1206 // Add predicate operands.
1211 case ARM::BMOVPCRX_CALL: {
1212 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1215 // Add predicate operands.
1218 // Add 's' bit operand (always reg0 for this)
1221 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1223 .addReg(MI->getOperand(0).getReg())
1224 // Add predicate operands.
1227 // Add 's' bit operand (always reg0 for this)
1231 case ARM::BMOVPCB_CALL: {
1232 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1235 // Add predicate operands.
1238 // Add 's' bit operand (always reg0 for this)
1241 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1242 MCSymbol *GVSym = getSymbol(GV);
1243 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1244 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1246 // Add predicate operands.
1251 case ARM::MOVi16_ga_pcrel:
1252 case ARM::t2MOVi16_ga_pcrel: {
1254 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1255 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1257 unsigned TF = MI->getOperand(1).getTargetFlags();
1258 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1259 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1260 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1262 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1263 getFunctionNumber(),
1264 MI->getOperand(2).getImm(), OutContext);
1265 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1266 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1267 const MCExpr *PCRelExpr =
1268 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1269 MCBinaryExpr::CreateAdd(LabelSymExpr,
1270 MCConstantExpr::Create(PCAdj, OutContext),
1271 OutContext), OutContext), OutContext);
1272 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1274 // Add predicate operands.
1275 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1276 TmpInst.addOperand(MCOperand::CreateReg(0));
1277 // Add 's' bit operand (always reg0 for this)
1278 TmpInst.addOperand(MCOperand::CreateReg(0));
1279 OutStreamer.EmitInstruction(TmpInst);
1282 case ARM::MOVTi16_ga_pcrel:
1283 case ARM::t2MOVTi16_ga_pcrel: {
1285 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1286 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1287 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1288 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1290 unsigned TF = MI->getOperand(2).getTargetFlags();
1291 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1292 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1293 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1295 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1296 getFunctionNumber(),
1297 MI->getOperand(3).getImm(), OutContext);
1298 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1299 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1300 const MCExpr *PCRelExpr =
1301 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1302 MCBinaryExpr::CreateAdd(LabelSymExpr,
1303 MCConstantExpr::Create(PCAdj, OutContext),
1304 OutContext), OutContext), OutContext);
1305 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1306 // Add predicate operands.
1307 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1308 TmpInst.addOperand(MCOperand::CreateReg(0));
1309 // Add 's' bit operand (always reg0 for this)
1310 TmpInst.addOperand(MCOperand::CreateReg(0));
1311 OutStreamer.EmitInstruction(TmpInst);
1314 case ARM::tPICADD: {
1315 // This is a pseudo op for a label + instruction sequence, which looks like:
1318 // This adds the address of LPC0 to r0.
1321 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1322 getFunctionNumber(), MI->getOperand(2).getImm(),
1325 // Form and emit the add.
1326 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1327 .addReg(MI->getOperand(0).getReg())
1328 .addReg(MI->getOperand(0).getReg())
1330 // Add predicate operands.
1336 // This is a pseudo op for a label + instruction sequence, which looks like:
1339 // This adds the address of LPC0 to r0.
1342 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1343 getFunctionNumber(), MI->getOperand(2).getImm(),
1346 // Form and emit the add.
1347 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1348 .addReg(MI->getOperand(0).getReg())
1350 .addReg(MI->getOperand(1).getReg())
1351 // Add predicate operands.
1352 .addImm(MI->getOperand(3).getImm())
1353 .addReg(MI->getOperand(4).getReg())
1354 // Add 's' bit operand (always reg0 for this)
1365 case ARM::PICLDRSH: {
1366 // This is a pseudo op for a label + instruction sequence, which looks like:
1369 // The LCP0 label is referenced by a constant pool entry in order to get
1370 // a PC-relative address at the ldr instruction.
1373 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1374 getFunctionNumber(), MI->getOperand(2).getImm(),
1377 // Form and emit the load
1379 switch (MI->getOpcode()) {
1381 llvm_unreachable("Unexpected opcode!");
1382 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1383 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1384 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1385 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1386 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1387 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1388 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1389 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1391 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1392 .addReg(MI->getOperand(0).getReg())
1394 .addReg(MI->getOperand(1).getReg())
1396 // Add predicate operands.
1397 .addImm(MI->getOperand(3).getImm())
1398 .addReg(MI->getOperand(4).getReg()));
1402 case ARM::CONSTPOOL_ENTRY: {
1403 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1404 /// in the function. The first operand is the ID# for this instruction, the
1405 /// second is the index into the MachineConstantPool that this is, the third
1406 /// is the size in bytes of this constant pool entry.
1407 /// The required alignment is specified on the basic block holding this MI.
1408 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1409 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1411 // If this is the first entry of the pool, mark it.
1412 if (!InConstantPool) {
1413 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1414 InConstantPool = true;
1417 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1419 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1420 if (MCPE.isMachineConstantPoolEntry())
1421 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1423 EmitGlobalConstant(MCPE.Val.ConstVal);
1426 case ARM::t2BR_JT: {
1427 // Lower and emit the instruction itself, then the jump table following it.
1428 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1430 .addReg(MI->getOperand(0).getReg())
1431 // Add predicate operands.
1435 // Output the data for the jump table itself
1439 case ARM::t2TBB_JT: {
1440 // Lower and emit the instruction itself, then the jump table following it.
1441 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1443 .addReg(MI->getOperand(0).getReg())
1444 // Add predicate operands.
1448 // Output the data for the jump table itself
1450 // Make sure the next instruction is 2-byte aligned.
1454 case ARM::t2TBH_JT: {
1455 // Lower and emit the instruction itself, then the jump table following it.
1456 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1458 .addReg(MI->getOperand(0).getReg())
1459 // Add predicate operands.
1463 // Output the data for the jump table itself
1469 // Lower and emit the instruction itself, then the jump table following it.
1472 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1473 ARM::MOVr : ARM::tMOVr;
1474 TmpInst.setOpcode(Opc);
1475 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1476 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1477 // Add predicate operands.
1478 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1479 TmpInst.addOperand(MCOperand::CreateReg(0));
1480 // Add 's' bit operand (always reg0 for this)
1481 if (Opc == ARM::MOVr)
1482 TmpInst.addOperand(MCOperand::CreateReg(0));
1483 OutStreamer.EmitInstruction(TmpInst);
1485 // Make sure the Thumb jump table is 4-byte aligned.
1486 if (Opc == ARM::tMOVr)
1489 // Output the data for the jump table itself
1494 // Lower and emit the instruction itself, then the jump table following it.
1497 if (MI->getOperand(1).getReg() == 0) {
1499 TmpInst.setOpcode(ARM::LDRi12);
1500 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1501 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1502 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1504 TmpInst.setOpcode(ARM::LDRrs);
1505 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1506 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1507 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1508 TmpInst.addOperand(MCOperand::CreateImm(0));
1510 // Add predicate operands.
1511 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1512 TmpInst.addOperand(MCOperand::CreateReg(0));
1513 OutStreamer.EmitInstruction(TmpInst);
1515 // Output the data for the jump table itself
1519 case ARM::BR_JTadd: {
1520 // Lower and emit the instruction itself, then the jump table following it.
1521 // add pc, target, idx
1522 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1524 .addReg(MI->getOperand(0).getReg())
1525 .addReg(MI->getOperand(1).getReg())
1526 // Add predicate operands.
1529 // Add 's' bit operand (always reg0 for this)
1532 // Output the data for the jump table itself
1537 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1538 // FIXME: Remove this special case when they do.
1539 if (!Subtarget->isTargetMachO()) {
1540 //.long 0xe7ffdefe @ trap
1541 uint32_t Val = 0xe7ffdefeUL;
1542 OutStreamer.AddComment("trap");
1543 OutStreamer.EmitIntValue(Val, 4);
1548 case ARM::TRAPNaCl: {
1549 //.long 0xe7fedef0 @ trap
1550 uint32_t Val = 0xe7fedef0UL;
1551 OutStreamer.AddComment("trap");
1552 OutStreamer.EmitIntValue(Val, 4);
1556 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1557 // FIXME: Remove this special case when they do.
1558 if (!Subtarget->isTargetMachO()) {
1559 //.short 57086 @ trap
1560 uint16_t Val = 0xdefe;
1561 OutStreamer.AddComment("trap");
1562 OutStreamer.EmitIntValue(Val, 2);
1567 case ARM::t2Int_eh_sjlj_setjmp:
1568 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1569 case ARM::tInt_eh_sjlj_setjmp: {
1570 // Two incoming args: GPR:$src, GPR:$val
1573 // str $val, [$src, #4]
1578 unsigned SrcReg = MI->getOperand(0).getReg();
1579 unsigned ValReg = MI->getOperand(1).getReg();
1580 MCSymbol *Label = GetARMSJLJEHLabel();
1581 OutStreamer.AddComment("eh_setjmp begin");
1582 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1589 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1599 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1602 // The offset immediate is #4. The operand value is scaled by 4 for the
1603 // tSTR instruction.
1609 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1617 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1618 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1619 .addExpr(SymbolExpr)
1623 OutStreamer.AddComment("eh_setjmp end");
1624 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1632 OutStreamer.EmitLabel(Label);
1636 case ARM::Int_eh_sjlj_setjmp_nofp:
1637 case ARM::Int_eh_sjlj_setjmp: {
1638 // Two incoming args: GPR:$src, GPR:$val
1640 // str $val, [$src, #+4]
1644 unsigned SrcReg = MI->getOperand(0).getReg();
1645 unsigned ValReg = MI->getOperand(1).getReg();
1647 OutStreamer.AddComment("eh_setjmp begin");
1648 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1655 // 's' bit operand (always reg0 for this).
1658 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1666 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1672 // 's' bit operand (always reg0 for this).
1675 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1682 // 's' bit operand (always reg0 for this).
1685 OutStreamer.AddComment("eh_setjmp end");
1686 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1692 // 's' bit operand (always reg0 for this).
1696 case ARM::Int_eh_sjlj_longjmp: {
1697 // ldr sp, [$src, #8]
1698 // ldr $scratch, [$src, #4]
1701 unsigned SrcReg = MI->getOperand(0).getReg();
1702 unsigned ScratchReg = MI->getOperand(1).getReg();
1703 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1711 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1719 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1727 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1734 case ARM::tInt_eh_sjlj_longjmp: {
1735 // ldr $scratch, [$src, #8]
1737 // ldr $scratch, [$src, #4]
1740 unsigned SrcReg = MI->getOperand(0).getReg();
1741 unsigned ScratchReg = MI->getOperand(1).getReg();
1742 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1745 // The offset immediate is #8. The operand value is scaled by 4 for the
1746 // tLDR instruction.
1752 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1759 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1767 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1775 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1785 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1787 OutStreamer.EmitInstruction(TmpInst);
1790 //===----------------------------------------------------------------------===//
1791 // Target Registry Stuff
1792 //===----------------------------------------------------------------------===//
1794 // Force static initialization.
1795 extern "C" void LLVMInitializeARMAsmPrinter() {
1796 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1797 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);