1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMFPUName.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMBuildAttrs.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/ADT/SetVector.h"
28 #include "llvm/ADT/SmallString.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/DebugInfo.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/Mangler.h"
36 #include "llvm/IR/Module.h"
37 #include "llvm/IR/Type.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCAssembler.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCELFStreamer.h"
42 #include "llvm/MC/MCInst.h"
43 #include "llvm/MC/MCInstBuilder.h"
44 #include "llvm/MC/MCObjectStreamer.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/MC/MCStreamer.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 /// EmitDwarfRegOp - Emit dwarf register operation.
59 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
60 bool Indirect) const {
61 const TargetRegisterInfo *RI = TM.getRegisterInfo();
62 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
63 AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
66 assert(MLoc.isReg() && !Indirect &&
67 "This doesn't support offset/indirection - implement it if needed");
68 unsigned Reg = MLoc.getReg();
69 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
70 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
71 // S registers are described as bit-pieces of a register
72 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
73 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
75 unsigned SReg = Reg - ARM::S0;
76 bool odd = SReg & 0x1;
77 unsigned Rx = 256 + (SReg >> 1);
79 OutStreamer.AddComment("DW_OP_regx for S register");
80 EmitInt8(dwarf::DW_OP_regx);
82 OutStreamer.AddComment(Twine(SReg));
86 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
87 EmitInt8(dwarf::DW_OP_bit_piece);
91 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
92 EmitInt8(dwarf::DW_OP_bit_piece);
96 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
97 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
98 // Q registers Q0-Q15 are described by composing two D registers together.
99 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
102 unsigned QReg = Reg - ARM::Q0;
103 unsigned D1 = 256 + 2 * QReg;
104 unsigned D2 = D1 + 1;
106 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
107 EmitInt8(dwarf::DW_OP_regx);
109 OutStreamer.AddComment("DW_OP_piece 8");
110 EmitInt8(dwarf::DW_OP_piece);
113 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
114 EmitInt8(dwarf::DW_OP_regx);
116 OutStreamer.AddComment("DW_OP_piece 8");
117 EmitInt8(dwarf::DW_OP_piece);
122 void ARMAsmPrinter::EmitFunctionBodyEnd() {
123 // Make sure to terminate any constant pools that were at the end
127 InConstantPool = false;
128 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
131 void ARMAsmPrinter::EmitFunctionEntryLabel() {
132 if (AFI->isThumbFunction()) {
133 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
134 OutStreamer.EmitThumbFunc(CurrentFnSym);
137 OutStreamer.EmitLabel(CurrentFnSym);
140 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
141 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
142 assert(Size && "C++ constructor pointer had zero size!");
144 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
145 assert(GV && "C++ constructor pointer was not a GlobalValue!");
147 const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
148 (Subtarget->isTargetELF()
149 ? MCSymbolRefExpr::VK_ARM_TARGET1
150 : MCSymbolRefExpr::VK_None),
153 OutStreamer.EmitValue(E, Size);
156 /// runOnMachineFunction - This uses the EmitInstruction()
157 /// method to print assembly for each instruction.
159 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
160 AFI = MF.getInfo<ARMFunctionInfo>();
161 MCP = MF.getConstantPool();
163 return AsmPrinter::runOnMachineFunction(MF);
166 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
167 raw_ostream &O, const char *Modifier) {
168 const MachineOperand &MO = MI->getOperand(OpNum);
169 unsigned TF = MO.getTargetFlags();
171 switch (MO.getType()) {
172 default: llvm_unreachable("<unknown operand type>");
173 case MachineOperand::MO_Register: {
174 unsigned Reg = MO.getReg();
175 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
176 assert(!MO.getSubReg() && "Subregs should be eliminated!");
177 if(ARM::GPRPairRegClass.contains(Reg)) {
178 const MachineFunction &MF = *MI->getParent()->getParent();
179 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
180 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
182 O << ARMInstPrinter::getRegisterName(Reg);
185 case MachineOperand::MO_Immediate: {
186 int64_t Imm = MO.getImm();
188 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
189 (TF == ARMII::MO_LO16))
191 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
192 (TF == ARMII::MO_HI16))
197 case MachineOperand::MO_MachineBasicBlock:
198 O << *MO.getMBB()->getSymbol();
200 case MachineOperand::MO_GlobalAddress: {
201 const GlobalValue *GV = MO.getGlobal();
202 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
203 (TF & ARMII::MO_LO16))
205 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
206 (TF & ARMII::MO_HI16))
210 printOffset(MO.getOffset(), O);
211 if (TF == ARMII::MO_PLT)
215 case MachineOperand::MO_ConstantPoolIndex:
216 O << *GetCPISymbol(MO.getIndex());
221 //===--------------------------------------------------------------------===//
223 MCSymbol *ARMAsmPrinter::
224 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
225 const DataLayout *DL = TM.getDataLayout();
226 SmallString<60> Name;
227 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
228 << getFunctionNumber() << '_' << uid << '_' << uid2;
229 return OutContext.GetOrCreateSymbol(Name.str());
233 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
234 const DataLayout *DL = TM.getDataLayout();
235 SmallString<60> Name;
236 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
237 << getFunctionNumber();
238 return OutContext.GetOrCreateSymbol(Name.str());
241 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
242 unsigned AsmVariant, const char *ExtraCode,
244 // Does this asm operand have a single letter operand modifier?
245 if (ExtraCode && ExtraCode[0]) {
246 if (ExtraCode[1] != 0) return true; // Unknown modifier.
248 switch (ExtraCode[0]) {
250 // See if this is a generic print operand
251 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
252 case 'a': // Print as a memory address.
253 if (MI->getOperand(OpNum).isReg()) {
255 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
260 case 'c': // Don't print "#" before an immediate operand.
261 if (!MI->getOperand(OpNum).isImm())
263 O << MI->getOperand(OpNum).getImm();
265 case 'P': // Print a VFP double precision register.
266 case 'q': // Print a NEON quad precision register.
267 printOperand(MI, OpNum, O);
269 case 'y': // Print a VFP single precision register as indexed double.
270 if (MI->getOperand(OpNum).isReg()) {
271 unsigned Reg = MI->getOperand(OpNum).getReg();
272 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
273 // Find the 'd' register that has this 's' register as a sub-register,
274 // and determine the lane number.
275 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
276 if (!ARM::DPRRegClass.contains(*SR))
278 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
279 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
284 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
285 if (!MI->getOperand(OpNum).isImm())
287 O << ~(MI->getOperand(OpNum).getImm());
289 case 'L': // The low 16 bits of an immediate constant.
290 if (!MI->getOperand(OpNum).isImm())
292 O << (MI->getOperand(OpNum).getImm() & 0xffff);
294 case 'M': { // A register range suitable for LDM/STM.
295 if (!MI->getOperand(OpNum).isReg())
297 const MachineOperand &MO = MI->getOperand(OpNum);
298 unsigned RegBegin = MO.getReg();
299 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
300 // already got the operands in registers that are operands to the
301 // inline asm statement.
303 if (ARM::GPRPairRegClass.contains(RegBegin)) {
304 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
305 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
306 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
307 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
309 O << ARMInstPrinter::getRegisterName(RegBegin);
311 // FIXME: The register allocator not only may not have given us the
312 // registers in sequence, but may not be in ascending registers. This
313 // will require changes in the register allocator that'll need to be
314 // propagated down here if the operands change.
315 unsigned RegOps = OpNum + 1;
316 while (MI->getOperand(RegOps).isReg()) {
318 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
326 case 'R': // The most significant register of a pair.
327 case 'Q': { // The least significant register of a pair.
330 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
331 if (!FlagsOP.isImm())
333 unsigned Flags = FlagsOP.getImm();
335 // This operand may not be the one that actually provides the register. If
336 // it's tied to a previous one then we should refer instead to that one
337 // for registers and their classes.
339 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
340 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
341 unsigned OpFlags = MI->getOperand(OpNum).getImm();
342 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
344 Flags = MI->getOperand(OpNum).getImm();
346 // Later code expects OpNum to be pointing at the register rather than
351 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
353 InlineAsm::hasRegClassConstraint(Flags, RC);
354 if (RC == ARM::GPRPairRegClassID) {
357 const MachineOperand &MO = MI->getOperand(OpNum);
360 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
361 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
362 ARM::gsub_0 : ARM::gsub_1);
363 O << ARMInstPrinter::getRegisterName(Reg);
368 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
369 if (RegOp >= MI->getNumOperands())
371 const MachineOperand &MO = MI->getOperand(RegOp);
374 unsigned Reg = MO.getReg();
375 O << ARMInstPrinter::getRegisterName(Reg);
379 case 'e': // The low doubleword register of a NEON quad register.
380 case 'f': { // The high doubleword register of a NEON quad register.
381 if (!MI->getOperand(OpNum).isReg())
383 unsigned Reg = MI->getOperand(OpNum).getReg();
384 if (!ARM::QPRRegClass.contains(Reg))
386 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
387 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
388 ARM::dsub_0 : ARM::dsub_1);
389 O << ARMInstPrinter::getRegisterName(SubReg);
393 // This modifier is not yet supported.
394 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
396 case 'H': { // The highest-numbered register of a pair.
397 const MachineOperand &MO = MI->getOperand(OpNum);
400 const MachineFunction &MF = *MI->getParent()->getParent();
401 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
402 unsigned Reg = MO.getReg();
403 if(!ARM::GPRPairRegClass.contains(Reg))
405 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
406 O << ARMInstPrinter::getRegisterName(Reg);
412 printOperand(MI, OpNum, O);
416 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
417 unsigned OpNum, unsigned AsmVariant,
418 const char *ExtraCode,
420 // Does this asm operand have a single letter operand modifier?
421 if (ExtraCode && ExtraCode[0]) {
422 if (ExtraCode[1] != 0) return true; // Unknown modifier.
424 switch (ExtraCode[0]) {
425 case 'A': // A memory operand for a VLD1/VST1 instruction.
426 default: return true; // Unknown modifier.
427 case 'm': // The base register of a memory operand.
428 if (!MI->getOperand(OpNum).isReg())
430 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
435 const MachineOperand &MO = MI->getOperand(OpNum);
436 assert(MO.isReg() && "unexpected inline asm memory operand");
437 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
441 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
442 if (Subtarget->isTargetMachO()) {
443 Reloc::Model RelocM = TM.getRelocationModel();
444 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
445 // Declare all the text sections up front (before the DWARF sections
446 // emitted by AsmPrinter::doInitialization) so the assembler will keep
447 // them together at the beginning of the object file. This helps
448 // avoid out-of-range branches that are due a fundamental limitation of
449 // the way symbol offsets are encoded with the current Darwin ARM
451 const TargetLoweringObjectFileMachO &TLOFMacho =
452 static_cast<const TargetLoweringObjectFileMachO &>(
453 getObjFileLowering());
455 // Collect the set of sections our functions will go into.
456 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
457 SmallPtrSet<const MCSection *, 8> > TextSections;
458 // Default text section comes first.
459 TextSections.insert(TLOFMacho.getTextSection());
460 // Now any user defined text sections from function attributes.
461 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
462 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
463 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
464 // Now the coalescable sections.
465 TextSections.insert(TLOFMacho.getTextCoalSection());
466 TextSections.insert(TLOFMacho.getConstTextCoalSection());
468 // Emit the sections in the .s file header to fix the order.
469 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
470 OutStreamer.SwitchSection(TextSections[i]);
472 if (RelocM == Reloc::DynamicNoPIC) {
473 const MCSection *sect =
474 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
475 MCSectionMachO::S_SYMBOL_STUBS,
476 12, SectionKind::getText());
477 OutStreamer.SwitchSection(sect);
479 const MCSection *sect =
480 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
481 MCSectionMachO::S_SYMBOL_STUBS,
482 16, SectionKind::getText());
483 OutStreamer.SwitchSection(sect);
485 const MCSection *StaticInitSect =
486 OutContext.getMachOSection("__TEXT", "__StaticInit",
487 MCSectionMachO::S_REGULAR |
488 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
489 SectionKind::getText());
490 OutStreamer.SwitchSection(StaticInitSect);
493 // Compiling with debug info should not affect the code
494 // generation! Since some of the data sections are first switched
495 // to only in ASMPrinter::doFinalization(), the debug info
496 // sections would come before the data sections in the object
497 // file. This is problematic, since PC-relative loads have to use
498 // different instruction sequences in order to reach global data
499 // in the same object file.
500 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
501 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
502 OutStreamer.SwitchSection(getObjFileLowering().getDataCommonSection());
503 OutStreamer.SwitchSection(getObjFileLowering().getDataBSSSection());
504 OutStreamer.SwitchSection(getObjFileLowering().getNonLazySymbolPointerSection());
507 // Use unified assembler syntax.
508 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
510 // Emit ARM Build Attributes
511 if (Subtarget->isTargetELF())
516 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
517 if (Subtarget->isTargetMachO()) {
518 // All darwin targets use mach-o.
519 const TargetLoweringObjectFileMachO &TLOFMacho =
520 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
521 MachineModuleInfoMachO &MMIMacho =
522 MMI->getObjFileInfo<MachineModuleInfoMachO>();
524 // Output non-lazy-pointers for external and common global variables.
525 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
527 if (!Stubs.empty()) {
528 // Switch with ".non_lazy_symbol_pointer" directive.
529 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
531 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
533 OutStreamer.EmitLabel(Stubs[i].first);
534 // .indirect_symbol _foo
535 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
536 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
539 // External to current translation unit.
540 OutStreamer.EmitIntValue(0, 4/*size*/);
542 // Internal to current translation unit.
544 // When we place the LSDA into the TEXT section, the type info
545 // pointers need to be indirect and pc-rel. We accomplish this by
546 // using NLPs; however, sometimes the types are local to the file.
547 // We need to fill in the value for the NLP in those cases.
548 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
554 OutStreamer.AddBlankLine();
557 Stubs = MMIMacho.GetHiddenGVStubList();
558 if (!Stubs.empty()) {
559 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
561 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
563 OutStreamer.EmitLabel(Stubs[i].first);
565 OutStreamer.EmitValue(MCSymbolRefExpr::
566 Create(Stubs[i].second.getPointer(),
572 OutStreamer.AddBlankLine();
575 // Funny Darwin hack: This flag tells the linker that no global symbols
576 // contain code that falls through to other global symbols (e.g. the obvious
577 // implementation of multiple entry points). If this doesn't occur, the
578 // linker can safely perform dead code stripping. Since LLVM never
579 // generates code that does this, it is always safe to set.
580 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
584 //===----------------------------------------------------------------------===//
585 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
587 // The following seem like one-off assembler flags, but they actually need
588 // to appear in the .ARM.attributes section in ELF.
589 // Instead of subclassing the MCELFStreamer, we do the work here.
591 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
592 const ARMSubtarget *Subtarget) {
594 return ARMBuildAttrs::v5TEJ;
596 if (Subtarget->hasV8Ops())
597 return ARMBuildAttrs::v8;
598 else if (Subtarget->hasV7Ops()) {
599 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
600 return ARMBuildAttrs::v7E_M;
601 return ARMBuildAttrs::v7;
602 } else if (Subtarget->hasV6T2Ops())
603 return ARMBuildAttrs::v6T2;
604 else if (Subtarget->hasV6MOps())
605 return ARMBuildAttrs::v6S_M;
606 else if (Subtarget->hasV6Ops())
607 return ARMBuildAttrs::v6;
608 else if (Subtarget->hasV5TEOps())
609 return ARMBuildAttrs::v5TE;
610 else if (Subtarget->hasV5TOps())
611 return ARMBuildAttrs::v5T;
612 else if (Subtarget->hasV4TOps())
613 return ARMBuildAttrs::v4T;
615 return ARMBuildAttrs::v4;
618 void ARMAsmPrinter::emitAttributes() {
619 MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
620 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
622 ATS.switchVendor("aeabi");
624 std::string CPUString = Subtarget->getCPUString();
626 // FIXME: remove krait check when GNU tools support krait cpu
627 if (CPUString != "generic" && CPUString != "krait")
628 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
630 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
631 getArchForCPU(CPUString, Subtarget));
633 if (Subtarget->isAClass()) {
634 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
635 ARMBuildAttrs::ApplicationProfile);
636 } else if (Subtarget->isRClass()) {
637 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
638 ARMBuildAttrs::RealTimeProfile);
639 } else if (Subtarget->isMClass()){
640 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
641 ARMBuildAttrs::MicroControllerProfile);
644 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
645 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
646 if (Subtarget->isThumb1Only()) {
647 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
648 ARMBuildAttrs::Allowed);
649 } else if (Subtarget->hasThumb2()) {
650 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
651 ARMBuildAttrs::AllowThumb32);
654 if (Subtarget->hasNEON()) {
655 /* NEON is not exactly a VFP architecture, but GAS emit one of
656 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
657 if (Subtarget->hasFPARMv8()) {
658 if (Subtarget->hasCrypto())
659 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
661 ATS.emitFPU(ARM::NEON_FP_ARMV8);
663 else if (Subtarget->hasVFP4())
664 ATS.emitFPU(ARM::NEON_VFPV4);
666 ATS.emitFPU(ARM::NEON);
667 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
668 if (Subtarget->hasV8Ops())
669 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
670 ARMBuildAttrs::AllowNeonARMv8);
672 if (Subtarget->hasFPARMv8())
673 ATS.emitFPU(ARM::FP_ARMV8);
674 else if (Subtarget->hasVFP4())
675 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
676 else if (Subtarget->hasVFP3())
677 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
678 else if (Subtarget->hasVFP2())
679 ATS.emitFPU(ARM::VFPV2);
682 // Signal various FP modes.
683 if (!TM.Options.UnsafeFPMath) {
684 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
685 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
686 ARMBuildAttrs::Allowed);
689 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
690 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
691 ARMBuildAttrs::Allowed);
693 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
694 ARMBuildAttrs::AllowIEE754);
696 // FIXME: add more flags to ARMBuildAttrs.h
697 // 8-bytes alignment stuff.
698 ATS.emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
699 ATS.emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
701 // ABI_HardFP_use attribute to indicate single precision FP.
702 if (Subtarget->isFPOnlySP())
703 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
704 ARMBuildAttrs::HardFPSinglePrecision);
706 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
707 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
708 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
710 // FIXME: Should we signal R9 usage?
712 if (Subtarget->hasFP16())
713 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
715 if (Subtarget->hasMPExtension())
716 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
718 if (Subtarget->hasDivide()) {
719 // Check if hardware divide is only available in thumb2 or ARM as well.
720 ATS.emitAttribute(ARMBuildAttrs::DIV_use,
721 Subtarget->hasDivideInARMMode() ? ARMBuildAttrs::AllowDIVExt :
722 ARMBuildAttrs::AllowDIVIfExists);
725 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
726 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
727 ARMBuildAttrs::AllowTZVirtualization);
728 else if (Subtarget->hasTrustZone())
729 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
730 ARMBuildAttrs::AllowTZ);
731 else if (Subtarget->hasVirtualization())
732 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
733 ARMBuildAttrs::AllowVirtualization);
735 ATS.finishAttributeSection();
738 void ARMAsmPrinter::emitARMAttributeSection() {
740 // [ <section-length> "vendor-name"
741 // [ <file-tag> <size> <attribute>*
742 // | <section-tag> <size> <section-number>* 0 <attribute>*
743 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
747 if (OutStreamer.hasRawTextSupport())
750 const ARMElfTargetObjectFile &TLOFELF =
751 static_cast<const ARMElfTargetObjectFile &>
752 (getObjFileLowering());
754 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
757 OutStreamer.EmitIntValue(0x41, 1);
760 //===----------------------------------------------------------------------===//
762 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
763 unsigned LabelId, MCContext &Ctx) {
765 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
766 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
770 static MCSymbolRefExpr::VariantKind
771 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
773 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
774 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
775 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
776 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
777 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
778 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
780 llvm_unreachable("Invalid ARMCPModifier!");
783 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
784 unsigned char TargetFlags) {
785 bool isIndirect = Subtarget->isTargetMachO() &&
786 (TargetFlags & ARMII::MO_NONLAZY) &&
787 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
789 return getSymbol(GV);
791 // FIXME: Remove this when Darwin transition to @GOT like syntax.
792 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
793 MachineModuleInfoMachO &MMIMachO =
794 MMI->getObjFileInfo<MachineModuleInfoMachO>();
795 MachineModuleInfoImpl::StubValueTy &StubSym =
796 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
797 MMIMachO.getGVStubEntry(MCSym);
798 if (StubSym.getPointer() == 0)
799 StubSym = MachineModuleInfoImpl::
800 StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
805 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
806 const DataLayout *DL = TM.getDataLayout();
807 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
809 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
812 if (ACPV->isLSDA()) {
813 SmallString<128> Str;
814 raw_svector_ostream OS(Str);
815 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
816 MCSym = OutContext.GetOrCreateSymbol(OS.str());
817 } else if (ACPV->isBlockAddress()) {
818 const BlockAddress *BA =
819 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
820 MCSym = GetBlockAddressSymbol(BA);
821 } else if (ACPV->isGlobalValue()) {
822 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
824 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
825 // flag the global as MO_NONLAZY.
826 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
827 MCSym = GetARMGVSymbol(GV, TF);
828 } else if (ACPV->isMachineBasicBlock()) {
829 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
830 MCSym = MBB->getSymbol();
832 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
833 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
834 MCSym = GetExternalSymbolSymbol(Sym);
837 // Create an MCSymbol for the reference.
839 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
842 if (ACPV->getPCAdjustment()) {
843 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
847 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
849 MCBinaryExpr::CreateAdd(PCRelExpr,
850 MCConstantExpr::Create(ACPV->getPCAdjustment(),
853 if (ACPV->mustAddCurrentAddress()) {
854 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
855 // label, so just emit a local label end reference that instead.
856 MCSymbol *DotSym = OutContext.CreateTempSymbol();
857 OutStreamer.EmitLabel(DotSym);
858 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
859 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
861 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
863 OutStreamer.EmitValue(Expr, Size);
866 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
867 unsigned Opcode = MI->getOpcode();
869 if (Opcode == ARM::BR_JTadd)
871 else if (Opcode == ARM::BR_JTm)
874 const MachineOperand &MO1 = MI->getOperand(OpNum);
875 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
876 unsigned JTI = MO1.getIndex();
878 // Emit a label for the jump table.
879 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
880 OutStreamer.EmitLabel(JTISymbol);
882 // Mark the jump table as data-in-code.
883 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
885 // Emit each entry of the table.
886 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
887 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
888 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
890 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
891 MachineBasicBlock *MBB = JTBBs[i];
892 // Construct an MCExpr for the entry. We want a value of the form:
893 // (BasicBlockAddr - TableBeginAddr)
895 // For example, a table with entries jumping to basic blocks BB0 and BB1
898 // .word (LBB0 - LJTI_0_0)
899 // .word (LBB1 - LJTI_0_0)
900 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
902 if (TM.getRelocationModel() == Reloc::PIC_)
903 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
906 // If we're generating a table of Thumb addresses in static relocation
907 // model, we need to add one to keep interworking correctly.
908 else if (AFI->isThumbFunction())
909 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
911 OutStreamer.EmitValue(Expr, 4);
913 // Mark the end of jump table data-in-code region.
914 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
917 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
918 unsigned Opcode = MI->getOpcode();
919 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
920 const MachineOperand &MO1 = MI->getOperand(OpNum);
921 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
922 unsigned JTI = MO1.getIndex();
924 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
925 OutStreamer.EmitLabel(JTISymbol);
927 // Emit each entry of the table.
928 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
929 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
930 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
931 unsigned OffsetWidth = 4;
932 if (MI->getOpcode() == ARM::t2TBB_JT) {
934 // Mark the jump table as data-in-code.
935 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
936 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
938 // Mark the jump table as data-in-code.
939 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
942 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
943 MachineBasicBlock *MBB = JTBBs[i];
944 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
946 // If this isn't a TBB or TBH, the entries are direct branch instructions.
947 if (OffsetWidth == 4) {
948 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
949 .addExpr(MBBSymbolExpr)
954 // Otherwise it's an offset from the dispatch instruction. Construct an
955 // MCExpr for the entry. We want a value of the form:
956 // (BasicBlockAddr - TableBeginAddr) / 2
958 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
961 // .byte (LBB0 - LJTI_0_0) / 2
962 // .byte (LBB1 - LJTI_0_0) / 2
964 MCBinaryExpr::CreateSub(MBBSymbolExpr,
965 MCSymbolRefExpr::Create(JTISymbol, OutContext),
967 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
969 OutStreamer.EmitValue(Expr, OffsetWidth);
971 // Mark the end of jump table data-in-code region. 32-bit offsets use
972 // actual branch instructions here, so we don't mark those as a data-region
974 if (OffsetWidth != 4)
975 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
978 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
979 assert(MI->getFlag(MachineInstr::FrameSetup) &&
980 "Only instruction which are involved into frame setup code are allowed");
982 MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
983 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
984 const MachineFunction &MF = *MI->getParent()->getParent();
985 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
986 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
988 unsigned FramePtr = RegInfo->getFrameRegister(MF);
989 unsigned Opc = MI->getOpcode();
990 unsigned SrcReg, DstReg;
992 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
993 // Two special cases:
994 // 1) tPUSH does not have src/dst regs.
995 // 2) for Thumb1 code we sometimes materialize the constant via constpool
996 // load. Yes, this is pretty fragile, but for now I don't see better
998 SrcReg = DstReg = ARM::SP;
1000 SrcReg = MI->getOperand(1).getReg();
1001 DstReg = MI->getOperand(0).getReg();
1004 // Try to figure out the unwinding opcode out of src / dst regs.
1005 if (MI->mayStore()) {
1007 assert(DstReg == ARM::SP &&
1008 "Only stack pointer as a destination reg is supported");
1010 SmallVector<unsigned, 4> RegList;
1011 // Skip src & dst reg, and pred ops.
1012 unsigned StartOp = 2 + 2;
1013 // Use all the operands.
1014 unsigned NumOffset = 0;
1019 llvm_unreachable("Unsupported opcode for unwinding information");
1021 // Special case here: no src & dst reg, but two extra imp ops.
1022 StartOp = 2; NumOffset = 2;
1023 case ARM::STMDB_UPD:
1024 case ARM::t2STMDB_UPD:
1025 case ARM::VSTMDDB_UPD:
1026 assert(SrcReg == ARM::SP &&
1027 "Only stack pointer as a source reg is supported");
1028 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1030 const MachineOperand &MO = MI->getOperand(i);
1031 // Actually, there should never be any impdef stuff here. Skip it
1032 // temporary to workaround PR11902.
1033 if (MO.isImplicit())
1035 RegList.push_back(MO.getReg());
1038 case ARM::STR_PRE_IMM:
1039 case ARM::STR_PRE_REG:
1040 case ARM::t2STR_PRE:
1041 assert(MI->getOperand(2).getReg() == ARM::SP &&
1042 "Only stack pointer as a source reg is supported");
1043 RegList.push_back(SrcReg);
1046 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1048 // Changes of stack / frame pointer.
1049 if (SrcReg == ARM::SP) {
1054 llvm_unreachable("Unsupported opcode for unwinding information");
1060 Offset = -MI->getOperand(2).getImm();
1064 Offset = MI->getOperand(2).getImm();
1067 Offset = MI->getOperand(2).getImm()*4;
1071 Offset = -MI->getOperand(2).getImm()*4;
1073 case ARM::tLDRpci: {
1074 // Grab the constpool index and check, whether it corresponds to
1075 // original or cloned constpool entry.
1076 unsigned CPI = MI->getOperand(1).getIndex();
1077 const MachineConstantPool *MCP = MF.getConstantPool();
1078 if (CPI >= MCP->getConstants().size())
1079 CPI = AFI.getOriginalCPIdx(CPI);
1080 assert(CPI != -1U && "Invalid constpool index");
1082 // Derive the actual offset.
1083 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1084 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1085 // FIXME: Check for user, it should be "add" instruction!
1086 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1091 if (DstReg == FramePtr && FramePtr != ARM::SP)
1092 // Set-up of the frame pointer. Positive values correspond to "add"
1094 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1095 else if (DstReg == ARM::SP) {
1096 // Change of SP by an offset. Positive values correspond to "sub"
1098 ATS.emitPad(Offset);
1101 llvm_unreachable("Unsupported opcode for unwinding information");
1103 } else if (DstReg == ARM::SP) {
1104 // FIXME: .movsp goes here
1106 llvm_unreachable("Unsupported opcode for unwinding information");
1110 llvm_unreachable("Unsupported opcode for unwinding information");
1115 extern cl::opt<bool> EnableARMEHABI;
1117 // Simple pseudo-instructions have their lowering (with expansion to real
1118 // instructions) auto-generated.
1119 #include "ARMGenMCPseudoLowering.inc"
1121 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1122 const DataLayout *DL = TM.getDataLayout();
1124 // If we just ended a constant pool, mark it as such.
1125 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1126 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1127 InConstantPool = false;
1130 // Emit unwinding stuff for frame-related instructions
1131 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1132 EmitUnwindingInstruction(MI);
1134 // Do any auto-generated pseudo lowerings.
1135 if (emitPseudoExpansionLowering(OutStreamer, MI))
1138 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1139 "Pseudo flag setting opcode should be expanded early");
1141 // Check for manual lowerings.
1142 unsigned Opc = MI->getOpcode();
1144 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1145 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1147 case ARM::tLEApcrel:
1148 case ARM::t2LEApcrel: {
1149 // FIXME: Need to also handle globals and externals
1150 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1151 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1152 ARM::t2LEApcrel ? ARM::t2ADR
1153 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1155 .addReg(MI->getOperand(0).getReg())
1156 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1157 // Add predicate operands.
1158 .addImm(MI->getOperand(2).getImm())
1159 .addReg(MI->getOperand(3).getReg()));
1162 case ARM::LEApcrelJT:
1163 case ARM::tLEApcrelJT:
1164 case ARM::t2LEApcrelJT: {
1165 MCSymbol *JTIPICSymbol =
1166 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1167 MI->getOperand(2).getImm());
1168 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1169 ARM::t2LEApcrelJT ? ARM::t2ADR
1170 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1172 .addReg(MI->getOperand(0).getReg())
1173 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1174 // Add predicate operands.
1175 .addImm(MI->getOperand(3).getImm())
1176 .addReg(MI->getOperand(4).getReg()));
1179 // Darwin call instructions are just normal call instructions with different
1180 // clobber semantics (they clobber R9).
1181 case ARM::BX_CALL: {
1182 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1185 // Add predicate operands.
1188 // Add 's' bit operand (always reg0 for this)
1191 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1192 .addReg(MI->getOperand(0).getReg()));
1195 case ARM::tBX_CALL: {
1196 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1199 // Add predicate operands.
1203 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1204 .addReg(MI->getOperand(0).getReg())
1205 // Add predicate operands.
1210 case ARM::BMOVPCRX_CALL: {
1211 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1214 // Add predicate operands.
1217 // Add 's' bit operand (always reg0 for this)
1220 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1222 .addReg(MI->getOperand(0).getReg())
1223 // Add predicate operands.
1226 // Add 's' bit operand (always reg0 for this)
1230 case ARM::BMOVPCB_CALL: {
1231 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1234 // Add predicate operands.
1237 // Add 's' bit operand (always reg0 for this)
1240 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1241 MCSymbol *GVSym = getSymbol(GV);
1242 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1243 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1245 // Add predicate operands.
1250 case ARM::MOVi16_ga_pcrel:
1251 case ARM::t2MOVi16_ga_pcrel: {
1253 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1254 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1256 unsigned TF = MI->getOperand(1).getTargetFlags();
1257 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1258 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1259 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1261 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1262 getFunctionNumber(),
1263 MI->getOperand(2).getImm(), OutContext);
1264 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1265 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1266 const MCExpr *PCRelExpr =
1267 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1268 MCBinaryExpr::CreateAdd(LabelSymExpr,
1269 MCConstantExpr::Create(PCAdj, OutContext),
1270 OutContext), OutContext), OutContext);
1271 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1273 // Add predicate operands.
1274 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1275 TmpInst.addOperand(MCOperand::CreateReg(0));
1276 // Add 's' bit operand (always reg0 for this)
1277 TmpInst.addOperand(MCOperand::CreateReg(0));
1278 OutStreamer.EmitInstruction(TmpInst);
1281 case ARM::MOVTi16_ga_pcrel:
1282 case ARM::t2MOVTi16_ga_pcrel: {
1284 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1285 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1286 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1287 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1289 unsigned TF = MI->getOperand(2).getTargetFlags();
1290 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1291 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1292 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1294 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1295 getFunctionNumber(),
1296 MI->getOperand(3).getImm(), OutContext);
1297 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1298 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1299 const MCExpr *PCRelExpr =
1300 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1301 MCBinaryExpr::CreateAdd(LabelSymExpr,
1302 MCConstantExpr::Create(PCAdj, OutContext),
1303 OutContext), OutContext), OutContext);
1304 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1305 // Add predicate operands.
1306 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1307 TmpInst.addOperand(MCOperand::CreateReg(0));
1308 // Add 's' bit operand (always reg0 for this)
1309 TmpInst.addOperand(MCOperand::CreateReg(0));
1310 OutStreamer.EmitInstruction(TmpInst);
1313 case ARM::tPICADD: {
1314 // This is a pseudo op for a label + instruction sequence, which looks like:
1317 // This adds the address of LPC0 to r0.
1320 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1321 getFunctionNumber(), MI->getOperand(2).getImm(),
1324 // Form and emit the add.
1325 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1326 .addReg(MI->getOperand(0).getReg())
1327 .addReg(MI->getOperand(0).getReg())
1329 // Add predicate operands.
1335 // This is a pseudo op for a label + instruction sequence, which looks like:
1338 // This adds the address of LPC0 to r0.
1341 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1342 getFunctionNumber(), MI->getOperand(2).getImm(),
1345 // Form and emit the add.
1346 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1347 .addReg(MI->getOperand(0).getReg())
1349 .addReg(MI->getOperand(1).getReg())
1350 // Add predicate operands.
1351 .addImm(MI->getOperand(3).getImm())
1352 .addReg(MI->getOperand(4).getReg())
1353 // Add 's' bit operand (always reg0 for this)
1364 case ARM::PICLDRSH: {
1365 // This is a pseudo op for a label + instruction sequence, which looks like:
1368 // The LCP0 label is referenced by a constant pool entry in order to get
1369 // a PC-relative address at the ldr instruction.
1372 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1373 getFunctionNumber(), MI->getOperand(2).getImm(),
1376 // Form and emit the load
1378 switch (MI->getOpcode()) {
1380 llvm_unreachable("Unexpected opcode!");
1381 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1382 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1383 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1384 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1385 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1386 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1387 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1388 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1390 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1391 .addReg(MI->getOperand(0).getReg())
1393 .addReg(MI->getOperand(1).getReg())
1395 // Add predicate operands.
1396 .addImm(MI->getOperand(3).getImm())
1397 .addReg(MI->getOperand(4).getReg()));
1401 case ARM::CONSTPOOL_ENTRY: {
1402 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1403 /// in the function. The first operand is the ID# for this instruction, the
1404 /// second is the index into the MachineConstantPool that this is, the third
1405 /// is the size in bytes of this constant pool entry.
1406 /// The required alignment is specified on the basic block holding this MI.
1407 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1408 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1410 // If this is the first entry of the pool, mark it.
1411 if (!InConstantPool) {
1412 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1413 InConstantPool = true;
1416 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1418 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1419 if (MCPE.isMachineConstantPoolEntry())
1420 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1422 EmitGlobalConstant(MCPE.Val.ConstVal);
1425 case ARM::t2BR_JT: {
1426 // Lower and emit the instruction itself, then the jump table following it.
1427 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1429 .addReg(MI->getOperand(0).getReg())
1430 // Add predicate operands.
1434 // Output the data for the jump table itself
1438 case ARM::t2TBB_JT: {
1439 // Lower and emit the instruction itself, then the jump table following it.
1440 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1442 .addReg(MI->getOperand(0).getReg())
1443 // Add predicate operands.
1447 // Output the data for the jump table itself
1449 // Make sure the next instruction is 2-byte aligned.
1453 case ARM::t2TBH_JT: {
1454 // Lower and emit the instruction itself, then the jump table following it.
1455 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1457 .addReg(MI->getOperand(0).getReg())
1458 // Add predicate operands.
1462 // Output the data for the jump table itself
1468 // Lower and emit the instruction itself, then the jump table following it.
1471 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1472 ARM::MOVr : ARM::tMOVr;
1473 TmpInst.setOpcode(Opc);
1474 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1475 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1476 // Add predicate operands.
1477 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1478 TmpInst.addOperand(MCOperand::CreateReg(0));
1479 // Add 's' bit operand (always reg0 for this)
1480 if (Opc == ARM::MOVr)
1481 TmpInst.addOperand(MCOperand::CreateReg(0));
1482 OutStreamer.EmitInstruction(TmpInst);
1484 // Make sure the Thumb jump table is 4-byte aligned.
1485 if (Opc == ARM::tMOVr)
1488 // Output the data for the jump table itself
1493 // Lower and emit the instruction itself, then the jump table following it.
1496 if (MI->getOperand(1).getReg() == 0) {
1498 TmpInst.setOpcode(ARM::LDRi12);
1499 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1500 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1501 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1503 TmpInst.setOpcode(ARM::LDRrs);
1504 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1505 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1506 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1507 TmpInst.addOperand(MCOperand::CreateImm(0));
1509 // Add predicate operands.
1510 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1511 TmpInst.addOperand(MCOperand::CreateReg(0));
1512 OutStreamer.EmitInstruction(TmpInst);
1514 // Output the data for the jump table itself
1518 case ARM::BR_JTadd: {
1519 // Lower and emit the instruction itself, then the jump table following it.
1520 // add pc, target, idx
1521 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1523 .addReg(MI->getOperand(0).getReg())
1524 .addReg(MI->getOperand(1).getReg())
1525 // Add predicate operands.
1528 // Add 's' bit operand (always reg0 for this)
1531 // Output the data for the jump table itself
1536 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1537 // FIXME: Remove this special case when they do.
1538 if (!Subtarget->isTargetMachO()) {
1539 //.long 0xe7ffdefe @ trap
1540 uint32_t Val = 0xe7ffdefeUL;
1541 OutStreamer.AddComment("trap");
1542 OutStreamer.EmitIntValue(Val, 4);
1547 case ARM::TRAPNaCl: {
1548 //.long 0xe7fedef0 @ trap
1549 uint32_t Val = 0xe7fedef0UL;
1550 OutStreamer.AddComment("trap");
1551 OutStreamer.EmitIntValue(Val, 4);
1555 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1556 // FIXME: Remove this special case when they do.
1557 if (!Subtarget->isTargetMachO()) {
1558 //.short 57086 @ trap
1559 uint16_t Val = 0xdefe;
1560 OutStreamer.AddComment("trap");
1561 OutStreamer.EmitIntValue(Val, 2);
1566 case ARM::t2Int_eh_sjlj_setjmp:
1567 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1568 case ARM::tInt_eh_sjlj_setjmp: {
1569 // Two incoming args: GPR:$src, GPR:$val
1572 // str $val, [$src, #4]
1577 unsigned SrcReg = MI->getOperand(0).getReg();
1578 unsigned ValReg = MI->getOperand(1).getReg();
1579 MCSymbol *Label = GetARMSJLJEHLabel();
1580 OutStreamer.AddComment("eh_setjmp begin");
1581 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1588 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1598 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1601 // The offset immediate is #4. The operand value is scaled by 4 for the
1602 // tSTR instruction.
1608 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1616 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1617 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1618 .addExpr(SymbolExpr)
1622 OutStreamer.AddComment("eh_setjmp end");
1623 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1631 OutStreamer.EmitLabel(Label);
1635 case ARM::Int_eh_sjlj_setjmp_nofp:
1636 case ARM::Int_eh_sjlj_setjmp: {
1637 // Two incoming args: GPR:$src, GPR:$val
1639 // str $val, [$src, #+4]
1643 unsigned SrcReg = MI->getOperand(0).getReg();
1644 unsigned ValReg = MI->getOperand(1).getReg();
1646 OutStreamer.AddComment("eh_setjmp begin");
1647 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1654 // 's' bit operand (always reg0 for this).
1657 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1665 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1671 // 's' bit operand (always reg0 for this).
1674 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1681 // 's' bit operand (always reg0 for this).
1684 OutStreamer.AddComment("eh_setjmp end");
1685 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1691 // 's' bit operand (always reg0 for this).
1695 case ARM::Int_eh_sjlj_longjmp: {
1696 // ldr sp, [$src, #8]
1697 // ldr $scratch, [$src, #4]
1700 unsigned SrcReg = MI->getOperand(0).getReg();
1701 unsigned ScratchReg = MI->getOperand(1).getReg();
1702 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1710 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1718 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1726 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1733 case ARM::tInt_eh_sjlj_longjmp: {
1734 // ldr $scratch, [$src, #8]
1736 // ldr $scratch, [$src, #4]
1739 unsigned SrcReg = MI->getOperand(0).getReg();
1740 unsigned ScratchReg = MI->getOperand(1).getReg();
1741 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1744 // The offset immediate is #8. The operand value is scaled by 4 for the
1745 // tLDR instruction.
1751 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1758 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1766 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1774 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1784 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1786 OutStreamer.EmitInstruction(TmpInst);
1789 //===----------------------------------------------------------------------===//
1790 // Target Registry Stuff
1791 //===----------------------------------------------------------------------===//
1793 // Force static initialization.
1794 extern "C" void LLVMInitializeARMAsmPrinter() {
1795 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1796 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);