1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMBuildAttrs.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMConstantPoolValue.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMMCExpr.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "InstPrinter/ARMInstPrinter.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Target/TargetRegistry.h"
49 #include "llvm/ADT/SmallPtrSet.h"
50 #include "llvm/ADT/SmallString.h"
51 #include "llvm/ADT/StringExtras.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 MCObjectStreamer &Streamer;
104 StringRef CurrentVendor;
105 SmallString<64> Contents;
108 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
109 Streamer(Streamer_), CurrentVendor("") { }
111 void MaybeSwitchVendor(StringRef Vendor) {
112 assert(!Vendor.empty() && "Vendor cannot be empty.");
114 if (CurrentVendor.empty())
115 CurrentVendor = Vendor;
116 else if (CurrentVendor == Vendor)
121 CurrentVendor = Vendor;
123 assert(Contents.size() == 0);
126 void EmitAttribute(unsigned Attribute, unsigned Value) {
127 // FIXME: should be ULEB
128 Contents += Attribute;
132 void EmitTextAttribute(unsigned Attribute, StringRef String) {
133 Contents += Attribute;
134 Contents += UppercaseString(String);
139 const size_t ContentsSize = Contents.size();
141 // Vendor size + Vendor name + '\0'
142 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
145 const size_t TagHeaderSize = 1 + 4;
147 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
148 Streamer.EmitBytes(CurrentVendor, 0);
149 Streamer.EmitIntValue(0, 1); // '\0'
151 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
152 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
154 Streamer.EmitBytes(Contents, 0);
160 } // end of anonymous namespace
162 MachineLocation ARMAsmPrinter::
163 getDebugValueLocation(const MachineInstr *MI) const {
164 MachineLocation Location;
165 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
166 // Frame address. Currently handles register +- offset only.
167 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
168 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
170 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
175 /// getDwarfRegOpSize - get size required to emit given machine location using
177 unsigned ARMAsmPrinter::getDwarfRegOpSize(const MachineLocation &MLoc) const {
178 const TargetRegisterInfo *RI = TM.getRegisterInfo();
179 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
180 return AsmPrinter::getDwarfRegOpSize(MLoc);
182 unsigned Reg = MLoc.getReg();
183 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
184 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
185 // S registers are described as bit-pieces of a register
186 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
187 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
189 unsigned SReg = Reg - ARM::S0;
190 unsigned Rx = 256 + (SReg >> 1);
191 // DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB
192 // 1 + ULEB(Rx) + 1 + 1 + 1
193 return 4 + MCAsmInfo::getULEB128Size(Rx);
196 if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
197 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
198 // Q registers Q0-Q15 are described by composing two D registers together.
199 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
201 unsigned QReg = Reg - ARM::Q0;
202 unsigned D1 = 256 + 2 * QReg;
203 unsigned D2 = D1 + 1;
205 // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) +
206 // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8);
207 // 6 + ULEB(D1) + ULEB(D2)
208 return 6 + MCAsmInfo::getULEB128Size(D1) + MCAsmInfo::getULEB128Size(D2);
214 /// EmitDwarfRegOp - Emit dwarf register operation.
215 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
216 const TargetRegisterInfo *RI = TM.getRegisterInfo();
217 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
218 AsmPrinter::EmitDwarfRegOp(MLoc);
220 unsigned Reg = MLoc.getReg();
221 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
222 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
223 // S registers are described as bit-pieces of a register
224 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
225 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
227 unsigned SReg = Reg - ARM::S0;
228 bool odd = SReg & 0x1;
229 unsigned Rx = 256 + (SReg >> 1);
231 OutStreamer.AddComment("DW_OP_regx for S register");
232 EmitInt8(dwarf::DW_OP_regx);
234 OutStreamer.AddComment(Twine(SReg));
238 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
239 EmitInt8(dwarf::DW_OP_bit_piece);
243 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
244 EmitInt8(dwarf::DW_OP_bit_piece);
248 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
249 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
250 // Q registers Q0-Q15 are described by composing two D registers together.
251 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
253 unsigned QReg = Reg - ARM::Q0;
254 unsigned D1 = 256 + 2 * QReg;
255 unsigned D2 = D1 + 1;
257 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
258 EmitInt8(dwarf::DW_OP_regx);
260 OutStreamer.AddComment("DW_OP_piece 8");
261 EmitInt8(dwarf::DW_OP_piece);
264 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
265 EmitInt8(dwarf::DW_OP_regx);
267 OutStreamer.AddComment("DW_OP_piece 8");
268 EmitInt8(dwarf::DW_OP_piece);
274 void ARMAsmPrinter::EmitFunctionEntryLabel() {
275 if (AFI->isThumbFunction()) {
276 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
277 OutStreamer.EmitThumbFunc(CurrentFnSym);
280 OutStreamer.EmitLabel(CurrentFnSym);
283 /// runOnMachineFunction - This uses the EmitInstruction()
284 /// method to print assembly for each instruction.
286 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
287 AFI = MF.getInfo<ARMFunctionInfo>();
288 MCP = MF.getConstantPool();
290 return AsmPrinter::runOnMachineFunction(MF);
293 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
294 raw_ostream &O, const char *Modifier) {
295 const MachineOperand &MO = MI->getOperand(OpNum);
296 unsigned TF = MO.getTargetFlags();
298 switch (MO.getType()) {
300 assert(0 && "<unknown operand type>");
301 case MachineOperand::MO_Register: {
302 unsigned Reg = MO.getReg();
303 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
304 assert(!MO.getSubReg() && "Subregs should be eliminated!");
305 O << ARMInstPrinter::getRegisterName(Reg);
308 case MachineOperand::MO_Immediate: {
309 int64_t Imm = MO.getImm();
311 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
312 (TF == ARMII::MO_LO16))
314 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
315 (TF == ARMII::MO_HI16))
320 case MachineOperand::MO_MachineBasicBlock:
321 O << *MO.getMBB()->getSymbol();
323 case MachineOperand::MO_GlobalAddress: {
324 const GlobalValue *GV = MO.getGlobal();
325 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
326 (TF & ARMII::MO_LO16))
328 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
329 (TF & ARMII::MO_HI16))
331 O << *Mang->getSymbol(GV);
333 printOffset(MO.getOffset(), O);
334 if (TF == ARMII::MO_PLT)
338 case MachineOperand::MO_ExternalSymbol: {
339 O << *GetExternalSymbolSymbol(MO.getSymbolName());
340 if (TF == ARMII::MO_PLT)
344 case MachineOperand::MO_ConstantPoolIndex:
345 O << *GetCPISymbol(MO.getIndex());
347 case MachineOperand::MO_JumpTableIndex:
348 O << *GetJTISymbol(MO.getIndex());
353 //===--------------------------------------------------------------------===//
355 MCSymbol *ARMAsmPrinter::
356 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
357 const MachineBasicBlock *MBB) const {
358 SmallString<60> Name;
359 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
360 << getFunctionNumber() << '_' << uid << '_' << uid2
361 << "_set_" << MBB->getNumber();
362 return OutContext.GetOrCreateSymbol(Name.str());
365 MCSymbol *ARMAsmPrinter::
366 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
367 SmallString<60> Name;
368 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
369 << getFunctionNumber() << '_' << uid << '_' << uid2;
370 return OutContext.GetOrCreateSymbol(Name.str());
374 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
375 SmallString<60> Name;
376 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
377 << getFunctionNumber();
378 return OutContext.GetOrCreateSymbol(Name.str());
381 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
382 unsigned AsmVariant, const char *ExtraCode,
384 // Does this asm operand have a single letter operand modifier?
385 if (ExtraCode && ExtraCode[0]) {
386 if (ExtraCode[1] != 0) return true; // Unknown modifier.
388 switch (ExtraCode[0]) {
389 default: return true; // Unknown modifier.
390 case 'a': // Print as a memory address.
391 if (MI->getOperand(OpNum).isReg()) {
393 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
398 case 'c': // Don't print "#" before an immediate operand.
399 if (!MI->getOperand(OpNum).isImm())
401 O << MI->getOperand(OpNum).getImm();
403 case 'P': // Print a VFP double precision register.
404 case 'q': // Print a NEON quad precision register.
405 printOperand(MI, OpNum, O);
407 case 'y': // Print a VFP single precision register as indexed double.
408 // This uses the ordering of the alias table to get the first 'd' register
409 // that overlaps the 's' register. Also, s0 is an odd register, hence the
410 // odd modulus check below.
411 if (MI->getOperand(OpNum).isReg()) {
412 unsigned Reg = MI->getOperand(OpNum).getReg();
413 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
414 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
415 (((Reg % 2) == 1) ? "[0]" : "[1]");
419 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
420 if (!MI->getOperand(OpNum).isImm())
422 O << ~(MI->getOperand(OpNum).getImm());
424 case 'L': // The low 16 bits of an immediate constant.
425 if (!MI->getOperand(OpNum).isImm())
427 O << (MI->getOperand(OpNum).getImm() & 0xffff);
429 case 'm': // The base register of a memory operand.
430 case 'M': // A register range suitable for LDM/STM.
431 case 'p': // The high single-precision register of a VFP double-precision
433 case 'e': // The low doubleword register of a NEON quad register.
434 case 'f': // The high doubleword register of a NEON quad register.
435 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
436 case 'A': // A memory operand for a VLD1/VST1 instruction.
437 case 'Q': // The least significant register of a pair.
438 case 'R': // The most significant register of a pair.
439 case 'H': // The highest-numbered register of a pair.
440 // These modifiers are not yet supported.
445 printOperand(MI, OpNum, O);
449 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
450 unsigned OpNum, unsigned AsmVariant,
451 const char *ExtraCode,
453 if (ExtraCode && ExtraCode[0])
454 return true; // Unknown modifier.
456 const MachineOperand &MO = MI->getOperand(OpNum);
457 assert(MO.isReg() && "unexpected inline asm memory operand");
458 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
462 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
463 if (Subtarget->isTargetDarwin()) {
464 Reloc::Model RelocM = TM.getRelocationModel();
465 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
466 // Declare all the text sections up front (before the DWARF sections
467 // emitted by AsmPrinter::doInitialization) so the assembler will keep
468 // them together at the beginning of the object file. This helps
469 // avoid out-of-range branches that are due a fundamental limitation of
470 // the way symbol offsets are encoded with the current Darwin ARM
472 const TargetLoweringObjectFileMachO &TLOFMacho =
473 static_cast<const TargetLoweringObjectFileMachO &>(
474 getObjFileLowering());
475 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
476 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
477 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
478 if (RelocM == Reloc::DynamicNoPIC) {
479 const MCSection *sect =
480 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
481 MCSectionMachO::S_SYMBOL_STUBS,
482 12, SectionKind::getText());
483 OutStreamer.SwitchSection(sect);
485 const MCSection *sect =
486 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
487 MCSectionMachO::S_SYMBOL_STUBS,
488 16, SectionKind::getText());
489 OutStreamer.SwitchSection(sect);
491 const MCSection *StaticInitSect =
492 OutContext.getMachOSection("__TEXT", "__StaticInit",
493 MCSectionMachO::S_REGULAR |
494 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
495 SectionKind::getText());
496 OutStreamer.SwitchSection(StaticInitSect);
500 // Use unified assembler syntax.
501 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
503 // Emit ARM Build Attributes
504 if (Subtarget->isTargetELF()) {
511 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
512 if (Subtarget->isTargetDarwin()) {
513 // All darwin targets use mach-o.
514 const TargetLoweringObjectFileMachO &TLOFMacho =
515 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
516 MachineModuleInfoMachO &MMIMacho =
517 MMI->getObjFileInfo<MachineModuleInfoMachO>();
519 // Output non-lazy-pointers for external and common global variables.
520 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
522 if (!Stubs.empty()) {
523 // Switch with ".non_lazy_symbol_pointer" directive.
524 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
526 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
528 OutStreamer.EmitLabel(Stubs[i].first);
529 // .indirect_symbol _foo
530 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
531 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
534 // External to current translation unit.
535 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
537 // Internal to current translation unit.
539 // When we place the LSDA into the TEXT section, the type info
540 // pointers need to be indirect and pc-rel. We accomplish this by
541 // using NLPs; however, sometimes the types are local to the file.
542 // We need to fill in the value for the NLP in those cases.
543 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
545 4/*size*/, 0/*addrspace*/);
549 OutStreamer.AddBlankLine();
552 Stubs = MMIMacho.GetHiddenGVStubList();
553 if (!Stubs.empty()) {
554 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
556 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
558 OutStreamer.EmitLabel(Stubs[i].first);
560 OutStreamer.EmitValue(MCSymbolRefExpr::
561 Create(Stubs[i].second.getPointer(),
563 4/*size*/, 0/*addrspace*/);
567 OutStreamer.AddBlankLine();
570 // Funny Darwin hack: This flag tells the linker that no global symbols
571 // contain code that falls through to other global symbols (e.g. the obvious
572 // implementation of multiple entry points). If this doesn't occur, the
573 // linker can safely perform dead code stripping. Since LLVM never
574 // generates code that does this, it is always safe to set.
575 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
579 //===----------------------------------------------------------------------===//
580 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
582 // The following seem like one-off assembler flags, but they actually need
583 // to appear in the .ARM.attributes section in ELF.
584 // Instead of subclassing the MCELFStreamer, we do the work here.
586 void ARMAsmPrinter::emitAttributes() {
588 emitARMAttributeSection();
590 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
591 bool emitFPU = false;
592 AttributeEmitter *AttrEmitter;
593 if (OutStreamer.hasRawTextSupport()) {
594 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
597 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
598 AttrEmitter = new ObjectAttributeEmitter(O);
601 AttrEmitter->MaybeSwitchVendor("aeabi");
603 std::string CPUString = Subtarget->getCPUString();
605 if (CPUString == "cortex-a8" ||
606 Subtarget->isCortexA8()) {
607 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
608 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
609 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
610 ARMBuildAttrs::ApplicationProfile);
611 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
612 ARMBuildAttrs::Allowed);
613 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
614 ARMBuildAttrs::AllowThumb32);
615 // Fixme: figure out when this is emitted.
616 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
617 // ARMBuildAttrs::AllowWMMXv1);
620 /// ADD additional Else-cases here!
621 } else if (CPUString == "xscale") {
622 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
623 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
624 ARMBuildAttrs::Allowed);
625 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
626 ARMBuildAttrs::Allowed);
627 } else if (CPUString == "generic") {
628 // FIXME: Why these defaults?
629 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
630 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
631 ARMBuildAttrs::Allowed);
632 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
633 ARMBuildAttrs::Allowed);
636 if (Subtarget->hasNEON() && emitFPU) {
637 /* NEON is not exactly a VFP architecture, but GAS emit one of
638 * neon/vfpv3/vfpv2 for .fpu parameters */
639 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
640 /* If emitted for NEON, omit from VFP below, since you can have both
641 * NEON and VFP in build attributes but only one .fpu */
646 if (Subtarget->hasVFP3()) {
647 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
648 ARMBuildAttrs::AllowFPv3A);
650 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
653 } else if (Subtarget->hasVFP2()) {
654 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
655 ARMBuildAttrs::AllowFPv2);
657 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
660 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
661 * since NEON can have 1 (allowed) or 2 (fused MAC operations) */
662 if (Subtarget->hasNEON()) {
663 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
664 ARMBuildAttrs::Allowed);
667 // Signal various FP modes.
669 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
670 ARMBuildAttrs::Allowed);
671 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
672 ARMBuildAttrs::Allowed);
675 if (NoInfsFPMath && NoNaNsFPMath)
676 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
677 ARMBuildAttrs::Allowed);
679 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
680 ARMBuildAttrs::AllowIEE754);
682 // FIXME: add more flags to ARMBuildAttrs.h
683 // 8-bytes alignment stuff.
684 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
685 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
687 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
688 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
689 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
690 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
692 // FIXME: Should we signal R9 usage?
694 if (Subtarget->hasDivide())
695 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
697 AttrEmitter->Finish();
701 void ARMAsmPrinter::emitARMAttributeSection() {
703 // [ <section-length> "vendor-name"
704 // [ <file-tag> <size> <attribute>*
705 // | <section-tag> <size> <section-number>* 0 <attribute>*
706 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
710 if (OutStreamer.hasRawTextSupport())
713 const ARMElfTargetObjectFile &TLOFELF =
714 static_cast<const ARMElfTargetObjectFile &>
715 (getObjFileLowering());
717 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
720 OutStreamer.EmitIntValue(0x41, 1);
723 //===----------------------------------------------------------------------===//
725 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
726 unsigned LabelId, MCContext &Ctx) {
728 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
729 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
733 static MCSymbolRefExpr::VariantKind
734 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
736 default: llvm_unreachable("Unknown modifier!");
737 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
738 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
739 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
740 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
741 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
742 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
744 return MCSymbolRefExpr::VK_None;
747 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
748 bool isIndirect = Subtarget->isTargetDarwin() &&
749 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
751 return Mang->getSymbol(GV);
753 // FIXME: Remove this when Darwin transition to @GOT like syntax.
754 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
755 MachineModuleInfoMachO &MMIMachO =
756 MMI->getObjFileInfo<MachineModuleInfoMachO>();
757 MachineModuleInfoImpl::StubValueTy &StubSym =
758 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
759 MMIMachO.getGVStubEntry(MCSym);
760 if (StubSym.getPointer() == 0)
761 StubSym = MachineModuleInfoImpl::
762 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
767 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
768 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
770 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
773 if (ACPV->isLSDA()) {
774 SmallString<128> Str;
775 raw_svector_ostream OS(Str);
776 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
777 MCSym = OutContext.GetOrCreateSymbol(OS.str());
778 } else if (ACPV->isBlockAddress()) {
779 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
780 } else if (ACPV->isGlobalValue()) {
781 const GlobalValue *GV = ACPV->getGV();
782 MCSym = GetARMGVSymbol(GV);
784 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
785 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
788 // Create an MCSymbol for the reference.
790 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
793 if (ACPV->getPCAdjustment()) {
794 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
798 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
800 MCBinaryExpr::CreateAdd(PCRelExpr,
801 MCConstantExpr::Create(ACPV->getPCAdjustment(),
804 if (ACPV->mustAddCurrentAddress()) {
805 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
806 // label, so just emit a local label end reference that instead.
807 MCSymbol *DotSym = OutContext.CreateTempSymbol();
808 OutStreamer.EmitLabel(DotSym);
809 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
810 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
812 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
814 OutStreamer.EmitValue(Expr, Size);
817 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
818 unsigned Opcode = MI->getOpcode();
820 if (Opcode == ARM::BR_JTadd)
822 else if (Opcode == ARM::BR_JTm)
825 const MachineOperand &MO1 = MI->getOperand(OpNum);
826 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
827 unsigned JTI = MO1.getIndex();
829 // Emit a label for the jump table.
830 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
831 OutStreamer.EmitLabel(JTISymbol);
833 // Emit each entry of the table.
834 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
835 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
836 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
838 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
839 MachineBasicBlock *MBB = JTBBs[i];
840 // Construct an MCExpr for the entry. We want a value of the form:
841 // (BasicBlockAddr - TableBeginAddr)
843 // For example, a table with entries jumping to basic blocks BB0 and BB1
846 // .word (LBB0 - LJTI_0_0)
847 // .word (LBB1 - LJTI_0_0)
848 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
850 if (TM.getRelocationModel() == Reloc::PIC_)
851 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
854 OutStreamer.EmitValue(Expr, 4);
858 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
859 unsigned Opcode = MI->getOpcode();
860 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
861 const MachineOperand &MO1 = MI->getOperand(OpNum);
862 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
863 unsigned JTI = MO1.getIndex();
865 // Emit a label for the jump table.
866 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
867 OutStreamer.EmitLabel(JTISymbol);
869 // Emit each entry of the table.
870 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
871 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
872 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
873 unsigned OffsetWidth = 4;
874 if (MI->getOpcode() == ARM::t2TBB_JT)
876 else if (MI->getOpcode() == ARM::t2TBH_JT)
879 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
880 MachineBasicBlock *MBB = JTBBs[i];
881 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
883 // If this isn't a TBB or TBH, the entries are direct branch instructions.
884 if (OffsetWidth == 4) {
886 BrInst.setOpcode(ARM::t2B);
887 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
888 OutStreamer.EmitInstruction(BrInst);
891 // Otherwise it's an offset from the dispatch instruction. Construct an
892 // MCExpr for the entry. We want a value of the form:
893 // (BasicBlockAddr - TableBeginAddr) / 2
895 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
898 // .byte (LBB0 - LJTI_0_0) / 2
899 // .byte (LBB1 - LJTI_0_0) / 2
901 MCBinaryExpr::CreateSub(MBBSymbolExpr,
902 MCSymbolRefExpr::Create(JTISymbol, OutContext),
904 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
906 OutStreamer.EmitValue(Expr, OffsetWidth);
910 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
912 unsigned NOps = MI->getNumOperands();
914 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
915 // cast away const; DIetc do not take const operands for some reason.
916 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
919 // Frame address. Currently handles register +- offset only.
920 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
921 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
924 printOperand(MI, NOps-2, OS);
927 static void populateADROperands(MCInst &Inst, unsigned Dest,
928 const MCSymbol *Label,
929 unsigned pred, unsigned ccreg,
931 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
932 Inst.addOperand(MCOperand::CreateReg(Dest));
933 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
934 // Add predicate operands.
935 Inst.addOperand(MCOperand::CreateImm(pred));
936 Inst.addOperand(MCOperand::CreateReg(ccreg));
939 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
943 // Emit the instruction as usual, just patch the opcode.
944 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
945 TmpInst.setOpcode(Opcode);
946 OutStreamer.EmitInstruction(TmpInst);
949 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
950 assert(MI->getFlag(MachineInstr::FrameSetup) &&
951 "Only instruction which are involved into frame setup code are allowed");
953 const MachineFunction &MF = *MI->getParent()->getParent();
954 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
955 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
957 unsigned FramePtr = RegInfo->getFrameRegister(MF);
958 unsigned Opc = MI->getOpcode();
959 unsigned SrcReg, DstReg;
961 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
962 // Two special cases:
963 // 1) tPUSH does not have src/dst regs.
964 // 2) for Thumb1 code we sometimes materialize the constant via constpool
965 // load. Yes, this is pretty fragile, but for now I don't see better
967 SrcReg = DstReg = ARM::SP;
969 SrcReg = MI->getOperand(1).getReg();
970 DstReg = MI->getOperand(0).getReg();
973 // Try to figure out the unwinding opcode out of src / dst regs.
974 if (MI->getDesc().mayStore()) {
976 assert(DstReg == ARM::SP &&
977 "Only stack pointer as a destination reg is supported");
979 SmallVector<unsigned, 4> RegList;
980 // Skip src & dst reg, and pred ops.
981 unsigned StartOp = 2 + 2;
982 // Use all the operands.
983 unsigned NumOffset = 0;
988 assert(0 && "Unsupported opcode for unwinding information");
990 // Special case here: no src & dst reg, but two extra imp ops.
991 StartOp = 2; NumOffset = 2;
993 case ARM::t2STMDB_UPD:
994 case ARM::VSTMDDB_UPD:
995 assert(SrcReg == ARM::SP &&
996 "Only stack pointer as a source reg is supported");
997 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
999 RegList.push_back(MI->getOperand(i).getReg());
1002 assert(MI->getOperand(2).getReg() == ARM::SP &&
1003 "Only stack pointer as a source reg is supported");
1004 RegList.push_back(SrcReg);
1007 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1009 // Changes of stack / frame pointer.
1010 if (SrcReg == ARM::SP) {
1015 assert(0 && "Unsupported opcode for unwinding information");
1017 case ARM::tMOVgpr2gpr:
1018 case ARM::tMOVgpr2tgpr:
1022 Offset = -MI->getOperand(2).getImm();
1025 case ARM::t2SUBrSPi:
1026 Offset = MI->getOperand(2).getImm();
1029 Offset = MI->getOperand(2).getImm()*4;
1033 Offset = -MI->getOperand(2).getImm()*4;
1035 case ARM::tLDRpci: {
1036 // Grab the constpool index and check, whether it corresponds to
1037 // original or cloned constpool entry.
1038 unsigned CPI = MI->getOperand(1).getIndex();
1039 const MachineConstantPool *MCP = MF.getConstantPool();
1040 if (CPI >= MCP->getConstants().size())
1041 CPI = AFI.getOriginalCPIdx(CPI);
1042 assert(CPI != -1U && "Invalid constpool index");
1044 // Derive the actual offset.
1045 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1046 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1047 // FIXME: Check for user, it should be "add" instruction!
1048 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1053 if (DstReg == FramePtr && FramePtr != ARM::SP)
1054 // Set-up of the frame pointer. Positive values correspond to "add"
1056 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1057 else if (DstReg == ARM::SP) {
1058 // Change of SP by an offset. Positive values correspond to "sub"
1060 OutStreamer.EmitPad(Offset);
1063 assert(0 && "Unsupported opcode for unwinding information");
1065 } else if (DstReg == ARM::SP) {
1066 // FIXME: .movsp goes here
1068 assert(0 && "Unsupported opcode for unwinding information");
1072 assert(0 && "Unsupported opcode for unwinding information");
1077 extern cl::opt<bool> EnableARMEHABI;
1079 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1080 unsigned Opc = MI->getOpcode();
1084 // B is just a Bcc with an 'always' predicate.
1086 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1087 TmpInst.setOpcode(ARM::Bcc);
1088 // Add predicate operands.
1089 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1090 TmpInst.addOperand(MCOperand::CreateReg(0));
1091 OutStreamer.EmitInstruction(TmpInst);
1094 case ARM::LDMIA_RET: {
1095 // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
1096 // such has additional code-gen properties and scheduling information.
1097 // To emit it, we just construct as normal and set the opcode to LDMIA_UPD.
1099 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1100 TmpInst.setOpcode(ARM::LDMIA_UPD);
1101 OutStreamer.EmitInstruction(TmpInst);
1104 case ARM::t2ADDrSPi:
1105 case ARM::t2ADDrSPi12:
1106 case ARM::t2SUBrSPi:
1107 case ARM::t2SUBrSPi12:
1108 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
1109 "Unexpected source register!");
1112 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1113 case ARM::DBG_VALUE: {
1114 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1115 SmallString<128> TmpStr;
1116 raw_svector_ostream OS(TmpStr);
1117 PrintDebugValueComment(MI, OS);
1118 OutStreamer.EmitRawText(StringRef(OS.str()));
1124 TmpInst.setOpcode(ARM::tBL);
1125 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
1126 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
1127 OutStreamer.EmitInstruction(TmpInst);
1131 case ARM::tLEApcrel:
1132 case ARM::t2LEApcrel: {
1133 // FIXME: Need to also handle globals and externals
1135 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1136 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1138 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1139 GetCPISymbol(MI->getOperand(1).getIndex()),
1140 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1142 OutStreamer.EmitInstruction(TmpInst);
1145 case ARM::LEApcrelJT:
1146 case ARM::tLEApcrelJT:
1147 case ARM::t2LEApcrelJT: {
1149 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1150 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1152 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1153 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1154 MI->getOperand(2).getImm()),
1155 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1157 OutStreamer.EmitInstruction(TmpInst);
1160 case ARM::MOVPCRX: {
1162 TmpInst.setOpcode(ARM::MOVr);
1163 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1164 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1165 // Add predicate operands.
1166 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1167 TmpInst.addOperand(MCOperand::CreateReg(0));
1168 // Add 's' bit operand (always reg0 for this)
1169 TmpInst.addOperand(MCOperand::CreateReg(0));
1170 OutStreamer.EmitInstruction(TmpInst);
1173 // Darwin call instructions are just normal call instructions with different
1174 // clobber semantics (they clobber R9).
1176 case ARM::BLr9_pred:
1178 case ARM::BLXr9_pred: {
1182 case ARM::BLr9: newOpc = ARM::BL; break;
1183 case ARM::BLr9_pred: newOpc = ARM::BL_pred; break;
1184 case ARM::BLXr9: newOpc = ARM::BLX; break;
1185 case ARM::BLXr9_pred: newOpc = ARM::BLX_pred; break;
1188 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1189 TmpInst.setOpcode(newOpc);
1190 OutStreamer.EmitInstruction(TmpInst);
1193 case ARM::BXr9_CALL:
1194 case ARM::BX_CALL: {
1197 TmpInst.setOpcode(ARM::MOVr);
1198 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1199 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1200 // Add predicate operands.
1201 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1202 TmpInst.addOperand(MCOperand::CreateReg(0));
1203 // Add 's' bit operand (always reg0 for this)
1204 TmpInst.addOperand(MCOperand::CreateReg(0));
1205 OutStreamer.EmitInstruction(TmpInst);
1209 TmpInst.setOpcode(ARM::BX);
1210 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1211 OutStreamer.EmitInstruction(TmpInst);
1215 case ARM::BMOVPCRXr9_CALL:
1216 case ARM::BMOVPCRX_CALL: {
1219 TmpInst.setOpcode(ARM::MOVr);
1220 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1221 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1222 // Add predicate operands.
1223 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1224 TmpInst.addOperand(MCOperand::CreateReg(0));
1225 // Add 's' bit operand (always reg0 for this)
1226 TmpInst.addOperand(MCOperand::CreateReg(0));
1227 OutStreamer.EmitInstruction(TmpInst);
1231 TmpInst.setOpcode(ARM::MOVr);
1232 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1233 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1234 // Add predicate operands.
1235 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1236 TmpInst.addOperand(MCOperand::CreateReg(0));
1237 // Add 's' bit operand (always reg0 for this)
1238 TmpInst.addOperand(MCOperand::CreateReg(0));
1239 OutStreamer.EmitInstruction(TmpInst);
1243 case ARM::MOVi16_ga_pcrel:
1244 case ARM::t2MOVi16_ga_pcrel: {
1246 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1247 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1249 unsigned TF = MI->getOperand(1).getTargetFlags();
1250 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1251 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1252 MCSymbol *GVSym = GetARMGVSymbol(GV);
1253 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1255 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1256 getFunctionNumber(),
1257 MI->getOperand(2).getImm(), OutContext);
1258 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1259 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1260 const MCExpr *PCRelExpr =
1261 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1262 MCBinaryExpr::CreateAdd(LabelSymExpr,
1263 MCConstantExpr::Create(PCAdj, OutContext),
1264 OutContext), OutContext), OutContext);
1265 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1267 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1268 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1271 // Add predicate operands.
1272 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1273 TmpInst.addOperand(MCOperand::CreateReg(0));
1274 // Add 's' bit operand (always reg0 for this)
1275 TmpInst.addOperand(MCOperand::CreateReg(0));
1276 OutStreamer.EmitInstruction(TmpInst);
1279 case ARM::MOVTi16_ga_pcrel:
1280 case ARM::t2MOVTi16_ga_pcrel: {
1282 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1283 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1284 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1285 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1287 unsigned TF = MI->getOperand(2).getTargetFlags();
1288 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1289 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1290 MCSymbol *GVSym = GetARMGVSymbol(GV);
1291 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1293 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1294 getFunctionNumber(),
1295 MI->getOperand(3).getImm(), OutContext);
1296 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1297 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1298 const MCExpr *PCRelExpr =
1299 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1300 MCBinaryExpr::CreateAdd(LabelSymExpr,
1301 MCConstantExpr::Create(PCAdj, OutContext),
1302 OutContext), OutContext), OutContext);
1303 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1305 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1306 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1308 // Add predicate operands.
1309 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1310 TmpInst.addOperand(MCOperand::CreateReg(0));
1311 // Add 's' bit operand (always reg0 for this)
1312 TmpInst.addOperand(MCOperand::CreateReg(0));
1313 OutStreamer.EmitInstruction(TmpInst);
1316 case ARM::tPICADD: {
1317 // This is a pseudo op for a label + instruction sequence, which looks like:
1320 // This adds the address of LPC0 to r0.
1323 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1324 getFunctionNumber(), MI->getOperand(2).getImm(),
1327 // Form and emit the add.
1329 AddInst.setOpcode(ARM::tADDhirr);
1330 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1331 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1332 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1333 // Add predicate operands.
1334 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1335 AddInst.addOperand(MCOperand::CreateReg(0));
1336 OutStreamer.EmitInstruction(AddInst);
1340 // This is a pseudo op for a label + instruction sequence, which looks like:
1343 // This adds the address of LPC0 to r0.
1346 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1347 getFunctionNumber(), MI->getOperand(2).getImm(),
1350 // Form and emit the add.
1352 AddInst.setOpcode(ARM::ADDrr);
1353 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1354 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1355 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1356 // Add predicate operands.
1357 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1358 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1359 // Add 's' bit operand (always reg0 for this)
1360 AddInst.addOperand(MCOperand::CreateReg(0));
1361 OutStreamer.EmitInstruction(AddInst);
1371 case ARM::PICLDRSH: {
1372 // This is a pseudo op for a label + instruction sequence, which looks like:
1375 // The LCP0 label is referenced by a constant pool entry in order to get
1376 // a PC-relative address at the ldr instruction.
1379 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1380 getFunctionNumber(), MI->getOperand(2).getImm(),
1383 // Form and emit the load
1385 switch (MI->getOpcode()) {
1387 llvm_unreachable("Unexpected opcode!");
1388 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1389 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1390 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1391 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1392 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1393 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1394 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1395 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1398 LdStInst.setOpcode(Opcode);
1399 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1400 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1401 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1402 LdStInst.addOperand(MCOperand::CreateImm(0));
1403 // Add predicate operands.
1404 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1405 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1406 OutStreamer.EmitInstruction(LdStInst);
1410 case ARM::CONSTPOOL_ENTRY: {
1411 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1412 /// in the function. The first operand is the ID# for this instruction, the
1413 /// second is the index into the MachineConstantPool that this is, the third
1414 /// is the size in bytes of this constant pool entry.
1415 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1416 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1419 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1421 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1422 if (MCPE.isMachineConstantPoolEntry())
1423 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1425 EmitGlobalConstant(MCPE.Val.ConstVal);
1429 case ARM::t2BR_JT: {
1430 // Lower and emit the instruction itself, then the jump table following it.
1432 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1433 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1434 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1435 // Add predicate operands.
1436 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1437 TmpInst.addOperand(MCOperand::CreateReg(0));
1438 OutStreamer.EmitInstruction(TmpInst);
1439 // Output the data for the jump table itself
1443 case ARM::t2TBB_JT: {
1444 // Lower and emit the instruction itself, then the jump table following it.
1447 TmpInst.setOpcode(ARM::t2TBB);
1448 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1449 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1450 // Add predicate operands.
1451 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1452 TmpInst.addOperand(MCOperand::CreateReg(0));
1453 OutStreamer.EmitInstruction(TmpInst);
1454 // Output the data for the jump table itself
1456 // Make sure the next instruction is 2-byte aligned.
1460 case ARM::t2TBH_JT: {
1461 // Lower and emit the instruction itself, then the jump table following it.
1464 TmpInst.setOpcode(ARM::t2TBH);
1465 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1466 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1467 // Add predicate operands.
1468 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1469 TmpInst.addOperand(MCOperand::CreateReg(0));
1470 OutStreamer.EmitInstruction(TmpInst);
1471 // Output the data for the jump table itself
1477 // Lower and emit the instruction itself, then the jump table following it.
1480 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1481 ARM::MOVr : ARM::tMOVgpr2gpr;
1482 TmpInst.setOpcode(Opc);
1483 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1484 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1485 // Add predicate operands.
1486 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1487 TmpInst.addOperand(MCOperand::CreateReg(0));
1488 // Add 's' bit operand (always reg0 for this)
1489 if (Opc == ARM::MOVr)
1490 TmpInst.addOperand(MCOperand::CreateReg(0));
1491 OutStreamer.EmitInstruction(TmpInst);
1493 // Make sure the Thumb jump table is 4-byte aligned.
1494 if (Opc == ARM::tMOVgpr2gpr)
1497 // Output the data for the jump table itself
1502 // Lower and emit the instruction itself, then the jump table following it.
1505 if (MI->getOperand(1).getReg() == 0) {
1507 TmpInst.setOpcode(ARM::LDRi12);
1508 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1509 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1510 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1512 TmpInst.setOpcode(ARM::LDRrs);
1513 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1514 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1515 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1516 TmpInst.addOperand(MCOperand::CreateImm(0));
1518 // Add predicate operands.
1519 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1520 TmpInst.addOperand(MCOperand::CreateReg(0));
1521 OutStreamer.EmitInstruction(TmpInst);
1523 // Output the data for the jump table itself
1527 case ARM::BR_JTadd: {
1528 // Lower and emit the instruction itself, then the jump table following it.
1529 // add pc, target, idx
1531 TmpInst.setOpcode(ARM::ADDrr);
1532 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1533 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1534 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1535 // Add predicate operands.
1536 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1537 TmpInst.addOperand(MCOperand::CreateReg(0));
1538 // Add 's' bit operand (always reg0 for this)
1539 TmpInst.addOperand(MCOperand::CreateReg(0));
1540 OutStreamer.EmitInstruction(TmpInst);
1542 // Output the data for the jump table itself
1547 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1548 // FIXME: Remove this special case when they do.
1549 if (!Subtarget->isTargetDarwin()) {
1550 //.long 0xe7ffdefe @ trap
1551 uint32_t Val = 0xe7ffdefeUL;
1552 OutStreamer.AddComment("trap");
1553 OutStreamer.EmitIntValue(Val, 4);
1559 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1560 // FIXME: Remove this special case when they do.
1561 if (!Subtarget->isTargetDarwin()) {
1562 //.short 57086 @ trap
1563 uint16_t Val = 0xdefe;
1564 OutStreamer.AddComment("trap");
1565 OutStreamer.EmitIntValue(Val, 2);
1570 case ARM::t2Int_eh_sjlj_setjmp:
1571 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1572 case ARM::tInt_eh_sjlj_setjmp: {
1573 // Two incoming args: GPR:$src, GPR:$val
1576 // str $val, [$src, #4]
1581 unsigned SrcReg = MI->getOperand(0).getReg();
1582 unsigned ValReg = MI->getOperand(1).getReg();
1583 MCSymbol *Label = GetARMSJLJEHLabel();
1586 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1587 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1588 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1590 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1591 OutStreamer.AddComment("eh_setjmp begin");
1592 OutStreamer.EmitInstruction(TmpInst);
1596 TmpInst.setOpcode(ARM::tADDi3);
1597 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1599 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1600 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1601 TmpInst.addOperand(MCOperand::CreateImm(7));
1603 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1604 TmpInst.addOperand(MCOperand::CreateReg(0));
1605 OutStreamer.EmitInstruction(TmpInst);
1609 TmpInst.setOpcode(ARM::tSTRi);
1610 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1611 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1612 // The offset immediate is #4. The operand value is scaled by 4 for the
1613 // tSTR instruction.
1614 TmpInst.addOperand(MCOperand::CreateImm(1));
1616 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1617 TmpInst.addOperand(MCOperand::CreateReg(0));
1618 OutStreamer.EmitInstruction(TmpInst);
1622 TmpInst.setOpcode(ARM::tMOVi8);
1623 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1624 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1625 TmpInst.addOperand(MCOperand::CreateImm(0));
1627 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1628 TmpInst.addOperand(MCOperand::CreateReg(0));
1629 OutStreamer.EmitInstruction(TmpInst);
1632 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1634 TmpInst.setOpcode(ARM::tB);
1635 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1636 OutStreamer.EmitInstruction(TmpInst);
1640 TmpInst.setOpcode(ARM::tMOVi8);
1641 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1642 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1643 TmpInst.addOperand(MCOperand::CreateImm(1));
1645 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1646 TmpInst.addOperand(MCOperand::CreateReg(0));
1647 OutStreamer.AddComment("eh_setjmp end");
1648 OutStreamer.EmitInstruction(TmpInst);
1650 OutStreamer.EmitLabel(Label);
1654 case ARM::Int_eh_sjlj_setjmp_nofp:
1655 case ARM::Int_eh_sjlj_setjmp: {
1656 // Two incoming args: GPR:$src, GPR:$val
1658 // str $val, [$src, #+4]
1662 unsigned SrcReg = MI->getOperand(0).getReg();
1663 unsigned ValReg = MI->getOperand(1).getReg();
1667 TmpInst.setOpcode(ARM::ADDri);
1668 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1669 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1670 TmpInst.addOperand(MCOperand::CreateImm(8));
1672 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1673 TmpInst.addOperand(MCOperand::CreateReg(0));
1674 // 's' bit operand (always reg0 for this).
1675 TmpInst.addOperand(MCOperand::CreateReg(0));
1676 OutStreamer.AddComment("eh_setjmp begin");
1677 OutStreamer.EmitInstruction(TmpInst);
1681 TmpInst.setOpcode(ARM::STRi12);
1682 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1683 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1684 TmpInst.addOperand(MCOperand::CreateImm(4));
1686 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1687 TmpInst.addOperand(MCOperand::CreateReg(0));
1688 OutStreamer.EmitInstruction(TmpInst);
1692 TmpInst.setOpcode(ARM::MOVi);
1693 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1694 TmpInst.addOperand(MCOperand::CreateImm(0));
1696 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1697 TmpInst.addOperand(MCOperand::CreateReg(0));
1698 // 's' bit operand (always reg0 for this).
1699 TmpInst.addOperand(MCOperand::CreateReg(0));
1700 OutStreamer.EmitInstruction(TmpInst);
1704 TmpInst.setOpcode(ARM::ADDri);
1705 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1706 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1707 TmpInst.addOperand(MCOperand::CreateImm(0));
1709 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1710 TmpInst.addOperand(MCOperand::CreateReg(0));
1711 // 's' bit operand (always reg0 for this).
1712 TmpInst.addOperand(MCOperand::CreateReg(0));
1713 OutStreamer.EmitInstruction(TmpInst);
1717 TmpInst.setOpcode(ARM::MOVi);
1718 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1719 TmpInst.addOperand(MCOperand::CreateImm(1));
1721 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1722 TmpInst.addOperand(MCOperand::CreateReg(0));
1723 // 's' bit operand (always reg0 for this).
1724 TmpInst.addOperand(MCOperand::CreateReg(0));
1725 OutStreamer.AddComment("eh_setjmp end");
1726 OutStreamer.EmitInstruction(TmpInst);
1730 case ARM::Int_eh_sjlj_longjmp: {
1731 // ldr sp, [$src, #8]
1732 // ldr $scratch, [$src, #4]
1735 unsigned SrcReg = MI->getOperand(0).getReg();
1736 unsigned ScratchReg = MI->getOperand(1).getReg();
1739 TmpInst.setOpcode(ARM::LDRi12);
1740 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1741 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1742 TmpInst.addOperand(MCOperand::CreateImm(8));
1744 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1745 TmpInst.addOperand(MCOperand::CreateReg(0));
1746 OutStreamer.EmitInstruction(TmpInst);
1750 TmpInst.setOpcode(ARM::LDRi12);
1751 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1752 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1753 TmpInst.addOperand(MCOperand::CreateImm(4));
1755 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1756 TmpInst.addOperand(MCOperand::CreateReg(0));
1757 OutStreamer.EmitInstruction(TmpInst);
1761 TmpInst.setOpcode(ARM::LDRi12);
1762 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1763 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1764 TmpInst.addOperand(MCOperand::CreateImm(0));
1766 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1767 TmpInst.addOperand(MCOperand::CreateReg(0));
1768 OutStreamer.EmitInstruction(TmpInst);
1772 TmpInst.setOpcode(ARM::BX);
1773 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1775 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1776 TmpInst.addOperand(MCOperand::CreateReg(0));
1777 OutStreamer.EmitInstruction(TmpInst);
1781 case ARM::tInt_eh_sjlj_longjmp: {
1782 // ldr $scratch, [$src, #8]
1784 // ldr $scratch, [$src, #4]
1787 unsigned SrcReg = MI->getOperand(0).getReg();
1788 unsigned ScratchReg = MI->getOperand(1).getReg();
1791 TmpInst.setOpcode(ARM::tLDRi);
1792 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1793 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1794 // The offset immediate is #8. The operand value is scaled by 4 for the
1795 // tLDR instruction.
1796 TmpInst.addOperand(MCOperand::CreateImm(2));
1798 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1799 TmpInst.addOperand(MCOperand::CreateReg(0));
1800 OutStreamer.EmitInstruction(TmpInst);
1804 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1805 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1806 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1808 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1809 TmpInst.addOperand(MCOperand::CreateReg(0));
1810 OutStreamer.EmitInstruction(TmpInst);
1814 TmpInst.setOpcode(ARM::tLDRi);
1815 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1816 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1817 TmpInst.addOperand(MCOperand::CreateImm(1));
1819 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1820 TmpInst.addOperand(MCOperand::CreateReg(0));
1821 OutStreamer.EmitInstruction(TmpInst);
1825 TmpInst.setOpcode(ARM::tLDRr);
1826 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1827 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1828 TmpInst.addOperand(MCOperand::CreateReg(0));
1830 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1831 TmpInst.addOperand(MCOperand::CreateReg(0));
1832 OutStreamer.EmitInstruction(TmpInst);
1836 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1837 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1839 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1840 TmpInst.addOperand(MCOperand::CreateReg(0));
1841 OutStreamer.EmitInstruction(TmpInst);
1845 // Tail jump branches are really just branch instructions with additional
1846 // code-gen attributes. Convert them to the canonical form here.
1848 case ARM::TAILJMPdND: {
1849 MCInst TmpInst, TmpInst2;
1850 // Lower the instruction as-is to get the operands properly converted.
1851 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1852 TmpInst.setOpcode(ARM::Bcc);
1853 TmpInst.addOperand(TmpInst2.getOperand(0));
1854 // Add predicate operands.
1855 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1856 TmpInst.addOperand(MCOperand::CreateReg(0));
1857 OutStreamer.AddComment("TAILCALL");
1858 OutStreamer.EmitInstruction(TmpInst);
1861 case ARM::tTAILJMPd:
1862 case ARM::tTAILJMPdND: {
1863 MCInst TmpInst, TmpInst2;
1864 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1865 // The Darwin toolchain doesn't support tail call relocations of 16-bit
1867 TmpInst.setOpcode(Opc == ARM::tTAILJMPd ? ARM::t2B : ARM::tB);
1868 TmpInst.addOperand(TmpInst2.getOperand(0));
1869 OutStreamer.AddComment("TAILCALL");
1870 OutStreamer.EmitInstruction(TmpInst);
1873 case ARM::TAILJMPrND:
1874 case ARM::tTAILJMPrND:
1876 case ARM::tTAILJMPr: {
1877 unsigned newOpc = (Opc == ARM::TAILJMPr || Opc == ARM::TAILJMPrND)
1878 ? ARM::BX : ARM::tBX;
1880 TmpInst.setOpcode(newOpc);
1881 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1883 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1884 TmpInst.addOperand(MCOperand::CreateReg(0));
1885 OutStreamer.AddComment("TAILCALL");
1886 OutStreamer.EmitInstruction(TmpInst);
1890 // These are the pseudos created to comply with stricter operand restrictions
1891 // on ARMv5. Lower them now to "normal" instructions, since all the
1892 // restrictions are already satisfied.
1894 EmitPatchedInstruction(MI, ARM::MUL);
1897 EmitPatchedInstruction(MI, ARM::MLA);
1900 EmitPatchedInstruction(MI, ARM::SMULL);
1903 EmitPatchedInstruction(MI, ARM::UMULL);
1906 EmitPatchedInstruction(MI, ARM::SMLAL);
1909 EmitPatchedInstruction(MI, ARM::UMLAL);
1912 EmitPatchedInstruction(MI, ARM::UMAAL);
1917 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1919 // Emit unwinding stuff for frame-related instructions
1920 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1921 EmitUnwindingInstruction(MI);
1923 OutStreamer.EmitInstruction(TmpInst);
1926 //===----------------------------------------------------------------------===//
1927 // Target Registry Stuff
1928 //===----------------------------------------------------------------------===//
1930 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1932 unsigned SyntaxVariant,
1933 const MCAsmInfo &MAI) {
1934 if (SyntaxVariant == 0)
1935 return new ARMInstPrinter(TM, MAI);
1939 // Force static initialization.
1940 extern "C" void LLVMInitializeARMAsmPrinter() {
1941 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1942 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1944 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1945 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);