1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCObjectFormat.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCSectionELF.h"
19 #include "llvm/MC/MCSectionMachO.h"
20 #include "llvm/Support/ELF.h"
21 #include "llvm/Support/MachO.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetRegistry.h"
28 class ARMAsmBackend : public TargetAsmBackend {
30 ARMAsmBackend(const Target &T) : TargetAsmBackend(T) {}
32 bool MayNeedRelaxation(const MCInst &Inst) const;
34 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
36 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
38 unsigned getPointerSize() const {
42 } // end anonymous namespace
44 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
45 // FIXME: Thumb targets, different move constant targets..
49 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
50 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
54 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
55 // if ((Count % 4) != 0) {
56 // // Fixme: % 2 for Thumb?
59 // FIXME: Zero fill for now. That's not right, but at least will get the
60 // section size right.
61 for (uint64_t i = 0; i != Count; ++i)
67 // FIXME: This should be in a separate file.
68 // ELF is an ELF of course...
69 class ELFARMAsmBackend : public ARMAsmBackend {
70 MCELFObjectFormat Format;
73 Triple::OSType OSType;
74 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
75 : ARMAsmBackend(T), OSType(_OSType) {
76 HasScatteredSymbols = true;
79 virtual const MCObjectFormat &getObjectFormat() const {
83 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
84 uint64_t Value) const;
86 bool isVirtualSection(const MCSection &Section) const {
87 const MCSectionELF &SE = static_cast<const MCSectionELF&>(Section);
88 return SE.getType() == MCSectionELF::SHT_NOBITS;
91 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
92 return createELFObjectWriter(OS, /*Is64Bit=*/false,
94 /*IsLittleEndian=*/true,
95 /*HasRelocationAddend=*/false);
99 // Fixme: can we raise this to share code between Darwin and ELF?
100 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
101 uint64_t Value) const {
102 assert(0 && "ELFARMAsmBackend::ApplyFixup() unimplemented");
106 // FIXME: This should be in a separate file.
107 class DarwinARMAsmBackend : public ARMAsmBackend {
108 MCMachOObjectFormat Format;
110 DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) {
111 HasScatteredSymbols = true;
114 virtual const MCObjectFormat &getObjectFormat() const {
118 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
119 uint64_t Value) const;
121 bool isVirtualSection(const MCSection &Section) const {
122 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
123 return (SMO.getType() == MCSectionMachO::S_ZEROFILL ||
124 SMO.getType() == MCSectionMachO::S_GB_ZEROFILL ||
125 SMO.getType() == MCSectionMachO::S_THREAD_LOCAL_ZEROFILL);
128 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
129 // FIXME: Subtarget info should be derived. Force v7 for now.
130 return createMachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPUTypeARM,
131 MachO::CPUSubType_ARM_V7,
132 /*IsLittleEndian=*/true);
135 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
139 } // end anonymous namespace
141 static unsigned getFixupKindNumBytes(unsigned Kind) {
143 default: llvm_unreachable("Unknown fixup kind!");
144 case FK_Data_4: return 4;
145 case ARM::fixup_arm_pcrel_12: return 2;
146 case ARM::fixup_arm_vfp_pcrel_12: return 1;
147 case ARM::fixup_arm_branch: return 3;
151 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
154 llvm_unreachable("Unknown fixup kind!");
157 case ARM::fixup_arm_pcrel_12:
158 // ARM PC-relative values are offset by 8.
160 case ARM::fixup_arm_branch:
161 case ARM::fixup_arm_vfp_pcrel_12:
162 // These values don't encode the low two bits since they're always zero.
163 // Offset by 8 just as above.
164 return (Value - 8) >> 2;
168 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
169 uint64_t Value) const {
170 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
171 Value = adjustFixupValue(Fixup.getKind(), Value);
173 assert(Fixup.getOffset() + NumBytes <= DF.getContents().size() &&
174 "Invalid fixup offset!");
175 // For each byte of the fragment that the fixup touches, mask in the
176 // bits from the fixup value.
177 for (unsigned i = 0; i != NumBytes; ++i)
178 DF.getContents()[Fixup.getOffset() + i] |= uint8_t(Value >> (i * 8));
180 } // end anonymous namespace
182 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
183 const std::string &TT) {
184 switch (Triple(TT).getOS()) {
186 return new DarwinARMAsmBackend(T);
187 case Triple::MinGW32:
190 assert(0 && "Windows not supported on ARM");
192 return new ELFARMAsmBackend(T, Triple(TT).getOS());