1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
27 "Use software floating point features.">;
29 //===----------------------------------------------------------------------===//
30 // ARM Subtarget features.
33 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
34 "Enable VFP2 instructions">;
35 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
36 "Enable VFP3 instructions",
38 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
39 "Enable NEON instructions",
41 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
42 "Enable Thumb2 instructions">;
43 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
44 "Does not support ARM mode execution",
46 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
47 "Enable half-precision floating point">;
48 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
49 "Enable VFP4 instructions",
50 [FeatureVFP3, FeatureFP16]>;
51 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
52 "true", "Enable ARMv8 FP",
54 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
55 "Restrict VFP3 to 16 double registers">;
56 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
57 "Enable divide instructions">;
58 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
59 "HasHardwareDivideInARM", "true",
60 "Enable divide instructions in ARM mode">;
61 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
62 "Enable Thumb2 extract and pack instructions">;
63 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
64 "Has data barrier (dmb / dsb) instructions">;
65 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
66 "FP compare + branch is slow">;
67 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
68 "Floating point unit supports single precision only">;
69 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
70 "Enable support for Performance Monitor extensions">;
71 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
72 "Enable support for TrustZone security extensions">;
73 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
74 "Enable support for Cryptography extensions",
76 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
77 "Enable support for CRC instructions">;
79 // Cyclone has preferred instructions for zeroing VFP registers, which can
80 // execute in 0 cycles.
81 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
82 "Has zero-cycle zeroing instructions">;
84 // Some processors have FP multiply-accumulate instructions that don't
85 // play nicely with other VFP / NEON instructions, and it's generally better
86 // to just not use them.
87 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
88 "Disable VFP / NEON MAC instructions">;
90 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
91 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
92 "HasVMLxForwarding", "true",
93 "Has multiplier accumulator forwarding">;
95 // Some processors benefit from using NEON instructions for scalar
96 // single-precision FP operations.
97 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
99 "Use NEON for single precision FP">;
101 // Disable 32-bit to 16-bit narrowing for experimentation.
102 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
103 "Prefer 32-bit Thumb instrs">;
105 /// Some instructions update CPSR partially, which can add false dependency for
106 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
107 /// mapped to a separate physical register. Avoid partial CPSR update for these
109 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
110 "AvoidCPSRPartialUpdate", "true",
111 "Avoid CPSR partial update for OOO execution">;
113 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
114 "AvoidMOVsShifterOperand", "true",
115 "Avoid movs instructions with shifter operand">;
117 // Some processors perform return stack prediction. CodeGen should avoid issue
118 // "normal" call instructions to callees which do not return.
119 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
120 "Has return address stack">;
123 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
124 "Supports DSP instructions in ARM and/or Thumb2">;
126 // Multiprocessing extension.
127 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
128 "Supports Multiprocessing extension">;
130 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
131 def FeatureVirtualization : SubtargetFeature<"virtualization",
132 "HasVirtualization", "true",
133 "Supports Virtualization extension",
134 [FeatureHWDiv, FeatureHWDivARM]>;
137 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
138 "Is microcontroller profile ('M' series)">;
141 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
142 "Is realtime profile ('R' series)">;
145 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
146 "Is application profile ('A' series)">;
148 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
149 // See ARMInstrInfo.td for details.
150 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
153 def FeatureStrictAlign : SubtargetFeature<"strict-align",
154 "StrictAlign", "true",
155 "Disallow all unaligned memory "
158 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
159 "Generate calls via indirect call "
162 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
163 "Reserve R9, making it unavailable as "
166 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
167 "Don't use movt/movw pairs for 32-bit "
171 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
172 "Support ARM v4T instructions">;
173 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
174 "Support ARM v5T instructions",
176 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
177 "Support ARM v5TE, v5TEj, and v5TExp instructions",
179 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
180 "Support ARM v6 instructions",
182 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
183 "Support ARM v6M instructions",
185 def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
186 "Support ARM v6k instructions",
188 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
189 "Support ARM v6t2 instructions",
190 [HasV6MOps, HasV6KOps, FeatureThumb2]>;
191 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
192 "Support ARM v7 instructions",
193 [HasV6T2Ops, FeaturePerfMon]>;
194 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
195 "Support ARM v8 instructions",
196 [HasV7Ops, FeatureVirtualization,
198 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
199 "Support ARM v8.1a instructions",
200 [HasV8Ops, FeatureAClass, FeatureCRC]>;
202 //===----------------------------------------------------------------------===//
203 // ARM Processors supported.
206 include "ARMSchedule.td"
208 // ARM processor families.
209 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
210 "Cortex-A5 ARM processors",
211 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
212 FeatureVMLxForwarding, FeatureT2XtPk,
213 FeatureTrustZone, FeatureMP]>;
214 def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
215 "Cortex-A7 ARM processors",
216 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
217 FeatureVMLxForwarding, FeatureT2XtPk,
218 FeatureVFP4, FeatureMP,
219 FeatureHWDiv, FeatureHWDivARM,
220 FeatureTrustZone, FeatureVirtualization]>;
221 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
222 "Cortex-A8 ARM processors",
223 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
224 FeatureVMLxForwarding, FeatureT2XtPk,
226 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
227 "Cortex-A9 ARM processors",
228 [FeatureVMLxForwarding,
229 FeatureT2XtPk, FeatureFP16,
230 FeatureAvoidPartialCPSR,
232 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
233 "Swift ARM processors",
234 [FeatureNEONForFP, FeatureT2XtPk,
235 FeatureVFP4, FeatureMP, FeatureHWDiv,
236 FeatureHWDivARM, FeatureAvoidPartialCPSR,
237 FeatureAvoidMOVsShOp,
238 FeatureHasSlowFPVMLx, FeatureTrustZone]>;
239 def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
240 "Cortex-A12 ARM processors",
241 [FeatureVMLxForwarding,
242 FeatureT2XtPk, FeatureVFP4,
243 FeatureHWDiv, FeatureHWDivARM,
244 FeatureAvoidPartialCPSR,
245 FeatureVirtualization,
249 // FIXME: It has not been determined if A15 has these features.
250 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
251 "Cortex-A15 ARM processors",
252 [FeatureT2XtPk, FeatureVFP4,
253 FeatureMP, FeatureHWDiv, FeatureHWDivARM,
254 FeatureAvoidPartialCPSR,
255 FeatureTrustZone, FeatureVirtualization]>;
257 def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
258 "Cortex-A17 ARM processors",
259 [FeatureVMLxForwarding,
260 FeatureT2XtPk, FeatureVFP4,
261 FeatureHWDiv, FeatureHWDivARM,
262 FeatureAvoidPartialCPSR,
263 FeatureVirtualization,
266 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
267 "Cortex-A53 ARM processors",
268 [FeatureHWDiv, FeatureHWDivARM,
269 FeatureTrustZone, FeatureT2XtPk,
270 FeatureCrypto, FeatureCRC]>;
272 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
273 "Cortex-A57 ARM processors",
274 [FeatureHWDiv, FeatureHWDivARM,
275 FeatureTrustZone, FeatureT2XtPk,
276 FeatureCrypto, FeatureCRC]>;
278 def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
279 "Cortex-R4 ARM processors",
281 FeatureAvoidPartialCPSR,
282 FeatureDSP, FeatureT2XtPk, HasV7Ops,
283 FeatureDB, FeatureHasRAS, FeatureRClass]>;
285 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
286 "Cortex-R5 ARM processors",
288 FeatureHWDiv, FeatureHWDivARM,
289 FeatureHasSlowFPVMLx,
290 FeatureAvoidPartialCPSR,
293 // FIXME: krait has currently the same features as A9
294 // plus VFP4 and hardware division features.
295 def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
296 "Qualcomm ARM processors",
297 [FeatureVMLxForwarding,
298 FeatureT2XtPk, FeatureFP16,
299 FeatureAvoidPartialCPSR,
306 class ProcNoItin<string Name, list<SubtargetFeature> Features>
307 : Processor<Name, NoItineraries, Features>;
310 def : ProcNoItin<"generic", []>;
311 def : ProcNoItin<"arm8", []>;
312 def : ProcNoItin<"arm810", []>;
313 def : ProcNoItin<"strongarm", []>;
314 def : ProcNoItin<"strongarm110", []>;
315 def : ProcNoItin<"strongarm1100", []>;
316 def : ProcNoItin<"strongarm1110", []>;
319 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
320 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
321 def : ProcNoItin<"arm710t", [HasV4TOps]>;
322 def : ProcNoItin<"arm720t", [HasV4TOps]>;
323 def : ProcNoItin<"arm9", [HasV4TOps]>;
324 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
325 def : ProcNoItin<"arm920", [HasV4TOps]>;
326 def : ProcNoItin<"arm920t", [HasV4TOps]>;
327 def : ProcNoItin<"arm922t", [HasV4TOps]>;
328 def : ProcNoItin<"arm940t", [HasV4TOps]>;
329 def : ProcNoItin<"ep9312", [HasV4TOps]>;
332 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
333 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
336 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
337 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
338 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
339 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
340 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
341 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
342 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
343 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
344 def : ProcNoItin<"xscale", [HasV5TEOps]>;
345 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
348 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
349 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
350 FeatureHasSlowFPVMLx]>;
353 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
354 FeatureDB, FeatureMClass]>;
355 def : Processor<"cortex-m0plus", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
356 FeatureDB, FeatureMClass]>;
357 def : Processor<"cortex-m1", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
358 FeatureDB, FeatureMClass]>;
359 def : Processor<"sc000", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
360 FeatureDB, FeatureMClass]>;
363 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6KOps,
365 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
367 FeatureHasSlowFPVMLx]>;
368 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6KOps]>;
369 def : Processor<"mpcore", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
370 FeatureHasSlowFPVMLx]>;
373 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops, FeatureDSP]>;
374 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
375 FeatureHasSlowFPVMLx,
379 // FIXME: A5 has currently the same Schedule model as A8
380 def : ProcessorModel<"cortex-a5", CortexA8Model,
381 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
382 FeatureVFP4, FeatureDSP,
383 FeatureHasRAS, FeatureAClass]>;
384 def : ProcessorModel<"cortex-a7", CortexA8Model,
385 [ProcA7, HasV7Ops, FeatureNEON, FeatureDB,
386 FeatureDSP, FeatureHasRAS, FeatureAClass]>;
387 def : ProcessorModel<"cortex-a8", CortexA8Model,
388 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
389 FeatureDSP, FeatureHasRAS, FeatureAClass]>;
390 def : ProcessorModel<"cortex-a9", CortexA9Model,
391 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
392 FeatureDSP, FeatureHasRAS, FeatureMP,
395 // FIXME: A12 has currently the same Schedule model as A9
396 def : ProcessorModel<"cortex-a12", CortexA9Model,
397 [ProcA12, HasV7Ops, FeatureNEON, FeatureDB,
398 FeatureDSP, FeatureMP,
399 FeatureHasRAS, FeatureAClass]>;
401 // FIXME: A15 has currently the same ProcessorModel as A9.
402 def : ProcessorModel<"cortex-a15", CortexA9Model,
403 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
404 FeatureDSP, FeatureHasRAS, FeatureAClass]>;
406 // FIXME: A17 has currently the same Schedule model as A9
407 def : ProcessorModel<"cortex-a17", CortexA9Model,
408 [ProcA17, HasV7Ops, FeatureNEON, FeatureDB,
409 FeatureDSP, FeatureMP,
410 FeatureHasRAS, FeatureAClass]>;
412 // FIXME: krait has currently the same Schedule model as A9
413 def : ProcessorModel<"krait", CortexA9Model,
414 [ProcKrait, HasV7Ops,
415 FeatureNEON, FeatureDB,
416 FeatureDSP, FeatureHasRAS, FeatureAClass]>;
418 // FIXME: R4 has currently the same ProcessorModel as A8.
419 def : ProcessorModel<"cortex-r4", CortexA8Model,
422 // FIXME: R4F has currently the same ProcessorModel as A8.
423 def : ProcessorModel<"cortex-r4f", CortexA8Model,
425 FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
426 FeatureVFP3, FeatureD16]>;
428 // FIXME: R5 has currently the same ProcessorModel as A8.
429 def : ProcessorModel<"cortex-r5", CortexA8Model,
430 [ProcR5, HasV7Ops, FeatureDB,
431 FeatureVFP3, FeatureDSP, FeatureHasRAS,
432 FeatureD16, FeatureRClass]>;
434 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
435 def : ProcessorModel<"cortex-r7", CortexA8Model,
436 [ProcR5, HasV7Ops, FeatureDB,
437 FeatureVFP3, FeatureDSP,
438 FeatureHasRAS, FeatureVFPOnlySP,
439 FeatureD16, FeatureMP, FeatureRClass]>;
442 def : ProcNoItin<"cortex-m3", [HasV7Ops,
443 FeatureThumb2, FeatureNoARM, FeatureDB,
444 FeatureHWDiv, FeatureMClass]>;
445 def : ProcNoItin<"sc300", [HasV7Ops,
446 FeatureThumb2, FeatureNoARM, FeatureDB,
447 FeatureHWDiv, FeatureMClass]>;
450 def : ProcNoItin<"cortex-m4", [HasV7Ops,
451 FeatureThumb2, FeatureNoARM, FeatureDB,
452 FeatureHWDiv, FeatureDSP, FeatureT2XtPk,
453 FeatureVFP4, FeatureVFPOnlySP, FeatureD16,
455 def : ProcNoItin<"cortex-m7", [HasV7Ops,
456 FeatureThumb2, FeatureNoARM, FeatureDB,
457 FeatureHWDiv, FeatureDSP,
458 FeatureT2XtPk, FeatureFPARMv8,
459 FeatureD16, FeatureMClass]>;
462 // Swift uArch Processors.
463 def : ProcessorModel<"swift", SwiftModel,
464 [ProcSwift, HasV7Ops, FeatureNEON,
465 FeatureDB, FeatureDSP,
466 FeatureHasRAS, FeatureAClass]>;
469 def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
470 FeatureDB, FeatureFPARMv8,
471 FeatureNEON, FeatureDSP]>;
472 def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
473 FeatureDB, FeatureFPARMv8,
474 FeatureNEON, FeatureDSP]>;
475 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
476 def : ProcNoItin<"cortex-a72", [ProcA57, HasV8Ops, FeatureAClass,
477 FeatureDB, FeatureFPARMv8,
478 FeatureNEON, FeatureDSP]>;
480 // Cyclone is very similar to swift
481 def : ProcessorModel<"cyclone", SwiftModel,
482 [ProcSwift, HasV8Ops, HasV7Ops,
483 FeatureCrypto, FeatureFPARMv8,
484 FeatureDB, FeatureDSP,
485 FeatureHasRAS, FeatureZCZeroing]>;
487 //===----------------------------------------------------------------------===//
488 // Register File Description
489 //===----------------------------------------------------------------------===//
491 include "ARMRegisterInfo.td"
493 include "ARMCallingConv.td"
495 //===----------------------------------------------------------------------===//
496 // Instruction Descriptions
497 //===----------------------------------------------------------------------===//
499 include "ARMInstrInfo.td"
501 def ARMInstrInfo : InstrInfo;
503 //===----------------------------------------------------------------------===//
504 // Declare the target which we are implementing
505 //===----------------------------------------------------------------------===//
507 def ARMAsmWriter : AsmWriter {
508 string AsmWriterClassName = "InstPrinter";
509 int PassSubtarget = 1;
511 bit isMCAsmWriter = 1;
514 def ARMAsmParserVariant : AsmParserVariant {
517 string BreakCharacters = ".";
521 // Pull in Instruction Info:
522 let InstructionSet = ARMInstrInfo;
523 let AssemblyWriters = [ARMAsmWriter];
524 let AssemblyParserVariants = [ARMAsmParserVariant];