1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36 "Enable NEON instructions",
38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39 "Enable Thumb2 instructions">;
40 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
41 "Does not support ARM mode execution">;
42 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
43 "Enable half-precision floating point">;
44 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
45 "Enable VFP4 instructions",
46 [FeatureVFP3, FeatureFP16]>;
47 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
48 "Restrict VFP3 to 16 double registers">;
49 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
50 "Enable divide instructions">;
51 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
52 "HasHardwareDivideInARM", "true",
53 "Enable divide instructions in ARM mode">;
54 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
55 "Enable Thumb2 extract and pack instructions">;
56 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
57 "Has data barrier (dmb / dsb) instructions">;
58 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
59 "FP compare + branch is slow">;
60 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
61 "Floating point unit supports single precision only">;
62 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
63 "Enable support for Performance Monitor extensions">;
64 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
65 "Enable support for TrustZone security extensions">;
67 // Some processors have FP multiply-accumulate instructions that don't
68 // play nicely with other VFP / NEON instructions, and it's generally better
69 // to just not use them.
70 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
71 "Disable VFP / NEON MAC instructions">;
73 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
74 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
75 "HasVMLxForwarding", "true",
76 "Has multiplier accumulator forwarding">;
78 // Some processors benefit from using NEON instructions for scalar
79 // single-precision FP operations.
80 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
82 "Use NEON for single precision FP">;
84 // Disable 32-bit to 16-bit narrowing for experimentation.
85 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
86 "Prefer 32-bit Thumb instrs">;
88 /// Some instructions update CPSR partially, which can add false dependency for
89 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
90 /// mapped to a separate physical register. Avoid partial CPSR update for these
92 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
93 "AvoidCPSRPartialUpdate", "true",
94 "Avoid CPSR partial update for OOO execution">;
96 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
97 "AvoidMOVsShifterOperand", "true",
98 "Avoid movs instructions with shifter operand">;
100 // Some processors perform return stack prediction. CodeGen should avoid issue
101 // "normal" call instructions to callees which do not return.
102 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
103 "Has return address stack">;
105 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
106 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
107 "Supports v7 DSP instructions in Thumb2">;
109 // Multiprocessing extension.
110 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
111 "Supports Multiprocessing extension">;
114 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
115 "Is microcontroller profile ('M' series)">;
117 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
118 // See ARMInstrInfo.td for details.
119 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
123 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
124 "Support ARM v4T instructions">;
125 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
126 "Support ARM v5T instructions",
128 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
129 "Support ARM v5TE, v5TEj, and v5TExp instructions",
131 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
132 "Support ARM v6 instructions",
134 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
135 "Support ARM v6t2 instructions",
136 [HasV6Ops, FeatureThumb2]>;
137 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
138 "Support ARM v7 instructions",
139 [HasV6T2Ops, FeaturePerfMon]>;
141 //===----------------------------------------------------------------------===//
142 // ARM Processors supported.
145 include "ARMSchedule.td"
147 // ARM processor families.
148 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
149 "Cortex-A5 ARM processors",
150 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
151 FeatureVMLxForwarding, FeatureT2XtPk,
153 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
154 "Cortex-A8 ARM processors",
155 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
156 FeatureVMLxForwarding, FeatureT2XtPk,
158 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
159 "Cortex-A9 ARM processors",
160 [FeatureVMLxForwarding,
161 FeatureT2XtPk, FeatureFP16,
162 FeatureAvoidPartialCPSR,
164 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
165 "Swift ARM processors",
166 [FeatureNEONForFP, FeatureT2XtPk,
167 FeatureVFP4, FeatureMP, FeatureHWDiv,
168 FeatureHWDivARM, FeatureAvoidPartialCPSR,
169 FeatureAvoidMOVsShOp,
170 FeatureHasSlowFPVMLx, FeatureTrustZone]>;
172 // FIXME: It has not been determined if A15 has these features.
173 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
174 "Cortex-A15 ARM processors",
175 [FeatureT2XtPk, FeatureFP16,
176 FeatureAvoidPartialCPSR,
178 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
179 "Cortex-R5 ARM processors",
181 FeatureHWDiv, FeatureHWDivARM,
182 FeatureHasSlowFPVMLx,
183 FeatureAvoidPartialCPSR,
186 class ProcNoItin<string Name, list<SubtargetFeature> Features>
187 : Processor<Name, NoItineraries, Features>;
190 def : ProcNoItin<"generic", []>;
191 def : ProcNoItin<"arm8", []>;
192 def : ProcNoItin<"arm810", []>;
193 def : ProcNoItin<"strongarm", []>;
194 def : ProcNoItin<"strongarm110", []>;
195 def : ProcNoItin<"strongarm1100", []>;
196 def : ProcNoItin<"strongarm1110", []>;
199 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
200 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
201 def : ProcNoItin<"arm710t", [HasV4TOps]>;
202 def : ProcNoItin<"arm720t", [HasV4TOps]>;
203 def : ProcNoItin<"arm9", [HasV4TOps]>;
204 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
205 def : ProcNoItin<"arm920", [HasV4TOps]>;
206 def : ProcNoItin<"arm920t", [HasV4TOps]>;
207 def : ProcNoItin<"arm922t", [HasV4TOps]>;
208 def : ProcNoItin<"arm940t", [HasV4TOps]>;
209 def : ProcNoItin<"ep9312", [HasV4TOps]>;
212 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
213 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
216 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
217 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
218 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
219 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
220 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
221 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
222 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
223 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
224 def : ProcNoItin<"xscale", [HasV5TEOps]>;
225 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
228 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
229 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
230 FeatureHasSlowFPVMLx]>;
231 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
232 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
233 FeatureHasSlowFPVMLx]>;
234 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
235 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
236 FeatureHasSlowFPVMLx]>;
239 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
240 FeatureDB, FeatureMClass]>;
243 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
245 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
246 FeatureHasSlowFPVMLx,
250 // FIXME: A5 has currently the same Schedule model as A8
251 def : ProcessorModel<"cortex-a5", CortexA8Model,
252 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
253 FeatureVFP4, FeatureDSPThumb2,
255 def : ProcessorModel<"cortex-a8", CortexA8Model,
256 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
257 FeatureDSPThumb2, FeatureHasRAS]>;
258 def : ProcessorModel<"cortex-a9", CortexA9Model,
259 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
260 FeatureDSPThumb2, FeatureHasRAS]>;
261 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
262 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
263 FeatureDSPThumb2, FeatureMP,
265 // FIXME: A15 has currently the same ProcessorModel as A9.
266 def : ProcessorModel<"cortex-a15", CortexA9Model,
267 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
268 FeatureDSPThumb2, FeatureHasRAS]>;
269 // FIXME: R5 has currently the same ProcessorModel as A8.
270 def : ProcessorModel<"cortex-r5", CortexA8Model,
271 [ProcR5, HasV7Ops, FeatureDB,
272 FeatureVFP3, FeatureDSPThumb2,
276 def : ProcNoItin<"cortex-m3", [HasV7Ops,
277 FeatureThumb2, FeatureNoARM, FeatureDB,
278 FeatureHWDiv, FeatureMClass]>;
281 def : ProcNoItin<"cortex-m4", [HasV7Ops,
282 FeatureThumb2, FeatureNoARM, FeatureDB,
283 FeatureHWDiv, FeatureDSPThumb2,
284 FeatureT2XtPk, FeatureVFP4,
285 FeatureVFPOnlySP, FeatureMClass]>;
287 // Swift uArch Processors.
288 def : ProcessorModel<"swift", SwiftModel,
289 [ProcSwift, HasV7Ops, FeatureNEON,
290 FeatureDB, FeatureDSPThumb2,
293 //===----------------------------------------------------------------------===//
294 // Register File Description
295 //===----------------------------------------------------------------------===//
297 include "ARMRegisterInfo.td"
299 include "ARMCallingConv.td"
301 //===----------------------------------------------------------------------===//
302 // Instruction Descriptions
303 //===----------------------------------------------------------------------===//
305 include "ARMInstrInfo.td"
307 def ARMInstrInfo : InstrInfo;
310 //===----------------------------------------------------------------------===//
312 //===----------------------------------------------------------------------===//
313 // ARM Uses the MC printer for asm output, so make sure the TableGen
314 // AsmWriter bits get associated with the correct class.
315 def ARMAsmWriter : AsmWriter {
316 string AsmWriterClassName = "InstPrinter";
317 bit isMCAsmWriter = 1;
320 //===----------------------------------------------------------------------===//
321 // Declare the target which we are implementing
322 //===----------------------------------------------------------------------===//
325 // Pull in Instruction Info:
326 let InstructionSet = ARMInstrInfo;
328 let AssemblyWriters = [ARMAsmWriter];