1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36 "Enable NEON instructions",
38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39 "Enable Thumb2 instructions">;
40 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
41 "Does not support ARM mode execution",
43 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
44 "Enable half-precision floating point">;
45 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
46 "Enable VFP4 instructions",
47 [FeatureVFP3, FeatureFP16]>;
48 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
49 "true", "Enable ARMv8 FP",
51 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
52 "Restrict VFP3 to 16 double registers">;
53 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
54 "Enable divide instructions">;
55 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
56 "HasHardwareDivideInARM", "true",
57 "Enable divide instructions in ARM mode">;
58 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
59 "Enable Thumb2 extract and pack instructions">;
60 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
61 "Has data barrier (dmb / dsb) instructions">;
62 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
63 "FP compare + branch is slow">;
64 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
65 "Floating point unit supports single precision only">;
66 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
67 "Enable support for Performance Monitor extensions">;
68 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
69 "Enable support for TrustZone security extensions">;
70 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
71 "Enable support for Cryptography extensions",
73 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
74 "Enable support for CRC instructions">;
76 // Some processors have FP multiply-accumulate instructions that don't
77 // play nicely with other VFP / NEON instructions, and it's generally better
78 // to just not use them.
79 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
80 "Disable VFP / NEON MAC instructions">;
82 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
83 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
84 "HasVMLxForwarding", "true",
85 "Has multiplier accumulator forwarding">;
87 // Some processors benefit from using NEON instructions for scalar
88 // single-precision FP operations.
89 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
91 "Use NEON for single precision FP">;
93 // Disable 32-bit to 16-bit narrowing for experimentation.
94 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
95 "Prefer 32-bit Thumb instrs">;
97 /// Some instructions update CPSR partially, which can add false dependency for
98 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
99 /// mapped to a separate physical register. Avoid partial CPSR update for these
101 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
102 "AvoidCPSRPartialUpdate", "true",
103 "Avoid CPSR partial update for OOO execution">;
105 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
106 "AvoidMOVsShifterOperand", "true",
107 "Avoid movs instructions with shifter operand">;
109 // Some processors perform return stack prediction. CodeGen should avoid issue
110 // "normal" call instructions to callees which do not return.
111 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
112 "Has return address stack">;
114 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
115 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
116 "Supports v7 DSP instructions in Thumb2">;
118 // Multiprocessing extension.
119 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
120 "Supports Multiprocessing extension">;
123 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
124 "Is microcontroller profile ('M' series)">;
127 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
128 "Is realtime profile ('R' series)">;
131 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
132 "Is application profile ('A' series)">;
134 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
135 // See ARMInstrInfo.td for details.
136 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
140 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
141 "Support ARM v4T instructions">;
142 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
143 "Support ARM v5T instructions",
145 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
146 "Support ARM v5TE, v5TEj, and v5TExp instructions",
148 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
149 "Support ARM v6 instructions",
151 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
152 "Support ARM v6M instructions",
154 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
155 "Support ARM v6t2 instructions",
156 [HasV6MOps, FeatureThumb2]>;
157 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
158 "Support ARM v7 instructions",
159 [HasV6T2Ops, FeaturePerfMon]>;
160 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
161 "Support ARM v8 instructions",
164 //===----------------------------------------------------------------------===//
165 // ARM Processors supported.
168 include "ARMSchedule.td"
170 // ARM processor families.
171 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
172 "Cortex-A5 ARM processors",
173 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
174 FeatureVMLxForwarding, FeatureT2XtPk,
176 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
177 "Cortex-A8 ARM processors",
178 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
179 FeatureVMLxForwarding, FeatureT2XtPk,
181 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
182 "Cortex-A9 ARM processors",
183 [FeatureVMLxForwarding,
184 FeatureT2XtPk, FeatureFP16,
185 FeatureAvoidPartialCPSR,
187 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
188 "Swift ARM processors",
189 [FeatureNEONForFP, FeatureT2XtPk,
190 FeatureVFP4, FeatureMP, FeatureHWDiv,
191 FeatureHWDivARM, FeatureAvoidPartialCPSR,
192 FeatureAvoidMOVsShOp,
193 FeatureHasSlowFPVMLx, FeatureTrustZone]>;
195 // FIXME: It has not been determined if A15 has these features.
196 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
197 "Cortex-A15 ARM processors",
198 [FeatureT2XtPk, FeatureVFP4,
199 FeatureMP, FeatureHWDiv, FeatureHWDivARM,
200 FeatureAvoidPartialCPSR,
203 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
204 "Cortex-A53 ARM processors",
205 [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
206 FeatureTrustZone, FeatureT2XtPk,
207 FeatureCrypto, FeatureCRC]>;
209 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
210 "Cortex-A57 ARM processors",
211 [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
212 FeatureTrustZone, FeatureT2XtPk,
213 FeatureCrypto, FeatureCRC]>;
215 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
216 "Cortex-R5 ARM processors",
218 FeatureHWDiv, FeatureHWDivARM,
219 FeatureHasSlowFPVMLx,
220 FeatureAvoidPartialCPSR,
223 class ProcNoItin<string Name, list<SubtargetFeature> Features>
224 : Processor<Name, NoItineraries, Features>;
227 def : ProcNoItin<"generic", []>;
228 def : ProcNoItin<"arm8", []>;
229 def : ProcNoItin<"arm810", []>;
230 def : ProcNoItin<"strongarm", []>;
231 def : ProcNoItin<"strongarm110", []>;
232 def : ProcNoItin<"strongarm1100", []>;
233 def : ProcNoItin<"strongarm1110", []>;
236 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
237 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
238 def : ProcNoItin<"arm710t", [HasV4TOps]>;
239 def : ProcNoItin<"arm720t", [HasV4TOps]>;
240 def : ProcNoItin<"arm9", [HasV4TOps]>;
241 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
242 def : ProcNoItin<"arm920", [HasV4TOps]>;
243 def : ProcNoItin<"arm920t", [HasV4TOps]>;
244 def : ProcNoItin<"arm922t", [HasV4TOps]>;
245 def : ProcNoItin<"arm940t", [HasV4TOps]>;
246 def : ProcNoItin<"ep9312", [HasV4TOps]>;
249 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
250 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
253 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
254 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
255 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
256 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
257 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
258 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
259 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
260 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
261 def : ProcNoItin<"xscale", [HasV5TEOps]>;
262 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
265 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
266 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
267 FeatureHasSlowFPVMLx]>;
268 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
269 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
270 FeatureHasSlowFPVMLx]>;
271 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
272 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
273 FeatureHasSlowFPVMLx]>;
276 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
277 FeatureDB, FeatureMClass]>;
280 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
282 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
283 FeatureHasSlowFPVMLx,
287 // FIXME: A5 has currently the same Schedule model as A8
288 def : ProcessorModel<"cortex-a5", CortexA8Model,
289 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
290 FeatureVFP4, FeatureDSPThumb2,
291 FeatureHasRAS, FeatureAClass]>;
292 def : ProcessorModel<"cortex-a8", CortexA8Model,
293 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
294 FeatureDSPThumb2, FeatureHasRAS,
296 def : ProcessorModel<"cortex-a9", CortexA9Model,
297 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
298 FeatureDSPThumb2, FeatureHasRAS,
300 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
301 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
302 FeatureDSPThumb2, FeatureMP,
303 FeatureHasRAS, FeatureAClass]>;
304 // FIXME: A15 has currently the same ProcessorModel as A9.
305 def : ProcessorModel<"cortex-a15", CortexA9Model,
306 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
307 FeatureDSPThumb2, FeatureHasRAS,
309 // FIXME: R5 has currently the same ProcessorModel as A8.
310 def : ProcessorModel<"cortex-r5", CortexA8Model,
311 [ProcR5, HasV7Ops, FeatureDB,
312 FeatureVFP3, FeatureDSPThumb2,
313 FeatureHasRAS, FeatureVFPOnlySP,
314 FeatureD16, FeatureRClass]>;
317 def : ProcNoItin<"cortex-m3", [HasV7Ops,
318 FeatureThumb2, FeatureNoARM, FeatureDB,
319 FeatureHWDiv, FeatureMClass]>;
322 def : ProcNoItin<"cortex-m4", [HasV7Ops,
323 FeatureThumb2, FeatureNoARM, FeatureDB,
324 FeatureHWDiv, FeatureDSPThumb2,
325 FeatureT2XtPk, FeatureVFP4,
326 FeatureVFPOnlySP, FeatureD16,
329 // Swift uArch Processors.
330 def : ProcessorModel<"swift", SwiftModel,
331 [ProcSwift, HasV7Ops, FeatureNEON,
332 FeatureDB, FeatureDSPThumb2,
333 FeatureHasRAS, FeatureAClass]>;
336 def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
337 FeatureDB, FeatureFPARMv8,
338 FeatureNEON, FeatureDSPThumb2]>;
339 def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
340 FeatureDB, FeatureFPARMv8,
341 FeatureNEON, FeatureDSPThumb2]>;
343 //===----------------------------------------------------------------------===//
344 // Register File Description
345 //===----------------------------------------------------------------------===//
347 include "ARMRegisterInfo.td"
349 include "ARMCallingConv.td"
351 //===----------------------------------------------------------------------===//
352 // Instruction Descriptions
353 //===----------------------------------------------------------------------===//
355 include "ARMInstrInfo.td"
357 def ARMInstrInfo : InstrInfo;
360 //===----------------------------------------------------------------------===//
362 //===----------------------------------------------------------------------===//
363 // ARM Uses the MC printer for asm output, so make sure the TableGen
364 // AsmWriter bits get associated with the correct class.
365 def ARMAsmWriter : AsmWriter {
366 string AsmWriterClassName = "InstPrinter";
367 bit isMCAsmWriter = 1;
370 //===----------------------------------------------------------------------===//
371 // Declare the target which we are implementing
372 //===----------------------------------------------------------------------===//
375 // Pull in Instruction Info:
376 let InstructionSet = ARMInstrInfo;
378 let AssemblyWriters = [ARMAsmWriter];