lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  24                                   "Thumb mode">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // ARM Subtarget features.
  28 //
  29
  30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  31                                    "Enable VFP2 instructions">;
  32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  33                                    "Enable VFP3 instructions",
  34                                    [FeatureVFP2]>;
  35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  36                                    "Enable NEON instructions",
  37                                    [FeatureVFP3]>;
  38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  39                                      "Enable Thumb2 instructions">;
  40 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  41                                      "Does not support ARM mode execution",
  42                                      [ModeThumb]>;
  43 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  44                                      "Enable half-precision floating point">;
  45 def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  46                                      "Enable VFP4 instructions",
  47                                      [FeatureVFP3, FeatureFP16]>;
  48 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
  49                                    "true", "Enable ARMv8 FP",
  50                                    [FeatureVFP4]>;
  51 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  52                                      "Restrict VFP3 to 16 double registers">;
  53 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  54                                      "Enable divide instructions">;
  55 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
  56                                         "HasHardwareDivideInARM", "true",
  57                                       "Enable divide instructions in ARM mode">;
  58 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  59                                  "Enable Thumb2 extract and pack instructions">;
  60 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  61                                    "Has data barrier (dmb / dsb) instructions">;
  62 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  63                                          "FP compare + branch is slow">;
  64 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  65                           "Floating point unit supports single precision only">;
  66 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  67                            "Enable support for Performance Monitor extensions">;
  68 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
  69                           "Enable support for TrustZone security extensions">;
  70 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  71                           "Enable support for Cryptography extensions",
  72                           [FeatureNEON]>;
  73
  74 // Some processors have FP multiply-accumulate instructions that don't
  75 // play nicely with other VFP / NEON instructions, and it's generally better
  76 // to just not use them.
  77 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  78                                          "Disable VFP / NEON MAC instructions">;
  79
  80 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
  81 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
  82                                        "HasVMLxForwarding", "true",
  83                                        "Has multiplier accumulator forwarding">;
  84
  85 // Some processors benefit from using NEON instructions for scalar
  86 // single-precision FP operations.
  87 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  88                                         "true",
  89                                         "Use NEON for single precision FP">;
  90
  91 // Disable 32-bit to 16-bit narrowing for experimentation.
  92 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  93                                              "Prefer 32-bit Thumb instrs">;
  94
  95 /// Some instructions update CPSR partially, which can add false dependency for
  96 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
  97 /// mapped to a separate physical register. Avoid partial CPSR update for these
  98 /// processors.
  99 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 100                                                "AvoidCPSRPartialUpdate", "true",
 101                                  "Avoid CPSR partial update for OOO execution">;
 102
 103 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
 104                                             "AvoidMOVsShifterOperand", "true",
 105                                 "Avoid movs instructions with shifter operand">;
 106
 107 // Some processors perform return stack prediction. CodeGen should avoid issue
 108 // "normal" call instructions to callees which do not return.
 109 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
 110                                      "Has return address stack">;
 111
 112 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
 113 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
 114                                  "Supports v7 DSP instructions in Thumb2">;
 115
 116 // Multiprocessing extension.
 117 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
 118                                  "Supports Multiprocessing extension">;
 119
 120 // M-series ISA
 121 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 122                                      "Is microcontroller profile ('M' series)">;
 123
 124 // R-series ISA
 125 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 126                                      "Is realtime profile ('R' series)">;
 127
 128 // A-series ISA
 129 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 130                                      "Is application profile ('A' series)">;
 131
 132 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 133 // See ARMInstrInfo.td for details.
 134 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 135                                        "NaCl trap">;
 136
 137 // ARM ISAs.
 138 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 139                                    "Support ARM v4T instructions">;
 140 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 141                                    "Support ARM v5T instructions",
 142                                    [HasV4TOps]>;
 143 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 144                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 145                                    [HasV5TOps]>;
 146 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 147                                    "Support ARM v6 instructions",
 148                                    [HasV5TEOps]>;
 149 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 150                                    "Support ARM v6t2 instructions",
 151                                    [HasV6Ops, FeatureThumb2]>;
 152 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 153                                    "Support ARM v7 instructions",
 154                                    [HasV6T2Ops, FeaturePerfMon]>;
 155 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 156                                    "Support ARM v8 instructions",
 157                                    [HasV7Ops]>;
 158
 159 //===----------------------------------------------------------------------===//
 160 // ARM Processors supported.
 161 //
 162
 163 include "ARMSchedule.td"
 164
 165 // ARM processor families.
 166 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 167                                    "Cortex-A5 ARM processors",
 168                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 169                                     FeatureVMLxForwarding, FeatureT2XtPk,
 170                                     FeatureTrustZone]>;
 171 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 172                                    "Cortex-A8 ARM processors",
 173                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 174                                     FeatureVMLxForwarding, FeatureT2XtPk,
 175                                     FeatureTrustZone]>;
 176 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 177                                    "Cortex-A9 ARM processors",
 178                                    [FeatureVMLxForwarding,
 179                                     FeatureT2XtPk, FeatureFP16,
 180                                     FeatureAvoidPartialCPSR,
 181                                     FeatureTrustZone]>;
 182 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 183                                    "Swift ARM processors",
 184                                    [FeatureNEONForFP, FeatureT2XtPk,
 185                                     FeatureVFP4, FeatureMP, FeatureHWDiv,
 186                                     FeatureHWDivARM, FeatureAvoidPartialCPSR,
 187                                     FeatureAvoidMOVsShOp,
 188                                     FeatureHasSlowFPVMLx, FeatureTrustZone]>;
 189
 190 // FIXME: It has not been determined if A15 has these features.
 191 def ProcA15      : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 192                                    "Cortex-A15 ARM processors",
 193                                    [FeatureT2XtPk, FeatureVFP4,
 194                                     FeatureAvoidPartialCPSR,
 195                                     FeatureTrustZone]>;
 196 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 197                                    "Cortex-R5 ARM processors",
 198                                    [FeatureSlowFPBrcc,
 199                                     FeatureHWDiv, FeatureHWDivARM,
 200                                     FeatureHasSlowFPVMLx,
 201                                     FeatureAvoidPartialCPSR,
 202                                     FeatureT2XtPk]>;
 203
 204 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 205  : Processor<Name, NoItineraries, Features>;
 206
 207 // V4 Processors.
 208 def : ProcNoItin<"generic",         []>;
 209 def : ProcNoItin<"arm8",            []>;
 210 def : ProcNoItin<"arm810",          []>;
 211 def : ProcNoItin<"strongarm",       []>;
 212 def : ProcNoItin<"strongarm110",    []>;
 213 def : ProcNoItin<"strongarm1100",   []>;
 214 def : ProcNoItin<"strongarm1110",   []>;
 215
 216 // V4T Processors.
 217 def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
 218 def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
 219 def : ProcNoItin<"arm710t",         [HasV4TOps]>;
 220 def : ProcNoItin<"arm720t",         [HasV4TOps]>;
 221 def : ProcNoItin<"arm9",            [HasV4TOps]>;
 222 def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
 223 def : ProcNoItin<"arm920",          [HasV4TOps]>;
 224 def : ProcNoItin<"arm920t",         [HasV4TOps]>;
 225 def : ProcNoItin<"arm922t",         [HasV4TOps]>;
 226 def : ProcNoItin<"arm940t",         [HasV4TOps]>;
 227 def : ProcNoItin<"ep9312",          [HasV4TOps]>;
 228
 229 // V5T Processors.
 230 def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
 231 def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
 232
 233 // V5TE Processors.
 234 def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
 235 def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
 236 def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
 237 def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
 238 def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
 239 def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
 240 def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
 241 def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
 242 def : ProcNoItin<"xscale",          [HasV5TEOps]>;
 243 def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
 244
 245 // V6 Processors.
 246 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
 247 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 248                                                        FeatureHasSlowFPVMLx]>;
 249 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
 250 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 251                                                        FeatureHasSlowFPVMLx]>;
 252 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
 253 def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 254                                                        FeatureHasSlowFPVMLx]>;
 255
 256 // V6M Processors.
 257 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
 258                                                        FeatureDB, FeatureMClass]>;
 259
 260 // V6T2 Processors.
 261 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
 262                                                        FeatureDSPThumb2]>;
 263 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
 264                                                        FeatureHasSlowFPVMLx,
 265                                                        FeatureDSPThumb2]>;
 266
 267 // V7a Processors.
 268 // FIXME: A5 has currently the same Schedule model as A8
 269 def : ProcessorModel<"cortex-a5",   CortexA8Model,
 270                                     [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
 271                                      FeatureVFP4, FeatureDSPThumb2,
 272                                      FeatureHasRAS, FeatureAClass]>;
 273 def : ProcessorModel<"cortex-a8",   CortexA8Model,
 274                                     [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
 275                                      FeatureDSPThumb2, FeatureHasRAS,
 276                                      FeatureAClass]>;
 277 def : ProcessorModel<"cortex-a9",   CortexA9Model,
 278                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 279                                      FeatureDSPThumb2, FeatureHasRAS,
 280                                      FeatureAClass]>;
 281 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
 282                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 283                                      FeatureDSPThumb2, FeatureMP,
 284                                      FeatureHasRAS, FeatureAClass]>;
 285 // FIXME: A15 has currently the same ProcessorModel as A9.
 286 def : ProcessorModel<"cortex-a15",   CortexA9Model,
 287                                     [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
 288                                      FeatureDSPThumb2, FeatureHasRAS,
 289                                      FeatureAClass]>;
 290 // FIXME: R5 has currently the same ProcessorModel as A8.
 291 def : ProcessorModel<"cortex-r5",   CortexA8Model,
 292                                     [ProcR5, HasV7Ops, FeatureDB,
 293                                      FeatureVFP3, FeatureDSPThumb2,
 294                                      FeatureHasRAS, FeatureRClass]>;
 295
 296 // V7M Processors.
 297 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
 298                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 299                                      FeatureHWDiv, FeatureMClass]>;
 300
 301 // V7EM Processors.
 302 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
 303                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 304                                      FeatureHWDiv, FeatureDSPThumb2,
 305                                      FeatureT2XtPk, FeatureVFP4,
 306                                      FeatureVFPOnlySP, FeatureMClass]>;
 307
 308 // Swift uArch Processors.
 309 def : ProcessorModel<"swift",       SwiftModel,
 310                                     [ProcSwift, HasV7Ops, FeatureNEON,
 311                                      FeatureDB, FeatureDSPThumb2,
 312                                      FeatureHasRAS, FeatureAClass]>;
 313
 314 // V8 Processors
 315 def : ProcNoItin<"cortex-a53",      [HasV8Ops, FeatureAClass]>;
 316
 317 //===----------------------------------------------------------------------===//
 318 // Register File Description
 319 //===----------------------------------------------------------------------===//
 320
 321 include "ARMRegisterInfo.td"
 322
 323 include "ARMCallingConv.td"
 324
 325 //===----------------------------------------------------------------------===//
 326 // Instruction Descriptions
 327 //===----------------------------------------------------------------------===//
 328
 329 include "ARMInstrInfo.td"
 330
 331 def ARMInstrInfo : InstrInfo;
 332
 333
 334 //===----------------------------------------------------------------------===//
 335 // Assembly printer
 336 //===----------------------------------------------------------------------===//
 337 // ARM Uses the MC printer for asm output, so make sure the TableGen
 338 // AsmWriter bits get associated with the correct class.
 339 def ARMAsmWriter : AsmWriter {
 340   string AsmWriterClassName  = "InstPrinter";
 341   bit isMCAsmWriter = 1;
 342 }
 343
 344 //===----------------------------------------------------------------------===//
 345 // Declare the target which we are implementing
 346 //===----------------------------------------------------------------------===//
 347
 348 def ARM : Target {
 349   // Pull in Instruction Info:
 350   let InstructionSet = ARMInstrInfo;
 351
 352   let AssemblyWriters = [ARMAsmWriter];
 353 }