1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "SIDefines.h"
21 #include "SIRegisterInfo.h"
25 class SIInstrInfo : public AMDGPUInstrInfo {
27 const SIRegisterInfo RI;
29 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
30 MachineRegisterInfo &MRI,
31 MachineOperand &SuperReg,
32 const TargetRegisterClass *SuperRC,
34 const TargetRegisterClass *SubRC) const;
35 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
36 MachineRegisterInfo &MRI,
37 MachineOperand &SuperReg,
38 const TargetRegisterClass *SuperRC,
40 const TargetRegisterClass *SubRC) const;
42 void swapOperands(MachineBasicBlock::iterator Inst) const;
44 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
45 MachineInstr *Inst, unsigned Opcode) const;
47 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
50 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst) const;
52 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
53 MachineInstr *Inst) const;
55 void addUsersToMoveToVALUWorklist(
56 unsigned Reg, MachineRegisterInfo &MRI,
57 SmallVectorImpl<MachineInstr *> &Worklist) const;
59 bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
60 MachineInstr *MIb) const;
62 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
65 explicit SIInstrInfo(const AMDGPUSubtarget &st);
67 const SIRegisterInfo &getRegisterInfo() const override {
71 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
72 AliasAnalysis *AA) const override;
74 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
76 int64_t &Offset2) const override;
78 bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
80 const TargetRegisterInfo *TRI) const final;
82 bool shouldClusterLoads(MachineInstr *FirstLdSt,
83 MachineInstr *SecondLdSt,
84 unsigned NumLoads) const final;
86 void copyPhysReg(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MI, DebugLoc DL,
88 unsigned DestReg, unsigned SrcReg,
89 bool KillSrc) const override;
91 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
98 void storeRegToStackSlot(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator MI,
100 unsigned SrcReg, bool isKill, int FrameIndex,
101 const TargetRegisterClass *RC,
102 const TargetRegisterInfo *TRI) const override;
104 void loadRegFromStackSlot(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator MI,
106 unsigned DestReg, int FrameIndex,
107 const TargetRegisterClass *RC,
108 const TargetRegisterInfo *TRI) const override;
110 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
112 // \brief Returns an opcode that can be used to move a value to a \p DstRC
113 // register. If there is no hardware instruction that can store to \p
114 // DstRC, then AMDGPU::COPY is returned.
115 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
118 int commuteOpcode(const MachineInstr &MI) const;
120 MachineInstr *commuteInstruction(MachineInstr *MI,
121 bool NewMI = false) const override;
122 bool findCommutedOpIndices(MachineInstr *MI,
124 unsigned &SrcOpIdx2) const override;
126 bool areMemAccessesTriviallyDisjoint(
127 MachineInstr *MIa, MachineInstr *MIb,
128 AliasAnalysis *AA = nullptr) const override;
130 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
131 MachineBasicBlock::iterator I,
132 unsigned DstReg, unsigned SrcReg) const override;
133 bool isMov(unsigned Opcode) const override;
135 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
136 unsigned Reg, MachineRegisterInfo *MRI) const final;
138 unsigned getMachineCSELookAheadLimit() const override { return 500; }
140 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
141 MachineBasicBlock::iterator &MI,
142 LiveVariables *LV) const override;
144 bool isSALU(uint16_t Opcode) const {
145 return get(Opcode).TSFlags & SIInstrFlags::SALU;
148 bool isVALU(uint16_t Opcode) const {
149 return get(Opcode).TSFlags & SIInstrFlags::VALU;
152 bool isSOP1(uint16_t Opcode) const {
153 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
156 bool isSOP2(uint16_t Opcode) const {
157 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
160 bool isSOPC(uint16_t Opcode) const {
161 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
164 bool isSOPK(uint16_t Opcode) const {
165 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
168 bool isSOPP(uint16_t Opcode) const {
169 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
172 bool isVOP1(uint16_t Opcode) const {
173 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
176 bool isVOP2(uint16_t Opcode) const {
177 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
180 bool isVOP3(uint16_t Opcode) const {
181 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
184 bool isVOPC(uint16_t Opcode) const {
185 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
188 bool isMUBUF(uint16_t Opcode) const {
189 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
192 bool isMTBUF(uint16_t Opcode) const {
193 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
196 bool isSMRD(uint16_t Opcode) const {
197 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
200 bool isDS(uint16_t Opcode) const {
201 return get(Opcode).TSFlags & SIInstrFlags::DS;
204 bool isMIMG(uint16_t Opcode) const {
205 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
208 bool isFLAT(uint16_t Opcode) const {
209 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
212 bool isWQM(uint16_t Opcode) const {
213 return get(Opcode).TSFlags & SIInstrFlags::WQM;
216 bool isVGPRSpill(uint16_t Opcode) const {
217 return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
220 bool isInlineConstant(const APInt &Imm) const;
221 bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
222 bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
224 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
225 const MachineOperand &MO) const;
227 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
228 /// This function will return false if you pass it a 32-bit instruction.
229 bool hasVALU32BitEncoding(unsigned Opcode) const;
231 /// \brief Returns true if this operand uses the constant bus.
232 bool usesConstantBus(const MachineRegisterInfo &MRI,
233 const MachineOperand &MO,
234 unsigned OpSize) const;
236 /// \brief Return true if this instruction has any modifiers.
237 /// e.g. src[012]_mod, omod, clamp.
238 bool hasModifiers(unsigned Opcode) const;
240 bool hasModifiersSet(const MachineInstr &MI,
241 unsigned OpName) const;
243 bool verifyInstruction(const MachineInstr *MI,
244 StringRef &ErrInfo) const override;
246 static unsigned getVALUOp(const MachineInstr &MI);
248 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
250 /// \brief Return the correct register class for \p OpNo. For target-specific
251 /// instructions, this will return the register class that has been defined
252 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
253 /// the register class of its machine operand.
254 /// to infer the correct register class base on the other operands.
255 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
256 unsigned OpNo) const;
258 /// \brief Return the size in bytes of the operand OpNo on the given
259 // instruction opcode.
260 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
261 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
263 if (OpInfo.RegClass == -1) {
264 // If this is an immediate operand, this must be a 32-bit literal.
265 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
269 return RI.getRegClass(OpInfo.RegClass)->getSize();
272 /// \brief This form should usually be preferred since it handles operands
273 /// with unknown register classes.
274 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
275 return getOpRegClass(MI, OpNo)->getSize();
278 /// \returns true if it is legal for the operand at index \p OpNo
280 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
282 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
283 /// a MOV. For example:
284 /// ADD_I32_e32 VGPR0, 15
287 /// ADD_I32_e32 VGPR0, VGPR1
289 /// If the operand being legalized is a register, then a COPY will be used
291 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
293 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
295 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
296 const MachineOperand *MO = nullptr) const;
298 /// \brief Legalize all operands in this instruction. This function may
299 /// create new instruction and insert them before \p MI.
300 void legalizeOperands(MachineInstr *MI) const;
302 /// \brief Split an SMRD instruction into two smaller loads of half the
303 // size storing the results in \p Lo and \p Hi.
304 void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
305 unsigned HalfImmOp, unsigned HalfSGPROp,
306 MachineInstr *&Lo, MachineInstr *&Hi) const;
308 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI,
309 SmallVectorImpl<MachineInstr *> &Worklist) const;
311 /// \brief Replace this instruction's opcode with the equivalent VALU
312 /// opcode. This function will also move the users of \p MI to the
313 /// VALU if necessary.
314 void moveToVALU(MachineInstr &MI) const;
316 unsigned calculateIndirectAddress(unsigned RegIndex,
317 unsigned Channel) const override;
319 const TargetRegisterClass *getIndirectAddrRegClass() const override;
321 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
322 MachineBasicBlock::iterator I,
325 unsigned OffsetReg) const override;
327 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
328 MachineBasicBlock::iterator I,
331 unsigned OffsetReg) const override;
332 void reserveIndirectRegisters(BitVector &Reserved,
333 const MachineFunction &MF) const;
335 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
336 unsigned SavReg, unsigned IndexReg) const;
338 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
340 /// \brief Returns the operand named \p Op. If \p MI does not have an
341 /// operand named \c Op, this function returns nullptr.
343 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
346 const MachineOperand *getNamedOperand(const MachineInstr &MI,
347 unsigned OpName) const {
348 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
351 uint64_t getDefaultRsrcDataFormat() const;
357 int getVOPe64(uint16_t Opcode);
360 int getVOPe32(uint16_t Opcode);
363 int getCommuteRev(uint16_t Opcode);
366 int getCommuteOrig(uint16_t Opcode);
369 int getAddr64Inst(uint16_t Opcode);
372 int getAtomicRetOp(uint16_t Opcode);
375 int getAtomicNoRetOp(uint16_t Opcode);
377 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
378 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
380 } // End namespace AMDGPU
383 namespace KernelInputOffsets {
385 /// Offsets in bytes from the start of the input buffer
398 } // End namespace KernelInputOffsets
399 } // End namespace SI
401 } // End namespace llvm