1 //===-- SIFoldOperands.cpp - Fold operands --- ----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
13 #include "AMDGPUSubtarget.h"
14 #include "SIInstrInfo.h"
15 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
16 #include "llvm/CodeGen/MachineDominators.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/LLVMContext.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetMachine.h"
26 #define DEBUG_TYPE "si-fold-operands"
31 class SIFoldOperands : public MachineFunctionPass {
36 SIFoldOperands() : MachineFunctionPass(ID) {
37 initializeSIFoldOperandsPass(*PassRegistry::getPassRegistry());
40 bool runOnMachineFunction(MachineFunction &MF) override;
42 const char *getPassName() const override {
43 return "SI Fold Operands";
46 void getAnalysisUsage(AnalysisUsage &AU) const override {
47 AU.addRequired<MachineDominatorTree>();
49 MachineFunctionPass::getAnalysisUsage(AU);
53 struct FoldCandidate {
56 MachineOperand *OpToFold;
59 FoldCandidate(MachineInstr *MI, unsigned OpNo, MachineOperand *FoldOp) :
60 UseMI(MI), UseOpNo(OpNo) {
62 if (FoldOp->isImm()) {
64 ImmToFold = FoldOp->getImm();
66 assert(FoldOp->isReg());
76 } // End anonymous namespace.
78 INITIALIZE_PASS_BEGIN(SIFoldOperands, DEBUG_TYPE,
79 "SI Fold Operands", false, false)
80 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
81 INITIALIZE_PASS_END(SIFoldOperands, DEBUG_TYPE,
82 "SI Fold Operands", false, false)
84 char SIFoldOperands::ID = 0;
86 char &llvm::SIFoldOperandsID = SIFoldOperands::ID;
88 FunctionPass *llvm::createSIFoldOperandsPass() {
89 return new SIFoldOperands();
92 static bool isSafeToFold(unsigned Opcode) {
94 case AMDGPU::V_MOV_B32_e32:
95 case AMDGPU::V_MOV_B32_e64:
96 case AMDGPU::V_MOV_B64_PSEUDO:
97 case AMDGPU::S_MOV_B32:
98 case AMDGPU::S_MOV_B64:
106 static bool updateOperand(FoldCandidate &Fold,
107 const TargetRegisterInfo &TRI) {
108 MachineInstr *MI = Fold.UseMI;
109 MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
113 Old.ChangeToImmediate(Fold.ImmToFold);
117 MachineOperand *New = Fold.OpToFold;
118 if (TargetRegisterInfo::isVirtualRegister(Old.getReg()) &&
119 TargetRegisterInfo::isVirtualRegister(New->getReg())) {
120 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
124 // FIXME: Handle physical registers.
129 static bool isUseMIInFoldList(const std::vector<FoldCandidate> &FoldList,
130 const MachineInstr *MI) {
131 for (auto Candidate : FoldList) {
132 if (Candidate.UseMI == MI)
138 static bool tryAddToFoldList(std::vector<FoldCandidate> &FoldList,
139 MachineInstr *MI, unsigned OpNo,
140 MachineOperand *OpToFold,
141 const SIInstrInfo *TII) {
142 if (!TII->isOperandLegal(MI, OpNo, OpToFold)) {
144 // Special case for v_mac_f32_e64 if we are trying to fold into src2
145 unsigned Opc = MI->getOpcode();
146 if (Opc == AMDGPU::V_MAC_F32_e64 &&
147 (int)OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)) {
148 // Check if changing this to a v_mad_f32 instruction will allow us to
150 MI->setDesc(TII->get(AMDGPU::V_MAD_F32));
151 bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII);
153 MI->untieRegOperand(OpNo);
156 MI->setDesc(TII->get(Opc));
159 // If we are already folding into another operand of MI, then
160 // we can't commute the instruction, otherwise we risk making the
161 // other fold illegal.
162 if (isUseMIInFoldList(FoldList, MI))
165 // Operand is not legal, so try to commute the instruction to
166 // see if this makes it possible to fold.
167 unsigned CommuteIdx0;
168 unsigned CommuteIdx1;
169 bool CanCommute = TII->findCommutedOpIndices(MI, CommuteIdx0, CommuteIdx1);
172 if (CommuteIdx0 == OpNo)
174 else if (CommuteIdx1 == OpNo)
178 if (!CanCommute || !TII->commuteInstruction(MI))
181 if (!TII->isOperandLegal(MI, OpNo, OpToFold))
185 FoldList.push_back(FoldCandidate(MI, OpNo, OpToFold));
189 static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
191 std::vector<FoldCandidate> &FoldList,
192 const SIInstrInfo *TII, const SIRegisterInfo &TRI,
193 MachineRegisterInfo &MRI) {
194 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx);
196 // FIXME: Fold operands with subregs.
197 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) ||
198 UseOp.isImplicit())) {
202 bool FoldingImm = OpToFold.isImm();
206 unsigned UseReg = UseOp.getReg();
207 const TargetRegisterClass *UseRC
208 = TargetRegisterInfo::isVirtualRegister(UseReg) ?
209 MRI.getRegClass(UseReg) :
210 TRI.getPhysRegClass(UseReg);
212 Imm = APInt(64, OpToFold.getImm());
214 // Split 64-bit constants into 32-bits for folding.
215 if (UseOp.getSubReg()) {
216 if (UseRC->getSize() != 8)
219 if (UseOp.getSubReg() == AMDGPU::sub0) {
220 Imm = Imm.getLoBits(32);
222 assert(UseOp.getSubReg() == AMDGPU::sub1);
223 Imm = Imm.getHiBits(32);
227 // In order to fold immediates into copies, we need to change the
229 if (UseMI->getOpcode() == AMDGPU::COPY) {
230 unsigned DestReg = UseMI->getOperand(0).getReg();
231 const TargetRegisterClass *DestRC
232 = TargetRegisterInfo::isVirtualRegister(DestReg) ?
233 MRI.getRegClass(DestReg) :
234 TRI.getPhysRegClass(DestReg);
236 unsigned MovOp = TII->getMovOpcode(DestRC);
237 if (MovOp == AMDGPU::COPY)
240 UseMI->setDesc(TII->get(MovOp));
244 const MCInstrDesc &UseDesc = UseMI->getDesc();
246 // Don't fold into target independent nodes. Target independent opcodes
247 // don't have defined register classes.
248 if (UseDesc.isVariadic() ||
249 UseDesc.OpInfo[UseOpIdx].RegClass == -1)
253 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue());
254 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII);
258 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII);
260 // FIXME: We could try to change the instruction from 64-bit to 32-bit
261 // to enable more folding opportunites. The shrink operands pass
262 // already does this.
266 bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
267 MachineRegisterInfo &MRI = MF.getRegInfo();
268 const SIInstrInfo *TII =
269 static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
270 const SIRegisterInfo &TRI = TII->getRegisterInfo();
272 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
275 MachineBasicBlock &MBB = *BI;
276 MachineBasicBlock::iterator I, Next;
277 for (I = MBB.begin(); I != MBB.end(); I = Next) {
279 MachineInstr &MI = *I;
281 if (!isSafeToFold(MI.getOpcode()))
284 unsigned OpSize = TII->getOpSize(MI, 1);
285 MachineOperand &OpToFold = MI.getOperand(1);
286 bool FoldingImm = OpToFold.isImm();
288 // FIXME: We could also be folding things like FrameIndexes and
290 if (!FoldingImm && !OpToFold.isReg())
293 // Folding immediates with more than one use will increase program size.
294 // FIXME: This will also reduce register usage, which may be better
295 // in some cases. A better heuristic is needed.
296 if (FoldingImm && !TII->isInlineConstant(OpToFold, OpSize) &&
297 !MRI.hasOneUse(MI.getOperand(0).getReg()))
300 // FIXME: Fold operands with subregs.
301 if (OpToFold.isReg() &&
302 (!TargetRegisterInfo::isVirtualRegister(OpToFold.getReg()) ||
303 OpToFold.getSubReg()))
306 std::vector<FoldCandidate> FoldList;
307 for (MachineRegisterInfo::use_iterator
308 Use = MRI.use_begin(MI.getOperand(0).getReg()), E = MRI.use_end();
311 MachineInstr *UseMI = Use->getParent();
313 foldOperand(OpToFold, UseMI, Use.getOperandNo(), FoldList,
317 for (FoldCandidate &Fold : FoldList) {
318 if (updateOperand(Fold, TRI)) {
321 assert(Fold.OpToFold && Fold.OpToFold->isReg());
322 Fold.OpToFold->setIsKill(false);
324 DEBUG(dbgs() << "Folded source from " << MI << " into OpNo " <<
325 Fold.UseOpNo << " of " << *Fold.UseMI << '\n');